1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L4xx_LL_PWR_H
21 #define STM32L4xx_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l4xx.h"
29
30 /** @addtogroup STM32L4xx_LL_Driver
31 * @{
32 */
33
34 #if defined(PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44
45 /* Private macros ------------------------------------------------------------*/
46
47 /* Exported types ------------------------------------------------------------*/
48 /* Exported constants --------------------------------------------------------*/
49 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
50 * @{
51 */
52
53 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
54 * @brief Flags defines which can be used with LL_PWR_WriteReg function
55 * @{
56 */
57 #define LL_PWR_SCR_CSBF PWR_SCR_CSBF
58 #define LL_PWR_SCR_CWUF PWR_SCR_CWUF
59 #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
60 #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
61 #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
62 #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
63 #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
64 /**
65 * @}
66 */
67
68 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
69 * @brief Flags defines which can be used with LL_PWR_ReadReg function
70 * @{
71 */
72 #define LL_PWR_SR1_WUFI PWR_SR1_WUFI
73 #if defined(PWR_SR1_EXT_SMPS_RDY)
74 #define LL_PWR_SR1_EXT_SMPS_RDY PWR_SR1_EXT_SMPS_RDY
75 #endif /* PWR_SR1_EXT_SMPS_RDY */
76 #define LL_PWR_SR1_SBF PWR_SR1_SBF
77 #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5
78 #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4
79 #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
80 #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
81 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
82 #if defined(PWR_SR2_PVMO4)
83 #define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4
84 #endif /* PWR_SR2_PVMO4 */
85 #if defined(PWR_SR2_PVMO3)
86 #define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
87 #endif /* PWR_SR2_PVMO3 */
88 #if defined(PWR_SR2_PVMO2)
89 #define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2
90 #endif /* PWR_SR2_PVMO2 */
91 #if defined(PWR_SR2_PVMO1)
92 #define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
93 #endif /* PWR_SR2_PVMO1 */
94 #define LL_PWR_SR2_PVDO PWR_SR2_PVDO
95 #define LL_PWR_SR2_VOSF PWR_SR2_VOSF
96 #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
97 #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
98 /**
99 * @}
100 */
101
102 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
103 * @{
104 */
105 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0)
106 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1)
107 /**
108 * @}
109 */
110
111 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
112 * @{
113 */
114 #define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0)
115 #define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1)
116 #define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_STOP2)
117 #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY)
118 #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN)
119 /**
120 * @}
121 */
122
123 /** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring
124 * @{
125 */
126 #if defined(PWR_CR2_PVME1)
127 #define LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */
128 #endif
129 #if defined(PWR_CR2_PVME2)
130 #define LL_PWR_PVM_VDDIO2_0_9V (PWR_CR2_PVME2) /* Monitoring VDDIO2 vs. 0.9V */
131 #endif
132 #if defined(PWR_CR2_PVME3)
133 #define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */
134 #endif
135 #if defined(PWR_CR2_PVME4)
136 #define LL_PWR_PVM_VDDA_2_2V (PWR_CR2_PVME4) /* Monitoring VDDA vs. 2.2V */
137 #endif
138 /**
139 * @}
140 */
141
142 /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
143 * @{
144 */
145 #define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */
146 #define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */
147 #define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */
148 #define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */
149 #define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */
150 #define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */
151 #define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */
152 #define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */
153 /**
154 * @}
155 */
156
157 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP
158 * @{
159 */
160 #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
161 #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
162 #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
163 #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
164 #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
165 /**
166 * @}
167 */
168
169 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
170 * @{
171 */
172 #define LL_PWR_BATT_CHARG_RESISTOR_5K (0x00000000U)
173 #define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)
174 /**
175 * @}
176 */
177
178 /** @defgroup PWR_LL_EC_SRAM2_CONTENT_RETENTION SRAM2 CONTENT RETENTION
179 * @{
180 */
181 #define LL_PWR_NO_SRAM2_RETENTION (0x00000000U)
182 #if defined(PWR_CR3_RRS_1)
183 #define LL_PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS_0
184 #define LL_PWR_4KBYTES_SRAM2_RETENTION PWR_CR3_RRS_1
185 #else
186 #define LL_PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS
187 #endif /* PWR_CR3_RRS_1 */
188 /**
189 * @}
190 */
191
192 /** @defgroup PWR_LL_EC_GPIO GPIO
193 * @{
194 */
195 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
196 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
197 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
198 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
199 #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
200 #if defined(GPIOF)
201 #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
202 #endif
203 #if defined(GPIOG)
204 #define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG)))
205 #endif
206 #if defined(GPIOH)
207 #define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH)))
208 #endif
209 #if defined(GPIOI)
210 #define LL_PWR_GPIO_I ((uint32_t)(&(PWR->PUCRI)))
211 #endif
212 /**
213 * @}
214 */
215
216 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
217 * @{
218 */
219 #define LL_PWR_GPIO_BIT_0 (0x00000001U)
220 #define LL_PWR_GPIO_BIT_1 (0x00000002U)
221 #define LL_PWR_GPIO_BIT_2 (0x00000004U)
222 #define LL_PWR_GPIO_BIT_3 (0x00000008U)
223 #define LL_PWR_GPIO_BIT_4 (0x00000010U)
224 #define LL_PWR_GPIO_BIT_5 (0x00000020U)
225 #define LL_PWR_GPIO_BIT_6 (0x00000040U)
226 #define LL_PWR_GPIO_BIT_7 (0x00000080U)
227 #define LL_PWR_GPIO_BIT_8 (0x00000100U)
228 #define LL_PWR_GPIO_BIT_9 (0x00000200U)
229 #define LL_PWR_GPIO_BIT_10 (0x00000400U)
230 #define LL_PWR_GPIO_BIT_11 (0x00000800U)
231 #define LL_PWR_GPIO_BIT_12 (0x00001000U)
232 #define LL_PWR_GPIO_BIT_13 (0x00002000U)
233 #define LL_PWR_GPIO_BIT_14 (0x00004000U)
234 #define LL_PWR_GPIO_BIT_15 (0x00008000U)
235 /**
236 * @}
237 */
238
239 /**
240 * @}
241 */
242
243 /* Exported macro ------------------------------------------------------------*/
244 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
245 * @{
246 */
247
248 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
249 * @{
250 */
251
252 /**
253 * @brief Write a value in PWR register
254 * @param __REG__ Register to be written
255 * @param __VALUE__ Value to be written in the register
256 * @retval None
257 */
258 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
259
260 /**
261 * @brief Read a value in PWR register
262 * @param __REG__ Register to be read
263 * @retval Register value
264 */
265 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
266 /**
267 * @}
268 */
269
270 /**
271 * @}
272 */
273
274
275 /* Exported functions --------------------------------------------------------*/
276 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
277 * @{
278 */
279
280 /** @defgroup PWR_LL_EF_Configuration Configuration
281 * @{
282 */
283
284 /**
285 * @brief Switch the regulator from main mode to low-power mode
286 * @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode
287 * @retval None
288 */
LL_PWR_EnableLowPowerRunMode(void)289 __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
290 {
291 SET_BIT(PWR->CR1, PWR_CR1_LPR);
292 }
293
294 /**
295 * @brief Switch the regulator from low-power mode to main mode
296 * @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode
297 * @retval None
298 */
LL_PWR_DisableLowPowerRunMode(void)299 __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
300 {
301 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
302 }
303
304 /**
305 * @brief Switch from run main mode to run low-power mode.
306 * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode
307 * @retval None
308 */
LL_PWR_EnterLowPowerRunMode(void)309 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
310 {
311 LL_PWR_EnableLowPowerRunMode();
312 }
313
314 /**
315 * @brief Switch from run main mode to low-power mode.
316 * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode
317 * @retval None
318 */
LL_PWR_ExitLowPowerRunMode(void)319 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
320 {
321 LL_PWR_DisableLowPowerRunMode();
322 }
323
324 /**
325 * @brief Check if the regulator is in low-power mode
326 * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
327 * @retval State of bit (1 or 0).
328 */
LL_PWR_IsEnabledLowPowerRunMode(void)329 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
330 {
331 return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL);
332 }
333
334 /**
335 * @brief Set the main internal regulator output voltage
336 * @note This configuration may be completed with LL_PWR_EnableRange1BoostMode() on STM32L4Rx/STM32L4Sx devices.
337 * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling
338 * @param VoltageScaling This parameter can be one of the following values:
339 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
340 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
341 * @retval None
342 */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)343 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
344 {
345 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
346 }
347
348 /**
349 * @brief Get the main internal regulator output voltage
350 * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling
351 * @retval Returned value can be one of the following values:
352 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
353 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
354 */
LL_PWR_GetRegulVoltageScaling(void)355 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
356 {
357 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
358 }
359
360 #if defined(PWR_CR5_R1MODE)
361 /**
362 * @brief Enable main regulator voltage range 1 boost mode
363 * @rmtoll CR5 R1MODE LL_PWR_EnableRange1BoostMode
364 * @retval None
365 */
LL_PWR_EnableRange1BoostMode(void)366 __STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void)
367 {
368 CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
369 }
370
371 /**
372 * @brief Disable main regulator voltage range 1 boost mode
373 * @rmtoll CR5 R1MODE LL_PWR_DisableRange1BoostMode
374 * @retval None
375 */
LL_PWR_DisableRange1BoostMode(void)376 __STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void)
377 {
378 SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
379 }
380
381 /**
382 * @brief Check if the main regulator voltage range 1 boost mode is enabled
383 * @rmtoll CR5 R1MODE LL_PWR_IsEnabledRange1BoostMode
384 * @retval Inverted state of bit (0 or 1).
385 */
LL_PWR_IsEnabledRange1BoostMode(void)386 __STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void)
387 {
388 return ((READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == 0x0U) ? 1UL : 0UL);
389 }
390 #endif /* PWR_CR5_R1MODE */
391
392 /**
393 * @brief Enable access to the backup domain
394 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
395 * @retval None
396 */
LL_PWR_EnableBkUpAccess(void)397 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
398 {
399 SET_BIT(PWR->CR1, PWR_CR1_DBP);
400 }
401
402 /**
403 * @brief Disable access to the backup domain
404 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
405 * @retval None
406 */
LL_PWR_DisableBkUpAccess(void)407 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
408 {
409 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
410 }
411
412 /**
413 * @brief Check if the backup domain is enabled
414 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
415 * @retval State of bit (1 or 0).
416 */
LL_PWR_IsEnabledBkUpAccess(void)417 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
418 {
419 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
420 }
421
422 /**
423 * @brief Set Low-Power mode
424 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
425 * @param LowPowerMode This parameter can be one of the following values:
426 * @arg @ref LL_PWR_MODE_STOP0
427 * @arg @ref LL_PWR_MODE_STOP1
428 * @arg @ref LL_PWR_MODE_STOP2
429 * @arg @ref LL_PWR_MODE_STANDBY
430 * @arg @ref LL_PWR_MODE_SHUTDOWN
431 * @retval None
432 */
LL_PWR_SetPowerMode(uint32_t LowPowerMode)433 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
434 {
435 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
436 }
437
438 /**
439 * @brief Get Low-Power mode
440 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
441 * @retval Returned value can be one of the following values:
442 * @arg @ref LL_PWR_MODE_STOP0
443 * @arg @ref LL_PWR_MODE_STOP1
444 * @arg @ref LL_PWR_MODE_STOP2
445 * @arg @ref LL_PWR_MODE_STANDBY
446 * @arg @ref LL_PWR_MODE_SHUTDOWN
447 */
LL_PWR_GetPowerMode(void)448 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
449 {
450 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
451 }
452
453 #if defined(PWR_CR1_RRSTP)
454 /**
455 * @brief Enable SRAM3 content retention in Stop mode
456 * @rmtoll CR1 RRSTP LL_PWR_EnableSRAM3Retention
457 * @retval None
458 */
LL_PWR_EnableSRAM3Retention(void)459 __STATIC_INLINE void LL_PWR_EnableSRAM3Retention(void)
460 {
461 SET_BIT(PWR->CR1, PWR_CR1_RRSTP);
462 }
463
464 /**
465 * @brief Disable SRAM3 content retention in Stop mode
466 * @rmtoll CR1 RRSTP LL_PWR_DisableSRAM3Retention
467 * @retval None
468 */
LL_PWR_DisableSRAM3Retention(void)469 __STATIC_INLINE void LL_PWR_DisableSRAM3Retention(void)
470 {
471 CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP);
472 }
473
474 /**
475 * @brief Check if SRAM3 content retention in Stop mode is enabled
476 * @rmtoll CR1 RRSTP LL_PWR_IsEnabledSRAM3Retention
477 * @retval State of bit (1 or 0).
478 */
LL_PWR_IsEnabledSRAM3Retention(void)479 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM3Retention(void)
480 {
481 return ((READ_BIT(PWR->CR1, PWR_CR1_RRSTP) == (PWR_CR1_RRSTP)) ? 1UL : 0UL);
482 }
483 #endif /* PWR_CR1_RRSTP */
484
485 #if defined(PWR_CR3_DSIPDEN)
486 /**
487 * @brief Enable pull-down activation on DSI pins
488 * @rmtoll CR3 DSIPDEN LL_PWR_EnableDSIPinsPDActivation
489 * @retval None
490 */
LL_PWR_EnableDSIPinsPDActivation(void)491 __STATIC_INLINE void LL_PWR_EnableDSIPinsPDActivation(void)
492 {
493 SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN);
494 }
495
496 /**
497 * @brief Disable pull-down activation on DSI pins
498 * @rmtoll CR3 DSIPDEN LL_PWR_DisableDSIPinsPDActivation
499 * @retval None
500 */
LL_PWR_DisableDSIPinsPDActivation(void)501 __STATIC_INLINE void LL_PWR_DisableDSIPinsPDActivation(void)
502 {
503 CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN);
504 }
505
506 /**
507 * @brief Check if pull-down activation on DSI pins is enabled
508 * @rmtoll CR3 DSIPDEN LL_PWR_IsEnabledDSIPinsPDActivation
509 * @retval State of bit (1 or 0).
510 */
LL_PWR_IsEnabledDSIPinsPDActivation(void)511 __STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPinsPDActivation(void)
512 {
513 return ((READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)) ? 1UL : 0UL);
514 }
515 #endif /* PWR_CR3_DSIPDEN */
516
517 #if defined(PWR_CR2_USV)
518 /**
519 * @brief Enable VDDUSB supply
520 * @rmtoll CR2 USV LL_PWR_EnableVddUSB
521 * @retval None
522 */
LL_PWR_EnableVddUSB(void)523 __STATIC_INLINE void LL_PWR_EnableVddUSB(void)
524 {
525 SET_BIT(PWR->CR2, PWR_CR2_USV);
526 }
527
528 /**
529 * @brief Disable VDDUSB supply
530 * @rmtoll CR2 USV LL_PWR_DisableVddUSB
531 * @retval None
532 */
LL_PWR_DisableVddUSB(void)533 __STATIC_INLINE void LL_PWR_DisableVddUSB(void)
534 {
535 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
536 }
537
538 /**
539 * @brief Check if VDDUSB supply is enabled
540 * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB
541 * @retval State of bit (1 or 0).
542 */
LL_PWR_IsEnabledVddUSB(void)543 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
544 {
545 return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL);
546 }
547 #endif
548
549 #if defined(PWR_CR2_IOSV)
550 /**
551 * @brief Enable VDDIO2 supply
552 * @rmtoll CR2 IOSV LL_PWR_EnableVddIO2
553 * @retval None
554 */
LL_PWR_EnableVddIO2(void)555 __STATIC_INLINE void LL_PWR_EnableVddIO2(void)
556 {
557 SET_BIT(PWR->CR2, PWR_CR2_IOSV);
558 }
559
560 /**
561 * @brief Disable VDDIO2 supply
562 * @rmtoll CR2 IOSV LL_PWR_DisableVddIO2
563 * @retval None
564 */
LL_PWR_DisableVddIO2(void)565 __STATIC_INLINE void LL_PWR_DisableVddIO2(void)
566 {
567 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
568 }
569
570 /**
571 * @brief Check if VDDIO2 supply is enabled
572 * @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2
573 * @retval State of bit (1 or 0).
574 */
LL_PWR_IsEnabledVddIO2(void)575 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
576 {
577 return ((READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)) ? 1UL : 0UL);
578 }
579 #endif
580
581 /**
582 * @brief Enable the Power Voltage Monitoring on a peripheral
583 * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n
584 * CR2 PVME2 LL_PWR_EnablePVM\n
585 * CR2 PVME3 LL_PWR_EnablePVM\n
586 * CR2 PVME4 LL_PWR_EnablePVM
587 * @param PeriphVoltage This parameter can be one of the following values:
588 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
589 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)
590 * @arg @ref LL_PWR_PVM_VDDA_1_62V
591 * @arg @ref LL_PWR_PVM_VDDA_2_2V
592 *
593 * (*) value not defined in all devices
594 * @retval None
595 */
LL_PWR_EnablePVM(uint32_t PeriphVoltage)596 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
597 {
598 SET_BIT(PWR->CR2, PeriphVoltage);
599 }
600
601 /**
602 * @brief Disable the Power Voltage Monitoring on a peripheral
603 * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n
604 * CR2 PVME2 LL_PWR_DisablePVM\n
605 * CR2 PVME3 LL_PWR_DisablePVM\n
606 * CR2 PVME4 LL_PWR_DisablePVM
607 * @param PeriphVoltage This parameter can be one of the following values:
608 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
609 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)
610 * @arg @ref LL_PWR_PVM_VDDA_1_62V
611 * @arg @ref LL_PWR_PVM_VDDA_2_2V
612 *
613 * (*) value not defined in all devices
614 * @retval None
615 */
LL_PWR_DisablePVM(uint32_t PeriphVoltage)616 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
617 {
618 CLEAR_BIT(PWR->CR2, PeriphVoltage);
619 }
620
621 /**
622 * @brief Check if Power Voltage Monitoring is enabled on a peripheral
623 * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n
624 * CR2 PVME2 LL_PWR_IsEnabledPVM\n
625 * CR2 PVME3 LL_PWR_IsEnabledPVM\n
626 * CR2 PVME4 LL_PWR_IsEnabledPVM
627 * @param PeriphVoltage This parameter can be one of the following values:
628 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
629 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)
630 * @arg @ref LL_PWR_PVM_VDDA_1_62V
631 * @arg @ref LL_PWR_PVM_VDDA_2_2V
632 *
633 * (*) value not defined in all devices
634 * @retval State of bit (1 or 0).
635 */
LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)636 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
637 {
638 return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL);
639 }
640
641 /**
642 * @brief Configure the voltage threshold detected by the Power Voltage Detector
643 * @rmtoll CR2 PLS LL_PWR_SetPVDLevel
644 * @param PVDLevel This parameter can be one of the following values:
645 * @arg @ref LL_PWR_PVDLEVEL_0
646 * @arg @ref LL_PWR_PVDLEVEL_1
647 * @arg @ref LL_PWR_PVDLEVEL_2
648 * @arg @ref LL_PWR_PVDLEVEL_3
649 * @arg @ref LL_PWR_PVDLEVEL_4
650 * @arg @ref LL_PWR_PVDLEVEL_5
651 * @arg @ref LL_PWR_PVDLEVEL_6
652 * @arg @ref LL_PWR_PVDLEVEL_7
653 * @retval None
654 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)655 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
656 {
657 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
658 }
659
660 /**
661 * @brief Get the voltage threshold detection
662 * @rmtoll CR2 PLS LL_PWR_GetPVDLevel
663 * @retval Returned value can be one of the following values:
664 * @arg @ref LL_PWR_PVDLEVEL_0
665 * @arg @ref LL_PWR_PVDLEVEL_1
666 * @arg @ref LL_PWR_PVDLEVEL_2
667 * @arg @ref LL_PWR_PVDLEVEL_3
668 * @arg @ref LL_PWR_PVDLEVEL_4
669 * @arg @ref LL_PWR_PVDLEVEL_5
670 * @arg @ref LL_PWR_PVDLEVEL_6
671 * @arg @ref LL_PWR_PVDLEVEL_7
672 */
LL_PWR_GetPVDLevel(void)673 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
674 {
675 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
676 }
677
678 /**
679 * @brief Enable Power Voltage Detector
680 * @rmtoll CR2 PVDE LL_PWR_EnablePVD
681 * @retval None
682 */
LL_PWR_EnablePVD(void)683 __STATIC_INLINE void LL_PWR_EnablePVD(void)
684 {
685 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
686 }
687
688 /**
689 * @brief Disable Power Voltage Detector
690 * @rmtoll CR2 PVDE LL_PWR_DisablePVD
691 * @retval None
692 */
LL_PWR_DisablePVD(void)693 __STATIC_INLINE void LL_PWR_DisablePVD(void)
694 {
695 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
696 }
697
698 /**
699 * @brief Check if Power Voltage Detector is enabled
700 * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD
701 * @retval State of bit (1 or 0).
702 */
LL_PWR_IsEnabledPVD(void)703 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
704 {
705 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL);
706 }
707
708 /**
709 * @brief Enable Internal Wake-up line
710 * @rmtoll CR3 EIWF LL_PWR_EnableInternWU
711 * @retval None
712 */
LL_PWR_EnableInternWU(void)713 __STATIC_INLINE void LL_PWR_EnableInternWU(void)
714 {
715 SET_BIT(PWR->CR3, PWR_CR3_EIWF);
716 }
717
718 /**
719 * @brief Disable Internal Wake-up line
720 * @rmtoll CR3 EIWF LL_PWR_DisableInternWU
721 * @retval None
722 */
LL_PWR_DisableInternWU(void)723 __STATIC_INLINE void LL_PWR_DisableInternWU(void)
724 {
725 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
726 }
727
728 /**
729 * @brief Check if Internal Wake-up line is enabled
730 * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU
731 * @retval State of bit (1 or 0).
732 */
LL_PWR_IsEnabledInternWU(void)733 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
734 {
735 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF)) ? 1UL : 0UL);
736 }
737
738 /**
739 * @brief Enable pull-up and pull-down configuration
740 * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg
741 * @retval None
742 */
LL_PWR_EnablePUPDCfg(void)743 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
744 {
745 SET_BIT(PWR->CR3, PWR_CR3_APC);
746 }
747
748 /**
749 * @brief Disable pull-up and pull-down configuration
750 * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg
751 * @retval None
752 */
LL_PWR_DisablePUPDCfg(void)753 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
754 {
755 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
756 }
757
758 /**
759 * @brief Check if pull-up and pull-down configuration is enabled
760 * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg
761 * @retval State of bit (1 or 0).
762 */
LL_PWR_IsEnabledPUPDCfg(void)763 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
764 {
765 return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL);
766 }
767
768 #if defined(PWR_CR3_DSIPDEN)
769 /**
770 * @brief Enable pull-down activation on DSI pins
771 * @rmtoll CR3 DSIPDEN LL_PWR_EnableDSIPullDown
772 * @retval None
773 */
LL_PWR_EnableDSIPullDown(void)774 __STATIC_INLINE void LL_PWR_EnableDSIPullDown(void)
775 {
776 SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN);
777 }
778
779 /**
780 * @brief Disable pull-down activation on DSI pins
781 * @rmtoll CR3 DSIPDEN LL_PWR_DisableDSIPullDown
782 * @retval None
783 */
LL_PWR_DisableDSIPullDown(void)784 __STATIC_INLINE void LL_PWR_DisableDSIPullDown(void)
785 {
786 CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN);
787 }
788
789 /**
790 * @brief Check if pull-down activation on DSI pins is enabled
791 * @rmtoll CR3 DSIPDEN LL_PWR_IsEnabledDSIPullDown
792 * @retval State of bit (1 or 0).
793 */
LL_PWR_IsEnabledDSIPullDown(void)794 __STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPullDown(void)
795 {
796 return ((READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)) ? 1UL : 0UL);
797 }
798 #endif /* PWR_CR3_DSIPDEN */
799
800 #if defined(PWR_CR3_ENULP)
801 /**
802 * @brief Enable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes
803 * @rmtoll CR3 ENULP LL_PWR_EnableBORPVD_ULP
804 * @retval None
805 */
LL_PWR_EnableBORPVD_ULP(void)806 __STATIC_INLINE void LL_PWR_EnableBORPVD_ULP(void)
807 {
808 SET_BIT(PWR->CR3, PWR_CR3_ENULP);
809 }
810
811 /**
812 * @brief Disable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes
813 * @rmtoll CR3 ENULP LL_PWR_DisableBORPVD_ULP
814 * @retval None
815 */
LL_PWR_DisableBORPVD_ULP(void)816 __STATIC_INLINE void LL_PWR_DisableBORPVD_ULP(void)
817 {
818 CLEAR_BIT(PWR->CR3, PWR_CR3_ENULP);
819 }
820
821 /**
822 * @brief Check if Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes is enabled
823 * @rmtoll CR3 ENULP LL_PWR_IsEnabledBORPVD_ULP
824 * @retval State of bit (1 or 0).
825 */
LL_PWR_IsEnabledBORPVD_ULP(void)826 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBORPVD_ULP(void)
827 {
828 return ((READ_BIT(PWR->CR3, PWR_CR3_ENULP) == (PWR_CR3_ENULP)) ? 1UL : 0UL);
829 }
830 #endif /* PWR_CR3_ENULP */
831
832 /**
833 * @brief Enable SRAM2 full content retention in Standby mode
834 * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention
835 * @retval None
836 */
LL_PWR_EnableSRAM2Retention(void)837 __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void)
838 {
839 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, LL_PWR_FULL_SRAM2_RETENTION);
840 }
841
842 /**
843 * @brief Disable SRAM2 content retention in Standby mode
844 * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention
845 * @retval None
846 */
LL_PWR_DisableSRAM2Retention(void)847 __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void)
848 {
849 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
850 }
851
852 /**
853 * @brief Check if SRAM2 full content retention in Standby mode is enabled
854 * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention
855 * @retval State of bit (1 or 0).
856 */
LL_PWR_IsEnabledSRAM2Retention(void)857 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void)
858 {
859 return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (LL_PWR_FULL_SRAM2_RETENTION)) ? 1UL : 0UL);
860 }
861
862 /**
863 * @brief Set SRAM2 content retention in Standby mode
864 * @rmtoll CR3 RRS LL_PWR_SetSRAM2ContentRetention
865 * @param SRAM2Size This parameter can be one of the following values:
866 * @arg @ref LL_PWR_NO_SRAM2_RETENTION
867 * @arg @ref LL_PWR_FULL_SRAM2_RETENTION
868 * @arg @ref LL_PWR_4KBYTES_SRAM2_RETENTION
869 * @note LL_PWR_4KBYTES_SRAM2_RETENTION parameter is not available on all devices
870 * @note Setting LL_PWR_NO_SRAM2_RETENTION is same as calling LL_PWR_DisableSRAM2Retention()
871 * @note Setting LL_PWR_FULL_SRAM2_RETENTION is same as calling LL_PWR_EnableSRAM2Retention()
872 * @retval None
873 */
LL_PWR_SetSRAM2ContentRetention(uint32_t SRAM2Size)874 __STATIC_INLINE void LL_PWR_SetSRAM2ContentRetention(uint32_t SRAM2Size)
875 {
876 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, SRAM2Size);
877 }
878
879 /**
880 * @brief Get SRAM2 content retention in Standby mode
881 * @rmtoll CR3 RRS LL_PWR_GetSRAM2ContentRetention
882 * @retval Returned value can be one of the following values:
883 * @arg @ref LL_PWR_NO_SRAM2_RETENTION
884 * @arg @ref LL_PWR_FULL_SRAM2_RETENTION
885 * @arg @ref LL_PWR_4KBYTES_SRAM2_RETENTION
886 * @note LL_PWR_4KBYTES_SRAM2_RETENTION parameter is not available on all devices
887 */
LL_PWR_GetSRAM2ContentRetention(void)888 __STATIC_INLINE uint32_t LL_PWR_GetSRAM2ContentRetention(void)
889 {
890 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_RRS));
891 }
892
893 /**
894 * @brief Enable the WakeUp PINx functionality
895 * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
896 * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n
897 * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n
898 * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n
899 * CR3 EWUP5 LL_PWR_EnableWakeUpPin\n
900 * @param WakeUpPin This parameter can be one of the following values:
901 * @arg @ref LL_PWR_WAKEUP_PIN1
902 * @arg @ref LL_PWR_WAKEUP_PIN2
903 * @arg @ref LL_PWR_WAKEUP_PIN3
904 * @arg @ref LL_PWR_WAKEUP_PIN4
905 * @arg @ref LL_PWR_WAKEUP_PIN5
906 * @retval None
907 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)908 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
909 {
910 SET_BIT(PWR->CR3, WakeUpPin);
911 }
912
913 /**
914 * @brief Disable the WakeUp PINx functionality
915 * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n
916 * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n
917 * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n
918 * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n
919 * CR3 EWUP5 LL_PWR_DisableWakeUpPin\n
920 * @param WakeUpPin This parameter can be one of the following values:
921 * @arg @ref LL_PWR_WAKEUP_PIN1
922 * @arg @ref LL_PWR_WAKEUP_PIN2
923 * @arg @ref LL_PWR_WAKEUP_PIN3
924 * @arg @ref LL_PWR_WAKEUP_PIN4
925 * @arg @ref LL_PWR_WAKEUP_PIN5
926 * @retval None
927 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)928 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
929 {
930 CLEAR_BIT(PWR->CR3, WakeUpPin);
931 }
932
933 /**
934 * @brief Check if the WakeUp PINx functionality is enabled
935 * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
936 * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
937 * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n
938 * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n
939 * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n
940 * @param WakeUpPin This parameter can be one of the following values:
941 * @arg @ref LL_PWR_WAKEUP_PIN1
942 * @arg @ref LL_PWR_WAKEUP_PIN2
943 * @arg @ref LL_PWR_WAKEUP_PIN3
944 * @arg @ref LL_PWR_WAKEUP_PIN4
945 * @arg @ref LL_PWR_WAKEUP_PIN5
946 * @retval State of bit (1 or 0).
947 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)948 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
949 {
950 return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
951 }
952
953 #if defined(PWR_CR4_EXT_SMPS_ON)
954 /**
955 * @brief Enable the CFLDO working @ 0.95V
956 * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the
957 * internal CFLDO can be reduced to 0.95V.
958 * @rmtoll CR4 EXT_SMPS_ON LL_PWR_EnableExtSMPS_0V95
959 * @retval None
960 */
LL_PWR_EnableExtSMPS_0V95(void)961 __STATIC_INLINE void LL_PWR_EnableExtSMPS_0V95(void)
962 {
963 SET_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON);
964 }
965
966 /**
967 * @brief Disable the CFLDO working @ 0.95V
968 * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the
969 * internal CFLDO can be reduced to 0.95V.
970 * @rmtoll CR4 EXT_SMPS_ON LL_PWR_DisableExtSMPS_0V95
971 * @retval None
972 */
LL_PWR_DisableExtSMPS_0V95(void)973 __STATIC_INLINE void LL_PWR_DisableExtSMPS_0V95(void)
974 {
975 CLEAR_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON);
976 }
977
978 /**
979 * @brief Check if CFLDO is working @ 0.95V
980 * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the
981 * internal CFLDO can be reduced to 0.95V.
982 * @rmtoll CR4 EXT_SMPS_ON LL_PWR_IsEnabledExtSMPS_0V95
983 * @retval State of bit (1 or 0).
984 */
LL_PWR_IsEnabledExtSMPS_0V95(void)985 __STATIC_INLINE uint32_t LL_PWR_IsEnabledExtSMPS_0V95(void)
986 {
987 return ((READ_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON) == (PWR_CR4_EXT_SMPS_ON)) ? 1UL : 0UL);
988 }
989 #endif /* PWR_CR4_EXT_SMPS_ON */
990
991 /**
992 * @brief Set the resistor impedance
993 * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor
994 * @param Resistor This parameter can be one of the following values:
995 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
996 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
997 * @retval None
998 */
LL_PWR_SetBattChargResistor(uint32_t Resistor)999 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
1000 {
1001 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
1002 }
1003
1004 /**
1005 * @brief Get the resistor impedance
1006 * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor
1007 * @retval Returned value can be one of the following values:
1008 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
1009 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
1010 */
LL_PWR_GetBattChargResistor(void)1011 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
1012 {
1013 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
1014 }
1015
1016 /**
1017 * @brief Enable battery charging
1018 * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging
1019 * @retval None
1020 */
LL_PWR_EnableBatteryCharging(void)1021 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
1022 {
1023 SET_BIT(PWR->CR4, PWR_CR4_VBE);
1024 }
1025
1026 /**
1027 * @brief Disable battery charging
1028 * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging
1029 * @retval None
1030 */
LL_PWR_DisableBatteryCharging(void)1031 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
1032 {
1033 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
1034 }
1035
1036 /**
1037 * @brief Check if battery charging is enabled
1038 * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging
1039 * @retval State of bit (1 or 0).
1040 */
LL_PWR_IsEnabledBatteryCharging(void)1041 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
1042 {
1043 return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL);
1044 }
1045
1046 /**
1047 * @brief Set the Wake-Up pin polarity low for the event detection
1048 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n
1049 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n
1050 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n
1051 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n
1052 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow
1053 * @param WakeUpPin This parameter can be one of the following values:
1054 * @arg @ref LL_PWR_WAKEUP_PIN1
1055 * @arg @ref LL_PWR_WAKEUP_PIN2
1056 * @arg @ref LL_PWR_WAKEUP_PIN3
1057 * @arg @ref LL_PWR_WAKEUP_PIN4
1058 * @arg @ref LL_PWR_WAKEUP_PIN5
1059 * @retval None
1060 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)1061 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
1062 {
1063 SET_BIT(PWR->CR4, WakeUpPin);
1064 }
1065
1066 /**
1067 * @brief Set the Wake-Up pin polarity high for the event detection
1068 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n
1069 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n
1070 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n
1071 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n
1072 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh
1073 * @param WakeUpPin This parameter can be one of the following values:
1074 * @arg @ref LL_PWR_WAKEUP_PIN1
1075 * @arg @ref LL_PWR_WAKEUP_PIN2
1076 * @arg @ref LL_PWR_WAKEUP_PIN3
1077 * @arg @ref LL_PWR_WAKEUP_PIN4
1078 * @arg @ref LL_PWR_WAKEUP_PIN5
1079 * @retval None
1080 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)1081 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
1082 {
1083 CLEAR_BIT(PWR->CR4, WakeUpPin);
1084 }
1085
1086 /**
1087 * @brief Get the Wake-Up pin polarity for the event detection
1088 * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n
1089 * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n
1090 * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n
1091 * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n
1092 * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow
1093 * @param WakeUpPin This parameter can be one of the following values:
1094 * @arg @ref LL_PWR_WAKEUP_PIN1
1095 * @arg @ref LL_PWR_WAKEUP_PIN2
1096 * @arg @ref LL_PWR_WAKEUP_PIN3
1097 * @arg @ref LL_PWR_WAKEUP_PIN4
1098 * @arg @ref LL_PWR_WAKEUP_PIN5
1099 * @retval State of bit (1 or 0).
1100 */
LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)1101 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
1102 {
1103 return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
1104 }
1105
1106 /**
1107 * @brief Enable GPIO pull-up state in Standby and Shutdown modes
1108 * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n
1109 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
1110 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
1111 * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n
1112 * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n
1113 * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp\n
1114 * PUCRG PU0-15 LL_PWR_EnableGPIOPullUp\n
1115 * PUCRH PU0-15 LL_PWR_EnableGPIOPullUp\n
1116 * PUCRI PU0-11 LL_PWR_EnableGPIOPullUp
1117 * @param GPIO This parameter can be one of the following values:
1118 * @arg @ref LL_PWR_GPIO_A
1119 * @arg @ref LL_PWR_GPIO_B
1120 * @arg @ref LL_PWR_GPIO_C
1121 * @arg @ref LL_PWR_GPIO_D
1122 * @arg @ref LL_PWR_GPIO_E
1123 * @arg @ref LL_PWR_GPIO_F (*)
1124 * @arg @ref LL_PWR_GPIO_G (*)
1125 * @arg @ref LL_PWR_GPIO_H
1126 * @arg @ref LL_PWR_GPIO_I (*)
1127 *
1128 * (*) value not defined in all devices
1129 * @param GPIONumber This parameter can be one of the following values:
1130 * @arg @ref LL_PWR_GPIO_BIT_0
1131 * @arg @ref LL_PWR_GPIO_BIT_1
1132 * @arg @ref LL_PWR_GPIO_BIT_2
1133 * @arg @ref LL_PWR_GPIO_BIT_3
1134 * @arg @ref LL_PWR_GPIO_BIT_4
1135 * @arg @ref LL_PWR_GPIO_BIT_5
1136 * @arg @ref LL_PWR_GPIO_BIT_6
1137 * @arg @ref LL_PWR_GPIO_BIT_7
1138 * @arg @ref LL_PWR_GPIO_BIT_8
1139 * @arg @ref LL_PWR_GPIO_BIT_9
1140 * @arg @ref LL_PWR_GPIO_BIT_10
1141 * @arg @ref LL_PWR_GPIO_BIT_11
1142 * @arg @ref LL_PWR_GPIO_BIT_12
1143 * @arg @ref LL_PWR_GPIO_BIT_13
1144 * @arg @ref LL_PWR_GPIO_BIT_14
1145 * @arg @ref LL_PWR_GPIO_BIT_15
1146 * @retval None
1147 */
LL_PWR_EnableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1148 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1149 {
1150 SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1151 }
1152
1153 /**
1154 * @brief Disable GPIO pull-up state in Standby and Shutdown modes
1155 * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n
1156 * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n
1157 * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n
1158 * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n
1159 * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n
1160 * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp\n
1161 * PUCRG PU0-15 LL_PWR_DisableGPIOPullUp\n
1162 * PUCRH PU0-15 LL_PWR_DisableGPIOPullUp\n
1163 * PUCRI PU0-11 LL_PWR_DisableGPIOPullUp
1164 * @param GPIO This parameter can be one of the following values:
1165 * @arg @ref LL_PWR_GPIO_A
1166 * @arg @ref LL_PWR_GPIO_B
1167 * @arg @ref LL_PWR_GPIO_C
1168 * @arg @ref LL_PWR_GPIO_D
1169 * @arg @ref LL_PWR_GPIO_E
1170 * @arg @ref LL_PWR_GPIO_F (*)
1171 * @arg @ref LL_PWR_GPIO_G (*)
1172 * @arg @ref LL_PWR_GPIO_H
1173 * @arg @ref LL_PWR_GPIO_I (*)
1174 *
1175 * (*) value not defined in all devices
1176 * @param GPIONumber This parameter can be one of the following values:
1177 * @arg @ref LL_PWR_GPIO_BIT_0
1178 * @arg @ref LL_PWR_GPIO_BIT_1
1179 * @arg @ref LL_PWR_GPIO_BIT_2
1180 * @arg @ref LL_PWR_GPIO_BIT_3
1181 * @arg @ref LL_PWR_GPIO_BIT_4
1182 * @arg @ref LL_PWR_GPIO_BIT_5
1183 * @arg @ref LL_PWR_GPIO_BIT_6
1184 * @arg @ref LL_PWR_GPIO_BIT_7
1185 * @arg @ref LL_PWR_GPIO_BIT_8
1186 * @arg @ref LL_PWR_GPIO_BIT_9
1187 * @arg @ref LL_PWR_GPIO_BIT_10
1188 * @arg @ref LL_PWR_GPIO_BIT_11
1189 * @arg @ref LL_PWR_GPIO_BIT_12
1190 * @arg @ref LL_PWR_GPIO_BIT_13
1191 * @arg @ref LL_PWR_GPIO_BIT_14
1192 * @arg @ref LL_PWR_GPIO_BIT_15
1193 * @retval None
1194 */
LL_PWR_DisableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1195 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1196 {
1197 CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1198 }
1199
1200 /**
1201 * @brief Check if GPIO pull-up state is enabled
1202 * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1203 * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1204 * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1205 * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1206 * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1207 * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1208 * PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1209 * PUCRH PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1210 * PUCRI PU0-11 LL_PWR_IsEnabledGPIOPullUp
1211 * @param GPIO This parameter can be one of the following values:
1212 * @arg @ref LL_PWR_GPIO_A
1213 * @arg @ref LL_PWR_GPIO_B
1214 * @arg @ref LL_PWR_GPIO_C
1215 * @arg @ref LL_PWR_GPIO_D
1216 * @arg @ref LL_PWR_GPIO_E
1217 * @arg @ref LL_PWR_GPIO_F (*)
1218 * @arg @ref LL_PWR_GPIO_G (*)
1219 * @arg @ref LL_PWR_GPIO_H
1220 * @arg @ref LL_PWR_GPIO_I (*)
1221 *
1222 * (*) value not defined in all devices
1223 * @param GPIONumber This parameter can be one of the following values:
1224 * @arg @ref LL_PWR_GPIO_BIT_0
1225 * @arg @ref LL_PWR_GPIO_BIT_1
1226 * @arg @ref LL_PWR_GPIO_BIT_2
1227 * @arg @ref LL_PWR_GPIO_BIT_3
1228 * @arg @ref LL_PWR_GPIO_BIT_4
1229 * @arg @ref LL_PWR_GPIO_BIT_5
1230 * @arg @ref LL_PWR_GPIO_BIT_6
1231 * @arg @ref LL_PWR_GPIO_BIT_7
1232 * @arg @ref LL_PWR_GPIO_BIT_8
1233 * @arg @ref LL_PWR_GPIO_BIT_9
1234 * @arg @ref LL_PWR_GPIO_BIT_10
1235 * @arg @ref LL_PWR_GPIO_BIT_11
1236 * @arg @ref LL_PWR_GPIO_BIT_12
1237 * @arg @ref LL_PWR_GPIO_BIT_13
1238 * @arg @ref LL_PWR_GPIO_BIT_14
1239 * @arg @ref LL_PWR_GPIO_BIT_15
1240 * @retval State of bit (1 or 0).
1241 */
LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1242 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1243 {
1244 return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1245 }
1246
1247 /**
1248 * @brief Enable GPIO pull-down state in Standby and Shutdown modes
1249 * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n
1250 * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n
1251 * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n
1252 * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n
1253 * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n
1254 * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown\n
1255 * PDCRG PD0-15 LL_PWR_EnableGPIOPullDown\n
1256 * PDCRH PD0-15 LL_PWR_EnableGPIOPullDown\n
1257 * PDCRI PD0-11 LL_PWR_EnableGPIOPullDown
1258 * @param GPIO This parameter can be one of the following values:
1259 * @arg @ref LL_PWR_GPIO_A
1260 * @arg @ref LL_PWR_GPIO_B
1261 * @arg @ref LL_PWR_GPIO_C
1262 * @arg @ref LL_PWR_GPIO_D
1263 * @arg @ref LL_PWR_GPIO_E
1264 * @arg @ref LL_PWR_GPIO_F (*)
1265 * @arg @ref LL_PWR_GPIO_G (*)
1266 * @arg @ref LL_PWR_GPIO_H
1267 * @arg @ref LL_PWR_GPIO_I (*)
1268 *
1269 * (*) value not defined in all devices
1270 * @param GPIONumber This parameter can be one of the following values:
1271 * @arg @ref LL_PWR_GPIO_BIT_0
1272 * @arg @ref LL_PWR_GPIO_BIT_1
1273 * @arg @ref LL_PWR_GPIO_BIT_2
1274 * @arg @ref LL_PWR_GPIO_BIT_3
1275 * @arg @ref LL_PWR_GPIO_BIT_4
1276 * @arg @ref LL_PWR_GPIO_BIT_5
1277 * @arg @ref LL_PWR_GPIO_BIT_6
1278 * @arg @ref LL_PWR_GPIO_BIT_7
1279 * @arg @ref LL_PWR_GPIO_BIT_8
1280 * @arg @ref LL_PWR_GPIO_BIT_9
1281 * @arg @ref LL_PWR_GPIO_BIT_10
1282 * @arg @ref LL_PWR_GPIO_BIT_11
1283 * @arg @ref LL_PWR_GPIO_BIT_12
1284 * @arg @ref LL_PWR_GPIO_BIT_13
1285 * @arg @ref LL_PWR_GPIO_BIT_14
1286 * @arg @ref LL_PWR_GPIO_BIT_15
1287 * @retval None
1288 */
LL_PWR_EnableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1289 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1290 {
1291 SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
1292 }
1293
1294 /**
1295 * @brief Disable GPIO pull-down state in Standby and Shutdown modes
1296 * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n
1297 * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n
1298 * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n
1299 * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n
1300 * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n
1301 * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown\n
1302 * PDCRG PD0-15 LL_PWR_DisableGPIOPullDown\n
1303 * PDCRH PD0-15 LL_PWR_DisableGPIOPullDown\n
1304 * PDCRI PD0-11 LL_PWR_DisableGPIOPullDown
1305 * @param GPIO This parameter can be one of the following values:
1306 * @arg @ref LL_PWR_GPIO_A
1307 * @arg @ref LL_PWR_GPIO_B
1308 * @arg @ref LL_PWR_GPIO_C
1309 * @arg @ref LL_PWR_GPIO_D
1310 * @arg @ref LL_PWR_GPIO_E
1311 * @arg @ref LL_PWR_GPIO_F (*)
1312 * @arg @ref LL_PWR_GPIO_G (*)
1313 * @arg @ref LL_PWR_GPIO_H
1314 * @arg @ref LL_PWR_GPIO_I (*)
1315 *
1316 * (*) value not defined in all devices
1317 * @param GPIONumber This parameter can be one of the following values:
1318 * @arg @ref LL_PWR_GPIO_BIT_0
1319 * @arg @ref LL_PWR_GPIO_BIT_1
1320 * @arg @ref LL_PWR_GPIO_BIT_2
1321 * @arg @ref LL_PWR_GPIO_BIT_3
1322 * @arg @ref LL_PWR_GPIO_BIT_4
1323 * @arg @ref LL_PWR_GPIO_BIT_5
1324 * @arg @ref LL_PWR_GPIO_BIT_6
1325 * @arg @ref LL_PWR_GPIO_BIT_7
1326 * @arg @ref LL_PWR_GPIO_BIT_8
1327 * @arg @ref LL_PWR_GPIO_BIT_9
1328 * @arg @ref LL_PWR_GPIO_BIT_10
1329 * @arg @ref LL_PWR_GPIO_BIT_11
1330 * @arg @ref LL_PWR_GPIO_BIT_12
1331 * @arg @ref LL_PWR_GPIO_BIT_13
1332 * @arg @ref LL_PWR_GPIO_BIT_14
1333 * @arg @ref LL_PWR_GPIO_BIT_15
1334 * @retval None
1335 */
LL_PWR_DisableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1336 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1337 {
1338 CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
1339 }
1340
1341 /**
1342 * @brief Check if GPIO pull-down state is enabled
1343 * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1344 * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1345 * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1346 * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1347 * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1348 * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1349 * PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1350 * PDCRH PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1351 * PDCRI PD0-11 LL_PWR_IsEnabledGPIOPullDown
1352 * @param GPIO This parameter can be one of the following values:
1353 * @arg @ref LL_PWR_GPIO_A
1354 * @arg @ref LL_PWR_GPIO_B
1355 * @arg @ref LL_PWR_GPIO_C
1356 * @arg @ref LL_PWR_GPIO_D
1357 * @arg @ref LL_PWR_GPIO_E
1358 * @arg @ref LL_PWR_GPIO_F (*)
1359 * @arg @ref LL_PWR_GPIO_G (*)
1360 * @arg @ref LL_PWR_GPIO_H
1361 * @arg @ref LL_PWR_GPIO_I (*)
1362 *
1363 * (*) value not defined in all devices
1364 * @param GPIONumber This parameter can be one of the following values:
1365 * @arg @ref LL_PWR_GPIO_BIT_0
1366 * @arg @ref LL_PWR_GPIO_BIT_1
1367 * @arg @ref LL_PWR_GPIO_BIT_2
1368 * @arg @ref LL_PWR_GPIO_BIT_3
1369 * @arg @ref LL_PWR_GPIO_BIT_4
1370 * @arg @ref LL_PWR_GPIO_BIT_5
1371 * @arg @ref LL_PWR_GPIO_BIT_6
1372 * @arg @ref LL_PWR_GPIO_BIT_7
1373 * @arg @ref LL_PWR_GPIO_BIT_8
1374 * @arg @ref LL_PWR_GPIO_BIT_9
1375 * @arg @ref LL_PWR_GPIO_BIT_10
1376 * @arg @ref LL_PWR_GPIO_BIT_11
1377 * @arg @ref LL_PWR_GPIO_BIT_12
1378 * @arg @ref LL_PWR_GPIO_BIT_13
1379 * @arg @ref LL_PWR_GPIO_BIT_14
1380 * @arg @ref LL_PWR_GPIO_BIT_15
1381 * @retval State of bit (1 or 0).
1382 */
LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1383 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1384 {
1385 return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1386 }
1387
1388 /**
1389 * @}
1390 */
1391
1392 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1393 * @{
1394 */
1395
1396 /**
1397 * @brief Get Internal Wake-up line Flag
1398 * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU
1399 * @retval State of bit (1 or 0).
1400 */
LL_PWR_IsActiveFlag_InternWU(void)1401 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
1402 {
1403 return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL);
1404 }
1405
1406 #if defined(PWR_SR1_EXT_SMPS_RDY)
1407 /**
1408 * @brief Get Ready Flag for switching to external SMPS
1409 * @rmtoll SR1 EXT_SMPS_RDY LL_PWR_IsActiveFlag_ExtSMPSReady
1410 * @retval State of bit (1 or 0).
1411 */
LL_PWR_IsActiveFlag_ExtSMPSReady(void)1412 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ExtSMPSReady(void)
1413 {
1414 return ((READ_BIT(PWR->SR1, PWR_SR1_EXT_SMPS_RDY) == (PWR_SR1_EXT_SMPS_RDY)) ? 1UL : 0UL);
1415 }
1416 #endif /* PWR_SR1_EXT_SMPS_RDY */
1417
1418 /**
1419 * @brief Get Stand-By Flag
1420 * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB
1421 * @retval State of bit (1 or 0).
1422 */
LL_PWR_IsActiveFlag_SB(void)1423 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
1424 {
1425 return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL);
1426 }
1427
1428 /**
1429 * @brief Get Wake-up Flag 5
1430 * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5
1431 * @retval State of bit (1 or 0).
1432 */
LL_PWR_IsActiveFlag_WU5(void)1433 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
1434 {
1435 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL);
1436 }
1437
1438 /**
1439 * @brief Get Wake-up Flag 4
1440 * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4
1441 * @retval State of bit (1 or 0).
1442 */
LL_PWR_IsActiveFlag_WU4(void)1443 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
1444 {
1445 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL);
1446 }
1447
1448 /**
1449 * @brief Get Wake-up Flag 3
1450 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
1451 * @retval State of bit (1 or 0).
1452 */
LL_PWR_IsActiveFlag_WU3(void)1453 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1454 {
1455 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL);
1456 }
1457
1458 /**
1459 * @brief Get Wake-up Flag 2
1460 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
1461 * @retval State of bit (1 or 0).
1462 */
LL_PWR_IsActiveFlag_WU2(void)1463 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1464 {
1465 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL);
1466 }
1467
1468 /**
1469 * @brief Get Wake-up Flag 1
1470 * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
1471 * @retval State of bit (1 or 0).
1472 */
LL_PWR_IsActiveFlag_WU1(void)1473 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1474 {
1475 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL);
1476 }
1477
1478 /**
1479 * @brief Clear Stand-By Flag
1480 * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB
1481 * @retval None
1482 */
LL_PWR_ClearFlag_SB(void)1483 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
1484 {
1485 WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
1486 }
1487
1488 /**
1489 * @brief Clear Wake-up Flags
1490 * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU
1491 * @retval None
1492 */
LL_PWR_ClearFlag_WU(void)1493 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
1494 {
1495 WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
1496 }
1497
1498 /**
1499 * @brief Clear Wake-up Flag 5
1500 * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5
1501 * @retval None
1502 */
LL_PWR_ClearFlag_WU5(void)1503 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
1504 {
1505 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
1506 }
1507
1508 /**
1509 * @brief Clear Wake-up Flag 4
1510 * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4
1511 * @retval None
1512 */
LL_PWR_ClearFlag_WU4(void)1513 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
1514 {
1515 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
1516 }
1517
1518 /**
1519 * @brief Clear Wake-up Flag 3
1520 * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3
1521 * @retval None
1522 */
LL_PWR_ClearFlag_WU3(void)1523 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
1524 {
1525 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
1526 }
1527
1528 /**
1529 * @brief Clear Wake-up Flag 2
1530 * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2
1531 * @retval None
1532 */
LL_PWR_ClearFlag_WU2(void)1533 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
1534 {
1535 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
1536 }
1537
1538 /**
1539 * @brief Clear Wake-up Flag 1
1540 * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1
1541 * @retval None
1542 */
LL_PWR_ClearFlag_WU1(void)1543 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
1544 {
1545 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
1546 }
1547
1548 /**
1549 * @brief Indicate whether VDDA voltage is below or above PVM4 threshold
1550 * @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4
1551 * @retval State of bit (1 or 0).
1552 */
LL_PWR_IsActiveFlag_PVMO4(void)1553 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void)
1554 {
1555 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4)) ? 1UL : 0UL);
1556 }
1557
1558 /**
1559 * @brief Indicate whether VDDA voltage is below or above PVM3 threshold
1560 * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3
1561 * @retval State of bit (1 or 0).
1562 */
LL_PWR_IsActiveFlag_PVMO3(void)1563 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void)
1564 {
1565 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)) ? 1UL : 0UL);
1566 }
1567
1568 #if defined(PWR_SR2_PVMO2)
1569 /**
1570 * @brief Indicate whether VDDIO2 voltage is below or above PVM2 threshold
1571 * @rmtoll SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2
1572 * @retval State of bit (1 or 0).
1573 */
LL_PWR_IsActiveFlag_PVMO2(void)1574 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void)
1575 {
1576 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO2) == (PWR_SR2_PVMO2)) ? 1UL : 0UL);
1577 }
1578 #endif /* PWR_SR2_PVMO2 */
1579
1580 #if defined(PWR_SR2_PVMO1)
1581 /**
1582 * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold
1583 * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1
1584 * @retval State of bit (1 or 0).
1585 */
LL_PWR_IsActiveFlag_PVMO1(void)1586 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void)
1587 {
1588 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)) ? 1UL : 0UL);
1589 }
1590 #endif /* PWR_SR2_PVMO1 */
1591
1592 /**
1593 * @brief Indicate whether VDD voltage is below or above the selected PVD threshold
1594 * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO
1595 * @retval State of bit (1 or 0).
1596 */
LL_PWR_IsActiveFlag_PVDO(void)1597 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
1598 {
1599 return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL);
1600 }
1601
1602 /**
1603 * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
1604 * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS
1605 * @retval State of bit (1 or 0).
1606 */
LL_PWR_IsActiveFlag_VOS(void)1607 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
1608 {
1609 return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL);
1610 }
1611
1612 /**
1613 * @brief Indicate whether the regulator is ready in main mode or is in low-power mode
1614 * @note Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
1615 * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
1616 * @retval State of bit (1 or 0).
1617 */
LL_PWR_IsActiveFlag_REGLPF(void)1618 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
1619 {
1620 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL);
1621 }
1622
1623 /**
1624 * @brief Indicate whether or not the low-power regulator is ready
1625 * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
1626 * @retval State of bit (1 or 0).
1627 */
LL_PWR_IsActiveFlag_REGLPS(void)1628 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
1629 {
1630 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL);
1631 }
1632
1633 /**
1634 * @}
1635 */
1636
1637 #if defined(USE_FULL_LL_DRIVER)
1638 /** @defgroup PWR_LL_EF_Init De-initialization function
1639 * @{
1640 */
1641 ErrorStatus LL_PWR_DeInit(void);
1642 /**
1643 * @}
1644 */
1645 #endif /* USE_FULL_LL_DRIVER */
1646
1647 /** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name
1648 * @{
1649 */
1650 /* Old functions name kept for legacy purpose, to be replaced by the */
1651 /* current functions name. */
1652 #define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS
1653 /**
1654 * @}
1655 */
1656
1657 /**
1658 * @}
1659 */
1660
1661 /**
1662 * @}
1663 */
1664
1665 #endif /* defined(PWR) */
1666
1667 /**
1668 * @}
1669 */
1670
1671 #ifdef __cplusplus
1672 }
1673 #endif
1674
1675 #endif /* STM32L4xx_LL_PWR_H */
1676
