1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_lpuart.h
4 * @author MCD Application Team
5 * @brief Header file of LPUART LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L4xx_LL_LPUART_H
21 #define STM32L4xx_LL_LPUART_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l4xx.h"
29
30 /** @addtogroup STM32L4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (LPUART1)
35
36 /** @defgroup LPUART_LL LPUART
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 #if defined(USART_PRESC_PRESCALER)
43 /** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
44 * @{
45 */
46 /* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
47 static const uint16_t LPUART_PRESCALER_TAB[] =
48 {
49 (uint16_t)1,
50 (uint16_t)2,
51 (uint16_t)4,
52 (uint16_t)6,
53 (uint16_t)8,
54 (uint16_t)10,
55 (uint16_t)12,
56 (uint16_t)16,
57 (uint16_t)32,
58 (uint16_t)64,
59 (uint16_t)128,
60 (uint16_t)256
61 };
62 /**
63 * @}
64 */
65 #endif /* USART_PRESC_PRESCALER */
66
67 /* Private constants ---------------------------------------------------------*/
68 /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
69 * @{
70 */
71 /* Defines used in Baud Rate related macros and corresponding register setting computation */
72 #define LPUART_LPUARTDIV_FREQ_MUL 256U
73 #define LPUART_BRR_MASK 0x000FFFFFU
74 #define LPUART_BRR_MIN_VALUE 0x00000300U
75 /**
76 * @}
77 */
78
79
80 /* Private macros ------------------------------------------------------------*/
81 #if defined(USE_FULL_LL_DRIVER)
82 /** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
83 * @{
84 */
85 /**
86 * @}
87 */
88 #endif /*USE_FULL_LL_DRIVER*/
89
90 /* Exported types ------------------------------------------------------------*/
91 #if defined(USE_FULL_LL_DRIVER)
92 /** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
93 * @{
94 */
95
96 /**
97 * @brief LL LPUART Init Structure definition
98 */
99 typedef struct
100 {
101 #if defined(USART_PRESC_PRESCALER)
102 uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
103 This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
104
105 This feature can be modified afterwards using unitary
106 function @ref LL_LPUART_SetPrescaler().*/
107
108 #endif /* USART_PRESC_PRESCALER */
109 uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate.
110
111 This feature can be modified afterwards using unitary
112 function @ref LL_LPUART_SetBaudRate().*/
113
114 uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
115 This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
116
117 This feature can be modified afterwards using unitary
118 function @ref LL_LPUART_SetDataWidth().*/
119
120 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
121 This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
122
123 This feature can be modified afterwards using unitary
124 function @ref LL_LPUART_SetStopBitsLength().*/
125
126 uint32_t Parity; /*!< Specifies the parity mode.
127 This parameter can be a value of @ref LPUART_LL_EC_PARITY.
128
129 This feature can be modified afterwards using unitary
130 function @ref LL_LPUART_SetParity().*/
131
132 uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
133 This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
134
135 This feature can be modified afterwards using unitary
136 function @ref LL_LPUART_SetTransferDirection().*/
137
138 uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
139 This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
140
141 This feature can be modified afterwards using unitary
142 function @ref LL_LPUART_SetHWFlowCtrl().*/
143
144 } LL_LPUART_InitTypeDef;
145
146 /**
147 * @}
148 */
149 #endif /* USE_FULL_LL_DRIVER */
150
151 /* Exported constants --------------------------------------------------------*/
152 /** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
153 * @{
154 */
155
156 /** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
157 * @brief Flags defines which can be used with LL_LPUART_WriteReg function
158 * @{
159 */
160 #define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
161 #define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
162 #define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */
163 #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
164 #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
165 #define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
166 #define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
167 #define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
168 #define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */
169 /**
170 * @}
171 */
172
173 /** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
174 * @brief Flags defines which can be used with LL_LPUART_ReadReg function
175 * @{
176 */
177 #define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
178 #define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
179 #define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
180 #define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
181 #define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
182 #if defined(USART_CR1_FIFOEN)
183 #define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
184 #else
185 #define LL_LPUART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */
186 #endif /* USART_CR1_FIFOEN */
187 #define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
188 #if defined(USART_CR1_FIFOEN)
189 #define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
190 #else
191 #define LL_LPUART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */
192 #endif /* USART_CR1_FIFOEN */
193 #define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
194 #define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
195 #define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
196 #define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
197 #define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
198 #define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
199 #define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
200 #define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
201 #define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
202 #if defined(USART_CR1_FIFOEN)
203 #define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
204 #define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
205 #define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
206 #define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
207 #endif /* USART_CR1_FIFOEN */
208 /**
209 * @}
210 */
211
212 /** @defgroup LPUART_LL_EC_IT IT Defines
213 * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
214 * @{
215 */
216 #define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
217 #if defined(USART_CR1_FIFOEN)
218 #define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
219 interrupt enable */
220 #else
221 #define LL_LPUART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */
222 #endif /* USART_CR1_FIFOEN */
223 #define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
224 #if defined(USART_CR1_FIFOEN)
225 #define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO
226 not full interrupt enable */
227 #else
228 #define LL_LPUART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */
229 #endif /* USART_CR1_FIFOEN */
230 #define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
231 #define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
232 #if defined(USART_CR1_FIFOEN)
233 #define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
234 #define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
235 #endif /* USART_CR1_FIFOEN */
236 #define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
237 #define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
238 #define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
239 #if defined(USART_CR1_FIFOEN)
240 #define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
241 #define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
242 #endif /* USART_CR1_FIFOEN */
243 /**
244 * @}
245 */
246 #if defined(USART_CR1_FIFOEN)
247
248 /** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
249 * @{
250 */
251 #define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */
252 #define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */
253 #define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */
254 #define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */
255 #define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */
256 #define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
257 /**
258 * @}
259 */
260 #endif /* USART_CR1_FIFOEN */
261
262 /** @defgroup LPUART_LL_EC_DIRECTION Direction
263 * @{
264 */
265 #define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
266 #define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
267 #define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
268 #define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
269 /**
270 * @}
271 */
272
273 /** @defgroup LPUART_LL_EC_PARITY Parity Control
274 * @{
275 */
276 #define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
277 #define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
278 #define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
279 /**
280 * @}
281 */
282
283 /** @defgroup LPUART_LL_EC_WAKEUP Wakeup
284 * @{
285 */
286 #define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
287 #define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
288 /**
289 * @}
290 */
291
292 /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
293 * @{
294 */
295 #define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
296 #define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
297 #define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
298 /**
299 * @}
300 */
301 #if defined(USART_PRESC_PRESCALER)
302
303 /** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
304 * @{
305 */
306 #define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
307 #define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
308 #define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
309 #define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\
310 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
311 #define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
312 #define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\
313 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
314 #define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\
315 USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
316 #define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\
317 USART_PRESC_PRESCALER_1 |\
318 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
319 #define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
320 #define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\
321 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
322 #define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
323 USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
324 #define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
325 USART_PRESC_PRESCALER_1 |\
326 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
327 /**
328 * @}
329 */
330 #endif /* USART_PRESC_PRESCALER */
331
332 /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
333 * @{
334 */
335 #define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
336 #define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
337 /**
338 * @}
339 */
340
341 /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
342 * @{
343 */
344 #define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
345 #define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
346 /**
347 * @}
348 */
349
350 /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
351 * @{
352 */
353 #define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
354 #define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
355 /**
356 * @}
357 */
358
359 /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
360 * @{
361 */
362 #define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
363 #define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
364 /**
365 * @}
366 */
367
368 /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
369 * @{
370 */
371 #define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received
372 in positive/direct logic. (1=H, 0=L) */
373 #define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
374 in negative/inverse logic. (1=L, 0=H).
375 The parity bit is also inverted. */
376 /**
377 * @}
378 */
379
380 /** @defgroup LPUART_LL_EC_BITORDER Bit Order
381 * @{
382 */
383 #define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first,
384 following the start bit */
385 #define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
386 following the start bit */
387 /**
388 * @}
389 */
390
391 /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
392 * @{
393 */
394 #define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
395 #define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
396 /**
397 * @}
398 */
399
400 /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
401 * @{
402 */
403 #define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
404 #define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested
405 when there is space in the receive buffer */
406 #define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted
407 when the nCTS input is asserted (tied to 0)*/
408 #define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
409 /**
410 * @}
411 */
412
413 /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
414 * @{
415 */
416 #define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
417 #define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
418 #define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
419 /**
420 * @}
421 */
422
423 /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
424 * @{
425 */
426 #define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
427 #define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
428 /**
429 * @}
430 */
431
432 /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
433 * @{
434 */
435 #define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
436 #define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
437 /**
438 * @}
439 */
440
441 /**
442 * @}
443 */
444
445 /* Exported macro ------------------------------------------------------------*/
446 /** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
447 * @{
448 */
449
450 /** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
451 * @{
452 */
453
454 /**
455 * @brief Write a value in LPUART register
456 * @param __INSTANCE__ LPUART Instance
457 * @param __REG__ Register to be written
458 * @param __VALUE__ Value to be written in the register
459 * @retval None
460 */
461 #define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
462
463 /**
464 * @brief Read a value in LPUART register
465 * @param __INSTANCE__ LPUART Instance
466 * @param __REG__ Register to be read
467 * @retval Register value
468 */
469 #define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
470 /**
471 * @}
472 */
473
474 /** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
475 * @{
476 */
477
478 /**
479 * @brief Compute LPUARTDIV value according to Peripheral Clock and
480 * expected Baud Rate (20-bit value of LPUARTDIV is returned)
481 * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
482 @if USART_PRESC_PRESCALER
483 * @param __PRESCALER__ This parameter can be one of the following values:
484 * @arg @ref LL_LPUART_PRESCALER_DIV1
485 * @arg @ref LL_LPUART_PRESCALER_DIV2
486 * @arg @ref LL_LPUART_PRESCALER_DIV4
487 * @arg @ref LL_LPUART_PRESCALER_DIV6
488 * @arg @ref LL_LPUART_PRESCALER_DIV8
489 * @arg @ref LL_LPUART_PRESCALER_DIV10
490 * @arg @ref LL_LPUART_PRESCALER_DIV12
491 * @arg @ref LL_LPUART_PRESCALER_DIV16
492 * @arg @ref LL_LPUART_PRESCALER_DIV32
493 * @arg @ref LL_LPUART_PRESCALER_DIV64
494 * @arg @ref LL_LPUART_PRESCALER_DIV128
495 * @arg @ref LL_LPUART_PRESCALER_DIV256
496 @endif
497 * @param __BAUDRATE__ Baud Rate value to achieve
498 * @retval LPUARTDIV value to be used for BRR register filling
499 */
500 #if defined(USART_PRESC_PRESCALER)
501 #define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
502 ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
503 * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
504 #else
505 #define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (uint32_t)(((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__))\
506 & LPUART_BRR_MASK)
507 #endif /* USART_PRESC_PRESCALER */
508
509 /**
510 * @}
511 */
512
513 /**
514 * @}
515 */
516
517 /* Exported functions --------------------------------------------------------*/
518 /** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
519 * @{
520 */
521
522 /** @defgroup LPUART_LL_EF_Configuration Configuration functions
523 * @{
524 */
525
526 /**
527 * @brief LPUART Enable
528 * @rmtoll CR1 UE LL_LPUART_Enable
529 * @param LPUARTx LPUART Instance
530 * @retval None
531 */
LL_LPUART_Enable(USART_TypeDef * LPUARTx)532 __STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
533 {
534 SET_BIT(LPUARTx->CR1, USART_CR1_UE);
535 }
536
537 /**
538 * @brief LPUART Disable
539 * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
540 * and current operations are discarded. The configuration of the LPUART is kept, but all the status
541 * flags, in the LPUARTx_ISR are set to their default values.
542 * @note In order to go into low-power mode without generating errors on the line,
543 * the TE bit must be reset before and the software must wait
544 * for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
545 * The DMA requests are also reset when UE = 0 so the DMA channel must
546 * be disabled before resetting the UE bit.
547 * @rmtoll CR1 UE LL_LPUART_Disable
548 * @param LPUARTx LPUART Instance
549 * @retval None
550 */
LL_LPUART_Disable(USART_TypeDef * LPUARTx)551 __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
552 {
553 CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
554 }
555
556 /**
557 * @brief Indicate if LPUART is enabled
558 * @rmtoll CR1 UE LL_LPUART_IsEnabled
559 * @param LPUARTx LPUART Instance
560 * @retval State of bit (1 or 0).
561 */
LL_LPUART_IsEnabled(const USART_TypeDef * LPUARTx)562 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx)
563 {
564 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
565 }
566
567 #if defined(USART_CR1_FIFOEN)
568 /**
569 * @brief FIFO Mode Enable
570 * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO
571 * @param LPUARTx LPUART Instance
572 * @retval None
573 */
LL_LPUART_EnableFIFO(USART_TypeDef * LPUARTx)574 __STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
575 {
576 SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
577 }
578
579 /**
580 * @brief FIFO Mode Disable
581 * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO
582 * @param LPUARTx LPUART Instance
583 * @retval None
584 */
LL_LPUART_DisableFIFO(USART_TypeDef * LPUARTx)585 __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
586 {
587 CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
588 }
589
590 /**
591 * @brief Indicate if FIFO Mode is enabled
592 * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO
593 * @param LPUARTx LPUART Instance
594 * @retval State of bit (1 or 0).
595 */
LL_LPUART_IsEnabledFIFO(const USART_TypeDef * LPUARTx)596 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx)
597 {
598 return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
599 }
600
601 /**
602 * @brief Configure TX FIFO Threshold
603 * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold
604 * @param LPUARTx LPUART Instance
605 * @param Threshold This parameter can be one of the following values:
606 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
607 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
608 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
609 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
610 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
611 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
612 * @retval None
613 */
LL_LPUART_SetTXFIFOThreshold(USART_TypeDef * LPUARTx,uint32_t Threshold)614 __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
615 {
616 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
617 }
618
619 /**
620 * @brief Return TX FIFO Threshold Configuration
621 * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold
622 * @param LPUARTx LPUART Instance
623 * @retval Returned value can be one of the following values:
624 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
625 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
626 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
627 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
628 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
629 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
630 */
LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef * LPUARTx)631 __STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx)
632 {
633 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
634 }
635
636 /**
637 * @brief Configure RX FIFO Threshold
638 * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold
639 * @param LPUARTx LPUART Instance
640 * @param Threshold This parameter can be one of the following values:
641 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
642 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
643 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
644 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
645 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
646 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
647 * @retval None
648 */
LL_LPUART_SetRXFIFOThreshold(USART_TypeDef * LPUARTx,uint32_t Threshold)649 __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
650 {
651 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
652 }
653
654 /**
655 * @brief Return RX FIFO Threshold Configuration
656 * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold
657 * @param LPUARTx LPUART Instance
658 * @retval Returned value can be one of the following values:
659 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
660 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
661 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
662 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
663 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
664 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
665 */
LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef * LPUARTx)666 __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx)
667 {
668 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
669 }
670
671 /**
672 * @brief Configure TX and RX FIFOs Threshold
673 * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n
674 * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold
675 * @param LPUARTx LPUART Instance
676 * @param TXThreshold This parameter can be one of the following values:
677 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
678 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
679 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
680 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
681 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
682 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
683 * @param RXThreshold This parameter can be one of the following values:
684 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
685 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
686 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
687 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
688 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
689 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
690 * @retval None
691 */
LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef * LPUARTx,uint32_t TXThreshold,uint32_t RXThreshold)692 __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
693 {
694 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
695 (RXThreshold << USART_CR3_RXFTCFG_Pos));
696 }
697 #endif /* USART_CR1_FIFOEN */
698
699 /**
700 * @brief LPUART enabled in STOP Mode
701 * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
702 * LPUART clock selection is HSI or LSE in RCC.
703 * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode
704 * @param LPUARTx LPUART Instance
705 * @retval None
706 */
LL_LPUART_EnableInStopMode(USART_TypeDef * LPUARTx)707 __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
708 {
709 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
710 }
711
712 /**
713 * @brief LPUART disabled in STOP Mode
714 * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
715 * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode
716 * @param LPUARTx LPUART Instance
717 * @retval None
718 */
LL_LPUART_DisableInStopMode(USART_TypeDef * LPUARTx)719 __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
720 {
721 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
722 }
723
724 /**
725 * @brief Indicate if LPUART is enabled in STOP Mode
726 * (able to wake up MCU from Stop mode or not)
727 * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode
728 * @param LPUARTx LPUART Instance
729 * @retval State of bit (1 or 0).
730 */
LL_LPUART_IsEnabledInStopMode(const USART_TypeDef * LPUARTx)731 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx)
732 {
733 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
734 }
735
736 #if defined(USART_CR3_UCESM)
737 /**
738 * @brief LPUART Clock enabled in STOP Mode
739 * @note When this function is called, LPUART Clock is enabled while in STOP mode
740 * @rmtoll CR3 UCESM LL_LPUART_EnableClockInStopMode
741 * @param LPUARTx LPUART Instance
742 * @retval None
743 */
LL_LPUART_EnableClockInStopMode(USART_TypeDef * LPUARTx)744 __STATIC_INLINE void LL_LPUART_EnableClockInStopMode(USART_TypeDef *LPUARTx)
745 {
746 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_UCESM);
747 }
748
749 /**
750 * @brief LPUART clock disabled in STOP Mode
751 * @note When this function is called, LPUART Clock is disabled while in STOP mode
752 * @rmtoll CR3 UCESM LL_LPUART_DisableClockInStopMode
753 * @param LPUARTx LPUART Instance
754 * @retval None
755 */
LL_LPUART_DisableClockInStopMode(USART_TypeDef * LPUARTx)756 __STATIC_INLINE void LL_LPUART_DisableClockInStopMode(USART_TypeDef *LPUARTx)
757 {
758 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_UCESM);
759 }
760
761 /**
762 * @brief Indicate if LPUART clock is enabled in STOP Mode
763 * @rmtoll CR3 UCESM LL_LPUART_IsClockEnabledInStopMode
764 * @param LPUARTx LPUART Instance
765 * @retval State of bit (1 or 0).
766 */
LL_LPUART_IsClockEnabledInStopMode(const USART_TypeDef * LPUARTx)767 __STATIC_INLINE uint32_t LL_LPUART_IsClockEnabledInStopMode(const USART_TypeDef *LPUARTx)
768 {
769 return ((READ_BIT(LPUARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)) ? 1UL : 0UL);
770 }
771
772 #endif /* USART_CR3_UCESM */
773 /**
774 * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
775 * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
776 * @param LPUARTx LPUART Instance
777 * @retval None
778 */
LL_LPUART_EnableDirectionRx(USART_TypeDef * LPUARTx)779 __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
780 {
781 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
782 }
783
784 /**
785 * @brief Receiver Disable
786 * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx
787 * @param LPUARTx LPUART Instance
788 * @retval None
789 */
LL_LPUART_DisableDirectionRx(USART_TypeDef * LPUARTx)790 __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
791 {
792 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
793 }
794
795 /**
796 * @brief Transmitter Enable
797 * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx
798 * @param LPUARTx LPUART Instance
799 * @retval None
800 */
LL_LPUART_EnableDirectionTx(USART_TypeDef * LPUARTx)801 __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
802 {
803 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
804 }
805
806 /**
807 * @brief Transmitter Disable
808 * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx
809 * @param LPUARTx LPUART Instance
810 * @retval None
811 */
LL_LPUART_DisableDirectionTx(USART_TypeDef * LPUARTx)812 __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
813 {
814 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
815 }
816
817 /**
818 * @brief Configure simultaneously enabled/disabled states
819 * of Transmitter and Receiver
820 * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n
821 * CR1 TE LL_LPUART_SetTransferDirection
822 * @param LPUARTx LPUART Instance
823 * @param TransferDirection This parameter can be one of the following values:
824 * @arg @ref LL_LPUART_DIRECTION_NONE
825 * @arg @ref LL_LPUART_DIRECTION_RX
826 * @arg @ref LL_LPUART_DIRECTION_TX
827 * @arg @ref LL_LPUART_DIRECTION_TX_RX
828 * @retval None
829 */
LL_LPUART_SetTransferDirection(USART_TypeDef * LPUARTx,uint32_t TransferDirection)830 __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
831 {
832 ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
833 }
834
835 /**
836 * @brief Return enabled/disabled states of Transmitter and Receiver
837 * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n
838 * CR1 TE LL_LPUART_GetTransferDirection
839 * @param LPUARTx LPUART Instance
840 * @retval Returned value can be one of the following values:
841 * @arg @ref LL_LPUART_DIRECTION_NONE
842 * @arg @ref LL_LPUART_DIRECTION_RX
843 * @arg @ref LL_LPUART_DIRECTION_TX
844 * @arg @ref LL_LPUART_DIRECTION_TX_RX
845 */
LL_LPUART_GetTransferDirection(const USART_TypeDef * LPUARTx)846 __STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx)
847 {
848 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
849 }
850
851 /**
852 * @brief Configure Parity (enabled/disabled and parity mode if enabled)
853 * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
854 * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
855 * (depending on data width) and parity is checked on the received data.
856 * @rmtoll CR1 PS LL_LPUART_SetParity\n
857 * CR1 PCE LL_LPUART_SetParity
858 * @param LPUARTx LPUART Instance
859 * @param Parity This parameter can be one of the following values:
860 * @arg @ref LL_LPUART_PARITY_NONE
861 * @arg @ref LL_LPUART_PARITY_EVEN
862 * @arg @ref LL_LPUART_PARITY_ODD
863 * @retval None
864 */
LL_LPUART_SetParity(USART_TypeDef * LPUARTx,uint32_t Parity)865 __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
866 {
867 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
868 }
869
870 /**
871 * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
872 * @rmtoll CR1 PS LL_LPUART_GetParity\n
873 * CR1 PCE LL_LPUART_GetParity
874 * @param LPUARTx LPUART Instance
875 * @retval Returned value can be one of the following values:
876 * @arg @ref LL_LPUART_PARITY_NONE
877 * @arg @ref LL_LPUART_PARITY_EVEN
878 * @arg @ref LL_LPUART_PARITY_ODD
879 */
LL_LPUART_GetParity(const USART_TypeDef * LPUARTx)880 __STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx)
881 {
882 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
883 }
884
885 /**
886 * @brief Set Receiver Wake Up method from Mute mode.
887 * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod
888 * @param LPUARTx LPUART Instance
889 * @param Method This parameter can be one of the following values:
890 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
891 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
892 * @retval None
893 */
LL_LPUART_SetWakeUpMethod(USART_TypeDef * LPUARTx,uint32_t Method)894 __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
895 {
896 MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
897 }
898
899 /**
900 * @brief Return Receiver Wake Up method from Mute mode
901 * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod
902 * @param LPUARTx LPUART Instance
903 * @retval Returned value can be one of the following values:
904 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
905 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
906 */
LL_LPUART_GetWakeUpMethod(const USART_TypeDef * LPUARTx)907 __STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx)
908 {
909 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
910 }
911
912 /**
913 * @brief Set Word length (nb of data bits, excluding start and stop bits)
914 * @rmtoll CR1 M LL_LPUART_SetDataWidth
915 * @param LPUARTx LPUART Instance
916 * @param DataWidth This parameter can be one of the following values:
917 * @arg @ref LL_LPUART_DATAWIDTH_7B
918 * @arg @ref LL_LPUART_DATAWIDTH_8B
919 * @arg @ref LL_LPUART_DATAWIDTH_9B
920 * @retval None
921 */
LL_LPUART_SetDataWidth(USART_TypeDef * LPUARTx,uint32_t DataWidth)922 __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
923 {
924 MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
925 }
926
927 /**
928 * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
929 * @rmtoll CR1 M LL_LPUART_GetDataWidth
930 * @param LPUARTx LPUART Instance
931 * @retval Returned value can be one of the following values:
932 * @arg @ref LL_LPUART_DATAWIDTH_7B
933 * @arg @ref LL_LPUART_DATAWIDTH_8B
934 * @arg @ref LL_LPUART_DATAWIDTH_9B
935 */
LL_LPUART_GetDataWidth(const USART_TypeDef * LPUARTx)936 __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx)
937 {
938 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
939 }
940
941 /**
942 * @brief Allow switch between Mute Mode and Active mode
943 * @rmtoll CR1 MME LL_LPUART_EnableMuteMode
944 * @param LPUARTx LPUART Instance
945 * @retval None
946 */
LL_LPUART_EnableMuteMode(USART_TypeDef * LPUARTx)947 __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
948 {
949 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
950 }
951
952 /**
953 * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
954 * @rmtoll CR1 MME LL_LPUART_DisableMuteMode
955 * @param LPUARTx LPUART Instance
956 * @retval None
957 */
LL_LPUART_DisableMuteMode(USART_TypeDef * LPUARTx)958 __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
959 {
960 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
961 }
962
963 /**
964 * @brief Indicate if switch between Mute Mode and Active mode is allowed
965 * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode
966 * @param LPUARTx LPUART Instance
967 * @retval State of bit (1 or 0).
968 */
LL_LPUART_IsEnabledMuteMode(const USART_TypeDef * LPUARTx)969 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx)
970 {
971 return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
972 }
973
974 #if defined(USART_PRESC_PRESCALER)
975 /**
976 * @brief Configure Clock source prescaler for baudrate generator and oversampling
977 * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler
978 * @param LPUARTx LPUART Instance
979 * @param PrescalerValue This parameter can be one of the following values:
980 * @arg @ref LL_LPUART_PRESCALER_DIV1
981 * @arg @ref LL_LPUART_PRESCALER_DIV2
982 * @arg @ref LL_LPUART_PRESCALER_DIV4
983 * @arg @ref LL_LPUART_PRESCALER_DIV6
984 * @arg @ref LL_LPUART_PRESCALER_DIV8
985 * @arg @ref LL_LPUART_PRESCALER_DIV10
986 * @arg @ref LL_LPUART_PRESCALER_DIV12
987 * @arg @ref LL_LPUART_PRESCALER_DIV16
988 * @arg @ref LL_LPUART_PRESCALER_DIV32
989 * @arg @ref LL_LPUART_PRESCALER_DIV64
990 * @arg @ref LL_LPUART_PRESCALER_DIV128
991 * @arg @ref LL_LPUART_PRESCALER_DIV256
992 * @retval None
993 */
LL_LPUART_SetPrescaler(USART_TypeDef * LPUARTx,uint32_t PrescalerValue)994 __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
995 {
996 MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
997 }
998
999 /**
1000 * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
1001 * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler
1002 * @param LPUARTx LPUART Instance
1003 * @retval Returned value can be one of the following values:
1004 * @arg @ref LL_LPUART_PRESCALER_DIV1
1005 * @arg @ref LL_LPUART_PRESCALER_DIV2
1006 * @arg @ref LL_LPUART_PRESCALER_DIV4
1007 * @arg @ref LL_LPUART_PRESCALER_DIV6
1008 * @arg @ref LL_LPUART_PRESCALER_DIV8
1009 * @arg @ref LL_LPUART_PRESCALER_DIV10
1010 * @arg @ref LL_LPUART_PRESCALER_DIV12
1011 * @arg @ref LL_LPUART_PRESCALER_DIV16
1012 * @arg @ref LL_LPUART_PRESCALER_DIV32
1013 * @arg @ref LL_LPUART_PRESCALER_DIV64
1014 * @arg @ref LL_LPUART_PRESCALER_DIV128
1015 * @arg @ref LL_LPUART_PRESCALER_DIV256
1016 */
LL_LPUART_GetPrescaler(const USART_TypeDef * LPUARTx)1017 __STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx)
1018 {
1019 return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
1020 }
1021 #endif /* USART_PRESC_PRESCALER */
1022
1023 /**
1024 * @brief Set the length of the stop bits
1025 * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength
1026 * @param LPUARTx LPUART Instance
1027 * @param StopBits This parameter can be one of the following values:
1028 * @arg @ref LL_LPUART_STOPBITS_1
1029 * @arg @ref LL_LPUART_STOPBITS_2
1030 * @retval None
1031 */
LL_LPUART_SetStopBitsLength(USART_TypeDef * LPUARTx,uint32_t StopBits)1032 __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
1033 {
1034 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
1035 }
1036
1037 /**
1038 * @brief Retrieve the length of the stop bits
1039 * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength
1040 * @param LPUARTx LPUART Instance
1041 * @retval Returned value can be one of the following values:
1042 * @arg @ref LL_LPUART_STOPBITS_1
1043 * @arg @ref LL_LPUART_STOPBITS_2
1044 */
LL_LPUART_GetStopBitsLength(const USART_TypeDef * LPUARTx)1045 __STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx)
1046 {
1047 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
1048 }
1049
1050 /**
1051 * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
1052 * @note Call of this function is equivalent to following function call sequence :
1053 * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
1054 * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
1055 * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
1056 * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n
1057 * CR1 PCE LL_LPUART_ConfigCharacter\n
1058 * CR1 M LL_LPUART_ConfigCharacter\n
1059 * CR2 STOP LL_LPUART_ConfigCharacter
1060 * @param LPUARTx LPUART Instance
1061 * @param DataWidth This parameter can be one of the following values:
1062 * @arg @ref LL_LPUART_DATAWIDTH_7B
1063 * @arg @ref LL_LPUART_DATAWIDTH_8B
1064 * @arg @ref LL_LPUART_DATAWIDTH_9B
1065 * @param Parity This parameter can be one of the following values:
1066 * @arg @ref LL_LPUART_PARITY_NONE
1067 * @arg @ref LL_LPUART_PARITY_EVEN
1068 * @arg @ref LL_LPUART_PARITY_ODD
1069 * @param StopBits This parameter can be one of the following values:
1070 * @arg @ref LL_LPUART_STOPBITS_1
1071 * @arg @ref LL_LPUART_STOPBITS_2
1072 * @retval None
1073 */
LL_LPUART_ConfigCharacter(USART_TypeDef * LPUARTx,uint32_t DataWidth,uint32_t Parity,uint32_t StopBits)1074 __STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
1075 uint32_t StopBits)
1076 {
1077 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
1078 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
1079 }
1080
1081 /**
1082 * @brief Configure TX/RX pins swapping setting.
1083 * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap
1084 * @param LPUARTx LPUART Instance
1085 * @param SwapConfig This parameter can be one of the following values:
1086 * @arg @ref LL_LPUART_TXRX_STANDARD
1087 * @arg @ref LL_LPUART_TXRX_SWAPPED
1088 * @retval None
1089 */
LL_LPUART_SetTXRXSwap(USART_TypeDef * LPUARTx,uint32_t SwapConfig)1090 __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
1091 {
1092 MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
1093 }
1094
1095 /**
1096 * @brief Retrieve TX/RX pins swapping configuration.
1097 * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap
1098 * @param LPUARTx LPUART Instance
1099 * @retval Returned value can be one of the following values:
1100 * @arg @ref LL_LPUART_TXRX_STANDARD
1101 * @arg @ref LL_LPUART_TXRX_SWAPPED
1102 */
LL_LPUART_GetTXRXSwap(const USART_TypeDef * LPUARTx)1103 __STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx)
1104 {
1105 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
1106 }
1107
1108 /**
1109 * @brief Configure RX pin active level logic
1110 * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel
1111 * @param LPUARTx LPUART Instance
1112 * @param PinInvMethod This parameter can be one of the following values:
1113 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
1114 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
1115 * @retval None
1116 */
LL_LPUART_SetRXPinLevel(USART_TypeDef * LPUARTx,uint32_t PinInvMethod)1117 __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1118 {
1119 MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
1120 }
1121
1122 /**
1123 * @brief Retrieve RX pin active level logic configuration
1124 * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel
1125 * @param LPUARTx LPUART Instance
1126 * @retval Returned value can be one of the following values:
1127 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
1128 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
1129 */
LL_LPUART_GetRXPinLevel(const USART_TypeDef * LPUARTx)1130 __STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx)
1131 {
1132 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
1133 }
1134
1135 /**
1136 * @brief Configure TX pin active level logic
1137 * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel
1138 * @param LPUARTx LPUART Instance
1139 * @param PinInvMethod This parameter can be one of the following values:
1140 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
1141 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
1142 * @retval None
1143 */
LL_LPUART_SetTXPinLevel(USART_TypeDef * LPUARTx,uint32_t PinInvMethod)1144 __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1145 {
1146 MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
1147 }
1148
1149 /**
1150 * @brief Retrieve TX pin active level logic configuration
1151 * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel
1152 * @param LPUARTx LPUART Instance
1153 * @retval Returned value can be one of the following values:
1154 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
1155 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
1156 */
LL_LPUART_GetTXPinLevel(const USART_TypeDef * LPUARTx)1157 __STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx)
1158 {
1159 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
1160 }
1161
1162 /**
1163 * @brief Configure Binary data logic.
1164 *
1165 * @note Allow to define how Logical data from the data register are send/received :
1166 * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
1167 * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic
1168 * @param LPUARTx LPUART Instance
1169 * @param DataLogic This parameter can be one of the following values:
1170 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
1171 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
1172 * @retval None
1173 */
LL_LPUART_SetBinaryDataLogic(USART_TypeDef * LPUARTx,uint32_t DataLogic)1174 __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
1175 {
1176 MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
1177 }
1178
1179 /**
1180 * @brief Retrieve Binary data configuration
1181 * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic
1182 * @param LPUARTx LPUART Instance
1183 * @retval Returned value can be one of the following values:
1184 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
1185 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
1186 */
LL_LPUART_GetBinaryDataLogic(const USART_TypeDef * LPUARTx)1187 __STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx)
1188 {
1189 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
1190 }
1191
1192 /**
1193 * @brief Configure transfer bit order (either Less or Most Significant Bit First)
1194 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
1195 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
1196 * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
1197 * @param LPUARTx LPUART Instance
1198 * @param BitOrder This parameter can be one of the following values:
1199 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
1200 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
1201 * @retval None
1202 */
LL_LPUART_SetTransferBitOrder(USART_TypeDef * LPUARTx,uint32_t BitOrder)1203 __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
1204 {
1205 MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
1206 }
1207
1208 /**
1209 * @brief Return transfer bit order (either Less or Most Significant Bit First)
1210 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
1211 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
1212 * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
1213 * @param LPUARTx LPUART Instance
1214 * @retval Returned value can be one of the following values:
1215 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
1216 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
1217 */
LL_LPUART_GetTransferBitOrder(const USART_TypeDef * LPUARTx)1218 __STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx)
1219 {
1220 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
1221 }
1222
1223 /**
1224 * @brief Set Address of the LPUART node.
1225 * @note This is used in multiprocessor communication during Mute mode or Stop mode,
1226 * for wake up with address mark detection.
1227 * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
1228 * (b7-b4 should be set to 0)
1229 * 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
1230 * (This is used in multiprocessor communication during Mute mode or Stop mode,
1231 * for wake up with 7-bit address mark detection.
1232 * The MSB of the character sent by the transmitter should be equal to 1.
1233 * It may also be used for character detection during normal reception,
1234 * Mute mode inactive (for example, end of block detection in ModBus protocol).
1235 * In this case, the whole received character (8-bit) is compared to the ADD[7:0]
1236 * value and CMF flag is set on match)
1237 * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n
1238 * CR2 ADDM7 LL_LPUART_ConfigNodeAddress
1239 * @param LPUARTx LPUART Instance
1240 * @param AddressLen This parameter can be one of the following values:
1241 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
1242 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
1243 * @param NodeAddress 4 or 7 bit Address of the LPUART node.
1244 * @retval None
1245 */
LL_LPUART_ConfigNodeAddress(USART_TypeDef * LPUARTx,uint32_t AddressLen,uint32_t NodeAddress)1246 __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
1247 {
1248 MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
1249 (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
1250 }
1251
1252 /**
1253 * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2.
1254 * @note If 4-bit Address Detection is selected in ADDM7,
1255 * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
1256 * If 7-bit Address Detection is selected in ADDM7,
1257 * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
1258 * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress
1259 * @param LPUARTx LPUART Instance
1260 * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
1261 */
LL_LPUART_GetNodeAddress(const USART_TypeDef * LPUARTx)1262 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx)
1263 {
1264 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
1265 }
1266
1267 /**
1268 * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
1269 * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen
1270 * @param LPUARTx LPUART Instance
1271 * @retval Returned value can be one of the following values:
1272 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
1273 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
1274 */
LL_LPUART_GetNodeAddressLen(const USART_TypeDef * LPUARTx)1275 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx)
1276 {
1277 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
1278 }
1279
1280 /**
1281 * @brief Enable RTS HW Flow Control
1282 * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
1283 * @param LPUARTx LPUART Instance
1284 * @retval None
1285 */
LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef * LPUARTx)1286 __STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1287 {
1288 SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1289 }
1290
1291 /**
1292 * @brief Disable RTS HW Flow Control
1293 * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
1294 * @param LPUARTx LPUART Instance
1295 * @retval None
1296 */
LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef * LPUARTx)1297 __STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1298 {
1299 CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1300 }
1301
1302 /**
1303 * @brief Enable CTS HW Flow Control
1304 * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
1305 * @param LPUARTx LPUART Instance
1306 * @retval None
1307 */
LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef * LPUARTx)1308 __STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1309 {
1310 SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1311 }
1312
1313 /**
1314 * @brief Disable CTS HW Flow Control
1315 * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
1316 * @param LPUARTx LPUART Instance
1317 * @retval None
1318 */
LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef * LPUARTx)1319 __STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1320 {
1321 CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1322 }
1323
1324 /**
1325 * @brief Configure HW Flow Control mode (both CTS and RTS)
1326 * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n
1327 * CR3 CTSE LL_LPUART_SetHWFlowCtrl
1328 * @param LPUARTx LPUART Instance
1329 * @param HardwareFlowControl This parameter can be one of the following values:
1330 * @arg @ref LL_LPUART_HWCONTROL_NONE
1331 * @arg @ref LL_LPUART_HWCONTROL_RTS
1332 * @arg @ref LL_LPUART_HWCONTROL_CTS
1333 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1334 * @retval None
1335 */
LL_LPUART_SetHWFlowCtrl(USART_TypeDef * LPUARTx,uint32_t HardwareFlowControl)1336 __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
1337 {
1338 MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
1339 }
1340
1341 /**
1342 * @brief Return HW Flow Control configuration (both CTS and RTS)
1343 * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n
1344 * CR3 CTSE LL_LPUART_GetHWFlowCtrl
1345 * @param LPUARTx LPUART Instance
1346 * @retval Returned value can be one of the following values:
1347 * @arg @ref LL_LPUART_HWCONTROL_NONE
1348 * @arg @ref LL_LPUART_HWCONTROL_RTS
1349 * @arg @ref LL_LPUART_HWCONTROL_CTS
1350 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1351 */
LL_LPUART_GetHWFlowCtrl(const USART_TypeDef * LPUARTx)1352 __STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx)
1353 {
1354 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
1355 }
1356
1357 /**
1358 * @brief Enable Overrun detection
1359 * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect
1360 * @param LPUARTx LPUART Instance
1361 * @retval None
1362 */
LL_LPUART_EnableOverrunDetect(USART_TypeDef * LPUARTx)1363 __STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
1364 {
1365 CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1366 }
1367
1368 /**
1369 * @brief Disable Overrun detection
1370 * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect
1371 * @param LPUARTx LPUART Instance
1372 * @retval None
1373 */
LL_LPUART_DisableOverrunDetect(USART_TypeDef * LPUARTx)1374 __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
1375 {
1376 SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1377 }
1378
1379 /**
1380 * @brief Indicate if Overrun detection is enabled
1381 * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
1382 * @param LPUARTx LPUART Instance
1383 * @retval State of bit (1 or 0).
1384 */
LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef * LPUARTx)1385 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx)
1386 {
1387 return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
1388 }
1389
1390 /**
1391 * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
1392 * @rmtoll CR3 WUS LL_LPUART_SetWKUPType
1393 * @param LPUARTx LPUART Instance
1394 * @param Type This parameter can be one of the following values:
1395 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
1396 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
1397 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
1398 * @retval None
1399 */
LL_LPUART_SetWKUPType(USART_TypeDef * LPUARTx,uint32_t Type)1400 __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
1401 {
1402 MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
1403 }
1404
1405 /**
1406 * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
1407 * @rmtoll CR3 WUS LL_LPUART_GetWKUPType
1408 * @param LPUARTx LPUART Instance
1409 * @retval Returned value can be one of the following values:
1410 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
1411 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
1412 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
1413 */
LL_LPUART_GetWKUPType(const USART_TypeDef * LPUARTx)1414 __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx)
1415 {
1416 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
1417 }
1418
1419 /**
1420 * @brief Configure LPUART BRR register for achieving expected Baud Rate value.
1421 *
1422 * @note Compute and set LPUARTDIV value in BRR Register (full BRR content)
1423 * according to used Peripheral Clock and expected Baud Rate values
1424 * @note Peripheral clock and Baud Rate values provided as function parameters should be valid
1425 * (Baud rate value != 0).
1426 * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
1427 * a care should be taken when generating high baud rates using high PeriphClk
1428 * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
1429 * @rmtoll BRR BRR LL_LPUART_SetBaudRate
1430 * @param LPUARTx LPUART Instance
1431 * @param PeriphClk Peripheral Clock
1432 @if USART_PRESC_PRESCALER
1433 * @param PrescalerValue This parameter can be one of the following values:
1434 * @arg @ref LL_LPUART_PRESCALER_DIV1
1435 * @arg @ref LL_LPUART_PRESCALER_DIV2
1436 * @arg @ref LL_LPUART_PRESCALER_DIV4
1437 * @arg @ref LL_LPUART_PRESCALER_DIV6
1438 * @arg @ref LL_LPUART_PRESCALER_DIV8
1439 * @arg @ref LL_LPUART_PRESCALER_DIV10
1440 * @arg @ref LL_LPUART_PRESCALER_DIV12
1441 * @arg @ref LL_LPUART_PRESCALER_DIV16
1442 * @arg @ref LL_LPUART_PRESCALER_DIV32
1443 * @arg @ref LL_LPUART_PRESCALER_DIV64
1444 * @arg @ref LL_LPUART_PRESCALER_DIV128
1445 * @arg @ref LL_LPUART_PRESCALER_DIV256
1446 @endif
1447 * @param BaudRate Baud Rate
1448 * @retval None
1449 */
1450 #if defined(USART_PRESC_PRESCALER)
LL_LPUART_SetBaudRate(USART_TypeDef * LPUARTx,uint32_t PeriphClk,uint32_t PrescalerValue,uint32_t BaudRate)1451 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
1452 uint32_t BaudRate)
1453 #else
1454 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate)
1455 #endif /* USART_PRESC_PRESCALER */
1456 {
1457 #if defined(USART_PRESC_PRESCALER)
1458 if (BaudRate != 0U)
1459 {
1460 LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
1461 }
1462 #else
1463 if (BaudRate != 0U)
1464 {
1465 LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate);
1466 }
1467 #endif /* USART_PRESC_PRESCALER */
1468 }
1469
1470 /**
1471 * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register
1472 * (full BRR content), and to used Peripheral Clock values
1473 * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
1474 * @rmtoll BRR BRR LL_LPUART_GetBaudRate
1475 * @param LPUARTx LPUART Instance
1476 * @param PeriphClk Peripheral Clock
1477 @if USART_PRESC_PRESCALER
1478 * @param PrescalerValue This parameter can be one of the following values:
1479 * @arg @ref LL_LPUART_PRESCALER_DIV1
1480 * @arg @ref LL_LPUART_PRESCALER_DIV2
1481 * @arg @ref LL_LPUART_PRESCALER_DIV4
1482 * @arg @ref LL_LPUART_PRESCALER_DIV6
1483 * @arg @ref LL_LPUART_PRESCALER_DIV8
1484 * @arg @ref LL_LPUART_PRESCALER_DIV10
1485 * @arg @ref LL_LPUART_PRESCALER_DIV12
1486 * @arg @ref LL_LPUART_PRESCALER_DIV16
1487 * @arg @ref LL_LPUART_PRESCALER_DIV32
1488 * @arg @ref LL_LPUART_PRESCALER_DIV64
1489 * @arg @ref LL_LPUART_PRESCALER_DIV128
1490 * @arg @ref LL_LPUART_PRESCALER_DIV256
1491 @endif
1492 * @retval Baud Rate
1493 */
1494 #if defined(USART_PRESC_PRESCALER)
LL_LPUART_GetBaudRate(const USART_TypeDef * LPUARTx,uint32_t PeriphClk,uint32_t PrescalerValue)1495 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
1496 #else
1497 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk)
1498 #endif /* USART_PRESC_PRESCALER */
1499 {
1500 uint32_t lpuartdiv;
1501 uint32_t brrresult;
1502 #if defined(USART_PRESC_PRESCALER)
1503 uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
1504 #endif /* USART_PRESC_PRESCALER */
1505
1506 lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
1507
1508 if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
1509 {
1510 #if defined(USART_PRESC_PRESCALER)
1511 brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
1512 #else
1513 brrresult = (uint32_t)(((uint64_t)(PeriphClk) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
1514 #endif /* USART_PRESC_PRESCALER */
1515 }
1516 else
1517 {
1518 brrresult = 0x0UL;
1519 }
1520
1521 return (brrresult);
1522 }
1523
1524 /**
1525 * @}
1526 */
1527
1528 /** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
1529 * @{
1530 */
1531
1532 /**
1533 * @brief Enable Single Wire Half-Duplex mode
1534 * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex
1535 * @param LPUARTx LPUART Instance
1536 * @retval None
1537 */
LL_LPUART_EnableHalfDuplex(USART_TypeDef * LPUARTx)1538 __STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
1539 {
1540 SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1541 }
1542
1543 /**
1544 * @brief Disable Single Wire Half-Duplex mode
1545 * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex
1546 * @param LPUARTx LPUART Instance
1547 * @retval None
1548 */
LL_LPUART_DisableHalfDuplex(USART_TypeDef * LPUARTx)1549 __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
1550 {
1551 CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1552 }
1553
1554 /**
1555 * @brief Indicate if Single Wire Half-Duplex mode is enabled
1556 * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
1557 * @param LPUARTx LPUART Instance
1558 * @retval State of bit (1 or 0).
1559 */
LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef * LPUARTx)1560 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx)
1561 {
1562 return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
1563 }
1564
1565 /**
1566 * @}
1567 */
1568
1569 /** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
1570 * @{
1571 */
1572
1573 /**
1574 * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1575 * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime
1576 * @param LPUARTx LPUART Instance
1577 * @param Time Value between Min_Data=0 and Max_Data=31
1578 * @retval None
1579 */
LL_LPUART_SetDEDeassertionTime(USART_TypeDef * LPUARTx,uint32_t Time)1580 __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1581 {
1582 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
1583 }
1584
1585 /**
1586 * @brief Return DEDT (Driver Enable De-Assertion Time)
1587 * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime
1588 * @param LPUARTx LPUART Instance
1589 * @retval Time value expressed on 5 bits ([4:0] bits) : c
1590 */
LL_LPUART_GetDEDeassertionTime(const USART_TypeDef * LPUARTx)1591 __STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx)
1592 {
1593 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
1594 }
1595
1596 /**
1597 * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1598 * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime
1599 * @param LPUARTx LPUART Instance
1600 * @param Time Value between Min_Data=0 and Max_Data=31
1601 * @retval None
1602 */
LL_LPUART_SetDEAssertionTime(USART_TypeDef * LPUARTx,uint32_t Time)1603 __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1604 {
1605 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
1606 }
1607
1608 /**
1609 * @brief Return DEAT (Driver Enable Assertion Time)
1610 * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime
1611 * @param LPUARTx LPUART Instance
1612 * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
1613 */
LL_LPUART_GetDEAssertionTime(const USART_TypeDef * LPUARTx)1614 __STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx)
1615 {
1616 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
1617 }
1618
1619 /**
1620 * @brief Enable Driver Enable (DE) Mode
1621 * @rmtoll CR3 DEM LL_LPUART_EnableDEMode
1622 * @param LPUARTx LPUART Instance
1623 * @retval None
1624 */
LL_LPUART_EnableDEMode(USART_TypeDef * LPUARTx)1625 __STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
1626 {
1627 SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
1628 }
1629
1630 /**
1631 * @brief Disable Driver Enable (DE) Mode
1632 * @rmtoll CR3 DEM LL_LPUART_DisableDEMode
1633 * @param LPUARTx LPUART Instance
1634 * @retval None
1635 */
LL_LPUART_DisableDEMode(USART_TypeDef * LPUARTx)1636 __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
1637 {
1638 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
1639 }
1640
1641 /**
1642 * @brief Indicate if Driver Enable (DE) Mode is enabled
1643 * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode
1644 * @param LPUARTx LPUART Instance
1645 * @retval State of bit (1 or 0).
1646 */
LL_LPUART_IsEnabledDEMode(const USART_TypeDef * LPUARTx)1647 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx)
1648 {
1649 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
1650 }
1651
1652 /**
1653 * @brief Select Driver Enable Polarity
1654 * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity
1655 * @param LPUARTx LPUART Instance
1656 * @param Polarity This parameter can be one of the following values:
1657 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1658 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1659 * @retval None
1660 */
LL_LPUART_SetDESignalPolarity(USART_TypeDef * LPUARTx,uint32_t Polarity)1661 __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
1662 {
1663 MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
1664 }
1665
1666 /**
1667 * @brief Return Driver Enable Polarity
1668 * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity
1669 * @param LPUARTx LPUART Instance
1670 * @retval Returned value can be one of the following values:
1671 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1672 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1673 */
LL_LPUART_GetDESignalPolarity(const USART_TypeDef * LPUARTx)1674 __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx)
1675 {
1676 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
1677 }
1678
1679 /**
1680 * @}
1681 */
1682
1683 /** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
1684 * @{
1685 */
1686
1687 /**
1688 * @brief Check if the LPUART Parity Error Flag is set or not
1689 * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE
1690 * @param LPUARTx LPUART Instance
1691 * @retval State of bit (1 or 0).
1692 */
LL_LPUART_IsActiveFlag_PE(const USART_TypeDef * LPUARTx)1693 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx)
1694 {
1695 return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
1696 }
1697
1698 /**
1699 * @brief Check if the LPUART Framing Error Flag is set or not
1700 * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE
1701 * @param LPUARTx LPUART Instance
1702 * @retval State of bit (1 or 0).
1703 */
LL_LPUART_IsActiveFlag_FE(const USART_TypeDef * LPUARTx)1704 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx)
1705 {
1706 return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
1707 }
1708
1709 /**
1710 * @brief Check if the LPUART Noise error detected Flag is set or not
1711 * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE
1712 * @param LPUARTx LPUART Instance
1713 * @retval State of bit (1 or 0).
1714 */
LL_LPUART_IsActiveFlag_NE(const USART_TypeDef * LPUARTx)1715 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx)
1716 {
1717 return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
1718 }
1719
1720 /**
1721 * @brief Check if the LPUART OverRun Error Flag is set or not
1722 * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE
1723 * @param LPUARTx LPUART Instance
1724 * @retval State of bit (1 or 0).
1725 */
LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef * LPUARTx)1726 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx)
1727 {
1728 return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
1729 }
1730
1731 /**
1732 * @brief Check if the LPUART IDLE line detected Flag is set or not
1733 * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE
1734 * @param LPUARTx LPUART Instance
1735 * @retval State of bit (1 or 0).
1736 */
LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef * LPUARTx)1737 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx)
1738 {
1739 return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
1740 }
1741
1742 #if defined(USART_CR1_FIFOEN)
1743 /* Legacy define */
1744 #define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
1745
1746 /**
1747 * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
1748 * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
1749 * @param LPUARTx LPUART Instance
1750 * @retval State of bit (1 or 0).
1751 */
LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef * LPUARTx)1752 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
1753 {
1754 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
1755 }
1756 #else
1757 /**
1758 * @brief Check if the LPUART Read Data Register Not Empty Flag is set or not
1759 * @rmtoll ISR RXNE LL_LPUART_IsActiveFlag_RXNE
1760 * @param LPUARTx LPUART Instance
1761 * @retval State of bit (1 or 0).
1762 */
LL_LPUART_IsActiveFlag_RXNE(const USART_TypeDef * LPUARTx)1763 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE(const USART_TypeDef *LPUARTx)
1764 {
1765 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL);
1766 }
1767 #endif /* USART_CR1_FIFOEN */
1768
1769 /**
1770 * @brief Check if the LPUART Transmission Complete Flag is set or not
1771 * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC
1772 * @param LPUARTx LPUART Instance
1773 * @retval State of bit (1 or 0).
1774 */
LL_LPUART_IsActiveFlag_TC(const USART_TypeDef * LPUARTx)1775 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx)
1776 {
1777 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
1778 }
1779
1780 #if defined(USART_CR1_FIFOEN)
1781 /* Legacy define */
1782 #define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF
1783
1784 /**
1785 * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
1786 * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF
1787 * @param LPUARTx LPUART Instance
1788 * @retval State of bit (1 or 0).
1789 */
LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef * LPUARTx)1790 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx)
1791 {
1792 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
1793 }
1794 #else
1795 /**
1796 * @brief Check if the LPUART Transmit Data Register Empty Flag is set or not
1797 * @rmtoll ISR TXE LL_LPUART_IsActiveFlag_TXE
1798 * @param LPUARTx LPUART Instance
1799 * @retval State of bit (1 or 0).
1800 */
LL_LPUART_IsActiveFlag_TXE(const USART_TypeDef * LPUARTx)1801 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(const USART_TypeDef *LPUARTx)
1802 {
1803 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL);
1804 }
1805 #endif /* USART_CR1_FIFOEN */
1806
1807 /**
1808 * @brief Check if the LPUART CTS interrupt Flag is set or not
1809 * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
1810 * @param LPUARTx LPUART Instance
1811 * @retval State of bit (1 or 0).
1812 */
LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef * LPUARTx)1813 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx)
1814 {
1815 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
1816 }
1817
1818 /**
1819 * @brief Check if the LPUART CTS Flag is set or not
1820 * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS
1821 * @param LPUARTx LPUART Instance
1822 * @retval State of bit (1 or 0).
1823 */
LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef * LPUARTx)1824 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx)
1825 {
1826 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
1827 }
1828
1829 /**
1830 * @brief Check if the LPUART Busy Flag is set or not
1831 * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY
1832 * @param LPUARTx LPUART Instance
1833 * @retval State of bit (1 or 0).
1834 */
LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef * LPUARTx)1835 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx)
1836 {
1837 return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
1838 }
1839
1840 /**
1841 * @brief Check if the LPUART Character Match Flag is set or not
1842 * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM
1843 * @param LPUARTx LPUART Instance
1844 * @retval State of bit (1 or 0).
1845 */
LL_LPUART_IsActiveFlag_CM(const USART_TypeDef * LPUARTx)1846 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx)
1847 {
1848 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
1849 }
1850
1851 /**
1852 * @brief Check if the LPUART Send Break Flag is set or not
1853 * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK
1854 * @param LPUARTx LPUART Instance
1855 * @retval State of bit (1 or 0).
1856 */
LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef * LPUARTx)1857 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx)
1858 {
1859 return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
1860 }
1861
1862 /**
1863 * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not
1864 * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU
1865 * @param LPUARTx LPUART Instance
1866 * @retval State of bit (1 or 0).
1867 */
LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef * LPUARTx)1868 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx)
1869 {
1870 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
1871 }
1872
1873 /**
1874 * @brief Check if the LPUART Wake Up from stop mode Flag is set or not
1875 * @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP
1876 * @param LPUARTx LPUART Instance
1877 * @retval State of bit (1 or 0).
1878 */
LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef * LPUARTx)1879 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx)
1880 {
1881 return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
1882 }
1883
1884 /**
1885 * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not
1886 * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK
1887 * @param LPUARTx LPUART Instance
1888 * @retval State of bit (1 or 0).
1889 */
LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef * LPUARTx)1890 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx)
1891 {
1892 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
1893 }
1894
1895 /**
1896 * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not
1897 * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK
1898 * @param LPUARTx LPUART Instance
1899 * @retval State of bit (1 or 0).
1900 */
LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef * LPUARTx)1901 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx)
1902 {
1903 return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
1904 }
1905
1906 #if defined(USART_CR1_FIFOEN)
1907 /**
1908 * @brief Check if the LPUART TX FIFO Empty Flag is set or not
1909 * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE
1910 * @param LPUARTx LPUART Instance
1911 * @retval State of bit (1 or 0).
1912 */
LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef * LPUARTx)1913 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx)
1914 {
1915 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
1916 }
1917
1918 /**
1919 * @brief Check if the LPUART RX FIFO Full Flag is set or not
1920 * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF
1921 * @param LPUARTx LPUART Instance
1922 * @retval State of bit (1 or 0).
1923 */
LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef * LPUARTx)1924 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx)
1925 {
1926 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
1927 }
1928
1929 /**
1930 * @brief Check if the LPUART TX FIFO Threshold Flag is set or not
1931 * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT
1932 * @param LPUARTx LPUART Instance
1933 * @retval State of bit (1 or 0).
1934 */
LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef * LPUARTx)1935 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx)
1936 {
1937 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
1938 }
1939
1940 /**
1941 * @brief Check if the LPUART RX FIFO Threshold Flag is set or not
1942 * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT
1943 * @param LPUARTx LPUART Instance
1944 * @retval State of bit (1 or 0).
1945 */
LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef * LPUARTx)1946 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx)
1947 {
1948 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
1949 }
1950 #endif /* USART_CR1_FIFOEN */
1951
1952 /**
1953 * @brief Clear Parity Error Flag
1954 * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE
1955 * @param LPUARTx LPUART Instance
1956 * @retval None
1957 */
LL_LPUART_ClearFlag_PE(USART_TypeDef * LPUARTx)1958 __STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
1959 {
1960 WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
1961 }
1962
1963 /**
1964 * @brief Clear Framing Error Flag
1965 * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE
1966 * @param LPUARTx LPUART Instance
1967 * @retval None
1968 */
LL_LPUART_ClearFlag_FE(USART_TypeDef * LPUARTx)1969 __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
1970 {
1971 WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
1972 }
1973
1974 /**
1975 * @brief Clear Noise detected Flag
1976 * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE
1977 * @param LPUARTx LPUART Instance
1978 * @retval None
1979 */
LL_LPUART_ClearFlag_NE(USART_TypeDef * LPUARTx)1980 __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
1981 {
1982 WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
1983 }
1984
1985 /**
1986 * @brief Clear OverRun Error Flag
1987 * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE
1988 * @param LPUARTx LPUART Instance
1989 * @retval None
1990 */
LL_LPUART_ClearFlag_ORE(USART_TypeDef * LPUARTx)1991 __STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
1992 {
1993 WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
1994 }
1995
1996 /**
1997 * @brief Clear IDLE line detected Flag
1998 * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE
1999 * @param LPUARTx LPUART Instance
2000 * @retval None
2001 */
LL_LPUART_ClearFlag_IDLE(USART_TypeDef * LPUARTx)2002 __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
2003 {
2004 WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
2005 }
2006
2007 /**
2008 * @brief Clear Transmission Complete Flag
2009 * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
2010 * @param LPUARTx LPUART Instance
2011 * @retval None
2012 */
LL_LPUART_ClearFlag_TC(USART_TypeDef * LPUARTx)2013 __STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
2014 {
2015 WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
2016 }
2017
2018 /**
2019 * @brief Clear CTS Interrupt Flag
2020 * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS
2021 * @param LPUARTx LPUART Instance
2022 * @retval None
2023 */
LL_LPUART_ClearFlag_nCTS(USART_TypeDef * LPUARTx)2024 __STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
2025 {
2026 WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
2027 }
2028
2029 /**
2030 * @brief Clear Character Match Flag
2031 * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM
2032 * @param LPUARTx LPUART Instance
2033 * @retval None
2034 */
LL_LPUART_ClearFlag_CM(USART_TypeDef * LPUARTx)2035 __STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
2036 {
2037 WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
2038 }
2039
2040 /**
2041 * @brief Clear Wake Up from stop mode Flag
2042 * @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP
2043 * @param LPUARTx LPUART Instance
2044 * @retval None
2045 */
LL_LPUART_ClearFlag_WKUP(USART_TypeDef * LPUARTx)2046 __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
2047 {
2048 WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
2049 }
2050
2051 /**
2052 * @}
2053 */
2054
2055 /** @defgroup LPUART_LL_EF_IT_Management IT_Management
2056 * @{
2057 */
2058
2059 /**
2060 * @brief Enable IDLE Interrupt
2061 * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE
2062 * @param LPUARTx LPUART Instance
2063 * @retval None
2064 */
LL_LPUART_EnableIT_IDLE(USART_TypeDef * LPUARTx)2065 __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
2066 {
2067 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
2068 }
2069
2070 #if defined(USART_CR1_FIFOEN)
2071 /* Legacy define */
2072 #define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE
2073
2074 /**
2075 * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
2076 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE
2077 * @param LPUARTx LPUART Instance
2078 * @retval None
2079 */
LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef * LPUARTx)2080 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
2081 {
2082 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
2083 }
2084 #else
2085
2086 /**
2087 * @brief Enable RX Not Empty Interrupt
2088 * @rmtoll CR1 RXNEIE LL_LPUART_EnableIT_RXNE
2089 * @param LPUARTx LPUART Instance
2090 * @retval None
2091 */
LL_LPUART_EnableIT_RXNE(USART_TypeDef * LPUARTx)2092 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE(USART_TypeDef *LPUARTx)
2093 {
2094 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
2095 }
2096 #endif /* USART_CR1_FIFOEN */
2097
2098 /**
2099 * @brief Enable Transmission Complete Interrupt
2100 * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC
2101 * @param LPUARTx LPUART Instance
2102 * @retval None
2103 */
LL_LPUART_EnableIT_TC(USART_TypeDef * LPUARTx)2104 __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
2105 {
2106 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
2107 }
2108
2109 #if defined(USART_CR1_FIFOEN)
2110 /* Legacy define */
2111 #define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF
2112
2113 /**
2114 * @brief Enable TX Empty and TX FIFO Not Full Interrupt
2115 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF
2116 * @param LPUARTx LPUART Instance
2117 * @retval None
2118 */
LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef * LPUARTx)2119 __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
2120 {
2121 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
2122 }
2123 #else
2124
2125 /**
2126 * @brief Enable TX Empty Interrupt
2127 * @rmtoll CR1 TXEIE LL_LPUART_EnableIT_TXE
2128 * @param LPUARTx LPUART Instance
2129 * @retval None
2130 */
LL_LPUART_EnableIT_TXE(USART_TypeDef * LPUARTx)2131 __STATIC_INLINE void LL_LPUART_EnableIT_TXE(USART_TypeDef *LPUARTx)
2132 {
2133 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
2134 }
2135 #endif /* USART_CR1_FIFOEN */
2136
2137 /**
2138 * @brief Enable Parity Error Interrupt
2139 * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE
2140 * @param LPUARTx LPUART Instance
2141 * @retval None
2142 */
LL_LPUART_EnableIT_PE(USART_TypeDef * LPUARTx)2143 __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
2144 {
2145 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
2146 }
2147
2148 /**
2149 * @brief Enable Character Match Interrupt
2150 * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM
2151 * @param LPUARTx LPUART Instance
2152 * @retval None
2153 */
LL_LPUART_EnableIT_CM(USART_TypeDef * LPUARTx)2154 __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
2155 {
2156 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
2157 }
2158
2159 #if defined(USART_CR1_FIFOEN)
2160 /**
2161 * @brief Enable TX FIFO Empty Interrupt
2162 * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE
2163 * @param LPUARTx LPUART Instance
2164 * @retval None
2165 */
LL_LPUART_EnableIT_TXFE(USART_TypeDef * LPUARTx)2166 __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
2167 {
2168 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
2169 }
2170
2171 /**
2172 * @brief Enable RX FIFO Full Interrupt
2173 * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF
2174 * @param LPUARTx LPUART Instance
2175 * @retval None
2176 */
LL_LPUART_EnableIT_RXFF(USART_TypeDef * LPUARTx)2177 __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
2178 {
2179 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
2180 }
2181 #endif /* USART_CR1_FIFOEN */
2182
2183 /**
2184 * @brief Enable Error Interrupt
2185 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
2186 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
2187 * - 0: Interrupt is inhibited
2188 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
2189 * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR
2190 * @param LPUARTx LPUART Instance
2191 * @retval None
2192 */
LL_LPUART_EnableIT_ERROR(USART_TypeDef * LPUARTx)2193 __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
2194 {
2195 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
2196 }
2197
2198 /**
2199 * @brief Enable CTS Interrupt
2200 * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS
2201 * @param LPUARTx LPUART Instance
2202 * @retval None
2203 */
LL_LPUART_EnableIT_CTS(USART_TypeDef * LPUARTx)2204 __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
2205 {
2206 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2207 }
2208
2209 /**
2210 * @brief Enable Wake Up from Stop Mode Interrupt
2211 * @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP
2212 * @param LPUARTx LPUART Instance
2213 * @retval None
2214 */
LL_LPUART_EnableIT_WKUP(USART_TypeDef * LPUARTx)2215 __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
2216 {
2217 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
2218 }
2219
2220 #if defined(USART_CR1_FIFOEN)
2221 /**
2222 * @brief Enable TX FIFO Threshold Interrupt
2223 * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT
2224 * @param LPUARTx LPUART Instance
2225 * @retval None
2226 */
LL_LPUART_EnableIT_TXFT(USART_TypeDef * LPUARTx)2227 __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
2228 {
2229 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2230 }
2231
2232 /**
2233 * @brief Enable RX FIFO Threshold Interrupt
2234 * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT
2235 * @param LPUARTx LPUART Instance
2236 * @retval None
2237 */
LL_LPUART_EnableIT_RXFT(USART_TypeDef * LPUARTx)2238 __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
2239 {
2240 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2241 }
2242 #endif /* USART_CR1_FIFOEN */
2243
2244 /**
2245 * @brief Disable IDLE Interrupt
2246 * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE
2247 * @param LPUARTx LPUART Instance
2248 * @retval None
2249 */
LL_LPUART_DisableIT_IDLE(USART_TypeDef * LPUARTx)2250 __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
2251 {
2252 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
2253 }
2254
2255 #if defined(USART_CR1_FIFOEN)
2256 /* Legacy define */
2257 #define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE
2258
2259 /**
2260 * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
2261 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE
2262 * @param LPUARTx LPUART Instance
2263 * @retval None
2264 */
LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef * LPUARTx)2265 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
2266 {
2267 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
2268 }
2269 #else
2270
2271 /**
2272 * @brief Disable RX Not Empty Interrupt
2273 * @rmtoll CR1 RXNEIE LL_LPUART_DisableIT_RXNE
2274 * @param LPUARTx LPUART Instance
2275 * @retval None
2276 */
LL_LPUART_DisableIT_RXNE(USART_TypeDef * LPUARTx)2277 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE(USART_TypeDef *LPUARTx)
2278 {
2279 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
2280 }
2281 #endif /* USART_CR1_FIFOEN */
2282
2283 /**
2284 * @brief Disable Transmission Complete Interrupt
2285 * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC
2286 * @param LPUARTx LPUART Instance
2287 * @retval None
2288 */
LL_LPUART_DisableIT_TC(USART_TypeDef * LPUARTx)2289 __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
2290 {
2291 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
2292 }
2293
2294 #if defined(USART_CR1_FIFOEN)
2295 /* Legacy define */
2296 #define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF
2297
2298 /**
2299 * @brief Disable TX Empty and TX FIFO Not Full Interrupt
2300 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF
2301 * @param LPUARTx LPUART Instance
2302 * @retval None
2303 */
LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef * LPUARTx)2304 __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
2305 {
2306 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
2307 }
2308 #else
2309
2310 /**
2311 * @brief Disable TX Empty Interrupt
2312 * @rmtoll CR1 TXEIE LL_LPUART_DisableIT_TXE
2313 * @param LPUARTx LPUART Instance
2314 * @retval None
2315 */
LL_LPUART_DisableIT_TXE(USART_TypeDef * LPUARTx)2316 __STATIC_INLINE void LL_LPUART_DisableIT_TXE(USART_TypeDef *LPUARTx)
2317 {
2318 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
2319 }
2320 #endif /* USART_CR1_FIFOEN */
2321
2322 /**
2323 * @brief Disable Parity Error Interrupt
2324 * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE
2325 * @param LPUARTx LPUART Instance
2326 * @retval None
2327 */
LL_LPUART_DisableIT_PE(USART_TypeDef * LPUARTx)2328 __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
2329 {
2330 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
2331 }
2332
2333 /**
2334 * @brief Disable Character Match Interrupt
2335 * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM
2336 * @param LPUARTx LPUART Instance
2337 * @retval None
2338 */
LL_LPUART_DisableIT_CM(USART_TypeDef * LPUARTx)2339 __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
2340 {
2341 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
2342 }
2343
2344 #if defined(USART_CR1_FIFOEN)
2345 /**
2346 * @brief Disable TX FIFO Empty Interrupt
2347 * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE
2348 * @param LPUARTx LPUART Instance
2349 * @retval None
2350 */
LL_LPUART_DisableIT_TXFE(USART_TypeDef * LPUARTx)2351 __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
2352 {
2353 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
2354 }
2355
2356 /**
2357 * @brief Disable RX FIFO Full Interrupt
2358 * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF
2359 * @param LPUARTx LPUART Instance
2360 * @retval None
2361 */
LL_LPUART_DisableIT_RXFF(USART_TypeDef * LPUARTx)2362 __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
2363 {
2364 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
2365 }
2366 #endif /* USART_CR1_FIFOEN */
2367
2368 /**
2369 * @brief Disable Error Interrupt
2370 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
2371 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
2372 * - 0: Interrupt is inhibited
2373 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
2374 * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR
2375 * @param LPUARTx LPUART Instance
2376 * @retval None
2377 */
LL_LPUART_DisableIT_ERROR(USART_TypeDef * LPUARTx)2378 __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
2379 {
2380 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
2381 }
2382
2383 /**
2384 * @brief Disable CTS Interrupt
2385 * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS
2386 * @param LPUARTx LPUART Instance
2387 * @retval None
2388 */
LL_LPUART_DisableIT_CTS(USART_TypeDef * LPUARTx)2389 __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
2390 {
2391 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2392 }
2393
2394 /**
2395 * @brief Disable Wake Up from Stop Mode Interrupt
2396 * @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP
2397 * @param LPUARTx LPUART Instance
2398 * @retval None
2399 */
LL_LPUART_DisableIT_WKUP(USART_TypeDef * LPUARTx)2400 __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
2401 {
2402 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
2403 }
2404
2405 #if defined(USART_CR1_FIFOEN)
2406 /**
2407 * @brief Disable TX FIFO Threshold Interrupt
2408 * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT
2409 * @param LPUARTx LPUART Instance
2410 * @retval None
2411 */
LL_LPUART_DisableIT_TXFT(USART_TypeDef * LPUARTx)2412 __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
2413 {
2414 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2415 }
2416
2417 /**
2418 * @brief Disable RX FIFO Threshold Interrupt
2419 * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT
2420 * @param LPUARTx LPUART Instance
2421 * @retval None
2422 */
LL_LPUART_DisableIT_RXFT(USART_TypeDef * LPUARTx)2423 __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
2424 {
2425 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2426 }
2427 #endif /* USART_CR1_FIFOEN */
2428
2429 /**
2430 * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled.
2431 * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
2432 * @param LPUARTx LPUART Instance
2433 * @retval State of bit (1 or 0).
2434 */
LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef * LPUARTx)2435 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx)
2436 {
2437 return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
2438 }
2439
2440 #if defined(USART_CR1_FIFOEN)
2441 /* Legacy define */
2442 #define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE
2443
2444 /**
2445 * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
2446 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE
2447 * @param LPUARTx LPUART Instance
2448 * @retval State of bit (1 or 0).
2449 */
LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef * LPUARTx)2450 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
2451 {
2452 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
2453 }
2454 #else
2455
2456 /**
2457 * @brief Check if the LPUART RX Not Empty Interrupt is enabled or disabled.
2458 * @rmtoll CR1 RXNEIE LL_LPUART_IsEnabledIT_RXNE
2459 * @param LPUARTx LPUART Instance
2460 * @retval State of bit (1 or 0).
2461 */
LL_LPUART_IsEnabledIT_RXNE(const USART_TypeDef * LPUARTx)2462 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE(const USART_TypeDef *LPUARTx)
2463 {
2464 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1UL : 0UL);
2465 }
2466 #endif /* USART_CR1_FIFOEN */
2467
2468 /**
2469 * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
2470 * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC
2471 * @param LPUARTx LPUART Instance
2472 * @retval State of bit (1 or 0).
2473 */
LL_LPUART_IsEnabledIT_TC(const USART_TypeDef * LPUARTx)2474 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx)
2475 {
2476 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
2477 }
2478
2479 #if defined(USART_CR1_FIFOEN)
2480 /* Legacy define */
2481 #define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF
2482
2483 /**
2484 * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
2485 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF
2486 * @param LPUARTx LPUART Instance
2487 * @retval State of bit (1 or 0).
2488 */
LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef * LPUARTx)2489 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx)
2490 {
2491 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
2492 }
2493 #else
2494
2495 /**
2496 * @brief Check if the LPUART TX Empty Interrupt is enabled or disabled.
2497 * @rmtoll CR1 TXEIE LL_LPUART_IsEnabledIT_TXE
2498 * @param LPUARTx LPUART Instance
2499 * @retval State of bit (1 or 0).
2500 */
LL_LPUART_IsEnabledIT_TXE(const USART_TypeDef * LPUARTx)2501 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE(const USART_TypeDef *LPUARTx)
2502 {
2503 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1UL : 0UL);
2504 }
2505 #endif /* USART_CR1_FIFOEN */
2506
2507 /**
2508 * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled.
2509 * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE
2510 * @param LPUARTx LPUART Instance
2511 * @retval State of bit (1 or 0).
2512 */
LL_LPUART_IsEnabledIT_PE(const USART_TypeDef * LPUARTx)2513 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx)
2514 {
2515 return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
2516 }
2517
2518 /**
2519 * @brief Check if the LPUART Character Match Interrupt is enabled or disabled.
2520 * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM
2521 * @param LPUARTx LPUART Instance
2522 * @retval State of bit (1 or 0).
2523 */
LL_LPUART_IsEnabledIT_CM(const USART_TypeDef * LPUARTx)2524 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx)
2525 {
2526 return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
2527 }
2528
2529 #if defined(USART_CR1_FIFOEN)
2530 /**
2531 * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
2532 * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
2533 * @param LPUARTx LPUART Instance
2534 * @retval State of bit (1 or 0).
2535 */
LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef * LPUARTx)2536 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx)
2537 {
2538 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
2539 }
2540
2541 /**
2542 * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
2543 * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF
2544 * @param LPUARTx LPUART Instance
2545 * @retval State of bit (1 or 0).
2546 */
LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef * LPUARTx)2547 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx)
2548 {
2549 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
2550 }
2551 #endif /* USART_CR1_FIFOEN */
2552
2553 /**
2554 * @brief Check if the LPUART Error Interrupt is enabled or disabled.
2555 * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR
2556 * @param LPUARTx LPUART Instance
2557 * @retval State of bit (1 or 0).
2558 */
LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef * LPUARTx)2559 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx)
2560 {
2561 return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
2562 }
2563
2564 /**
2565 * @brief Check if the LPUART CTS Interrupt is enabled or disabled.
2566 * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
2567 * @param LPUARTx LPUART Instance
2568 * @retval State of bit (1 or 0).
2569 */
LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef * LPUARTx)2570 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx)
2571 {
2572 return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
2573 }
2574
2575 /**
2576 * @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
2577 * @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
2578 * @param LPUARTx LPUART Instance
2579 * @retval State of bit (1 or 0).
2580 */
LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef * LPUARTx)2581 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx)
2582 {
2583 return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
2584 }
2585
2586 #if defined(USART_CR1_FIFOEN)
2587 /**
2588 * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
2589 * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT
2590 * @param LPUARTx LPUART Instance
2591 * @retval State of bit (1 or 0).
2592 */
LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef * LPUARTx)2593 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx)
2594 {
2595 return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
2596 }
2597
2598 /**
2599 * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
2600 * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT
2601 * @param LPUARTx LPUART Instance
2602 * @retval State of bit (1 or 0).
2603 */
LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef * LPUARTx)2604 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx)
2605 {
2606 return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
2607 }
2608 #endif /* USART_CR1_FIFOEN */
2609
2610 /**
2611 * @}
2612 */
2613
2614 /** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
2615 * @{
2616 */
2617
2618 /**
2619 * @brief Enable DMA Mode for reception
2620 * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX
2621 * @param LPUARTx LPUART Instance
2622 * @retval None
2623 */
LL_LPUART_EnableDMAReq_RX(USART_TypeDef * LPUARTx)2624 __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
2625 {
2626 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2627 }
2628
2629 /**
2630 * @brief Disable DMA Mode for reception
2631 * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX
2632 * @param LPUARTx LPUART Instance
2633 * @retval None
2634 */
LL_LPUART_DisableDMAReq_RX(USART_TypeDef * LPUARTx)2635 __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
2636 {
2637 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2638 }
2639
2640 /**
2641 * @brief Check if DMA Mode is enabled for reception
2642 * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
2643 * @param LPUARTx LPUART Instance
2644 * @retval State of bit (1 or 0).
2645 */
LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef * LPUARTx)2646 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx)
2647 {
2648 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
2649 }
2650
2651 /**
2652 * @brief Enable DMA Mode for transmission
2653 * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX
2654 * @param LPUARTx LPUART Instance
2655 * @retval None
2656 */
LL_LPUART_EnableDMAReq_TX(USART_TypeDef * LPUARTx)2657 __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
2658 {
2659 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2660 }
2661
2662 /**
2663 * @brief Disable DMA Mode for transmission
2664 * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX
2665 * @param LPUARTx LPUART Instance
2666 * @retval None
2667 */
LL_LPUART_DisableDMAReq_TX(USART_TypeDef * LPUARTx)2668 __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
2669 {
2670 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2671 }
2672
2673 /**
2674 * @brief Check if DMA Mode is enabled for transmission
2675 * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
2676 * @param LPUARTx LPUART Instance
2677 * @retval State of bit (1 or 0).
2678 */
LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef * LPUARTx)2679 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx)
2680 {
2681 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
2682 }
2683
2684 /**
2685 * @brief Enable DMA Disabling on Reception Error
2686 * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
2687 * @param LPUARTx LPUART Instance
2688 * @retval None
2689 */
LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef * LPUARTx)2690 __STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2691 {
2692 SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2693 }
2694
2695 /**
2696 * @brief Disable DMA Disabling on Reception Error
2697 * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
2698 * @param LPUARTx LPUART Instance
2699 * @retval None
2700 */
LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef * LPUARTx)2701 __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2702 {
2703 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2704 }
2705
2706 /**
2707 * @brief Indicate if DMA Disabling on Reception Error is disabled
2708 * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
2709 * @param LPUARTx LPUART Instance
2710 * @retval State of bit (1 or 0).
2711 */
LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef * LPUARTx)2712 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx)
2713 {
2714 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
2715 }
2716
2717 /**
2718 * @brief Get the LPUART data register address used for DMA transfer
2719 * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n
2720 * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr
2721 * @param LPUARTx LPUART Instance
2722 * @param Direction This parameter can be one of the following values:
2723 * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
2724 * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
2725 * @retval Address of data register
2726 */
LL_LPUART_DMA_GetRegAddr(const USART_TypeDef * LPUARTx,uint32_t Direction)2727 __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction)
2728 {
2729 uint32_t data_reg_addr;
2730
2731 if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
2732 {
2733 /* return address of TDR register */
2734 data_reg_addr = (uint32_t) &(LPUARTx->TDR);
2735 }
2736 else
2737 {
2738 /* return address of RDR register */
2739 data_reg_addr = (uint32_t) &(LPUARTx->RDR);
2740 }
2741
2742 return data_reg_addr;
2743 }
2744
2745 /**
2746 * @}
2747 */
2748
2749 /** @defgroup LPUART_LL_EF_Data_Management Data_Management
2750 * @{
2751 */
2752
2753 /**
2754 * @brief Read Receiver Data register (Receive Data value, 8 bits)
2755 * @rmtoll RDR RDR LL_LPUART_ReceiveData8
2756 * @param LPUARTx LPUART Instance
2757 * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
2758 */
LL_LPUART_ReceiveData8(const USART_TypeDef * LPUARTx)2759 __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx)
2760 {
2761 return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
2762 }
2763
2764 /**
2765 * @brief Read Receiver Data register (Receive Data value, 9 bits)
2766 * @rmtoll RDR RDR LL_LPUART_ReceiveData9
2767 * @param LPUARTx LPUART Instance
2768 * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
2769 */
LL_LPUART_ReceiveData9(const USART_TypeDef * LPUARTx)2770 __STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx)
2771 {
2772 return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
2773 }
2774
2775 /**
2776 * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
2777 * @rmtoll TDR TDR LL_LPUART_TransmitData8
2778 * @param LPUARTx LPUART Instance
2779 * @param Value between Min_Data=0x00 and Max_Data=0xFF
2780 * @retval None
2781 */
LL_LPUART_TransmitData8(USART_TypeDef * LPUARTx,uint8_t Value)2782 __STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
2783 {
2784 LPUARTx->TDR = Value;
2785 }
2786
2787 /**
2788 * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
2789 * @rmtoll TDR TDR LL_LPUART_TransmitData9
2790 * @param LPUARTx LPUART Instance
2791 * @param Value between Min_Data=0x00 and Max_Data=0x1FF
2792 * @retval None
2793 */
LL_LPUART_TransmitData9(USART_TypeDef * LPUARTx,uint16_t Value)2794 __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
2795 {
2796 LPUARTx->TDR = Value & 0x1FFUL;
2797 }
2798
2799 /**
2800 * @}
2801 */
2802
2803 /** @defgroup LPUART_LL_EF_Execution Execution
2804 * @{
2805 */
2806
2807 /**
2808 * @brief Request Break sending
2809 * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending
2810 * @param LPUARTx LPUART Instance
2811 * @retval None
2812 */
LL_LPUART_RequestBreakSending(USART_TypeDef * LPUARTx)2813 __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
2814 {
2815 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
2816 }
2817
2818 /**
2819 * @brief Put LPUART in mute mode and set the RWU flag
2820 * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode
2821 * @param LPUARTx LPUART Instance
2822 * @retval None
2823 */
LL_LPUART_RequestEnterMuteMode(USART_TypeDef * LPUARTx)2824 __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
2825 {
2826 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
2827 }
2828
2829 /**
2830 @if USART_CR1_FIFOEN
2831 * @brief Request a Receive Data and FIFO flush
2832 * @note Allows to discard the received data without reading them, and avoid an overrun
2833 * condition.
2834 @else
2835 * @brief Request a Receive Data flush
2836 @endif
2837 * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush
2838 * @param LPUARTx LPUART Instance
2839 * @retval None
2840 */
LL_LPUART_RequestRxDataFlush(USART_TypeDef * LPUARTx)2841 __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
2842 {
2843 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
2844 }
2845
2846 /**
2847 * @}
2848 */
2849
2850 #if defined(USE_FULL_LL_DRIVER)
2851 /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
2852 * @{
2853 */
2854 ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx);
2855 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct);
2856 void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
2857 /**
2858 * @}
2859 */
2860 #endif /* USE_FULL_LL_DRIVER */
2861
2862 /**
2863 * @}
2864 */
2865
2866 /**
2867 * @}
2868 */
2869
2870 #endif /* LPUART1 */
2871
2872 /**
2873 * @}
2874 */
2875
2876 #ifdef __cplusplus
2877 }
2878 #endif
2879
2880 #endif /* STM32L4xx_LL_LPUART_H */
2881
2882
