1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L4xx_LL_LPTIM_H
21 #define STM32L4xx_LL_LPTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l4xx.h"
29
30 /** @addtogroup STM32L4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (LPTIM1) || defined (LPTIM2)
35
36 /** @defgroup LPTIM_LL LPTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44
45 /* Private macros ------------------------------------------------------------*/
46 #if defined(USE_FULL_LL_DRIVER)
47 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
48 * @{
49 */
50 /**
51 * @}
52 */
53 #endif /*USE_FULL_LL_DRIVER*/
54
55 /* Exported types ------------------------------------------------------------*/
56 #if defined(USE_FULL_LL_DRIVER)
57 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
58 * @{
59 */
60
61 /**
62 * @brief LPTIM Init structure definition
63 */
64 typedef struct
65 {
66 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
67 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
68
69 This feature can be modified afterwards using unitary
70 function @ref LL_LPTIM_SetClockSource().*/
71
72 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
73 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
74
75 This feature can be modified afterwards using using unitary
76 function @ref LL_LPTIM_SetPrescaler().*/
77
78 uint32_t Waveform; /*!< Specifies the waveform shape.
79 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
80
81 This feature can be modified afterwards using unitary
82 function @ref LL_LPTIM_ConfigOutput().*/
83
84 uint32_t Polarity; /*!< Specifies waveform polarity.
85 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
86
87 This feature can be modified afterwards using unitary
88 function @ref LL_LPTIM_ConfigOutput().*/
89 } LL_LPTIM_InitTypeDef;
90
91 /**
92 * @}
93 */
94 #endif /* USE_FULL_LL_DRIVER */
95
96 /* Exported constants --------------------------------------------------------*/
97 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
98 * @{
99 */
100
101 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
102 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
103 * @{
104 */
105 #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */
106 #define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
107 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
108 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
109 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
110 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
111 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
112 #if defined(LPTIM_RCR_REP)
113 #define LL_LPTIM_ISR_UE LPTIM_ISR_UE /*!< Update event */
114 #define LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK /*!< Repetition register update OK */
115 #endif
116 /**
117 * @}
118 */
119
120 /** @defgroup LPTIM_LL_EC_IT IT Defines
121 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
122 * @{
123 */
124 #define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */
125 #define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */
126 #define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */
127 #define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */
128 #define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */
129 #define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */
130 #define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */
131 #if defined(LPTIM_RCR_REP)
132 #define LL_LPTIM_IER_UEIE LPTIM_IER_UEIE /*!< Update event */
133 #define LL_LPTIM_IER_REPOKIE LPTIM_IER_REPOKIE /*!< Repetition register update OK */
134 #endif
135 /**
136 * @}
137 */
138
139 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
140 * @{
141 */
142 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
143 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
144 /**
145 * @}
146 */
147
148 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
149 * @{
150 */
151 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
152 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
153 /**
154 * @}
155 */
156
157 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
158 * @{
159 */
160 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
161 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
162 /**
163 * @}
164 */
165
166 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
167 * @{
168 */
169 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
170 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
171 /**
172 * @}
173 */
174
175 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
176 * @{
177 */
178 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
179 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
180 /**
181 * @}
182 */
183
184 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
185 * @{
186 */
187 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
188 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
189 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
190 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
191 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
192 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
193 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
194 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
195 /**
196 * @}
197 */
198
199 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
200 * @{
201 */
202 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
203 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
204 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
205 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
206 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
207 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
208 #define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
209 #define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /*!<External input trigger is connected to COMP2 output*/
210 /**
211 * @}
212 */
213
214 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
215 * @{
216 */
217 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
218 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
219 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
220 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
221 /**
222 * @}
223 */
224
225 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
226 * @{
227 */
228 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
229 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
230 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
231 /**
232 * @}
233 */
234
235 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
236 * @{
237 */
238 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
239 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
240 /**
241 * @}
242 */
243
244 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
245 * @{
246 */
247 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
248 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
249 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
250 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
251 /**
252 * @}
253 */
254
255 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
256 * @{
257 */
258 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
259 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
260 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
261 /**
262 * @}
263 */
264
265 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
266 * @{
267 */
268 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
269 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
270 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
271 /**
272 * @}
273 */
274
275 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
276 * @{
277 */
278 #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U /*!< For LPTIM1 and LPTIM2 */
279 #define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_OR_OR_0 /*!< For LPTIM1 and LPTIM2 */
280 #define LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM2 */
281 #define LL_LPTIM_INPUT1_SRC_COMP1_COMP2 LPTIM_OR_OR /*!< For LPTIM2 */
282 /**
283 * @}
284 */
285
286 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
287 * @{
288 */
289 #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U /*!< For LPTIM1 */
290 #define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM1 */
291 /**
292 * @}
293 */
294
295 /**
296 * @}
297 */
298
299 /* Exported macro ------------------------------------------------------------*/
300 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
301 * @{
302 */
303
304 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
305 * @{
306 */
307
308 /**
309 * @brief Write a value in LPTIM register
310 * @param __INSTANCE__ LPTIM Instance
311 * @param __REG__ Register to be written
312 * @param __VALUE__ Value to be written in the register
313 * @retval None
314 */
315 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
316
317 /**
318 * @brief Read a value in LPTIM register
319 * @param __INSTANCE__ LPTIM Instance
320 * @param __REG__ Register to be read
321 * @retval Register value
322 */
323 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
324 /**
325 * @}
326 */
327
328 /**
329 * @}
330 */
331
332 /* Exported functions --------------------------------------------------------*/
333 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
334 * @{
335 */
336
337 #if defined(USE_FULL_LL_DRIVER)
338 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
339 * @{
340 */
341
342 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
343 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
344 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
345 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
346 /**
347 * @}
348 */
349 #endif /* USE_FULL_LL_DRIVER */
350
351 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
352 * @{
353 */
354
355 /**
356 * @brief Enable the LPTIM instance
357 * @note After setting the ENABLE bit, a delay of two counter clock is needed
358 * before the LPTIM instance is actually enabled.
359 * @rmtoll CR ENABLE LL_LPTIM_Enable
360 * @param LPTIMx Low-Power Timer instance
361 * @retval None
362 */
LL_LPTIM_Enable(LPTIM_TypeDef * LPTIMx)363 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
364 {
365 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
366 }
367
368 /**
369 * @brief Indicates whether the LPTIM instance is enabled.
370 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
371 * @param LPTIMx Low-Power Timer instance
372 * @retval State of bit (1 or 0).
373 */
LL_LPTIM_IsEnabled(const LPTIM_TypeDef * LPTIMx)374 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx)
375 {
376 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
377 }
378
379 /**
380 * @brief Starts the LPTIM counter in the desired mode.
381 * @note LPTIM instance must be enabled before starting the counter.
382 * @note It is possible to change on the fly from One Shot mode to
383 * Continuous mode.
384 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
385 * CR SNGSTRT LL_LPTIM_StartCounter
386 * @param LPTIMx Low-Power Timer instance
387 * @param OperatingMode This parameter can be one of the following values:
388 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
389 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
390 * @retval None
391 */
LL_LPTIM_StartCounter(LPTIM_TypeDef * LPTIMx,uint32_t OperatingMode)392 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
393 {
394 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
395 }
396
397 #if defined(LPTIM_CR_RSTARE)
398 /**
399 * @brief Enable reset after read.
400 * @note After calling this function any read access to LPTIM_CNT
401 * register will asynchronously reset the LPTIM_CNT register content.
402 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
403 * @param LPTIMx Low-Power Timer instance
404 * @retval None
405 */
LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef * LPTIMx)406 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
407 {
408 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
409 }
410
411 /**
412 * @brief Disable reset after read.
413 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
414 * @param LPTIMx Low-Power Timer instance
415 * @retval None
416 */
LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef * LPTIMx)417 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
418 {
419 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
420 }
421
422 /**
423 * @brief Indicate whether the reset after read feature is enabled.
424 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
425 * @param LPTIMx Low-Power Timer instance
426 * @retval State of bit (1 or 0).
427 */
LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef * LPTIMx)428 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx)
429 {
430 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
431 }
432 #endif
433
434 #if defined(LPTIM_CR_COUNTRST)
435 /**
436 * @brief Reset of the LPTIM_CNT counter register (synchronous).
437 * @note Due to the synchronous nature of this reset, it only takes
438 * place after a synchronization delay of 3 LPTIM core clock cycles
439 * (LPTIM core clock may be different from APB clock).
440 * @note COUNTRST is automatically cleared by hardware
441 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
442 * @param LPTIMx Low-Power Timer instance
443 * @retval None
444 */
LL_LPTIM_ResetCounter(LPTIM_TypeDef * LPTIMx)445 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
446 {
447 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
448 }
449 #endif
450
451 /**
452 * @brief Set the LPTIM registers update mode (enable/disable register preload)
453 * @note This function must be called when the LPTIM instance is disabled.
454 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
455 * @param LPTIMx Low-Power Timer instance
456 * @param UpdateMode This parameter can be one of the following values:
457 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
458 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
459 * @retval None
460 */
LL_LPTIM_SetUpdateMode(LPTIM_TypeDef * LPTIMx,uint32_t UpdateMode)461 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
462 {
463 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
464 }
465
466 /**
467 * @brief Get the LPTIM registers update mode
468 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
469 * @param LPTIMx Low-Power Timer instance
470 * @retval Returned value can be one of the following values:
471 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
472 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
473 */
LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef * LPTIMx)474 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx)
475 {
476 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
477 }
478
479 /**
480 * @brief Set the auto reload value
481 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
482 * @note After a write to the LPTIMx_ARR register a new write operation to the
483 * same register can only be performed when the previous write operation
484 * is completed. Any successive write before the ARROK flag is set, will
485 * lead to unpredictable results.
486 * @note autoreload value be strictly greater than the compare value.
487 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
488 * @param LPTIMx Low-Power Timer instance
489 * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
490 * @retval None
491 */
LL_LPTIM_SetAutoReload(LPTIM_TypeDef * LPTIMx,uint32_t AutoReload)492 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
493 {
494 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
495 }
496
497 /**
498 * @brief Get actual auto reload value
499 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
500 * @param LPTIMx Low-Power Timer instance
501 * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
502 */
LL_LPTIM_GetAutoReload(const LPTIM_TypeDef * LPTIMx)503 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx)
504 {
505 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
506 }
507
508 #if defined(LPTIM_RCR_REP)
509 /**
510 * @brief Set the repetition value
511 * @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled
512 * @rmtoll RCR REP LL_LPTIM_SetRepetition
513 * @param LPTIMx Low-Power Timer instance
514 * @param Repetition Value between Min_Data=0x00 and Max_Data=0xFF
515 * @retval None
516 */
LL_LPTIM_SetRepetition(LPTIM_TypeDef * LPTIMx,uint32_t Repetition)517 __STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repetition)
518 {
519 MODIFY_REG(LPTIMx->RCR, LPTIM_RCR_REP, Repetition);
520 }
521
522 /**
523 * @brief Get the repetition value
524 * @rmtoll RCR REP LL_LPTIM_GetRepetition
525 * @param LPTIMx Low-Power Timer instance
526 * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF
527 */
LL_LPTIM_GetRepetition(const LPTIM_TypeDef * LPTIMx)528 __STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(const LPTIM_TypeDef *LPTIMx)
529 {
530 return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP));
531 }
532 #endif
533
534 /**
535 * @brief Set the compare value
536 * @note After a write to the LPTIMx_CMP register a new write operation to the
537 * same register can only be performed when the previous write operation
538 * is completed. Any successive write before the CMPOK flag is set, will
539 * lead to unpredictable results.
540 * @rmtoll CMP CMP LL_LPTIM_SetCompare
541 * @param LPTIMx Low-Power Timer instance
542 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
543 * @retval None
544 */
LL_LPTIM_SetCompare(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)545 __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
546 {
547 MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
548 }
549
550 /**
551 * @brief Get actual compare value
552 * @rmtoll CMP CMP LL_LPTIM_GetCompare
553 * @param LPTIMx Low-Power Timer instance
554 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
555 */
LL_LPTIM_GetCompare(const LPTIM_TypeDef * LPTIMx)556 __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(const LPTIM_TypeDef *LPTIMx)
557 {
558 return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
559 }
560
561 /**
562 * @brief Get actual counter value
563 * @note When the LPTIM instance is running with an asynchronous clock, reading
564 * the LPTIMx_CNT register may return unreliable values. So in this case
565 * it is necessary to perform two consecutive read accesses and verify
566 * that the two returned values are identical.
567 * @rmtoll CNT CNT LL_LPTIM_GetCounter
568 * @param LPTIMx Low-Power Timer instance
569 * @retval Counter value
570 */
LL_LPTIM_GetCounter(const LPTIM_TypeDef * LPTIMx)571 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx)
572 {
573 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
574 }
575
576 /**
577 * @brief Set the counter mode (selection of the LPTIM counter clock source).
578 * @note The counter mode can be set only when the LPTIM instance is disabled.
579 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
580 * @param LPTIMx Low-Power Timer instance
581 * @param CounterMode This parameter can be one of the following values:
582 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
583 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
584 * @retval None
585 */
LL_LPTIM_SetCounterMode(LPTIM_TypeDef * LPTIMx,uint32_t CounterMode)586 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
587 {
588 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
589 }
590
591 /**
592 * @brief Get the counter mode
593 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
594 * @param LPTIMx Low-Power Timer instance
595 * @retval Returned value can be one of the following values:
596 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
597 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
598 */
LL_LPTIM_GetCounterMode(const LPTIM_TypeDef * LPTIMx)599 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx)
600 {
601 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
602 }
603
604 /**
605 * @brief Configure the LPTIM instance output (LPTIMx_OUT)
606 * @note This function must be called when the LPTIM instance is disabled.
607 * @note Regarding the LPTIM output polarity the change takes effect
608 * immediately, so the output default value will change immediately after
609 * the polarity is re-configured, even before the timer is enabled.
610 * @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n
611 * CFGR WAVPOL LL_LPTIM_ConfigOutput
612 * @param LPTIMx Low-Power Timer instance
613 * @param Waveform This parameter can be one of the following values:
614 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
615 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
616 * @param Polarity This parameter can be one of the following values:
617 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
618 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
619 * @retval None
620 */
LL_LPTIM_ConfigOutput(LPTIM_TypeDef * LPTIMx,uint32_t Waveform,uint32_t Polarity)621 __STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
622 {
623 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
624 }
625
626 /**
627 * @brief Set waveform shape
628 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
629 * @param LPTIMx Low-Power Timer instance
630 * @param Waveform This parameter can be one of the following values:
631 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
632 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
633 * @retval None
634 */
LL_LPTIM_SetWaveform(LPTIM_TypeDef * LPTIMx,uint32_t Waveform)635 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
636 {
637 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
638 }
639
640 /**
641 * @brief Get actual waveform shape
642 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
643 * @param LPTIMx Low-Power Timer instance
644 * @retval Returned value can be one of the following values:
645 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
646 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
647 */
LL_LPTIM_GetWaveform(const LPTIM_TypeDef * LPTIMx)648 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx)
649 {
650 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
651 }
652
653 /**
654 * @brief Set output polarity
655 * @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity
656 * @param LPTIMx Low-Power Timer instance
657 * @param Polarity This parameter can be one of the following values:
658 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
659 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
660 * @retval None
661 */
LL_LPTIM_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Polarity)662 __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
663 {
664 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
665 }
666
667 /**
668 * @brief Get actual output polarity
669 * @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity
670 * @param LPTIMx Low-Power Timer instance
671 * @retval Returned value can be one of the following values:
672 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
673 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
674 */
LL_LPTIM_GetPolarity(const LPTIM_TypeDef * LPTIMx)675 __STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(const LPTIM_TypeDef *LPTIMx)
676 {
677 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
678 }
679
680 /**
681 * @brief Set actual prescaler division ratio.
682 * @note This function must be called when the LPTIM instance is disabled.
683 * @note When the LPTIM is configured to be clocked by an internal clock source
684 * and the LPTIM counter is configured to be updated by active edges
685 * detected on the LPTIM external Input1, the internal clock provided to
686 * the LPTIM must be not be prescaled.
687 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
688 * @param LPTIMx Low-Power Timer instance
689 * @param Prescaler This parameter can be one of the following values:
690 * @arg @ref LL_LPTIM_PRESCALER_DIV1
691 * @arg @ref LL_LPTIM_PRESCALER_DIV2
692 * @arg @ref LL_LPTIM_PRESCALER_DIV4
693 * @arg @ref LL_LPTIM_PRESCALER_DIV8
694 * @arg @ref LL_LPTIM_PRESCALER_DIV16
695 * @arg @ref LL_LPTIM_PRESCALER_DIV32
696 * @arg @ref LL_LPTIM_PRESCALER_DIV64
697 * @arg @ref LL_LPTIM_PRESCALER_DIV128
698 * @retval None
699 */
LL_LPTIM_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Prescaler)700 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
701 {
702 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
703 }
704
705 /**
706 * @brief Get actual prescaler division ratio.
707 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
708 * @param LPTIMx Low-Power Timer instance
709 * @retval Returned value can be one of the following values:
710 * @arg @ref LL_LPTIM_PRESCALER_DIV1
711 * @arg @ref LL_LPTIM_PRESCALER_DIV2
712 * @arg @ref LL_LPTIM_PRESCALER_DIV4
713 * @arg @ref LL_LPTIM_PRESCALER_DIV8
714 * @arg @ref LL_LPTIM_PRESCALER_DIV16
715 * @arg @ref LL_LPTIM_PRESCALER_DIV32
716 * @arg @ref LL_LPTIM_PRESCALER_DIV64
717 * @arg @ref LL_LPTIM_PRESCALER_DIV128
718 */
LL_LPTIM_GetPrescaler(const LPTIM_TypeDef * LPTIMx)719 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx)
720 {
721 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
722 }
723
724 /**
725 * @brief Set LPTIM input 1 source (default GPIO).
726 * @rmtoll OR OR LL_LPTIM_SetInput1Src
727 * @param LPTIMx Low-Power Timer instance
728 * @param Src This parameter can be one of the following values:
729 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
730 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
731 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP2
732 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1_COMP2
733 * @retval None
734 */
LL_LPTIM_SetInput1Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)735 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
736 {
737 MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src);
738 }
739
740 /**
741 * @brief Set LPTIM input 2 source (default GPIO).
742 * @rmtoll OR OR LL_LPTIM_SetInput2Src
743 * @param LPTIMx Low-Power Timer instance
744 * @param Src This parameter can be one of the following values:
745 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
746 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
747 * @retval None
748 */
LL_LPTIM_SetInput2Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)749 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
750 {
751 MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src);
752 }
753
754 /**
755 * @}
756 */
757
758 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
759 * @{
760 */
761
762 /**
763 * @brief Enable the timeout function
764 * @note This function must be called when the LPTIM instance is disabled.
765 * @note The first trigger event will start the timer, any successive trigger
766 * event will reset the counter and the timer will restart.
767 * @note The timeout value corresponds to the compare value; if no trigger
768 * occurs within the expected time frame, the MCU is waked-up by the
769 * compare match event.
770 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
771 * @param LPTIMx Low-Power Timer instance
772 * @retval None
773 */
LL_LPTIM_EnableTimeout(LPTIM_TypeDef * LPTIMx)774 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
775 {
776 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
777 }
778
779 /**
780 * @brief Disable the timeout function
781 * @note This function must be called when the LPTIM instance is disabled.
782 * @note A trigger event arriving when the timer is already started will be
783 * ignored.
784 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
785 * @param LPTIMx Low-Power Timer instance
786 * @retval None
787 */
LL_LPTIM_DisableTimeout(LPTIM_TypeDef * LPTIMx)788 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
789 {
790 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
791 }
792
793 /**
794 * @brief Indicate whether the timeout function is enabled.
795 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
796 * @param LPTIMx Low-Power Timer instance
797 * @retval State of bit (1 or 0).
798 */
LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef * LPTIMx)799 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx)
800 {
801 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
802 }
803
804 /**
805 * @brief Start the LPTIM counter
806 * @note This function must be called when the LPTIM instance is disabled.
807 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
808 * @param LPTIMx Low-Power Timer instance
809 * @retval None
810 */
LL_LPTIM_TrigSw(LPTIM_TypeDef * LPTIMx)811 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
812 {
813 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
814 }
815
816 /**
817 * @brief Configure the external trigger used as a trigger event for the LPTIM.
818 * @note This function must be called when the LPTIM instance is disabled.
819 * @note An internal clock source must be present when a digital filter is
820 * required for the trigger.
821 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
822 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
823 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
824 * @param LPTIMx Low-Power Timer instance
825 * @param Source This parameter can be one of the following values:
826 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
827 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
828 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
829 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
830 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
831 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
832 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
833 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
834 * @param Filter This parameter can be one of the following values:
835 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
836 * @arg @ref LL_LPTIM_TRIG_FILTER_2
837 * @arg @ref LL_LPTIM_TRIG_FILTER_4
838 * @arg @ref LL_LPTIM_TRIG_FILTER_8
839 * @param Polarity This parameter can be one of the following values:
840 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
841 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
842 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
843 * @retval None
844 */
LL_LPTIM_ConfigTrigger(LPTIM_TypeDef * LPTIMx,uint32_t Source,uint32_t Filter,uint32_t Polarity)845 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
846 {
847 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
848 }
849
850 /**
851 * @brief Get actual external trigger source.
852 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
853 * @param LPTIMx Low-Power Timer instance
854 * @retval Returned value can be one of the following values:
855 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
856 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
857 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
858 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
859 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
860 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
861 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
862 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
863 */
LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef * LPTIMx)864 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx)
865 {
866 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
867 }
868
869 /**
870 * @brief Get actual external trigger filter.
871 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
872 * @param LPTIMx Low-Power Timer instance
873 * @retval Returned value can be one of the following values:
874 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
875 * @arg @ref LL_LPTIM_TRIG_FILTER_2
876 * @arg @ref LL_LPTIM_TRIG_FILTER_4
877 * @arg @ref LL_LPTIM_TRIG_FILTER_8
878 */
LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef * LPTIMx)879 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx)
880 {
881 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
882 }
883
884 /**
885 * @brief Get actual external trigger polarity.
886 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
887 * @param LPTIMx Low-Power Timer instance
888 * @retval Returned value can be one of the following values:
889 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
890 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
891 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
892 */
LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef * LPTIMx)893 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx)
894 {
895 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
896 }
897
898 /**
899 * @}
900 */
901
902 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
903 * @{
904 */
905
906 /**
907 * @brief Set the source of the clock used by the LPTIM instance.
908 * @note This function must be called when the LPTIM instance is disabled.
909 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
910 * @param LPTIMx Low-Power Timer instance
911 * @param ClockSource This parameter can be one of the following values:
912 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
913 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
914 * @retval None
915 */
LL_LPTIM_SetClockSource(LPTIM_TypeDef * LPTIMx,uint32_t ClockSource)916 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
917 {
918 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
919 }
920
921 /**
922 * @brief Get actual LPTIM instance clock source.
923 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
924 * @param LPTIMx Low-Power Timer instance
925 * @retval Returned value can be one of the following values:
926 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
927 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
928 */
LL_LPTIM_GetClockSource(const LPTIM_TypeDef * LPTIMx)929 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx)
930 {
931 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
932 }
933
934 /**
935 * @brief Configure the active edge or edges used by the counter when
936 the LPTIM is clocked by an external clock source.
937 * @note This function must be called when the LPTIM instance is disabled.
938 * @note When both external clock signal edges are considered active ones,
939 * the LPTIM must also be clocked by an internal clock source with a
940 * frequency equal to at least four times the external clock frequency.
941 * @note An internal clock source must be present when a digital filter is
942 * required for external clock.
943 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
944 * CFGR CKPOL LL_LPTIM_ConfigClock
945 * @param LPTIMx Low-Power Timer instance
946 * @param ClockFilter This parameter can be one of the following values:
947 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
948 * @arg @ref LL_LPTIM_CLK_FILTER_2
949 * @arg @ref LL_LPTIM_CLK_FILTER_4
950 * @arg @ref LL_LPTIM_CLK_FILTER_8
951 * @param ClockPolarity This parameter can be one of the following values:
952 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
953 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
954 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
955 * @retval None
956 */
LL_LPTIM_ConfigClock(LPTIM_TypeDef * LPTIMx,uint32_t ClockFilter,uint32_t ClockPolarity)957 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
958 {
959 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
960 }
961
962 /**
963 * @brief Get actual clock polarity
964 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
965 * @param LPTIMx Low-Power Timer instance
966 * @retval Returned value can be one of the following values:
967 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
968 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
969 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
970 */
LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef * LPTIMx)971 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx)
972 {
973 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
974 }
975
976 /**
977 * @brief Get actual clock digital filter
978 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
979 * @param LPTIMx Low-Power Timer instance
980 * @retval Returned value can be one of the following values:
981 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
982 * @arg @ref LL_LPTIM_CLK_FILTER_2
983 * @arg @ref LL_LPTIM_CLK_FILTER_4
984 * @arg @ref LL_LPTIM_CLK_FILTER_8
985 */
LL_LPTIM_GetClockFilter(const LPTIM_TypeDef * LPTIMx)986 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx)
987 {
988 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
989 }
990
991 /**
992 * @}
993 */
994
995 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
996 * @{
997 */
998
999 /**
1000 * @brief Configure the encoder mode.
1001 * @note This function must be called when the LPTIM instance is disabled.
1002 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
1003 * @param LPTIMx Low-Power Timer instance
1004 * @param EncoderMode This parameter can be one of the following values:
1005 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1006 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1007 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1008 * @retval None
1009 */
LL_LPTIM_SetEncoderMode(LPTIM_TypeDef * LPTIMx,uint32_t EncoderMode)1010 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
1011 {
1012 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
1013 }
1014
1015 /**
1016 * @brief Get actual encoder mode.
1017 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
1018 * @param LPTIMx Low-Power Timer instance
1019 * @retval Returned value can be one of the following values:
1020 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1021 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1022 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1023 */
LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef * LPTIMx)1024 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx)
1025 {
1026 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1027 }
1028
1029 /**
1030 * @brief Enable the encoder mode
1031 * @note This function must be called when the LPTIM instance is disabled.
1032 * @note In this mode the LPTIM instance must be clocked by an internal clock
1033 * source. Also, the prescaler division ratio must be equal to 1.
1034 * @note LPTIM instance must be configured in continuous mode prior enabling
1035 * the encoder mode.
1036 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
1037 * @param LPTIMx Low-Power Timer instance
1038 * @retval None
1039 */
LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef * LPTIMx)1040 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
1041 {
1042 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1043 }
1044
1045 /**
1046 * @brief Disable the encoder mode
1047 * @note This function must be called when the LPTIM instance is disabled.
1048 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
1049 * @param LPTIMx Low-Power Timer instance
1050 * @retval None
1051 */
LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef * LPTIMx)1052 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
1053 {
1054 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1055 }
1056
1057 /**
1058 * @brief Indicates whether the LPTIM operates in encoder mode.
1059 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
1060 * @param LPTIMx Low-Power Timer instance
1061 * @retval State of bit (1 or 0).
1062 */
LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef * LPTIMx)1063 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx)
1064 {
1065 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
1066 }
1067
1068 /**
1069 * @}
1070 */
1071
1072 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
1073 * @{
1074 */
1075
1076 /**
1077 * @brief Clear the compare match flag (CMPMCF)
1078 * @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
1079 * @param LPTIMx Low-Power Timer instance
1080 * @retval None
1081 */
LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef * LPTIMx)1082 __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
1083 {
1084 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
1085 }
1086
1087 /**
1088 * @brief Inform application whether a compare match interrupt has occurred.
1089 * @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
1090 * @param LPTIMx Low-Power Timer instance
1091 * @retval State of bit (1 or 0).
1092 */
LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef * LPTIMx)1093 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef *LPTIMx)
1094 {
1095 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
1096 }
1097
1098 /**
1099 * @brief Clear the autoreload match flag (ARRMCF)
1100 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
1101 * @param LPTIMx Low-Power Timer instance
1102 * @retval None
1103 */
LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef * LPTIMx)1104 __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
1105 {
1106 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
1107 }
1108
1109 /**
1110 * @brief Inform application whether a autoreload match interrupt has occurred.
1111 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
1112 * @param LPTIMx Low-Power Timer instance
1113 * @retval State of bit (1 or 0).
1114 */
LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef * LPTIMx)1115 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx)
1116 {
1117 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
1118 }
1119
1120 /**
1121 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1122 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1123 * @param LPTIMx Low-Power Timer instance
1124 * @retval None
1125 */
LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1126 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1127 {
1128 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1129 }
1130
1131 /**
1132 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1133 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1134 * @param LPTIMx Low-Power Timer instance
1135 * @retval State of bit (1 or 0).
1136 */
LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef * LPTIMx)1137 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
1138 {
1139 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
1140 }
1141
1142 /**
1143 * @brief Clear the compare register update interrupt flag (CMPOKCF).
1144 * @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
1145 * @param LPTIMx Low-Power Timer instance
1146 * @retval None
1147 */
LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef * LPTIMx)1148 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1149 {
1150 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
1151 }
1152
1153 /**
1154 * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully
1155 completed. If so, a new one can be initiated.
1156 * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
1157 * @param LPTIMx Low-Power Timer instance
1158 * @retval State of bit (1 or 0).
1159 */
LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef * LPTIMx)1160 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef *LPTIMx)
1161 {
1162 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
1163 }
1164
1165 /**
1166 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1167 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1168 * @param LPTIMx Low-Power Timer instance
1169 * @retval None
1170 */
LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef * LPTIMx)1171 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1172 {
1173 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1174 }
1175
1176 /**
1177 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
1178 completed. If so, a new one can be initiated.
1179 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1180 * @param LPTIMx Low-Power Timer instance
1181 * @retval State of bit (1 or 0).
1182 */
LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef * LPTIMx)1183 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx)
1184 {
1185 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
1186 }
1187
1188 /**
1189 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1190 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1191 * @param LPTIMx Low-Power Timer instance
1192 * @retval None
1193 */
LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef * LPTIMx)1194 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1195 {
1196 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1197 }
1198
1199 /**
1200 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
1201 operates in encoder mode).
1202 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1203 * @param LPTIMx Low-Power Timer instance
1204 * @retval State of bit (1 or 0).
1205 */
LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef * LPTIMx)1206 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx)
1207 {
1208 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
1209 }
1210
1211 /**
1212 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1213 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1214 * @param LPTIMx Low-Power Timer instance
1215 * @retval None
1216 */
LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef * LPTIMx)1217 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1218 {
1219 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1220 }
1221
1222 /**
1223 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
1224 operates in encoder mode).
1225 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1226 * @param LPTIMx Low-Power Timer instance
1227 * @retval State of bit (1 or 0).
1228 */
LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef * LPTIMx)1229 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx)
1230 {
1231 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
1232 }
1233
1234 #if defined(LPTIM_RCR_REP)
1235 /**
1236 * @brief Clear the repetition register update interrupt flag (REPOKCF).
1237 * @rmtoll ICR REPOKCF LL_LPTIM_ClearFlag_REPOK
1238 * @param LPTIMx Low-Power Timer instance
1239 * @retval None
1240 */
LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef * LPTIMx)1241 __STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx)
1242 {
1243 SET_BIT(LPTIMx->ICR, LPTIM_ICR_REPOKCF);
1244 }
1245
1246 /**
1247 * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully
1248 completed; If so, a new one can be initiated.
1249 * @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK
1250 * @param LPTIMx Low-Power Timer instance
1251 * @retval State of bit (1 or 0).
1252 */
LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef * LPTIMx)1253 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef *LPTIMx)
1254 {
1255 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL);
1256 }
1257
1258 /**
1259 * @brief Clear the update event flag (UECF).
1260 * @rmtoll ICR UECF LL_LPTIM_ClearFlag_UE
1261 * @param LPTIMx Low-Power Timer instance
1262 * @retval None
1263 */
LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef * LPTIMx)1264 __STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx)
1265 {
1266 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UECF);
1267 }
1268
1269 /**
1270 * @brief Informs application whether the LPTIMx update event has occurred.
1271 * @rmtoll ISR UE LL_LPTIM_IsActiveFlag_UE
1272 * @param LPTIMx Low-Power Timer instance
1273 * @retval State of bit (1 or 0).
1274 */
LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef * LPTIMx)1275 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef *LPTIMx)
1276 {
1277 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL);
1278 }
1279 #endif
1280
1281 /**
1282 * @}
1283 */
1284
1285 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1286 * @{
1287 */
1288
1289 /**
1290 * @brief Enable compare match interrupt (CMPMIE).
1291 * @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM
1292 * @param LPTIMx Low-Power Timer instance
1293 * @retval None
1294 */
LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef * LPTIMx)1295 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1296 {
1297 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1298 }
1299
1300 /**
1301 * @brief Disable compare match interrupt (CMPMIE).
1302 * @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM
1303 * @param LPTIMx Low-Power Timer instance
1304 * @retval None
1305 */
LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef * LPTIMx)1306 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1307 {
1308 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1309 }
1310
1311 /**
1312 * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
1313 * @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
1314 * @param LPTIMx Low-Power Timer instance
1315 * @retval State of bit (1 or 0).
1316 */
LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef * LPTIMx)1317 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef *LPTIMx)
1318 {
1319 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
1320 }
1321
1322 /**
1323 * @brief Enable autoreload match interrupt (ARRMIE).
1324 * @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM
1325 * @param LPTIMx Low-Power Timer instance
1326 * @retval None
1327 */
LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef * LPTIMx)1328 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1329 {
1330 SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1331 }
1332
1333 /**
1334 * @brief Disable autoreload match interrupt (ARRMIE).
1335 * @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM
1336 * @param LPTIMx Low-Power Timer instance
1337 * @retval None
1338 */
LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef * LPTIMx)1339 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1340 {
1341 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1342 }
1343
1344 /**
1345 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
1346 * @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
1347 * @param LPTIMx Low-Power Timer instance
1348 * @retval State of bit (1 or 0).
1349 */
LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef * LPTIMx)1350 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx)
1351 {
1352 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
1353 }
1354
1355 /**
1356 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
1357 * @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
1358 * @param LPTIMx Low-Power Timer instance
1359 * @retval None
1360 */
LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1361 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1362 {
1363 SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1364 }
1365
1366 /**
1367 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
1368 * @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
1369 * @param LPTIMx Low-Power Timer instance
1370 * @retval None
1371 */
LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1372 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1373 {
1374 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1375 }
1376
1377 /**
1378 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
1379 * @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
1380 * @param LPTIMx Low-Power Timer instance
1381 * @retval State of bit (1 or 0).
1382 */
LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef * LPTIMx)1383 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
1384 {
1385 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
1386 }
1387
1388 /**
1389 * @brief Enable compare register write completed interrupt (CMPOKIE).
1390 * @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
1391 * @param LPTIMx Low-Power Timer instance
1392 * @retval None
1393 */
LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef * LPTIMx)1394 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1395 {
1396 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1397 }
1398
1399 /**
1400 * @brief Disable compare register write completed interrupt (CMPOKIE).
1401 * @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
1402 * @param LPTIMx Low-Power Timer instance
1403 * @retval None
1404 */
LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef * LPTIMx)1405 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1406 {
1407 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1408 }
1409
1410 /**
1411 * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
1412 * @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
1413 * @param LPTIMx Low-Power Timer instance
1414 * @retval State of bit (1 or 0).
1415 */
LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef * LPTIMx)1416 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef *LPTIMx)
1417 {
1418 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
1419 }
1420
1421 /**
1422 * @brief Enable autoreload register write completed interrupt (ARROKIE).
1423 * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
1424 * @param LPTIMx Low-Power Timer instance
1425 * @retval None
1426 */
LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef * LPTIMx)1427 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1428 {
1429 SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1430 }
1431
1432 /**
1433 * @brief Disable autoreload register write completed interrupt (ARROKIE).
1434 * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
1435 * @param LPTIMx Low-Power Timer instance
1436 * @retval None
1437 */
LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef * LPTIMx)1438 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1439 {
1440 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1441 }
1442
1443 /**
1444 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
1445 * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
1446 * @param LPTIMx Low-Power Timer instance
1447 * @retval State of bit(1 or 0).
1448 */
LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef * LPTIMx)1449 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx)
1450 {
1451 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
1452 }
1453
1454 /**
1455 * @brief Enable direction change to up interrupt (UPIE).
1456 * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
1457 * @param LPTIMx Low-Power Timer instance
1458 * @retval None
1459 */
LL_LPTIM_EnableIT_UP(LPTIM_TypeDef * LPTIMx)1460 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
1461 {
1462 SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1463 }
1464
1465 /**
1466 * @brief Disable direction change to up interrupt (UPIE).
1467 * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
1468 * @param LPTIMx Low-Power Timer instance
1469 * @retval None
1470 */
LL_LPTIM_DisableIT_UP(LPTIM_TypeDef * LPTIMx)1471 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
1472 {
1473 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1474 }
1475
1476 /**
1477 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
1478 * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
1479 * @param LPTIMx Low-Power Timer instance
1480 * @retval State of bit(1 or 0).
1481 */
LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef * LPTIMx)1482 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx)
1483 {
1484 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
1485 }
1486
1487 /**
1488 * @brief Enable direction change to down interrupt (DOWNIE).
1489 * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
1490 * @param LPTIMx Low-Power Timer instance
1491 * @retval None
1492 */
LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef * LPTIMx)1493 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1494 {
1495 SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1496 }
1497
1498 /**
1499 * @brief Disable direction change to down interrupt (DOWNIE).
1500 * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
1501 * @param LPTIMx Low-Power Timer instance
1502 * @retval None
1503 */
LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef * LPTIMx)1504 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1505 {
1506 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1507 }
1508
1509 /**
1510 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
1511 * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
1512 * @param LPTIMx Low-Power Timer instance
1513 * @retval State of bit(1 or 0).
1514 */
LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef * LPTIMx)1515 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx)
1516 {
1517 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
1518 }
1519
1520 #if defined(LPTIM_RCR_REP)
1521 /**
1522 * @brief Enable repetition register update successfully completed interrupt (REPOKIE).
1523 * @rmtoll IER REPOKIE LL_LPTIM_EnableIT_REPOK
1524 * @param LPTIMx Low-Power Timer instance
1525 * @retval None
1526 */
LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef * LPTIMx)1527 __STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx)
1528 {
1529 SET_BIT(LPTIMx->IER, LPTIM_IER_REPOKIE);
1530 }
1531
1532 /**
1533 * @brief Disable repetition register update successfully completed interrupt (REPOKIE).
1534 * @rmtoll IER REPOKIE LL_LPTIM_DisableIT_REPOK
1535 * @param LPTIMx Low-Power Timer instance
1536 * @retval None
1537 */
LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef * LPTIMx)1538 __STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx)
1539 {
1540 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_REPOKIE);
1541 }
1542
1543 /**
1544 * @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled.
1545 * @rmtoll IER REPOKIE LL_LPTIM_IsEnabledIT_REPOK
1546 * @param LPTIMx Low-Power Timer instance
1547 * @retval State of bit(1 or 0).
1548 */
LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef * LPTIMx)1549 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef *LPTIMx)
1550 {
1551 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_REPOKIE) == (LPTIM_IER_REPOKIE)) ? 1UL : 0UL);
1552 }
1553
1554 /**
1555 * @brief Enable update event interrupt (UEIE).
1556 * @rmtoll IER UEIE LL_LPTIM_EnableIT_UE
1557 * @param LPTIMx Low-Power Timer instance
1558 * @retval None
1559 */
LL_LPTIM_EnableIT_UE(LPTIM_TypeDef * LPTIMx)1560 __STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx)
1561 {
1562 SET_BIT(LPTIMx->IER, LPTIM_IER_UEIE);
1563 }
1564
1565 /**
1566 * @brief Disable update event interrupt (UEIE).
1567 * @rmtoll IER UEIE LL_LPTIM_DisableIT_UE
1568 * @param LPTIMx Low-Power Timer instance
1569 * @retval None
1570 */
LL_LPTIM_DisableIT_UE(LPTIM_TypeDef * LPTIMx)1571 __STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx)
1572 {
1573 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UEIE);
1574 }
1575
1576 /**
1577 * @brief Indicates whether the update event interrupt (UEIE) is enabled.
1578 * @rmtoll IER UEIE LL_LPTIM_IsEnabledIT_UE
1579 * @param LPTIMx Low-Power Timer instance
1580 *@ retval State of bit(1 or 0).
1581 */
LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef * LPTIMx)1582 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef *LPTIMx)
1583 {
1584 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_UEIE) == (LPTIM_IER_UEIE)) ? 1UL : 0UL);
1585 }
1586 #endif
1587 /**
1588 * @}
1589 */
1590
1591 /**
1592 * @}
1593 */
1594
1595 /**
1596 * @}
1597 */
1598
1599 #endif /* LPTIM1 || LPTIM2 */
1600
1601 /**
1602 * @}
1603 */
1604
1605 #ifdef __cplusplus
1606 }
1607 #endif
1608
1609 #endif /* STM32L4xx_LL_LPTIM_H */
1610
