1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_dma2d.h
4 * @author MCD Application Team
5 * @brief Header file of DMA2D LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L4xx_LL_DMA2D_H
21 #define STM32L4xx_LL_DMA2D_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l4xx.h"
29
30 /** @addtogroup STM32L4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DMA2D)
35
36 /** @defgroup DMA2D_LL DMA2D
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 #if defined(USE_FULL_LL_DRIVER)
45 /** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros
46 * @{
47 */
48
49 /**
50 * @}
51 */
52 #endif /*USE_FULL_LL_DRIVER*/
53
54 /* Exported types ------------------------------------------------------------*/
55 #if defined(USE_FULL_LL_DRIVER)
56 /** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures
57 * @{
58 */
59
60 /**
61 * @brief LL DMA2D Init Structure Definition
62 */
63 typedef struct
64 {
65 uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
66 - This parameter can be one value of @ref DMA2D_LL_EC_MODE.
67
68 This parameter can be modified afterwards,
69 using unitary function @ref LL_DMA2D_SetMode(). */
70
71 uint32_t ColorMode; /*!< Specifies the color format of the output image.
72 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
73
74 This parameter can be modified afterwards using,
75 unitary function @ref LL_DMA2D_SetOutputColorMode(). */
76
77 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
78 - This parameter must be a number between:
79 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
80 - This parameter must be a number between:
81 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
82 - This parameter must be a number between:
83 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
84 - This parameter must be a number between:
85 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
86 - This parameter must be a number between:
87 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
88
89 This parameter can be modified afterwards,
90 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
91 function @ref LL_DMA2D_ConfigOutputColor(). */
92
93 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
94 - This parameter must be a number between:
95 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
96 - This parameter must be a number between:
97 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
98 - This parameter must be a number between:
99 Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
100 - This parameter must be a number between:
101 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
102 - This parameter must be a number between:
103 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
104
105 This parameter can be modified afterwards
106 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
107 function @ref LL_DMA2D_ConfigOutputColor(). */
108
109 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
110 - This parameter must be a number between:
111 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
112 - This parameter must be a number between:
113 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
114 - This parameter must be a number between:
115 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
116 - This parameter must be a number between:
117 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
118 - This parameter must be a number between:
119 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
120
121 This parameter can be modified afterwards
122 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
123 function @ref LL_DMA2D_ConfigOutputColor(). */
124
125 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
126 - This parameter must be a number between:
127 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
128 - This parameter must be a number between:
129 Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
130 - This parameter must be a number between:
131 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
132 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
133
134 This parameter can be modified afterwards using,
135 unitary function @ref LL_DMA2D_SetOutputColor() or configuration
136 function @ref LL_DMA2D_ConfigOutputColor(). */
137
138 uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
139 - This parameter must be a number between:
140 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
141
142 This parameter can be modified afterwards,
143 using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
144
145 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
146 uint32_t OutputSwapMode; /*!< Specifies the output swap mode color format of the output image.
147 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE.
148
149 This parameter can be modified afterwards,
150 using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */
151 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
152
153 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
154 uint32_t LineOffsetMode; /*!< Specifies the output line offset mode.
155 - This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE.
156
157 This parameter can be modified afterwards,
158 using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */
159 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
160
161 uint32_t LineOffset; /*!< Specifies the output line offset value.
162 - This parameter must be a number between:
163 Min_Data = 0x0000 and Max_Data = 0x3FFF on devices
164 where the Line Offset Mode feature is available.
165 else between Min_Data = 0x0000 and Max_Data = 0xFFFF on other devices.
166
167 This parameter can be modified afterwards,
168 using unitary function @ref LL_DMA2D_SetLineOffset(). */
169
170 uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
171 - This parameter must be a number between:
172 Min_Data = 0x0000 and Max_Data = 0xFFFF.
173
174 This parameter can be modified afterwards,
175 using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
176
177 uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred.
178 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
179
180 This parameter can be modified afterwards using,
181 unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
182
183 uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode.
184 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
185
186 This parameter can be modified afterwards,
187 using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
188
189 uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode.
190 - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP.
191
192 This parameter can be modified afterwards,
193 using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
194
195 } LL_DMA2D_InitTypeDef;
196
197 /**
198 * @brief LL DMA2D Layer Configuration Structure Definition
199 */
200 typedef struct
201 {
202 uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
203 - This parameter must be a number between:
204 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
205
206 This parameter can be modified afterwards using unitary functions
207 - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
208 - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
209
210 uint32_t LineOffset; /*!< Specifies the foreground or background line offset value.
211 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
212
213 This parameter can be modified afterwards using unitary functions
214 - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,
215 - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */
216
217 uint32_t ColorMode; /*!< Specifies the foreground or background color mode.
218 - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.
219
220 This parameter can be modified afterwards using unitary functions
221 - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,
222 - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */
223
224 uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode.
225 - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.
226
227 This parameter can be modified afterwards using unitary functions
228 - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
229 - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */
230
231 uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size.
232 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
233
234 This parameter can be modified afterwards using unitary functions
235 - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
236 - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */
237
238 uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode.
239 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.
240
241 This parameter can be modified afterwards using unitary functions
242 - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
243 - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */
244
245 uint32_t Alpha; /*!< Specifies the foreground or background Alpha value.
246 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
247
248 This parameter can be modified afterwards using unitary functions
249 - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,
250 - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */
251
252 uint32_t Blue; /*!< Specifies the foreground or background Blue color value.
253 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
254
255 This parameter can be modified afterwards using unitary functions
256 - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,
257 - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */
258
259 uint32_t Green; /*!< Specifies the foreground or background Green color value.
260 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
261
262 This parameter can be modified afterwards using unitary functions
263 - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,
264 - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */
265
266 uint32_t Red; /*!< Specifies the foreground or background Red color value.
267 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
268
269 This parameter can be modified afterwards using unitary functions
270 - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,
271 - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
272
273 uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
274 - This parameter must be a number between:
275 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
276
277 This parameter can be modified afterwards using unitary functions
278 - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
279 - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
280
281 uint32_t AlphaInversionMode; /*!< Specifies the foreground or background alpha inversion mode.
282 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
283
284 This parameter can be modified afterwards using unitary functions
285 - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer,
286 - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */
287
288 uint32_t RBSwapMode; /*!< Specifies the foreground or background Red Blue swap mode.
289 This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP .
290
291 This parameter can be modified afterwards using unitary functions
292 - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer,
293 - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */
294
295
296 } LL_DMA2D_LayerCfgTypeDef;
297
298 /**
299 * @brief LL DMA2D Output Color Structure Definition
300 */
301 typedef struct
302 {
303 uint32_t ColorMode; /*!< Specifies the color format of the output image.
304 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
305
306 This parameter can be modified afterwards using
307 unitary function @ref LL_DMA2D_SetOutputColorMode(). */
308
309 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
310 - This parameter must be a number between:
311 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
312 - This parameter must be a number between:
313 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
314 - This parameter must be a number between:
315 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
316 - This parameter must be a number between:
317 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
318 - This parameter must be a number between:
319 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
320
321 This parameter can be modified afterwards using,
322 unitary function @ref LL_DMA2D_SetOutputColor() or configuration
323 function @ref LL_DMA2D_ConfigOutputColor(). */
324
325 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
326 - This parameter must be a number between:
327 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
328 - This parameter must be a number between
329 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
330 - This parameter must be a number between:
331 Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
332 - This parameter must be a number between:
333 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
334 - This parameter must be a number between:
335 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
336
337 This parameter can be modified afterwards,
338 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
339 function @ref LL_DMA2D_ConfigOutputColor(). */
340
341 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
342 - This parameter must be a number between:
343 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
344 - This parameter must be a number between:
345 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
346 - This parameter must be a number between:
347 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
348 - This parameter must be a number between:
349 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
350 - This parameter must be a number between:
351 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
352
353 This parameter can be modified afterwards,
354 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
355 function @ref LL_DMA2D_ConfigOutputColor(). */
356
357 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
358 - This parameter must be a number between:
359 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
360 - This parameter must be a number between:
361 Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
362 - This parameter must be a number between:
363 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
364 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
365
366 This parameter can be modified afterwards,
367 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
368 function @ref LL_DMA2D_ConfigOutputColor(). */
369
370 } LL_DMA2D_ColorTypeDef;
371
372 /**
373 * @}
374 */
375 #endif /* USE_FULL_LL_DRIVER */
376
377 /* Exported constants --------------------------------------------------------*/
378 /** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants
379 * @{
380 */
381
382 /** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines
383 * @brief Flags defines which can be used with LL_DMA2D_ReadReg function
384 * @{
385 */
386 #define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
387 #define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
388 #define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
389 #define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
390 #define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
391 #define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
392 /**
393 * @}
394 */
395
396 /** @defgroup DMA2D_LL_EC_IT IT Defines
397 * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions
398 * @{
399 */
400 #define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
401 #define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
402 #define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
403 #define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
404 #define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
405 #define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
406 /**
407 * @}
408 */
409
410 /** @defgroup DMA2D_LL_EC_MODE Mode
411 * @{
412 */
413 #define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
414 #define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
415 #define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
416 #define LL_DMA2D_MODE_R2M (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1) /*!< DMA2D register to memory transfer mode */
417 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT)
418 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color foreground */
419 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2) /*!< DMA2D memory to memory with blending transfer mode and fixed color background */
420 #endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */
421 /**
422 * @}
423 */
424
425 /** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode
426 * @{
427 */
428 #define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
429 #define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */
430 #define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */
431 #define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */
432 #define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */
433 /**
434 * @}
435 */
436
437 /** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode
438 * @{
439 */
440 #define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
441 #define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */
442 #define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */
443 #define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */
444 #define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */
445 #define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */
446 #define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */
447 #define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */
448 #define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */
449 #define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */
450 #define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */
451 /**
452 * @}
453 */
454
455 /** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode
456 * @{
457 */
458 #define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
459 #define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by
460 programmed alpha value */
461 #define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by
462 programmed alpha value with,
463 original alpha channel value */
464 /**
465 * @}
466 */
467
468 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
469 /** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode
470 * @{
471 */
472 #define LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U /*!< Regular order */
473 #define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB /*!< Bytes swapped two by two */
474 /**
475 * @}
476 */
477 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
478
479 /** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap
480 * @{
481 */
482 #define LL_DMA2D_RB_MODE_REGULAR 0x00000000U /*!< RGB or ARGB */
483 #define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS /*!< BGR or ABGR */
484 /**
485 * @}
486 */
487
488 /** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion
489 * @{
490 */
491 #define LL_DMA2D_ALPHA_REGULAR 0x00000000U /*!< Regular alpha */
492 #define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI /*!< Inverted alpha */
493 /**
494 * @}
495 */
496
497
498 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
499 /** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode
500 * @{
501 */
502 #define LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U /*!< Line offsets are expressed in pixels */
503 #define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM /*!< Line offsets are expressed in bytes */
504 /**
505 * @}
506 */
507 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
508
509 /** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
510 * @{
511 */
512 #define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
513 #define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */
514 /**
515 * @}
516 */
517
518
519 /**
520 * @}
521 */
522
523 /* Exported macro ------------------------------------------------------------*/
524 /** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros
525 * @{
526 */
527
528 /** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros
529 * @{
530 */
531
532 /**
533 * @brief Write a value in DMA2D register.
534 * @param __INSTANCE__ DMA2D Instance
535 * @param __REG__ Register to be written
536 * @param __VALUE__ Value to be written in the register
537 * @retval None
538 */
539 #define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
540
541 /**
542 * @brief Read a value in DMA2D register.
543 * @param __INSTANCE__ DMA2D Instance
544 * @param __REG__ Register to be read
545 * @retval Register value
546 */
547 #define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
548 /**
549 * @}
550 */
551
552 /**
553 * @}
554 */
555
556 /* Exported functions --------------------------------------------------------*/
557 /** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions
558 * @{
559 */
560
561 /** @defgroup DMA2D_LL_EF_Configuration Configuration Functions
562 * @{
563 */
564
565 /**
566 * @brief Start a DMA2D transfer.
567 * @rmtoll CR START LL_DMA2D_Start
568 * @param DMA2Dx DMA2D Instance
569 * @retval None
570 */
LL_DMA2D_Start(DMA2D_TypeDef * DMA2Dx)571 __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
572 {
573 SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
574 }
575
576 /**
577 * @brief Indicate if a DMA2D transfer is ongoing.
578 * @rmtoll CR START LL_DMA2D_IsTransferOngoing
579 * @param DMA2Dx DMA2D Instance
580 * @retval State of bit (1 or 0).
581 */
LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef * DMA2Dx)582 __STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
583 {
584 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
585 }
586
587 /**
588 * @brief Suspend DMA2D transfer.
589 * @note This API can be used to suspend automatic foreground or background CLUT loading.
590 * @rmtoll CR SUSP LL_DMA2D_Suspend
591 * @param DMA2Dx DMA2D Instance
592 * @retval None
593 */
LL_DMA2D_Suspend(DMA2D_TypeDef * DMA2Dx)594 __STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
595 {
596 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
597 }
598
599 /**
600 * @brief Resume DMA2D transfer.
601 * @note This API can be used to resume automatic foreground or background CLUT loading.
602 * @rmtoll CR SUSP LL_DMA2D_Resume
603 * @param DMA2Dx DMA2D Instance
604 * @retval None
605 */
LL_DMA2D_Resume(DMA2D_TypeDef * DMA2Dx)606 __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
607 {
608 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
609 }
610
611 /**
612 * @brief Indicate if DMA2D transfer is suspended.
613 * @note This API can be used to indicate whether or not automatic foreground or
614 * background CLUT loading is suspended.
615 * @rmtoll CR SUSP LL_DMA2D_IsSuspended
616 * @param DMA2Dx DMA2D Instance
617 * @retval State of bit (1 or 0).
618 */
LL_DMA2D_IsSuspended(DMA2D_TypeDef * DMA2Dx)619 __STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
620 {
621 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
622 }
623
624 /**
625 * @brief Abort DMA2D transfer.
626 * @note This API can be used to abort automatic foreground or background CLUT loading.
627 * @rmtoll CR ABORT LL_DMA2D_Abort
628 * @param DMA2Dx DMA2D Instance
629 * @retval None
630 */
LL_DMA2D_Abort(DMA2D_TypeDef * DMA2Dx)631 __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
632 {
633 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
634 }
635
636 /**
637 * @brief Indicate if DMA2D transfer is aborted.
638 * @note This API can be used to indicate whether or not automatic foreground or
639 * background CLUT loading is aborted.
640 * @rmtoll CR ABORT LL_DMA2D_IsAborted
641 * @param DMA2Dx DMA2D Instance
642 * @retval State of bit (1 or 0).
643 */
LL_DMA2D_IsAborted(DMA2D_TypeDef * DMA2Dx)644 __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
645 {
646 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
647 }
648
649 /**
650 * @brief Set DMA2D mode.
651 * @rmtoll CR MODE LL_DMA2D_SetMode
652 * @param DMA2Dx DMA2D Instance
653 * @param Mode This parameter can be one of the following values:
654 * @arg @ref LL_DMA2D_MODE_M2M
655 * @arg @ref LL_DMA2D_MODE_M2M_PFC
656 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
657 * @arg @ref LL_DMA2D_MODE_R2M
658 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG (*)
659 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (*)
660 *
661 * (*) value not defined in all devices.
662 * @retval None
663 */
LL_DMA2D_SetMode(DMA2D_TypeDef * DMA2Dx,uint32_t Mode)664 __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
665 {
666 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
667 }
668
669 /**
670 * @brief Return DMA2D mode
671 * @rmtoll CR MODE LL_DMA2D_GetMode
672 * @param DMA2Dx DMA2D Instance
673 * @retval Returned value can be one of the following values:
674 * @arg @ref LL_DMA2D_MODE_M2M
675 * @arg @ref LL_DMA2D_MODE_M2M_PFC
676 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
677 * @arg @ref LL_DMA2D_MODE_R2M
678 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG (*)
679 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (*)
680 *
681 * (*) value not defined in all devices.
682 */
LL_DMA2D_GetMode(DMA2D_TypeDef * DMA2Dx)683 __STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)
684 {
685 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
686 }
687
688 /**
689 * @brief Set DMA2D output color mode.
690 * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode
691 * @param DMA2Dx DMA2D Instance
692 * @param ColorMode This parameter can be one of the following values:
693 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
694 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
695 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
696 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
697 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
698 * @retval None
699 */
LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)700 __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
701 {
702 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
703 }
704
705 /**
706 * @brief Return DMA2D output color mode.
707 * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode
708 * @param DMA2Dx DMA2D Instance
709 * @retval Returned value can be one of the following values:
710 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
711 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
712 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
713 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
714 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
715 */
LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef * DMA2Dx)716 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
717 {
718 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
719 }
720
721 /**
722 * @brief Set DMA2D output Red Blue swap mode.
723 * @rmtoll OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode
724 * @param DMA2Dx DMA2D Instance
725 * @param RBSwapMode This parameter can be one of the following values:
726 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
727 * @arg @ref LL_DMA2D_RB_MODE_SWAP
728 * @retval None
729 */
LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t RBSwapMode)730 __STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
731 {
732 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode);
733 }
734
735 /**
736 * @brief Return DMA2D output Red Blue swap mode.
737 * @rmtoll OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode
738 * @param DMA2Dx DMA2D Instance
739 * @retval Returned value can be one of the following values:
740 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
741 * @arg @ref LL_DMA2D_RB_MODE_SWAP
742 */
LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef * DMA2Dx)743 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx)
744 {
745 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS));
746 }
747
748 /**
749 * @brief Set DMA2D output alpha inversion mode.
750 * @rmtoll OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode
751 * @param DMA2Dx DMA2D Instance
752 * @param AlphaInversionMode This parameter can be one of the following values:
753 * @arg @ref LL_DMA2D_ALPHA_REGULAR
754 * @arg @ref LL_DMA2D_ALPHA_INVERTED
755 * @retval None
756 */
LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef * DMA2Dx,uint32_t AlphaInversionMode)757 __STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
758 {
759 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode);
760 }
761
762 /**
763 * @brief Return DMA2D output alpha inversion mode.
764 * @rmtoll OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode
765 * @param DMA2Dx DMA2D Instance
766 * @retval Returned value can be one of the following values:
767 * @arg @ref LL_DMA2D_ALPHA_REGULAR
768 * @arg @ref LL_DMA2D_ALPHA_INVERTED
769 */
LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef * DMA2Dx)770 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
771 {
772 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI));
773 }
774
775
776 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
777 /**
778 * @brief Set DMA2D output swap mode.
779 * @rmtoll OPFCCR SB LL_DMA2D_SetOutputSwapMode
780 * @param DMA2Dx DMA2D Instance
781 * @param OutputSwapMode This parameter can be one of the following values:
782 * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
783 * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
784 * @retval None
785 */
LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t OutputSwapMode)786 __STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode)
787 {
788 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode);
789 }
790
791 /**
792 * @brief Return DMA2D output swap mode.
793 * @rmtoll OPFCCR SB LL_DMA2D_GetOutputSwapMode
794 * @param DMA2Dx DMA2D Instance
795 * @retval Returned value can be one of the following values:
796 * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
797 * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
798 */
LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef * DMA2Dx)799 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx)
800 {
801 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB));
802 }
803 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
804
805 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
806 /**
807 * @brief Set DMA2D line offset mode.
808 * @rmtoll CR LOM LL_DMA2D_SetLineOffsetMode
809 * @param DMA2Dx DMA2D Instance
810 * @param LineOffsetMode This parameter can be one of the following values:
811 * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
812 * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
813 * @retval None
814 */
LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffsetMode)815 __STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode)
816 {
817 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode);
818 }
819
820 /**
821 * @brief Return DMA2D line offset mode.
822 * @rmtoll CR LOM LL_DMA2D_GetLineOffsetMode
823 * @param DMA2Dx DMA2D Instance
824 * @retval Returned value can be one of the following values:
825 * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
826 * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
827 */
LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef * DMA2Dx)828 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx)
829 {
830 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM));
831 }
832 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
833
834 /**
835 * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
836 * @rmtoll OOR LO LL_DMA2D_SetLineOffset
837 * @param DMA2Dx DMA2D Instance
838 @if DMA2D_LINE_OFFSET_MODE_SUPPORT
839 * @param LineOffset Value between Min_Data=0 and Max_Data=0xFFFF
840 @else
841 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FFF
842 @endif
843 * @retval None
844 */
LL_DMA2D_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)845 __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
846 {
847 MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
848 }
849
850 /**
851 * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
852 * @rmtoll OOR LO LL_DMA2D_GetLineOffset
853 * @param DMA2Dx DMA2D Instance
854 @if DMA2D_LINE_OFFSET_MODE_SUPPORT
855 * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF
856 @else
857 * @retval Line offset value between Min_Data=0 and Max_Data=0x3FFF
858 @endif
859 */
LL_DMA2D_GetLineOffset(DMA2D_TypeDef * DMA2Dx)860 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
861 {
862 return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
863 }
864
865 /**
866 * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
867 * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines
868 * @param DMA2Dx DMA2D Instance
869 * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
870 * @retval None
871 */
LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef * DMA2Dx,uint32_t NbrOfPixelsPerLines)872 __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
873 {
874 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
875 }
876
877 /**
878 * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
879 * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines
880 * @param DMA2Dx DMA2D Instance
881 * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
882 */
LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef * DMA2Dx)883 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)
884 {
885 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
886 }
887
888 /**
889 * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
890 * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines
891 * @param DMA2Dx DMA2D Instance
892 * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
893 * @retval None
894 */
LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef * DMA2Dx,uint32_t NbrOfLines)895 __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
896 {
897 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
898 }
899
900 /**
901 * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
902 * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines
903 * @param DMA2Dx DMA2D Instance
904 * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
905 */
LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef * DMA2Dx)906 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)
907 {
908 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
909 }
910
911 /**
912 * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
913 * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr
914 * @param DMA2Dx DMA2D Instance
915 * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
916 * @retval None
917 */
LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t OutputMemoryAddress)918 __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
919 {
920 LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
921 }
922
923 /**
924 * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
925 * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr
926 * @param DMA2Dx DMA2D Instance
927 * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
928 */
LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef * DMA2Dx)929 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
930 {
931 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
932 }
933
934 /**
935 * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits).
936 * @note Output color format depends on output color mode, ARGB8888, RGB888,
937 * RGB565, ARGB1555 or ARGB4444.
938 * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting
939 * with respect to color mode is not done by the user code.
940 * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n
941 * OCOLR GREEN LL_DMA2D_SetOutputColor\n
942 * OCOLR RED LL_DMA2D_SetOutputColor\n
943 * OCOLR ALPHA LL_DMA2D_SetOutputColor
944 * @param DMA2Dx DMA2D Instance
945 * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF
946 * @retval None
947 */
LL_DMA2D_SetOutputColor(DMA2D_TypeDef * DMA2Dx,uint32_t OutputColor)948 __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
949 {
950 MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \
951 OutputColor);
952 }
953
954 /**
955 * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits).
956 * @note Alpha channel and red, green, blue color values must be retrieved from the returned
957 * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444)
958 * as set by @ref LL_DMA2D_SetOutputColorMode.
959 * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n
960 * OCOLR GREEN LL_DMA2D_GetOutputColor\n
961 * OCOLR RED LL_DMA2D_GetOutputColor\n
962 * OCOLR ALPHA LL_DMA2D_GetOutputColor
963 * @param DMA2Dx DMA2D Instance
964 * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
965 */
LL_DMA2D_GetOutputColor(DMA2D_TypeDef * DMA2Dx)966 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)
967 {
968 return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
969 (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
970 }
971
972 /**
973 * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
974 * @rmtoll LWR LW LL_DMA2D_SetLineWatermark
975 * @param DMA2Dx DMA2D Instance
976 * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF
977 * @retval None
978 */
LL_DMA2D_SetLineWatermark(DMA2D_TypeDef * DMA2Dx,uint32_t LineWatermark)979 __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
980 {
981 MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
982 }
983
984 /**
985 * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
986 * @rmtoll LWR LW LL_DMA2D_GetLineWatermark
987 * @param DMA2Dx DMA2D Instance
988 * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
989 */
LL_DMA2D_GetLineWatermark(DMA2D_TypeDef * DMA2Dx)990 __STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)
991 {
992 return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
993 }
994
995 /**
996 * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
997 * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime
998 * @param DMA2Dx DMA2D Instance
999 * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF
1000 * @retval None
1001 */
LL_DMA2D_SetDeadTime(DMA2D_TypeDef * DMA2Dx,uint32_t DeadTime)1002 __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
1003 {
1004 MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
1005 }
1006
1007 /**
1008 * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
1009 * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime
1010 * @param DMA2Dx DMA2D Instance
1011 * @retval Dead time value between Min_Data=0 and Max_Data=0xFF
1012 */
LL_DMA2D_GetDeadTime(DMA2D_TypeDef * DMA2Dx)1013 __STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)
1014 {
1015 return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
1016 }
1017
1018 /**
1019 * @brief Enable DMA2D dead time functionality.
1020 * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime
1021 * @param DMA2Dx DMA2D Instance
1022 * @retval None
1023 */
LL_DMA2D_EnableDeadTime(DMA2D_TypeDef * DMA2Dx)1024 __STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
1025 {
1026 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
1027 }
1028
1029 /**
1030 * @brief Disable DMA2D dead time functionality.
1031 * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime
1032 * @param DMA2Dx DMA2D Instance
1033 * @retval None
1034 */
LL_DMA2D_DisableDeadTime(DMA2D_TypeDef * DMA2Dx)1035 __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
1036 {
1037 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
1038 }
1039
1040 /**
1041 * @brief Indicate if DMA2D dead time functionality is enabled.
1042 * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime
1043 * @param DMA2Dx DMA2D Instance
1044 * @retval State of bit (1 or 0).
1045 */
LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef * DMA2Dx)1046 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
1047 {
1048 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
1049 }
1050
1051 /** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
1052 * @{
1053 */
1054
1055 /**
1056 * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
1057 * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr
1058 * @param DMA2Dx DMA2D Instance
1059 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1060 * @retval None
1061 */
LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t MemoryAddress)1062 __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1063 {
1064 LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
1065 }
1066
1067 /**
1068 * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
1069 * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr
1070 * @param DMA2Dx DMA2D Instance
1071 * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1072 */
LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef * DMA2Dx)1073 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
1074 {
1075 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
1076 }
1077
1078 /**
1079 * @brief Enable DMA2D foreground CLUT loading.
1080 * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad
1081 * @param DMA2Dx DMA2D Instance
1082 * @retval None
1083 */
LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef * DMA2Dx)1084 __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1085 {
1086 SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
1087 }
1088
1089 /**
1090 * @brief Indicate if DMA2D foreground CLUT loading is enabled.
1091 * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad
1092 * @param DMA2Dx DMA2D Instance
1093 * @retval State of bit (1 or 0).
1094 */
LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef * DMA2Dx)1095 __STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1096 {
1097 return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
1098 }
1099
1100 /**
1101 * @brief Set DMA2D foreground color mode.
1102 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode
1103 * @param DMA2Dx DMA2D Instance
1104 * @param ColorMode This parameter can be one of the following values:
1105 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1106 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1107 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1108 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1109 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1110 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1111 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1112 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1113 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1114 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1115 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1116 * @retval None
1117 */
LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)1118 __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1119 {
1120 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
1121 }
1122
1123 /**
1124 * @brief Return DMA2D foreground color mode.
1125 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode
1126 * @param DMA2Dx DMA2D Instance
1127 * @retval Returned value can be one of the following values:
1128 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1129 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1130 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1131 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1132 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1133 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1134 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1135 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1136 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1137 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1138 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1139 */
LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef * DMA2Dx)1140 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
1141 {
1142 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
1143 }
1144
1145 /**
1146 * @brief Set DMA2D foreground alpha mode.
1147 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode
1148 * @param DMA2Dx DMA2D Instance
1149 * @param AphaMode This parameter can be one of the following values:
1150 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1151 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1152 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1153 * @retval None
1154 */
LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef * DMA2Dx,uint32_t AphaMode)1155 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1156 {
1157 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
1158 }
1159
1160 /**
1161 * @brief Return DMA2D foreground alpha mode.
1162 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode
1163 * @param DMA2Dx DMA2D Instance
1164 * @retval Returned value can be one of the following values:
1165 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1166 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1167 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1168 */
LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef * DMA2Dx)1169 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
1170 {
1171 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
1172 }
1173
1174 /**
1175 * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
1176 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha
1177 * @param DMA2Dx DMA2D Instance
1178 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1179 * @retval None
1180 */
LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef * DMA2Dx,uint32_t Alpha)1181 __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1182 {
1183 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
1184 }
1185
1186 /**
1187 * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
1188 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha
1189 * @param DMA2Dx DMA2D Instance
1190 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1191 */
LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef * DMA2Dx)1192 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
1193 {
1194 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
1195 }
1196
1197 /**
1198 * @brief Set DMA2D foreground Red Blue swap mode.
1199 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode
1200 * @param DMA2Dx DMA2D Instance
1201 * @param RBSwapMode This parameter can be one of the following values:
1202 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1203 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1204 * @retval None
1205 */
LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t RBSwapMode)1206 __STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1207 {
1208 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode);
1209 }
1210
1211 /**
1212 * @brief Return DMA2D foreground Red Blue swap mode.
1213 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode
1214 * @param DMA2Dx DMA2D Instance
1215 * @retval Returned value can be one of the following values:
1216 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1217 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1218 */
LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef * DMA2Dx)1219 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
1220 {
1221 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS));
1222 }
1223
1224 /**
1225 * @brief Set DMA2D foreground alpha inversion mode.
1226 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode
1227 * @param DMA2Dx DMA2D Instance
1228 * @param AlphaInversionMode This parameter can be one of the following values:
1229 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1230 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1231 * @retval None
1232 */
LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef * DMA2Dx,uint32_t AlphaInversionMode)1233 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1234 {
1235 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode);
1236 }
1237
1238 /**
1239 * @brief Return DMA2D foreground alpha inversion mode.
1240 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode
1241 * @param DMA2Dx DMA2D Instance
1242 * @retval Returned value can be one of the following values:
1243 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1244 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1245 */
LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef * DMA2Dx)1246 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
1247 {
1248 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI));
1249 }
1250
1251 /**
1252 * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1253 * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset
1254 * @param DMA2Dx DMA2D Instance
1255 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1256 * @retval None
1257 */
LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)1258 __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1259 {
1260 MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
1261 }
1262
1263 /**
1264 * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1265 * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset
1266 * @param DMA2Dx DMA2D Instance
1267 * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
1268 */
LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef * DMA2Dx)1269 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1270 {
1271 return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
1272 }
1273
1274 /**
1275 * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
1276 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor
1277 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor
1278 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor
1279 * @param DMA2Dx DMA2D Instance
1280 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1281 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1282 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1283 * @retval None
1284 */
LL_DMA2D_FGND_SetColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red,uint32_t Green,uint32_t Blue)1285 __STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1286 {
1287 MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
1288 ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
1289 }
1290
1291 /**
1292 * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1293 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor
1294 * @param DMA2Dx DMA2D Instance
1295 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1296 * @retval None
1297 */
LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red)1298 __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1299 {
1300 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
1301 }
1302
1303 /**
1304 * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1305 * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor
1306 * @param DMA2Dx DMA2D Instance
1307 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1308 */
LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef * DMA2Dx)1309 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1310 {
1311 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
1312 }
1313
1314 /**
1315 * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1316 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor
1317 * @param DMA2Dx DMA2D Instance
1318 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1319 * @retval None
1320 */
LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef * DMA2Dx,uint32_t Green)1321 __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1322 {
1323 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
1324 }
1325
1326 /**
1327 * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1328 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor
1329 * @param DMA2Dx DMA2D Instance
1330 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1331 */
LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef * DMA2Dx)1332 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1333 {
1334 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
1335 }
1336
1337 /**
1338 * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1339 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor
1340 * @param DMA2Dx DMA2D Instance
1341 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1342 * @retval None
1343 */
LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef * DMA2Dx,uint32_t Blue)1344 __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1345 {
1346 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
1347 }
1348
1349 /**
1350 * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1351 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor
1352 * @param DMA2Dx DMA2D Instance
1353 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1354 */
LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef * DMA2Dx)1355 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1356 {
1357 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
1358 }
1359
1360 /**
1361 * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1362 * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr
1363 * @param DMA2Dx DMA2D Instance
1364 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1365 * @retval None
1366 */
LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTMemoryAddress)1367 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1368 {
1369 LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
1370 }
1371
1372 /**
1373 * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1374 * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr
1375 * @param DMA2Dx DMA2D Instance
1376 * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1377 */
LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx)1378 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1379 {
1380 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
1381 }
1382
1383 /**
1384 * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1385 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize
1386 * @param DMA2Dx DMA2D Instance
1387 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1388 * @retval None
1389 */
LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTSize)1390 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1391 {
1392 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
1393 }
1394
1395 /**
1396 * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1397 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize
1398 * @param DMA2Dx DMA2D Instance
1399 * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
1400 */
LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef * DMA2Dx)1401 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1402 {
1403 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
1404 }
1405
1406 /**
1407 * @brief Set DMA2D foreground CLUT color mode.
1408 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode
1409 * @param DMA2Dx DMA2D Instance
1410 * @param CLUTColorMode This parameter can be one of the following values:
1411 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1412 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1413 * @retval None
1414 */
LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTColorMode)1415 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1416 {
1417 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
1418 }
1419
1420 /**
1421 * @brief Return DMA2D foreground CLUT color mode.
1422 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode
1423 * @param DMA2Dx DMA2D Instance
1424 * @retval Returned value can be one of the following values:
1425 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1426 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1427 */
LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef * DMA2Dx)1428 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1429 {
1430 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
1431 }
1432
1433 /**
1434 * @}
1435 */
1436
1437 /** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions
1438 * @{
1439 */
1440
1441 /**
1442 * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1443 * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr
1444 * @param DMA2Dx DMA2D Instance
1445 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1446 * @retval None
1447 */
LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t MemoryAddress)1448 __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1449 {
1450 LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
1451 }
1452
1453 /**
1454 * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1455 * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr
1456 * @param DMA2Dx DMA2D Instance
1457 * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1458 */
LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef * DMA2Dx)1459 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
1460 {
1461 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
1462 }
1463
1464 /**
1465 * @brief Enable DMA2D background CLUT loading.
1466 * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad
1467 * @param DMA2Dx DMA2D Instance
1468 * @retval None
1469 */
LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef * DMA2Dx)1470 __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1471 {
1472 SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
1473 }
1474
1475 /**
1476 * @brief Indicate if DMA2D background CLUT loading is enabled.
1477 * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad
1478 * @param DMA2Dx DMA2D Instance
1479 * @retval State of bit (1 or 0).
1480 */
LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef * DMA2Dx)1481 __STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1482 {
1483 return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
1484 }
1485
1486 /**
1487 * @brief Set DMA2D background color mode.
1488 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode
1489 * @param DMA2Dx DMA2D Instance
1490 * @param ColorMode This parameter can be one of the following values:
1491 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1492 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1493 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1494 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1495 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1496 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1497 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1498 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1499 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1500 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1501 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1502 * @retval None
1503 */
LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)1504 __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1505 {
1506 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
1507 }
1508
1509 /**
1510 * @brief Return DMA2D background color mode.
1511 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode
1512 * @param DMA2Dx DMA2D Instance
1513 * @retval Returned value can be one of the following values:
1514 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1515 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1516 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1517 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1518 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1519 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1520 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1521 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1522 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1523 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1524 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1525 */
LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef * DMA2Dx)1526 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
1527 {
1528 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
1529 }
1530
1531 /**
1532 * @brief Set DMA2D background alpha mode.
1533 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode
1534 * @param DMA2Dx DMA2D Instance
1535 * @param AphaMode This parameter can be one of the following values:
1536 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1537 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1538 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1539 * @retval None
1540 */
LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef * DMA2Dx,uint32_t AphaMode)1541 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1542 {
1543 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
1544 }
1545
1546 /**
1547 * @brief Return DMA2D background alpha mode.
1548 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode
1549 * @param DMA2Dx DMA2D Instance
1550 * @retval Returned value can be one of the following values:
1551 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1552 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1553 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1554 */
LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef * DMA2Dx)1555 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
1556 {
1557 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
1558 }
1559
1560 /**
1561 * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1562 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha
1563 * @param DMA2Dx DMA2D Instance
1564 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1565 * @retval None
1566 */
LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef * DMA2Dx,uint32_t Alpha)1567 __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1568 {
1569 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
1570 }
1571
1572 /**
1573 * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1574 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha
1575 * @param DMA2Dx DMA2D Instance
1576 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1577 */
LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef * DMA2Dx)1578 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
1579 {
1580 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
1581 }
1582
1583 /**
1584 * @brief Set DMA2D background Red Blue swap mode.
1585 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode
1586 * @param DMA2Dx DMA2D Instance
1587 * @param RBSwapMode This parameter can be one of the following values:
1588 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1589 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1590 * @retval None
1591 */
LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t RBSwapMode)1592 __STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1593 {
1594 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode);
1595 }
1596
1597 /**
1598 * @brief Return DMA2D background Red Blue swap mode.
1599 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode
1600 * @param DMA2Dx DMA2D Instance
1601 * @retval Returned value can be one of the following values:
1602 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1603 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1604 */
LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef * DMA2Dx)1605 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
1606 {
1607 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS));
1608 }
1609
1610 /**
1611 * @brief Set DMA2D background alpha inversion mode.
1612 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode
1613 * @param DMA2Dx DMA2D Instance
1614 * @param AlphaInversionMode This parameter can be one of the following values:
1615 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1616 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1617 * @retval None
1618 */
LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef * DMA2Dx,uint32_t AlphaInversionMode)1619 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1620 {
1621 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode);
1622 }
1623
1624 /**
1625 * @brief Return DMA2D background alpha inversion mode.
1626 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode
1627 * @param DMA2Dx DMA2D Instance
1628 * @retval Returned value can be one of the following values:
1629 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1630 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1631 */
LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef * DMA2Dx)1632 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
1633 {
1634 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI));
1635 }
1636
1637 /**
1638 * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1639 * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset
1640 * @param DMA2Dx DMA2D Instance
1641 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1642 * @retval None
1643 */
LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)1644 __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1645 {
1646 MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
1647 }
1648
1649 /**
1650 * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1651 * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset
1652 * @param DMA2Dx DMA2D Instance
1653 * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
1654 */
LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef * DMA2Dx)1655 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1656 {
1657 return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
1658 }
1659
1660 /**
1661 * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
1662 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor
1663 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor
1664 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor
1665 * @param DMA2Dx DMA2D Instance
1666 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1667 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1668 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1669 * @retval None
1670 */
LL_DMA2D_BGND_SetColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red,uint32_t Green,uint32_t Blue)1671 __STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1672 {
1673 MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
1674 ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
1675 }
1676
1677 /**
1678 * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1679 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor
1680 * @param DMA2Dx DMA2D Instance
1681 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1682 * @retval None
1683 */
LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red)1684 __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1685 {
1686 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
1687 }
1688
1689 /**
1690 * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1691 * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor
1692 * @param DMA2Dx DMA2D Instance
1693 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1694 */
LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef * DMA2Dx)1695 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1696 {
1697 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
1698 }
1699
1700 /**
1701 * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1702 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor
1703 * @param DMA2Dx DMA2D Instance
1704 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1705 * @retval None
1706 */
LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef * DMA2Dx,uint32_t Green)1707 __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1708 {
1709 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
1710 }
1711
1712 /**
1713 * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1714 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor
1715 * @param DMA2Dx DMA2D Instance
1716 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1717 */
LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef * DMA2Dx)1718 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1719 {
1720 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
1721 }
1722
1723 /**
1724 * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1725 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor
1726 * @param DMA2Dx DMA2D Instance
1727 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1728 * @retval None
1729 */
LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef * DMA2Dx,uint32_t Blue)1730 __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1731 {
1732 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
1733 }
1734
1735 /**
1736 * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1737 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor
1738 * @param DMA2Dx DMA2D Instance
1739 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1740 */
LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef * DMA2Dx)1741 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1742 {
1743 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
1744 }
1745
1746 /**
1747 * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1748 * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr
1749 * @param DMA2Dx DMA2D Instance
1750 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1751 * @retval None
1752 */
LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTMemoryAddress)1753 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1754 {
1755 LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
1756 }
1757
1758 /**
1759 * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1760 * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr
1761 * @param DMA2Dx DMA2D Instance
1762 * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1763 */
LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx)1764 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1765 {
1766 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
1767 }
1768
1769 /**
1770 * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1771 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize
1772 * @param DMA2Dx DMA2D Instance
1773 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1774 * @retval None
1775 */
LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTSize)1776 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1777 {
1778 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
1779 }
1780
1781 /**
1782 * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1783 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize
1784 * @param DMA2Dx DMA2D Instance
1785 * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
1786 */
LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef * DMA2Dx)1787 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1788 {
1789 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
1790 }
1791
1792 /**
1793 * @brief Set DMA2D background CLUT color mode.
1794 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode
1795 * @param DMA2Dx DMA2D Instance
1796 * @param CLUTColorMode This parameter can be one of the following values:
1797 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1798 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1799 * @retval None
1800 */
LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTColorMode)1801 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1802 {
1803 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
1804 }
1805
1806 /**
1807 * @brief Return DMA2D background CLUT color mode.
1808 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode
1809 * @param DMA2Dx DMA2D Instance
1810 * @retval Returned value can be one of the following values:
1811 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1812 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1813 */
LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef * DMA2Dx)1814 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1815 {
1816 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
1817 }
1818
1819 /**
1820 * @}
1821 */
1822
1823 /**
1824 * @}
1825 */
1826
1827
1828 /** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management
1829 * @{
1830 */
1831
1832 /**
1833 * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not
1834 * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE
1835 * @param DMA2Dx DMA2D Instance
1836 * @retval State of bit (1 or 0).
1837 */
LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef * DMA2Dx)1838 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
1839 {
1840 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
1841 }
1842
1843 /**
1844 * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not
1845 * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC
1846 * @param DMA2Dx DMA2D Instance
1847 * @retval State of bit (1 or 0).
1848 */
LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef * DMA2Dx)1849 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1850 {
1851 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
1852 }
1853
1854 /**
1855 * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not
1856 * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE
1857 * @param DMA2Dx DMA2D Instance
1858 * @retval State of bit (1 or 0).
1859 */
LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef * DMA2Dx)1860 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1861 {
1862 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
1863 }
1864
1865 /**
1866 * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not
1867 * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW
1868 * @param DMA2Dx DMA2D Instance
1869 * @retval State of bit (1 or 0).
1870 */
LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef * DMA2Dx)1871 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
1872 {
1873 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
1874 }
1875
1876 /**
1877 * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not
1878 * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC
1879 * @param DMA2Dx DMA2D Instance
1880 * @retval State of bit (1 or 0).
1881 */
LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef * DMA2Dx)1882 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
1883 {
1884 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
1885 }
1886
1887 /**
1888 * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not
1889 * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE
1890 * @param DMA2Dx DMA2D Instance
1891 * @retval State of bit (1 or 0).
1892 */
LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef * DMA2Dx)1893 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
1894 {
1895 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
1896 }
1897
1898 /**
1899 * @brief Clear DMA2D Configuration Error Interrupt Flag
1900 * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE
1901 * @param DMA2Dx DMA2D Instance
1902 * @retval None
1903 */
LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef * DMA2Dx)1904 __STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
1905 {
1906 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
1907 }
1908
1909 /**
1910 * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag
1911 * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC
1912 * @param DMA2Dx DMA2D Instance
1913 * @retval None
1914 */
LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef * DMA2Dx)1915 __STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1916 {
1917 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
1918 }
1919
1920 /**
1921 * @brief Clear DMA2D CLUT Access Error Interrupt Flag
1922 * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE
1923 * @param DMA2Dx DMA2D Instance
1924 * @retval None
1925 */
LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef * DMA2Dx)1926 __STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1927 {
1928 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
1929 }
1930
1931 /**
1932 * @brief Clear DMA2D Transfer Watermark Interrupt Flag
1933 * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW
1934 * @param DMA2Dx DMA2D Instance
1935 * @retval None
1936 */
LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef * DMA2Dx)1937 __STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
1938 {
1939 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
1940 }
1941
1942 /**
1943 * @brief Clear DMA2D Transfer Complete Interrupt Flag
1944 * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC
1945 * @param DMA2Dx DMA2D Instance
1946 * @retval None
1947 */
LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef * DMA2Dx)1948 __STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
1949 {
1950 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
1951 }
1952
1953 /**
1954 * @brief Clear DMA2D Transfer Error Interrupt Flag
1955 * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE
1956 * @param DMA2Dx DMA2D Instance
1957 * @retval None
1958 */
LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef * DMA2Dx)1959 __STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
1960 {
1961 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
1962 }
1963
1964 /**
1965 * @}
1966 */
1967
1968 /** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management
1969 * @{
1970 */
1971
1972 /**
1973 * @brief Enable Configuration Error Interrupt
1974 * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE
1975 * @param DMA2Dx DMA2D Instance
1976 * @retval None
1977 */
LL_DMA2D_EnableIT_CE(DMA2D_TypeDef * DMA2Dx)1978 __STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
1979 {
1980 SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
1981 }
1982
1983 /**
1984 * @brief Enable CLUT Transfer Complete Interrupt
1985 * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC
1986 * @param DMA2Dx DMA2D Instance
1987 * @retval None
1988 */
LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef * DMA2Dx)1989 __STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
1990 {
1991 SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
1992 }
1993
1994 /**
1995 * @brief Enable CLUT Access Error Interrupt
1996 * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE
1997 * @param DMA2Dx DMA2D Instance
1998 * @retval None
1999 */
LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef * DMA2Dx)2000 __STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
2001 {
2002 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
2003 }
2004
2005 /**
2006 * @brief Enable Transfer Watermark Interrupt
2007 * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW
2008 * @param DMA2Dx DMA2D Instance
2009 * @retval None
2010 */
LL_DMA2D_EnableIT_TW(DMA2D_TypeDef * DMA2Dx)2011 __STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
2012 {
2013 SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
2014 }
2015
2016 /**
2017 * @brief Enable Transfer Complete Interrupt
2018 * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC
2019 * @param DMA2Dx DMA2D Instance
2020 * @retval None
2021 */
LL_DMA2D_EnableIT_TC(DMA2D_TypeDef * DMA2Dx)2022 __STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
2023 {
2024 SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
2025 }
2026
2027 /**
2028 * @brief Enable Transfer Error Interrupt
2029 * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE
2030 * @param DMA2Dx DMA2D Instance
2031 * @retval None
2032 */
LL_DMA2D_EnableIT_TE(DMA2D_TypeDef * DMA2Dx)2033 __STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
2034 {
2035 SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
2036 }
2037
2038 /**
2039 * @brief Disable Configuration Error Interrupt
2040 * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE
2041 * @param DMA2Dx DMA2D Instance
2042 * @retval None
2043 */
LL_DMA2D_DisableIT_CE(DMA2D_TypeDef * DMA2Dx)2044 __STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
2045 {
2046 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
2047 }
2048
2049 /**
2050 * @brief Disable CLUT Transfer Complete Interrupt
2051 * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC
2052 * @param DMA2Dx DMA2D Instance
2053 * @retval None
2054 */
LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef * DMA2Dx)2055 __STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
2056 {
2057 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
2058 }
2059
2060 /**
2061 * @brief Disable CLUT Access Error Interrupt
2062 * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE
2063 * @param DMA2Dx DMA2D Instance
2064 * @retval None
2065 */
LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef * DMA2Dx)2066 __STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
2067 {
2068 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
2069 }
2070
2071 /**
2072 * @brief Disable Transfer Watermark Interrupt
2073 * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW
2074 * @param DMA2Dx DMA2D Instance
2075 * @retval None
2076 */
LL_DMA2D_DisableIT_TW(DMA2D_TypeDef * DMA2Dx)2077 __STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
2078 {
2079 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
2080 }
2081
2082 /**
2083 * @brief Disable Transfer Complete Interrupt
2084 * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC
2085 * @param DMA2Dx DMA2D Instance
2086 * @retval None
2087 */
LL_DMA2D_DisableIT_TC(DMA2D_TypeDef * DMA2Dx)2088 __STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
2089 {
2090 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
2091 }
2092
2093 /**
2094 * @brief Disable Transfer Error Interrupt
2095 * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE
2096 * @param DMA2Dx DMA2D Instance
2097 * @retval None
2098 */
LL_DMA2D_DisableIT_TE(DMA2D_TypeDef * DMA2Dx)2099 __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
2100 {
2101 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
2102 }
2103
2104 /**
2105 * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
2106 * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE
2107 * @param DMA2Dx DMA2D Instance
2108 * @retval State of bit (1 or 0).
2109 */
LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef * DMA2Dx)2110 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
2111 {
2112 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
2113 }
2114
2115 /**
2116 * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
2117 * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC
2118 * @param DMA2Dx DMA2D Instance
2119 * @retval State of bit (1 or 0).
2120 */
LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef * DMA2Dx)2121 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
2122 {
2123 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
2124 }
2125
2126 /**
2127 * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
2128 * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE
2129 * @param DMA2Dx DMA2D Instance
2130 * @retval State of bit (1 or 0).
2131 */
LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef * DMA2Dx)2132 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
2133 {
2134 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
2135 }
2136
2137 /**
2138 * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
2139 * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW
2140 * @param DMA2Dx DMA2D Instance
2141 * @retval State of bit (1 or 0).
2142 */
LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef * DMA2Dx)2143 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
2144 {
2145 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
2146 }
2147
2148 /**
2149 * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
2150 * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC
2151 * @param DMA2Dx DMA2D Instance
2152 * @retval State of bit (1 or 0).
2153 */
LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef * DMA2Dx)2154 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
2155 {
2156 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
2157 }
2158
2159 /**
2160 * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
2161 * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE
2162 * @param DMA2Dx DMA2D Instance
2163 * @retval State of bit (1 or 0).
2164 */
LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef * DMA2Dx)2165 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
2166 {
2167 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
2168 }
2169
2170
2171
2172 /**
2173 * @}
2174 */
2175
2176 #if defined(USE_FULL_LL_DRIVER)
2177 /** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
2178 * @{
2179 */
2180
2181 ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx);
2182 ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2183 void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2184 void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
2185 void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
2186 void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
2187 uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2188 uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2189 uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2190 uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2191 void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
2192
2193 /**
2194 * @}
2195 */
2196 #endif /* USE_FULL_LL_DRIVER */
2197
2198 /**
2199 * @}
2200 */
2201
2202 /**
2203 * @}
2204 */
2205
2206 #endif /* defined (DMA2D) */
2207
2208 /**
2209 * @}
2210 */
2211
2212 #ifdef __cplusplus
2213 }
2214 #endif
2215
2216 #endif /* STM32L4xx_LL_DMA2D_H */
2217
