1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L4xx_LL_DMA_H
21 #define STM32L4xx_LL_DMA_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l4xx.h"
29 #if defined(DMAMUX1)
30 #include "stm32l4xx_ll_dmamux.h"
31 #endif /* DMAMUX1 */
32
33 /** @addtogroup STM32L4xx_LL_Driver
34 * @{
35 */
36
37 #if defined (DMA1) || defined (DMA2)
38
39 /** @defgroup DMA_LL DMA
40 * @{
41 */
42
43 /* Private types -------------------------------------------------------------*/
44 /* Private variables ---------------------------------------------------------*/
45 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
46 * @{
47 */
48 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
49 static const uint8_t CHANNEL_OFFSET_TAB[] =
50 {
51 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
55 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
56 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
57 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
58 };
59 /**
60 * @}
61 */
62
63 /* Private constants ---------------------------------------------------------*/
64 #if defined(DMAMUX1)
65 #else
66 /** @defgroup DMA_LL_Private_Constants DMA Private Constants
67 * @{
68 */
69 /* Define used to get CSELR register offset */
70 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
71
72 /* Defines used for the bit position in the register and perform offsets */
73 #define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << (Channel*4U))
74 /**
75 * @}
76 */
77 #endif /* DMAMUX1 */
78 /* Private macros ------------------------------------------------------------*/
79 #if defined(DMAMUX1)
80
81 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
82 * @{
83 */
84 /**
85 * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel
86 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
87 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
88 * @param __DMA_INSTANCE__ DMAx
89 * @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0).
90 */
91 #define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \
92 (((__DMA_INSTANCE__) == DMA1) ? 0x00000000U : LL_DMA_CHANNEL_7)
93
94 /**
95 * @}
96 */
97 #else
98 #if defined(USE_FULL_LL_DRIVER)
99 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
100 * @{
101 */
102 /**
103 * @}
104 */
105 #endif /*USE_FULL_LL_DRIVER*/
106 #endif /* DMAMUX1 */
107 /* Exported types ------------------------------------------------------------*/
108 #if defined(USE_FULL_LL_DRIVER)
109 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
110 * @{
111 */
112 typedef struct
113 {
114 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
115 or as Source base address in case of memory to memory transfer direction.
116
117 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
118
119 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
120 or as Destination base address in case of memory to memory transfer direction.
121
122 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
123
124 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
125 from memory to memory or from peripheral to memory.
126 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
127
128 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
129
130 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
131 This parameter can be a value of @ref DMA_LL_EC_MODE
132 @note: The circular buffer mode cannot be used if the memory to memory
133 data transfer direction is configured on the selected Channel
134
135 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
136
137 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
138 is incremented or not.
139 This parameter can be a value of @ref DMA_LL_EC_PERIPH
140
141 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
142
143 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
144 is incremented or not.
145 This parameter can be a value of @ref DMA_LL_EC_MEMORY
146
147 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
148
149 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
150 in case of memory to memory transfer direction.
151 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
152
153 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
154
155 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
156 in case of memory to memory transfer direction.
157 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
158
159 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
160
161 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
162 The data unit is equal to the source buffer configuration set in PeripheralSize
163 or MemorySize parameters depending in the transfer direction.
164 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
165
166 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
167
168 #if defined(DMAMUX1)
169 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
170 This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
171
172 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
173 #else
174 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
175 This parameter can be a value of @ref DMA_LL_EC_REQUEST
176
177 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
178 #endif /* DMAMUX1 */
179
180 uint32_t Priority; /*!< Specifies the channel priority level.
181 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
182
183 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
184
185 } LL_DMA_InitTypeDef;
186 /**
187 * @}
188 */
189 #endif /*USE_FULL_LL_DRIVER*/
190
191 /* Exported constants --------------------------------------------------------*/
192 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
193 * @{
194 */
195 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
196 * @brief Flags defines which can be used with LL_DMA_WriteReg function
197 * @{
198 */
199 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
200 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
201 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
202 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
203 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
204 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
205 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
206 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
207 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
208 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
209 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
210 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
211 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
212 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
213 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
214 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
215 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
216 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
217 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
218 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
219 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
220 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
221 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
222 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
223 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
224 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
225 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
226 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
227 /**
228 * @}
229 */
230
231 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
232 * @brief Flags defines which can be used with LL_DMA_ReadReg function
233 * @{
234 */
235 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
236 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
237 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
238 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
239 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
240 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
241 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
242 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
243 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
244 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
245 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
246 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
247 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
248 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
249 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
250 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
251 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
252 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
253 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
254 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
255 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
256 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
257 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
258 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
259 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
260 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
261 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
262 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
263 /**
264 * @}
265 */
266
267 /** @defgroup DMA_LL_EC_IT IT Defines
268 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
269 * @{
270 */
271 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
272 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
273 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
274 /**
275 * @}
276 */
277
278 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
279 * @{
280 */
281 #define LL_DMA_CHANNEL_1 0x00000000U /*!< DMA Channel 1 */
282 #define LL_DMA_CHANNEL_2 0x00000001U /*!< DMA Channel 2 */
283 #define LL_DMA_CHANNEL_3 0x00000002U /*!< DMA Channel 3 */
284 #define LL_DMA_CHANNEL_4 0x00000003U /*!< DMA Channel 4 */
285 #define LL_DMA_CHANNEL_5 0x00000004U /*!< DMA Channel 5 */
286 #define LL_DMA_CHANNEL_6 0x00000005U /*!< DMA Channel 6 */
287 #define LL_DMA_CHANNEL_7 0x00000006U /*!< DMA Channel 7 */
288 #if defined(USE_FULL_LL_DRIVER)
289 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
290 #endif /*USE_FULL_LL_DRIVER*/
291 /**
292 * @}
293 */
294
295 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
296 * @{
297 */
298 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
299 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
300 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
301 /**
302 * @}
303 */
304
305 /** @defgroup DMA_LL_EC_MODE Transfer mode
306 * @{
307 */
308 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
309 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
310 /**
311 * @}
312 */
313
314 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
315 * @{
316 */
317 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
318 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
319 /**
320 * @}
321 */
322
323 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
324 * @{
325 */
326 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
327 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
328 /**
329 * @}
330 */
331
332 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
333 * @{
334 */
335 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
336 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
337 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
338 /**
339 * @}
340 */
341
342 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
343 * @{
344 */
345 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
346 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
347 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
348 /**
349 * @}
350 */
351
352 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
353 * @{
354 */
355 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
356 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
357 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
358 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
359 /**
360 * @}
361 */
362
363 #if !defined (DMAMUX1)
364 /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
365 * @{
366 */
367 #define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */
368 #define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */
369 #define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */
370 #define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */
371 #define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */
372 #define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */
373 #define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */
374 #define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */
375 /**
376 * @}
377 */
378 #endif /* !defined DMAMUX1 */
379 /**
380 * @}
381 */
382
383 /* Exported macro ------------------------------------------------------------*/
384 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
385 * @{
386 */
387
388 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
389 * @{
390 */
391 /**
392 * @brief Write a value in DMA register
393 * @param __INSTANCE__ DMA Instance
394 * @param __REG__ Register to be written
395 * @param __VALUE__ Value to be written in the register
396 * @retval None
397 */
398 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
399
400 /**
401 * @brief Read a value in DMA register
402 * @param __INSTANCE__ DMA Instance
403 * @param __REG__ Register to be read
404 * @retval Register value
405 */
406 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
407 /**
408 * @}
409 */
410
411 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
412 * @{
413 */
414 /**
415 * @brief Convert DMAx_Channely into DMAx
416 * @param __CHANNEL_INSTANCE__ DMAx_Channely
417 * @retval DMAx
418 */
419 #if defined(DMA2)
420 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
421 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
422 #else
423 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
424 #endif
425
426 /**
427 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
428 * @param __CHANNEL_INSTANCE__ DMAx_Channely
429 * @retval LL_DMA_CHANNEL_y
430 */
431 #if defined (DMA2)
432 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
433 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
434 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
435 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
436 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
437 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
438 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
439 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
440 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
441 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
442 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
443 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
444 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
445 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
446 LL_DMA_CHANNEL_7)
447 #else
448 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
449 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
450 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
451 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
452 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
453 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
454 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
455 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
456 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
457 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
458 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
459 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
460 LL_DMA_CHANNEL_7)
461 #endif
462 #else
463 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
464 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
465 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
466 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
467 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
468 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
469 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
470 LL_DMA_CHANNEL_7)
471 #endif
472
473 /**
474 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
475 * @param __DMA_INSTANCE__ DMAx
476 * @param __CHANNEL__ LL_DMA_CHANNEL_y
477 * @retval DMAx_Channely
478 */
479 #if defined (DMA2)
480 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
481 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
482 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
483 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
484 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
485 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
486 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
487 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
488 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
489 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
490 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
491 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
492 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
493 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
494 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
495 DMA2_Channel7)
496 #else
497 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
498 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
499 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
500 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
501 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
502 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
503 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
504 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
505 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
506 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
507 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
508 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
509 DMA1_Channel7)
510 #endif
511 #else
512 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
513 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
514 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
515 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
516 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
517 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
518 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
519 DMA1_Channel7)
520 #endif
521
522 /**
523 * @}
524 */
525
526 /**
527 * @}
528 */
529
530 /* Exported functions --------------------------------------------------------*/
531 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
532 * @{
533 */
534
535 /** @defgroup DMA_LL_EF_Configuration Configuration
536 * @{
537 */
538 /**
539 * @brief Enable DMA channel.
540 * @rmtoll CCR EN LL_DMA_EnableChannel
541 * @param DMAx DMAx Instance
542 * @param Channel This parameter can be one of the following values:
543 * @arg @ref LL_DMA_CHANNEL_1
544 * @arg @ref LL_DMA_CHANNEL_2
545 * @arg @ref LL_DMA_CHANNEL_3
546 * @arg @ref LL_DMA_CHANNEL_4
547 * @arg @ref LL_DMA_CHANNEL_5
548 * @arg @ref LL_DMA_CHANNEL_6
549 * @arg @ref LL_DMA_CHANNEL_7
550 * @retval None
551 */
LL_DMA_EnableChannel(DMA_TypeDef * DMAx,uint32_t Channel)552 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
553 {
554 uint32_t dma_base_addr = (uint32_t)DMAx;
555 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
556 }
557
558 /**
559 * @brief Disable DMA channel.
560 * @rmtoll CCR EN LL_DMA_DisableChannel
561 * @param DMAx DMAx Instance
562 * @param Channel This parameter can be one of the following values:
563 * @arg @ref LL_DMA_CHANNEL_1
564 * @arg @ref LL_DMA_CHANNEL_2
565 * @arg @ref LL_DMA_CHANNEL_3
566 * @arg @ref LL_DMA_CHANNEL_4
567 * @arg @ref LL_DMA_CHANNEL_5
568 * @arg @ref LL_DMA_CHANNEL_6
569 * @arg @ref LL_DMA_CHANNEL_7
570 * @retval None
571 */
LL_DMA_DisableChannel(DMA_TypeDef * DMAx,uint32_t Channel)572 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
573 {
574 uint32_t dma_base_addr = (uint32_t)DMAx;
575 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
576 }
577
578 /**
579 * @brief Check if DMA channel is enabled or disabled.
580 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
581 * @param DMAx DMAx Instance
582 * @param Channel This parameter can be one of the following values:
583 * @arg @ref LL_DMA_CHANNEL_1
584 * @arg @ref LL_DMA_CHANNEL_2
585 * @arg @ref LL_DMA_CHANNEL_3
586 * @arg @ref LL_DMA_CHANNEL_4
587 * @arg @ref LL_DMA_CHANNEL_5
588 * @arg @ref LL_DMA_CHANNEL_6
589 * @arg @ref LL_DMA_CHANNEL_7
590 * @retval State of bit (1 or 0).
591 */
LL_DMA_IsEnabledChannel(DMA_TypeDef * DMAx,uint32_t Channel)592 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
593 {
594 uint32_t dma_base_addr = (uint32_t)DMAx;
595 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
596 DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
597 }
598
599 /**
600 * @brief Configure all parameters link to DMA transfer.
601 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
602 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
603 * CCR CIRC LL_DMA_ConfigTransfer\n
604 * CCR PINC LL_DMA_ConfigTransfer\n
605 * CCR MINC LL_DMA_ConfigTransfer\n
606 * CCR PSIZE LL_DMA_ConfigTransfer\n
607 * CCR MSIZE LL_DMA_ConfigTransfer\n
608 * CCR PL LL_DMA_ConfigTransfer
609 * @param DMAx DMAx Instance
610 * @param Channel This parameter can be one of the following values:
611 * @arg @ref LL_DMA_CHANNEL_1
612 * @arg @ref LL_DMA_CHANNEL_2
613 * @arg @ref LL_DMA_CHANNEL_3
614 * @arg @ref LL_DMA_CHANNEL_4
615 * @arg @ref LL_DMA_CHANNEL_5
616 * @arg @ref LL_DMA_CHANNEL_6
617 * @arg @ref LL_DMA_CHANNEL_7
618 * @param Configuration This parameter must be a combination of all the following values:
619 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
620 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
621 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
622 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
623 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
624 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
625 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
626 * @retval None
627 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)628 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
629 {
630 uint32_t dma_base_addr = (uint32_t)DMAx;
631 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
632 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
633 Configuration);
634 }
635
636 /**
637 * @brief Set Data transfer direction (read from peripheral or from memory).
638 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
639 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
640 * @param DMAx DMAx Instance
641 * @param Channel This parameter can be one of the following values:
642 * @arg @ref LL_DMA_CHANNEL_1
643 * @arg @ref LL_DMA_CHANNEL_2
644 * @arg @ref LL_DMA_CHANNEL_3
645 * @arg @ref LL_DMA_CHANNEL_4
646 * @arg @ref LL_DMA_CHANNEL_5
647 * @arg @ref LL_DMA_CHANNEL_6
648 * @arg @ref LL_DMA_CHANNEL_7
649 * @param Direction This parameter can be one of the following values:
650 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
651 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
652 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
653 * @retval None
654 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)655 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
656 {
657 uint32_t dma_base_addr = (uint32_t)DMAx;
658 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
659 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
660 }
661
662 /**
663 * @brief Get Data transfer direction (read from peripheral or from memory).
664 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
665 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
666 * @param DMAx DMAx Instance
667 * @param Channel This parameter can be one of the following values:
668 * @arg @ref LL_DMA_CHANNEL_1
669 * @arg @ref LL_DMA_CHANNEL_2
670 * @arg @ref LL_DMA_CHANNEL_3
671 * @arg @ref LL_DMA_CHANNEL_4
672 * @arg @ref LL_DMA_CHANNEL_5
673 * @arg @ref LL_DMA_CHANNEL_6
674 * @arg @ref LL_DMA_CHANNEL_7
675 * @retval Returned value can be one of the following values:
676 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
677 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
678 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
679 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel)680 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
681 {
682 uint32_t dma_base_addr = (uint32_t)DMAx;
683 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
684 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
685 }
686
687 /**
688 * @brief Set DMA mode circular or normal.
689 * @note The circular buffer mode cannot be used if the memory-to-memory
690 * data transfer is configured on the selected Channel.
691 * @rmtoll CCR CIRC LL_DMA_SetMode
692 * @param DMAx DMAx Instance
693 * @param Channel This parameter can be one of the following values:
694 * @arg @ref LL_DMA_CHANNEL_1
695 * @arg @ref LL_DMA_CHANNEL_2
696 * @arg @ref LL_DMA_CHANNEL_3
697 * @arg @ref LL_DMA_CHANNEL_4
698 * @arg @ref LL_DMA_CHANNEL_5
699 * @arg @ref LL_DMA_CHANNEL_6
700 * @arg @ref LL_DMA_CHANNEL_7
701 * @param Mode This parameter can be one of the following values:
702 * @arg @ref LL_DMA_MODE_NORMAL
703 * @arg @ref LL_DMA_MODE_CIRCULAR
704 * @retval None
705 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)706 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
707 {
708 uint32_t dma_base_addr = (uint32_t)DMAx;
709 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CIRC,
710 Mode);
711 }
712
713 /**
714 * @brief Get DMA mode circular or normal.
715 * @rmtoll CCR CIRC LL_DMA_GetMode
716 * @param DMAx DMAx Instance
717 * @param Channel This parameter can be one of the following values:
718 * @arg @ref LL_DMA_CHANNEL_1
719 * @arg @ref LL_DMA_CHANNEL_2
720 * @arg @ref LL_DMA_CHANNEL_3
721 * @arg @ref LL_DMA_CHANNEL_4
722 * @arg @ref LL_DMA_CHANNEL_5
723 * @arg @ref LL_DMA_CHANNEL_6
724 * @arg @ref LL_DMA_CHANNEL_7
725 * @retval Returned value can be one of the following values:
726 * @arg @ref LL_DMA_MODE_NORMAL
727 * @arg @ref LL_DMA_MODE_CIRCULAR
728 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Channel)729 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
730 {
731 uint32_t dma_base_addr = (uint32_t)DMAx;
732 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
733 DMA_CCR_CIRC));
734 }
735
736 /**
737 * @brief Set Peripheral increment mode.
738 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
739 * @param DMAx DMAx Instance
740 * @param Channel This parameter can be one of the following values:
741 * @arg @ref LL_DMA_CHANNEL_1
742 * @arg @ref LL_DMA_CHANNEL_2
743 * @arg @ref LL_DMA_CHANNEL_3
744 * @arg @ref LL_DMA_CHANNEL_4
745 * @arg @ref LL_DMA_CHANNEL_5
746 * @arg @ref LL_DMA_CHANNEL_6
747 * @arg @ref LL_DMA_CHANNEL_7
748 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
749 * @arg @ref LL_DMA_PERIPH_INCREMENT
750 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
751 * @retval None
752 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcIncMode)753 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
754 {
755 uint32_t dma_base_addr = (uint32_t)DMAx;
756 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PINC,
757 PeriphOrM2MSrcIncMode);
758 }
759
760 /**
761 * @brief Get Peripheral increment mode.
762 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
763 * @param DMAx DMAx Instance
764 * @param Channel This parameter can be one of the following values:
765 * @arg @ref LL_DMA_CHANNEL_1
766 * @arg @ref LL_DMA_CHANNEL_2
767 * @arg @ref LL_DMA_CHANNEL_3
768 * @arg @ref LL_DMA_CHANNEL_4
769 * @arg @ref LL_DMA_CHANNEL_5
770 * @arg @ref LL_DMA_CHANNEL_6
771 * @arg @ref LL_DMA_CHANNEL_7
772 * @retval Returned value can be one of the following values:
773 * @arg @ref LL_DMA_PERIPH_INCREMENT
774 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
775 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel)776 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
777 {
778 uint32_t dma_base_addr = (uint32_t)DMAx;
779 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
780 DMA_CCR_PINC));
781 }
782
783 /**
784 * @brief Set Memory increment mode.
785 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
786 * @param DMAx DMAx Instance
787 * @param Channel This parameter can be one of the following values:
788 * @arg @ref LL_DMA_CHANNEL_1
789 * @arg @ref LL_DMA_CHANNEL_2
790 * @arg @ref LL_DMA_CHANNEL_3
791 * @arg @ref LL_DMA_CHANNEL_4
792 * @arg @ref LL_DMA_CHANNEL_5
793 * @arg @ref LL_DMA_CHANNEL_6
794 * @arg @ref LL_DMA_CHANNEL_7
795 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
796 * @arg @ref LL_DMA_MEMORY_INCREMENT
797 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
798 * @retval None
799 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstIncMode)800 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
801 {
802 uint32_t dma_base_addr = (uint32_t)DMAx;
803 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MINC,
804 MemoryOrM2MDstIncMode);
805 }
806
807 /**
808 * @brief Get Memory increment mode.
809 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
810 * @param DMAx DMAx Instance
811 * @param Channel This parameter can be one of the following values:
812 * @arg @ref LL_DMA_CHANNEL_1
813 * @arg @ref LL_DMA_CHANNEL_2
814 * @arg @ref LL_DMA_CHANNEL_3
815 * @arg @ref LL_DMA_CHANNEL_4
816 * @arg @ref LL_DMA_CHANNEL_5
817 * @arg @ref LL_DMA_CHANNEL_6
818 * @arg @ref LL_DMA_CHANNEL_7
819 * @retval Returned value can be one of the following values:
820 * @arg @ref LL_DMA_MEMORY_INCREMENT
821 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
822 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel)823 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
824 {
825 uint32_t dma_base_addr = (uint32_t)DMAx;
826 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
827 DMA_CCR_MINC));
828 }
829
830 /**
831 * @brief Set Peripheral size.
832 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
833 * @param DMAx DMAx Instance
834 * @param Channel This parameter can be one of the following values:
835 * @arg @ref LL_DMA_CHANNEL_1
836 * @arg @ref LL_DMA_CHANNEL_2
837 * @arg @ref LL_DMA_CHANNEL_3
838 * @arg @ref LL_DMA_CHANNEL_4
839 * @arg @ref LL_DMA_CHANNEL_5
840 * @arg @ref LL_DMA_CHANNEL_6
841 * @arg @ref LL_DMA_CHANNEL_7
842 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
843 * @arg @ref LL_DMA_PDATAALIGN_BYTE
844 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
845 * @arg @ref LL_DMA_PDATAALIGN_WORD
846 * @retval None
847 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcDataSize)848 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
849 {
850 uint32_t dma_base_addr = (uint32_t)DMAx;
851 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PSIZE,
852 PeriphOrM2MSrcDataSize);
853 }
854
855 /**
856 * @brief Get Peripheral size.
857 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
858 * @param DMAx DMAx Instance
859 * @param Channel This parameter can be one of the following values:
860 * @arg @ref LL_DMA_CHANNEL_1
861 * @arg @ref LL_DMA_CHANNEL_2
862 * @arg @ref LL_DMA_CHANNEL_3
863 * @arg @ref LL_DMA_CHANNEL_4
864 * @arg @ref LL_DMA_CHANNEL_5
865 * @arg @ref LL_DMA_CHANNEL_6
866 * @arg @ref LL_DMA_CHANNEL_7
867 * @retval Returned value can be one of the following values:
868 * @arg @ref LL_DMA_PDATAALIGN_BYTE
869 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
870 * @arg @ref LL_DMA_PDATAALIGN_WORD
871 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel)872 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
873 {
874 uint32_t dma_base_addr = (uint32_t)DMAx;
875 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
876 DMA_CCR_PSIZE));
877 }
878
879 /**
880 * @brief Set Memory size.
881 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
882 * @param DMAx DMAx Instance
883 * @param Channel This parameter can be one of the following values:
884 * @arg @ref LL_DMA_CHANNEL_1
885 * @arg @ref LL_DMA_CHANNEL_2
886 * @arg @ref LL_DMA_CHANNEL_3
887 * @arg @ref LL_DMA_CHANNEL_4
888 * @arg @ref LL_DMA_CHANNEL_5
889 * @arg @ref LL_DMA_CHANNEL_6
890 * @arg @ref LL_DMA_CHANNEL_7
891 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
892 * @arg @ref LL_DMA_MDATAALIGN_BYTE
893 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
894 * @arg @ref LL_DMA_MDATAALIGN_WORD
895 * @retval None
896 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstDataSize)897 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
898 {
899 uint32_t dma_base_addr = (uint32_t)DMAx;
900 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MSIZE,
901 MemoryOrM2MDstDataSize);
902 }
903
904 /**
905 * @brief Get Memory size.
906 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
907 * @param DMAx DMAx Instance
908 * @param Channel This parameter can be one of the following values:
909 * @arg @ref LL_DMA_CHANNEL_1
910 * @arg @ref LL_DMA_CHANNEL_2
911 * @arg @ref LL_DMA_CHANNEL_3
912 * @arg @ref LL_DMA_CHANNEL_4
913 * @arg @ref LL_DMA_CHANNEL_5
914 * @arg @ref LL_DMA_CHANNEL_6
915 * @arg @ref LL_DMA_CHANNEL_7
916 * @retval Returned value can be one of the following values:
917 * @arg @ref LL_DMA_MDATAALIGN_BYTE
918 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
919 * @arg @ref LL_DMA_MDATAALIGN_WORD
920 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel)921 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
922 {
923 uint32_t dma_base_addr = (uint32_t)DMAx;
924 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
925 DMA_CCR_MSIZE));
926 }
927
928 /**
929 * @brief Set Channel priority level.
930 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
931 * @param DMAx DMAx Instance
932 * @param Channel This parameter can be one of the following values:
933 * @arg @ref LL_DMA_CHANNEL_1
934 * @arg @ref LL_DMA_CHANNEL_2
935 * @arg @ref LL_DMA_CHANNEL_3
936 * @arg @ref LL_DMA_CHANNEL_4
937 * @arg @ref LL_DMA_CHANNEL_5
938 * @arg @ref LL_DMA_CHANNEL_6
939 * @arg @ref LL_DMA_CHANNEL_7
940 * @param Priority This parameter can be one of the following values:
941 * @arg @ref LL_DMA_PRIORITY_LOW
942 * @arg @ref LL_DMA_PRIORITY_MEDIUM
943 * @arg @ref LL_DMA_PRIORITY_HIGH
944 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
945 * @retval None
946 */
LL_DMA_SetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)947 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
948 {
949 uint32_t dma_base_addr = (uint32_t)DMAx;
950 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PL,
951 Priority);
952 }
953
954 /**
955 * @brief Get Channel priority level.
956 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
957 * @param DMAx DMAx Instance
958 * @param Channel This parameter can be one of the following values:
959 * @arg @ref LL_DMA_CHANNEL_1
960 * @arg @ref LL_DMA_CHANNEL_2
961 * @arg @ref LL_DMA_CHANNEL_3
962 * @arg @ref LL_DMA_CHANNEL_4
963 * @arg @ref LL_DMA_CHANNEL_5
964 * @arg @ref LL_DMA_CHANNEL_6
965 * @arg @ref LL_DMA_CHANNEL_7
966 * @retval Returned value can be one of the following values:
967 * @arg @ref LL_DMA_PRIORITY_LOW
968 * @arg @ref LL_DMA_PRIORITY_MEDIUM
969 * @arg @ref LL_DMA_PRIORITY_HIGH
970 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
971 */
LL_DMA_GetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel)972 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
973 {
974 uint32_t dma_base_addr = (uint32_t)DMAx;
975 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
976 DMA_CCR_PL));
977 }
978
979 /**
980 * @brief Set Number of data to transfer.
981 * @note This action has no effect if
982 * channel is enabled.
983 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
984 * @param DMAx DMAx Instance
985 * @param Channel This parameter can be one of the following values:
986 * @arg @ref LL_DMA_CHANNEL_1
987 * @arg @ref LL_DMA_CHANNEL_2
988 * @arg @ref LL_DMA_CHANNEL_3
989 * @arg @ref LL_DMA_CHANNEL_4
990 * @arg @ref LL_DMA_CHANNEL_5
991 * @arg @ref LL_DMA_CHANNEL_6
992 * @arg @ref LL_DMA_CHANNEL_7
993 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
994 * @retval None
995 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t NbData)996 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
997 {
998 uint32_t dma_base_addr = (uint32_t)DMAx;
999 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR,
1000 DMA_CNDTR_NDT, NbData);
1001 }
1002
1003 /**
1004 * @brief Get Number of data to transfer.
1005 * @note Once the channel is enabled, the return value indicate the
1006 * remaining bytes to be transmitted.
1007 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
1008 * @param DMAx DMAx Instance
1009 * @param Channel This parameter can be one of the following values:
1010 * @arg @ref LL_DMA_CHANNEL_1
1011 * @arg @ref LL_DMA_CHANNEL_2
1012 * @arg @ref LL_DMA_CHANNEL_3
1013 * @arg @ref LL_DMA_CHANNEL_4
1014 * @arg @ref LL_DMA_CHANNEL_5
1015 * @arg @ref LL_DMA_CHANNEL_6
1016 * @arg @ref LL_DMA_CHANNEL_7
1017 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1018 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Channel)1019 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
1020 {
1021 uint32_t dma_base_addr = (uint32_t)DMAx;
1022 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR,
1023 DMA_CNDTR_NDT));
1024 }
1025
1026 /**
1027 * @brief Configure the Source and Destination addresses.
1028 * @note This API must not be called when the DMA channel is enabled.
1029 * @note Each peripheral using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
1030 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
1031 * CMAR MA LL_DMA_ConfigAddresses
1032 * @param DMAx DMAx Instance
1033 * @param Channel This parameter can be one of the following values:
1034 * @arg @ref LL_DMA_CHANNEL_1
1035 * @arg @ref LL_DMA_CHANNEL_2
1036 * @arg @ref LL_DMA_CHANNEL_3
1037 * @arg @ref LL_DMA_CHANNEL_4
1038 * @arg @ref LL_DMA_CHANNEL_5
1039 * @arg @ref LL_DMA_CHANNEL_6
1040 * @arg @ref LL_DMA_CHANNEL_7
1041 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1042 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1043 * @param Direction This parameter can be one of the following values:
1044 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1045 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1046 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1047 * @retval None
1048 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)1049 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
1050 uint32_t DstAddress, uint32_t Direction)
1051 {
1052 uint32_t dma_base_addr = (uint32_t)DMAx;
1053 /* Direction Memory to Periph */
1054 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
1055 {
1056 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, SrcAddress);
1057 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, DstAddress);
1058 }
1059 /* Direction Periph to Memory and Memory to Memory */
1060 else
1061 {
1062 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, SrcAddress);
1063 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, DstAddress);
1064 }
1065 }
1066
1067 /**
1068 * @brief Set the Memory address.
1069 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1070 * @note This API must not be called when the DMA channel is enabled.
1071 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
1072 * @param DMAx DMAx Instance
1073 * @param Channel This parameter can be one of the following values:
1074 * @arg @ref LL_DMA_CHANNEL_1
1075 * @arg @ref LL_DMA_CHANNEL_2
1076 * @arg @ref LL_DMA_CHANNEL_3
1077 * @arg @ref LL_DMA_CHANNEL_4
1078 * @arg @ref LL_DMA_CHANNEL_5
1079 * @arg @ref LL_DMA_CHANNEL_6
1080 * @arg @ref LL_DMA_CHANNEL_7
1081 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1082 * @retval None
1083 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1084 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1085 {
1086 uint32_t dma_base_addr = (uint32_t)DMAx;
1087 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress);
1088 }
1089
1090 /**
1091 * @brief Set the Peripheral address.
1092 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1093 * @note This API must not be called when the DMA channel is enabled.
1094 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
1095 * @param DMAx DMAx Instance
1096 * @param Channel This parameter can be one of the following values:
1097 * @arg @ref LL_DMA_CHANNEL_1
1098 * @arg @ref LL_DMA_CHANNEL_2
1099 * @arg @ref LL_DMA_CHANNEL_3
1100 * @arg @ref LL_DMA_CHANNEL_4
1101 * @arg @ref LL_DMA_CHANNEL_5
1102 * @arg @ref LL_DMA_CHANNEL_6
1103 * @arg @ref LL_DMA_CHANNEL_7
1104 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1105 * @retval None
1106 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphAddress)1107 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
1108 {
1109 uint32_t dma_base_addr = (uint32_t)DMAx;
1110 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, PeriphAddress);
1111 }
1112
1113 /**
1114 * @brief Get Memory address.
1115 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1116 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
1117 * @param DMAx DMAx Instance
1118 * @param Channel This parameter can be one of the following values:
1119 * @arg @ref LL_DMA_CHANNEL_1
1120 * @arg @ref LL_DMA_CHANNEL_2
1121 * @arg @ref LL_DMA_CHANNEL_3
1122 * @arg @ref LL_DMA_CHANNEL_4
1123 * @arg @ref LL_DMA_CHANNEL_5
1124 * @arg @ref LL_DMA_CHANNEL_6
1125 * @arg @ref LL_DMA_CHANNEL_7
1126 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1127 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel)1128 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1129 {
1130 uint32_t dma_base_addr = (uint32_t)DMAx;
1131 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR));
1132 }
1133
1134 /**
1135 * @brief Get Peripheral address.
1136 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1137 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
1138 * @param DMAx DMAx Instance
1139 * @param Channel This parameter can be one of the following values:
1140 * @arg @ref LL_DMA_CHANNEL_1
1141 * @arg @ref LL_DMA_CHANNEL_2
1142 * @arg @ref LL_DMA_CHANNEL_3
1143 * @arg @ref LL_DMA_CHANNEL_4
1144 * @arg @ref LL_DMA_CHANNEL_5
1145 * @arg @ref LL_DMA_CHANNEL_6
1146 * @arg @ref LL_DMA_CHANNEL_7
1147 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1148 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel)1149 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1150 {
1151 uint32_t dma_base_addr = (uint32_t)DMAx;
1152 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR));
1153 }
1154
1155 /**
1156 * @brief Set the Memory to Memory Source address.
1157 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1158 * @note This API must not be called when the DMA channel is enabled.
1159 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
1160 * @param DMAx DMAx Instance
1161 * @param Channel This parameter can be one of the following values:
1162 * @arg @ref LL_DMA_CHANNEL_1
1163 * @arg @ref LL_DMA_CHANNEL_2
1164 * @arg @ref LL_DMA_CHANNEL_3
1165 * @arg @ref LL_DMA_CHANNEL_4
1166 * @arg @ref LL_DMA_CHANNEL_5
1167 * @arg @ref LL_DMA_CHANNEL_6
1168 * @arg @ref LL_DMA_CHANNEL_7
1169 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1170 * @retval None
1171 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1172 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1173 {
1174 uint32_t dma_base_addr = (uint32_t)DMAx;
1175 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, MemoryAddress);
1176 }
1177
1178 /**
1179 * @brief Set the Memory to Memory Destination address.
1180 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1181 * @note This API must not be called when the DMA channel is enabled.
1182 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
1183 * @param DMAx DMAx Instance
1184 * @param Channel This parameter can be one of the following values:
1185 * @arg @ref LL_DMA_CHANNEL_1
1186 * @arg @ref LL_DMA_CHANNEL_2
1187 * @arg @ref LL_DMA_CHANNEL_3
1188 * @arg @ref LL_DMA_CHANNEL_4
1189 * @arg @ref LL_DMA_CHANNEL_5
1190 * @arg @ref LL_DMA_CHANNEL_6
1191 * @arg @ref LL_DMA_CHANNEL_7
1192 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1193 * @retval None
1194 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1195 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1196 {
1197 uint32_t dma_base_addr = (uint32_t)DMAx;
1198 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress);
1199 }
1200
1201 /**
1202 * @brief Get the Memory to Memory Source address.
1203 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1204 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
1205 * @param DMAx DMAx Instance
1206 * @param Channel This parameter can be one of the following values:
1207 * @arg @ref LL_DMA_CHANNEL_1
1208 * @arg @ref LL_DMA_CHANNEL_2
1209 * @arg @ref LL_DMA_CHANNEL_3
1210 * @arg @ref LL_DMA_CHANNEL_4
1211 * @arg @ref LL_DMA_CHANNEL_5
1212 * @arg @ref LL_DMA_CHANNEL_6
1213 * @arg @ref LL_DMA_CHANNEL_7
1214 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1215 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel)1216 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1217 {
1218 uint32_t dma_base_addr = (uint32_t)DMAx;
1219 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR));
1220 }
1221
1222 /**
1223 * @brief Get the Memory to Memory Destination address.
1224 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1225 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
1226 * @param DMAx DMAx Instance
1227 * @param Channel This parameter can be one of the following values:
1228 * @arg @ref LL_DMA_CHANNEL_1
1229 * @arg @ref LL_DMA_CHANNEL_2
1230 * @arg @ref LL_DMA_CHANNEL_3
1231 * @arg @ref LL_DMA_CHANNEL_4
1232 * @arg @ref LL_DMA_CHANNEL_5
1233 * @arg @ref LL_DMA_CHANNEL_6
1234 * @arg @ref LL_DMA_CHANNEL_7
1235 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1236 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel)1237 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1238 {
1239 uint32_t dma_base_addr = (uint32_t)DMAx;
1240 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR));
1241 }
1242
1243 #if defined(DMAMUX1)
1244 /**
1245 * @brief Set DMA request for DMA Channels on DMAMUX Channel x.
1246 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1247 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
1248 * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
1249 * @param DMAx DMAx Instance
1250 * @param Channel This parameter can be one of the following values:
1251 * @arg @ref LL_DMA_CHANNEL_1
1252 * @arg @ref LL_DMA_CHANNEL_2
1253 * @arg @ref LL_DMA_CHANNEL_3
1254 * @arg @ref LL_DMA_CHANNEL_4
1255 * @arg @ref LL_DMA_CHANNEL_5
1256 * @arg @ref LL_DMA_CHANNEL_6
1257 * @arg @ref LL_DMA_CHANNEL_7
1258 * @param Request This parameter can be one of the following values:
1259 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1260 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1261 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1262 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1263 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1264 * @arg @ref LL_DMAMUX_REQ_ADC1
1265 * @arg @ref LL_DMAMUX_REQ_ADC2
1266 * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
1267 * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
1268 * @arg @ref LL_DMAMUX_REQ_TIM6_UP
1269 * @arg @ref LL_DMAMUX_REQ_TIM7_UP
1270 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1271 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1272 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
1273 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
1274 * @arg @ref LL_DMAMUX_REQ_SPI3_RX
1275 * @arg @ref LL_DMAMUX_REQ_SPI3_TX
1276 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1277 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1278 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
1279 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
1280 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
1281 * @arg @ref LL_DMAMUX_REQ_I2C3_TX
1282 * @arg @ref LL_DMAMUX_REQ_I2C4_RX
1283 * @arg @ref LL_DMAMUX_REQ_I2C4_TX
1284 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1285 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1286 * @arg @ref LL_DMAMUX_REQ_USART2_RX
1287 * @arg @ref LL_DMAMUX_REQ_USART2_TX
1288 * @arg @ref LL_DMAMUX_REQ_USART3_RX
1289 * @arg @ref LL_DMAMUX_REQ_USART3_TX
1290 * @arg @ref LL_DMAMUX_REQ_UART4_RX
1291 * @arg @ref LL_DMAMUX_REQ_UART4_TX
1292 * @arg @ref LL_DMAMUX_REQ_UART5_RX
1293 * @arg @ref LL_DMAMUX_REQ_UART5_TX
1294 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
1295 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
1296 * @arg @ref LL_DMAMUX_REQ_SAI1_A
1297 * @arg @ref LL_DMAMUX_REQ_SAI1_B
1298 * @arg @ref LL_DMAMUX_REQ_SAI2_A
1299 * @arg @ref LL_DMAMUX_REQ_SAI2_B
1300 * @arg @ref LL_DMAMUX_REQ_OSPI1
1301 * @arg @ref LL_DMAMUX_REQ_OSPI2
1302 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1303 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1304 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1305 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1306 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1307 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
1308 * @arg @ref LL_DMAMUX_REQ_TIM1_COM
1309 * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
1310 * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
1311 * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
1312 * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
1313 * @arg @ref LL_DMAMUX_REQ_TIM8_UP
1314 * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
1315 * @arg @ref LL_DMAMUX_REQ_TIM8_COM
1316 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
1317 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
1318 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
1319 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
1320 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
1321 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
1322 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
1323 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
1324 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
1325 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
1326 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
1327 * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
1328 * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
1329 * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
1330 * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
1331 * @arg @ref LL_DMAMUX_REQ_TIM4_UP
1332 * @arg @ref LL_DMAMUX_REQ_TIM5_CH1
1333 * @arg @ref LL_DMAMUX_REQ_TIM5_CH2
1334 * @arg @ref LL_DMAMUX_REQ_TIM5_CH3
1335 * @arg @ref LL_DMAMUX_REQ_TIM5_CH4
1336 * @arg @ref LL_DMAMUX_REQ_TIM5_UP
1337 * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG
1338 * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
1339 * @arg @ref LL_DMAMUX_REQ_TIM15_UP
1340 * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
1341 * @arg @ref LL_DMAMUX_REQ_TIM15_COM
1342 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1343 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1344 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1345 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1346 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0
1347 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1
1348 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2
1349 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3
1350 * @arg @ref LL_DMAMUX_REQ_DCMI
1351 * @arg @ref LL_DMAMUX_REQ_DCMI_PSSI
1352 * @arg @ref LL_DMAMUX_REQ_AES_IN
1353 * @arg @ref LL_DMAMUX_REQ_AES_OUT
1354 * @arg @ref LL_DMAMUX_REQ_HASH_IN
1355 * @retval None
1356 */
LL_DMA_SetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Request)1357 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
1358 {
1359 uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U);
1360 MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
1361 }
1362
1363 /**
1364 * @brief Get DMA request for DMA Channels on DMAMUX Channel x.
1365 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1366 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
1367 * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
1368 * @param DMAx DMAx Instance
1369 * @param Channel This parameter can be one of the following values:
1370 * @arg @ref LL_DMA_CHANNEL_1
1371 * @arg @ref LL_DMA_CHANNEL_2
1372 * @arg @ref LL_DMA_CHANNEL_3
1373 * @arg @ref LL_DMA_CHANNEL_4
1374 * @arg @ref LL_DMA_CHANNEL_5
1375 * @arg @ref LL_DMA_CHANNEL_6
1376 * @arg @ref LL_DMA_CHANNEL_7
1377 * @retval Returned value can be one of the following values:
1378 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1379 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1380 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1381 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1382 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1383 * @arg @ref LL_DMAMUX_REQ_ADC1
1384 * @arg @ref LL_DMAMUX_REQ_ADC2
1385 * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
1386 * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
1387 * @arg @ref LL_DMAMUX_REQ_TIM6_UP
1388 * @arg @ref LL_DMAMUX_REQ_TIM7_UP
1389 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1390 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1391 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
1392 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
1393 * @arg @ref LL_DMAMUX_REQ_SPI3_RX
1394 * @arg @ref LL_DMAMUX_REQ_SPI3_TX
1395 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1396 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1397 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
1398 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
1399 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
1400 * @arg @ref LL_DMAMUX_REQ_I2C3_TX
1401 * @arg @ref LL_DMAMUX_REQ_I2C4_RX
1402 * @arg @ref LL_DMAMUX_REQ_I2C4_TX
1403 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1404 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1405 * @arg @ref LL_DMAMUX_REQ_USART2_RX
1406 * @arg @ref LL_DMAMUX_REQ_USART2_TX
1407 * @arg @ref LL_DMAMUX_REQ_USART3_RX
1408 * @arg @ref LL_DMAMUX_REQ_USART3_TX
1409 * @arg @ref LL_DMAMUX_REQ_UART4_RX
1410 * @arg @ref LL_DMAMUX_REQ_UART4_TX
1411 * @arg @ref LL_DMAMUX_REQ_UART5_RX
1412 * @arg @ref LL_DMAMUX_REQ_UART5_TX
1413 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
1414 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
1415 * @arg @ref LL_DMAMUX_REQ_SAI1_A
1416 * @arg @ref LL_DMAMUX_REQ_SAI1_B
1417 * @arg @ref LL_DMAMUX_REQ_SAI2_A
1418 * @arg @ref LL_DMAMUX_REQ_SAI2_B
1419 * @arg @ref LL_DMAMUX_REQ_OSPI1
1420 * @arg @ref LL_DMAMUX_REQ_OSPI2
1421 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1422 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1423 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1424 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1425 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1426 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
1427 * @arg @ref LL_DMAMUX_REQ_TIM1_COM
1428 * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
1429 * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
1430 * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
1431 * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
1432 * @arg @ref LL_DMAMUX_REQ_TIM8_UP
1433 * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
1434 * @arg @ref LL_DMAMUX_REQ_TIM8_COM
1435 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
1436 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
1437 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
1438 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
1439 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
1440 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
1441 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
1442 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
1443 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
1444 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
1445 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
1446 * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
1447 * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
1448 * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
1449 * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
1450 * @arg @ref LL_DMAMUX_REQ_TIM4_UP
1451 * @arg @ref LL_DMAMUX_REQ_TIM5_CH1
1452 * @arg @ref LL_DMAMUX_REQ_TIM5_CH2
1453 * @arg @ref LL_DMAMUX_REQ_TIM5_CH3
1454 * @arg @ref LL_DMAMUX_REQ_TIM5_CH4
1455 * @arg @ref LL_DMAMUX_REQ_TIM5_UP
1456 * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG
1457 * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
1458 * @arg @ref LL_DMAMUX_REQ_TIM15_UP
1459 * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
1460 * @arg @ref LL_DMAMUX_REQ_TIM15_COM
1461 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1462 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1463 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1464 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1465 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0
1466 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1
1467 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2
1468 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3
1469 * @arg @ref LL_DMAMUX_REQ_DCMI
1470 * @arg @ref LL_DMAMUX_REQ_DCMI_PSSI
1471 * @arg @ref LL_DMAMUX_REQ_AES_IN
1472 * @arg @ref LL_DMAMUX_REQ_AES_OUT
1473 * @arg @ref LL_DMAMUX_REQ_HASH_IN
1474 */
LL_DMA_GetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel)1475 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
1476 {
1477 uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U);
1478 return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID));
1479 }
1480
1481 #else
1482 /**
1483 * @brief Set DMA request for DMA instance on Channel x.
1484 * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
1485 * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
1486 * CSELR C2S LL_DMA_SetPeriphRequest\n
1487 * CSELR C3S LL_DMA_SetPeriphRequest\n
1488 * CSELR C4S LL_DMA_SetPeriphRequest\n
1489 * CSELR C5S LL_DMA_SetPeriphRequest\n
1490 * CSELR C6S LL_DMA_SetPeriphRequest\n
1491 * CSELR C7S LL_DMA_SetPeriphRequest
1492 * @param DMAx DMAx Instance
1493 * @param Channel This parameter can be one of the following values:
1494 * @arg @ref LL_DMA_CHANNEL_1
1495 * @arg @ref LL_DMA_CHANNEL_2
1496 * @arg @ref LL_DMA_CHANNEL_3
1497 * @arg @ref LL_DMA_CHANNEL_4
1498 * @arg @ref LL_DMA_CHANNEL_5
1499 * @arg @ref LL_DMA_CHANNEL_6
1500 * @arg @ref LL_DMA_CHANNEL_7
1501 * @param PeriphRequest This parameter can be one of the following values:
1502 * @arg @ref LL_DMA_REQUEST_0
1503 * @arg @ref LL_DMA_REQUEST_1
1504 * @arg @ref LL_DMA_REQUEST_2
1505 * @arg @ref LL_DMA_REQUEST_3
1506 * @arg @ref LL_DMA_REQUEST_4
1507 * @arg @ref LL_DMA_REQUEST_5
1508 * @arg @ref LL_DMA_REQUEST_6
1509 * @arg @ref LL_DMA_REQUEST_7
1510 * @retval None
1511 */
LL_DMA_SetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphRequest)1512 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
1513 {
1514 MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
1515 DMA_CSELR_C1S << ((Channel) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
1516 }
1517
1518 /**
1519 * @brief Get DMA request for DMA instance on Channel x.
1520 * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
1521 * CSELR C2S LL_DMA_GetPeriphRequest\n
1522 * CSELR C3S LL_DMA_GetPeriphRequest\n
1523 * CSELR C4S LL_DMA_GetPeriphRequest\n
1524 * CSELR C5S LL_DMA_GetPeriphRequest\n
1525 * CSELR C6S LL_DMA_GetPeriphRequest\n
1526 * CSELR C7S LL_DMA_GetPeriphRequest
1527 * @param DMAx DMAx Instance
1528 * @param Channel This parameter can be one of the following values:
1529 * @arg @ref LL_DMA_CHANNEL_1
1530 * @arg @ref LL_DMA_CHANNEL_2
1531 * @arg @ref LL_DMA_CHANNEL_3
1532 * @arg @ref LL_DMA_CHANNEL_4
1533 * @arg @ref LL_DMA_CHANNEL_5
1534 * @arg @ref LL_DMA_CHANNEL_6
1535 * @arg @ref LL_DMA_CHANNEL_7
1536 * @retval Returned value can be one of the following values:
1537 * @arg @ref LL_DMA_REQUEST_0
1538 * @arg @ref LL_DMA_REQUEST_1
1539 * @arg @ref LL_DMA_REQUEST_2
1540 * @arg @ref LL_DMA_REQUEST_3
1541 * @arg @ref LL_DMA_REQUEST_4
1542 * @arg @ref LL_DMA_REQUEST_5
1543 * @arg @ref LL_DMA_REQUEST_6
1544 * @arg @ref LL_DMA_REQUEST_7
1545 */
LL_DMA_GetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel)1546 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
1547 {
1548 return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
1549 DMA_CSELR_C1S << ((Channel) * 4U)) >> DMA_POSITION_CSELR_CXS);
1550 }
1551
1552 #endif /* DMAMUX1 */
1553 /**
1554 * @}
1555 */
1556
1557 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1558 * @{
1559 */
1560
1561 /**
1562 * @brief Get Channel 1 global interrupt flag.
1563 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1564 * @param DMAx DMAx Instance
1565 * @retval State of bit (1 or 0).
1566 */
LL_DMA_IsActiveFlag_GI1(DMA_TypeDef * DMAx)1567 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1568 {
1569 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
1570 }
1571
1572 /**
1573 * @brief Get Channel 2 global interrupt flag.
1574 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1575 * @param DMAx DMAx Instance
1576 * @retval State of bit (1 or 0).
1577 */
LL_DMA_IsActiveFlag_GI2(DMA_TypeDef * DMAx)1578 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1579 {
1580 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
1581 }
1582
1583 /**
1584 * @brief Get Channel 3 global interrupt flag.
1585 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1586 * @param DMAx DMAx Instance
1587 * @retval State of bit (1 or 0).
1588 */
LL_DMA_IsActiveFlag_GI3(DMA_TypeDef * DMAx)1589 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1590 {
1591 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
1592 }
1593
1594 /**
1595 * @brief Get Channel 4 global interrupt flag.
1596 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
1597 * @param DMAx DMAx Instance
1598 * @retval State of bit (1 or 0).
1599 */
LL_DMA_IsActiveFlag_GI4(DMA_TypeDef * DMAx)1600 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
1601 {
1602 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
1603 }
1604
1605 /**
1606 * @brief Get Channel 5 global interrupt flag.
1607 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
1608 * @param DMAx DMAx Instance
1609 * @retval State of bit (1 or 0).
1610 */
LL_DMA_IsActiveFlag_GI5(DMA_TypeDef * DMAx)1611 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
1612 {
1613 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
1614 }
1615
1616 /**
1617 * @brief Get Channel 6 global interrupt flag.
1618 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
1619 * @param DMAx DMAx Instance
1620 * @retval State of bit (1 or 0).
1621 */
LL_DMA_IsActiveFlag_GI6(DMA_TypeDef * DMAx)1622 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
1623 {
1624 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
1625 }
1626
1627 /**
1628 * @brief Get Channel 7 global interrupt flag.
1629 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
1630 * @param DMAx DMAx Instance
1631 * @retval State of bit (1 or 0).
1632 */
LL_DMA_IsActiveFlag_GI7(DMA_TypeDef * DMAx)1633 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
1634 {
1635 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
1636 }
1637
1638 /**
1639 * @brief Get Channel 1 transfer complete flag.
1640 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
1641 * @param DMAx DMAx Instance
1642 * @retval State of bit (1 or 0).
1643 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)1644 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1645 {
1646 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
1647 }
1648
1649 /**
1650 * @brief Get Channel 2 transfer complete flag.
1651 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
1652 * @param DMAx DMAx Instance
1653 * @retval State of bit (1 or 0).
1654 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)1655 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1656 {
1657 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
1658 }
1659
1660 /**
1661 * @brief Get Channel 3 transfer complete flag.
1662 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
1663 * @param DMAx DMAx Instance
1664 * @retval State of bit (1 or 0).
1665 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)1666 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1667 {
1668 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
1669 }
1670
1671 /**
1672 * @brief Get Channel 4 transfer complete flag.
1673 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
1674 * @param DMAx DMAx Instance
1675 * @retval State of bit (1 or 0).
1676 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)1677 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1678 {
1679 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
1680 }
1681
1682 /**
1683 * @brief Get Channel 5 transfer complete flag.
1684 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
1685 * @param DMAx DMAx Instance
1686 * @retval State of bit (1 or 0).
1687 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)1688 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1689 {
1690 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
1691 }
1692
1693 /**
1694 * @brief Get Channel 6 transfer complete flag.
1695 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
1696 * @param DMAx DMAx Instance
1697 * @retval State of bit (1 or 0).
1698 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)1699 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1700 {
1701 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
1702 }
1703
1704 /**
1705 * @brief Get Channel 7 transfer complete flag.
1706 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
1707 * @param DMAx DMAx Instance
1708 * @retval State of bit (1 or 0).
1709 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)1710 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1711 {
1712 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
1713 }
1714
1715 /**
1716 * @brief Get Channel 1 half transfer flag.
1717 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
1718 * @param DMAx DMAx Instance
1719 * @retval State of bit (1 or 0).
1720 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1721 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1722 {
1723 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
1724 }
1725
1726 /**
1727 * @brief Get Channel 2 half transfer flag.
1728 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
1729 * @param DMAx DMAx Instance
1730 * @retval State of bit (1 or 0).
1731 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1732 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1733 {
1734 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
1735 }
1736
1737 /**
1738 * @brief Get Channel 3 half transfer flag.
1739 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
1740 * @param DMAx DMAx Instance
1741 * @retval State of bit (1 or 0).
1742 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1743 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1744 {
1745 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
1746 }
1747
1748 /**
1749 * @brief Get Channel 4 half transfer flag.
1750 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
1751 * @param DMAx DMAx Instance
1752 * @retval State of bit (1 or 0).
1753 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)1754 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1755 {
1756 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
1757 }
1758
1759 /**
1760 * @brief Get Channel 5 half transfer flag.
1761 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
1762 * @param DMAx DMAx Instance
1763 * @retval State of bit (1 or 0).
1764 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)1765 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1766 {
1767 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
1768 }
1769
1770 /**
1771 * @brief Get Channel 6 half transfer flag.
1772 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
1773 * @param DMAx DMAx Instance
1774 * @retval State of bit (1 or 0).
1775 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)1776 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1777 {
1778 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
1779 }
1780
1781 /**
1782 * @brief Get Channel 7 half transfer flag.
1783 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
1784 * @param DMAx DMAx Instance
1785 * @retval State of bit (1 or 0).
1786 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)1787 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1788 {
1789 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
1790 }
1791
1792 /**
1793 * @brief Get Channel 1 transfer error flag.
1794 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
1795 * @param DMAx DMAx Instance
1796 * @retval State of bit (1 or 0).
1797 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)1798 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1799 {
1800 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
1801 }
1802
1803 /**
1804 * @brief Get Channel 2 transfer error flag.
1805 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
1806 * @param DMAx DMAx Instance
1807 * @retval State of bit (1 or 0).
1808 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)1809 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1810 {
1811 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
1812 }
1813
1814 /**
1815 * @brief Get Channel 3 transfer error flag.
1816 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
1817 * @param DMAx DMAx Instance
1818 * @retval State of bit (1 or 0).
1819 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)1820 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1821 {
1822 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
1823 }
1824
1825 /**
1826 * @brief Get Channel 4 transfer error flag.
1827 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
1828 * @param DMAx DMAx Instance
1829 * @retval State of bit (1 or 0).
1830 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)1831 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1832 {
1833 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
1834 }
1835
1836 /**
1837 * @brief Get Channel 5 transfer error flag.
1838 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
1839 * @param DMAx DMAx Instance
1840 * @retval State of bit (1 or 0).
1841 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)1842 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1843 {
1844 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
1845 }
1846
1847 /**
1848 * @brief Get Channel 6 transfer error flag.
1849 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
1850 * @param DMAx DMAx Instance
1851 * @retval State of bit (1 or 0).
1852 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)1853 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1854 {
1855 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
1856 }
1857
1858 /**
1859 * @brief Get Channel 7 transfer error flag.
1860 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
1861 * @param DMAx DMAx Instance
1862 * @retval State of bit (1 or 0).
1863 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)1864 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1865 {
1866 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
1867 }
1868
1869 /**
1870 * @brief Clear Channel 1 global interrupt flag.
1871 * @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
1872 Instead clear specific flags transfer complete, half transfer & transfer
1873 error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
1874 LL_DMA_ClearFlag_TE1. bug 2.4.1/2.5.1 in Product Errata Sheet.
1875 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
1876 * @param DMAx DMAx Instance
1877 * @retval None
1878 */
LL_DMA_ClearFlag_GI1(DMA_TypeDef * DMAx)1879 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1880 {
1881 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
1882 }
1883
1884 /**
1885 * @brief Clear Channel 2 global interrupt flag.
1886 * @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
1887 Instead clear specific flags transfer complete, half transfer & transfer
1888 error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
1889 LL_DMA_ClearFlag_TE2. bug id 2.4.1/2.5.1 in Product Errata Sheet.
1890 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
1891 * @param DMAx DMAx Instance
1892 * @retval None
1893 */
LL_DMA_ClearFlag_GI2(DMA_TypeDef * DMAx)1894 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1895 {
1896 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
1897 }
1898
1899 /**
1900 * @brief Clear Channel 3 global interrupt flag.
1901 * @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
1902 Instead clear specific flags transfer complete, half transfer & transfer
1903 error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
1904 LL_DMA_ClearFlag_TE3. bug id 2.4.1/2.5.1 in Product Errata Sheet.
1905 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
1906 * @param DMAx DMAx Instance
1907 * @retval None
1908 */
LL_DMA_ClearFlag_GI3(DMA_TypeDef * DMAx)1909 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1910 {
1911 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
1912 }
1913
1914 /**
1915 * @brief Clear Channel 4 global interrupt flag.
1916 * @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
1917 Instead clear specific flags transfer complete, half transfer & transfer
1918 error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
1919 LL_DMA_ClearFlag_TE4. bug id 2.4.1/2.5.1 in Product Errata Sheet.
1920 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
1921 * @param DMAx DMAx Instance
1922 * @retval None
1923 */
LL_DMA_ClearFlag_GI4(DMA_TypeDef * DMAx)1924 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
1925 {
1926 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
1927 }
1928
1929 /**
1930 * @brief Clear Channel 5 global interrupt flag.
1931 * @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
1932 Instead clear specific flags transfer complete, half transfer & transfer
1933 error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
1934 LL_DMA_ClearFlag_TE5. bug id 2.4.1/2.5.1 in Product Errata Sheet.
1935 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
1936 * @param DMAx DMAx Instance
1937 * @retval None
1938 */
LL_DMA_ClearFlag_GI5(DMA_TypeDef * DMAx)1939 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
1940 {
1941 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
1942 }
1943
1944 /**
1945 * @brief Clear Channel 6 global interrupt flag.
1946 * @note Do not Clear Channel 6 global interrupt flag when the channel in ON.
1947 Instead clear specific flags transfer complete, half transfer & transfer
1948 error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6,
1949 LL_DMA_ClearFlag_TE6. bug id 2.4.1/2.5.1 in Product Errata Sheet.
1950 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
1951 * @param DMAx DMAx Instance
1952 * @retval None
1953 */
LL_DMA_ClearFlag_GI6(DMA_TypeDef * DMAx)1954 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
1955 {
1956 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
1957 }
1958
1959 /**
1960 * @brief Clear Channel 7 global interrupt flag.
1961 * @note Do not Clear Channel 7 global interrupt flag when the channel in ON.
1962 Instead clear specific flags transfer complete, half transfer & transfer
1963 error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7,
1964 LL_DMA_ClearFlag_TE7. bug id 2.4.1/2.5.1 in Product Errata Sheet.
1965 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
1966 * @param DMAx DMAx Instance
1967 * @retval None
1968 */
LL_DMA_ClearFlag_GI7(DMA_TypeDef * DMAx)1969 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
1970 {
1971 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
1972 }
1973
1974 /**
1975 * @brief Clear Channel 1 transfer complete flag.
1976 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
1977 * @param DMAx DMAx Instance
1978 * @retval None
1979 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)1980 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
1981 {
1982 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
1983 }
1984
1985 /**
1986 * @brief Clear Channel 2 transfer complete flag.
1987 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
1988 * @param DMAx DMAx Instance
1989 * @retval None
1990 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)1991 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
1992 {
1993 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
1994 }
1995
1996 /**
1997 * @brief Clear Channel 3 transfer complete flag.
1998 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
1999 * @param DMAx DMAx Instance
2000 * @retval None
2001 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)2002 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
2003 {
2004 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
2005 }
2006
2007 /**
2008 * @brief Clear Channel 4 transfer complete flag.
2009 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
2010 * @param DMAx DMAx Instance
2011 * @retval None
2012 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)2013 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
2014 {
2015 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
2016 }
2017
2018 /**
2019 * @brief Clear Channel 5 transfer complete flag.
2020 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
2021 * @param DMAx DMAx Instance
2022 * @retval None
2023 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)2024 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
2025 {
2026 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
2027 }
2028
2029 /**
2030 * @brief Clear Channel 6 transfer complete flag.
2031 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
2032 * @param DMAx DMAx Instance
2033 * @retval None
2034 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)2035 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
2036 {
2037 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
2038 }
2039
2040 /**
2041 * @brief Clear Channel 7 transfer complete flag.
2042 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
2043 * @param DMAx DMAx Instance
2044 * @retval None
2045 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)2046 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
2047 {
2048 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
2049 }
2050
2051 /**
2052 * @brief Clear Channel 1 half transfer flag.
2053 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
2054 * @param DMAx DMAx Instance
2055 * @retval None
2056 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)2057 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
2058 {
2059 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
2060 }
2061
2062 /**
2063 * @brief Clear Channel 2 half transfer flag.
2064 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
2065 * @param DMAx DMAx Instance
2066 * @retval None
2067 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)2068 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
2069 {
2070 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
2071 }
2072
2073 /**
2074 * @brief Clear Channel 3 half transfer flag.
2075 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
2076 * @param DMAx DMAx Instance
2077 * @retval None
2078 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)2079 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
2080 {
2081 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
2082 }
2083
2084 /**
2085 * @brief Clear Channel 4 half transfer flag.
2086 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
2087 * @param DMAx DMAx Instance
2088 * @retval None
2089 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)2090 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
2091 {
2092 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
2093 }
2094
2095 /**
2096 * @brief Clear Channel 5 half transfer flag.
2097 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
2098 * @param DMAx DMAx Instance
2099 * @retval None
2100 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)2101 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
2102 {
2103 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
2104 }
2105
2106 /**
2107 * @brief Clear Channel 6 half transfer flag.
2108 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
2109 * @param DMAx DMAx Instance
2110 * @retval None
2111 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)2112 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
2113 {
2114 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
2115 }
2116
2117 /**
2118 * @brief Clear Channel 7 half transfer flag.
2119 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
2120 * @param DMAx DMAx Instance
2121 * @retval None
2122 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)2123 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
2124 {
2125 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
2126 }
2127
2128 /**
2129 * @brief Clear Channel 1 transfer error flag.
2130 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
2131 * @param DMAx DMAx Instance
2132 * @retval None
2133 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)2134 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
2135 {
2136 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
2137 }
2138
2139 /**
2140 * @brief Clear Channel 2 transfer error flag.
2141 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
2142 * @param DMAx DMAx Instance
2143 * @retval None
2144 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)2145 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
2146 {
2147 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
2148 }
2149
2150 /**
2151 * @brief Clear Channel 3 transfer error flag.
2152 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
2153 * @param DMAx DMAx Instance
2154 * @retval None
2155 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)2156 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
2157 {
2158 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
2159 }
2160
2161 /**
2162 * @brief Clear Channel 4 transfer error flag.
2163 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
2164 * @param DMAx DMAx Instance
2165 * @retval None
2166 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)2167 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
2168 {
2169 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
2170 }
2171
2172 /**
2173 * @brief Clear Channel 5 transfer error flag.
2174 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
2175 * @param DMAx DMAx Instance
2176 * @retval None
2177 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)2178 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
2179 {
2180 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
2181 }
2182
2183 /**
2184 * @brief Clear Channel 6 transfer error flag.
2185 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
2186 * @param DMAx DMAx Instance
2187 * @retval None
2188 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)2189 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
2190 {
2191 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
2192 }
2193
2194 /**
2195 * @brief Clear Channel 7 transfer error flag.
2196 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
2197 * @param DMAx DMAx Instance
2198 * @retval None
2199 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)2200 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
2201 {
2202 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
2203 }
2204
2205 /**
2206 * @}
2207 */
2208
2209 /** @defgroup DMA_LL_EF_IT_Management IT_Management
2210 * @{
2211 */
2212 /**
2213 * @brief Enable Transfer complete interrupt.
2214 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
2215 * @param DMAx DMAx Instance
2216 * @param Channel This parameter can be one of the following values:
2217 * @arg @ref LL_DMA_CHANNEL_1
2218 * @arg @ref LL_DMA_CHANNEL_2
2219 * @arg @ref LL_DMA_CHANNEL_3
2220 * @arg @ref LL_DMA_CHANNEL_4
2221 * @arg @ref LL_DMA_CHANNEL_5
2222 * @arg @ref LL_DMA_CHANNEL_6
2223 * @arg @ref LL_DMA_CHANNEL_7
2224 * @retval None
2225 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2226 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2227 {
2228 uint32_t dma_base_addr = (uint32_t)DMAx;
2229 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
2230 }
2231
2232 /**
2233 * @brief Enable Half transfer interrupt.
2234 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
2235 * @param DMAx DMAx Instance
2236 * @param Channel This parameter can be one of the following values:
2237 * @arg @ref LL_DMA_CHANNEL_1
2238 * @arg @ref LL_DMA_CHANNEL_2
2239 * @arg @ref LL_DMA_CHANNEL_3
2240 * @arg @ref LL_DMA_CHANNEL_4
2241 * @arg @ref LL_DMA_CHANNEL_5
2242 * @arg @ref LL_DMA_CHANNEL_6
2243 * @arg @ref LL_DMA_CHANNEL_7
2244 * @retval None
2245 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2246 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2247 {
2248 uint32_t dma_base_addr = (uint32_t)DMAx;
2249 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
2250 }
2251
2252 /**
2253 * @brief Enable Transfer error interrupt.
2254 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
2255 * @param DMAx DMAx Instance
2256 * @param Channel This parameter can be one of the following values:
2257 * @arg @ref LL_DMA_CHANNEL_1
2258 * @arg @ref LL_DMA_CHANNEL_2
2259 * @arg @ref LL_DMA_CHANNEL_3
2260 * @arg @ref LL_DMA_CHANNEL_4
2261 * @arg @ref LL_DMA_CHANNEL_5
2262 * @arg @ref LL_DMA_CHANNEL_6
2263 * @arg @ref LL_DMA_CHANNEL_7
2264 * @retval None
2265 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2266 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2267 {
2268 uint32_t dma_base_addr = (uint32_t)DMAx;
2269 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE);
2270 }
2271
2272 /**
2273 * @brief Disable Transfer complete interrupt.
2274 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
2275 * @param DMAx DMAx Instance
2276 * @param Channel This parameter can be one of the following values:
2277 * @arg @ref LL_DMA_CHANNEL_1
2278 * @arg @ref LL_DMA_CHANNEL_2
2279 * @arg @ref LL_DMA_CHANNEL_3
2280 * @arg @ref LL_DMA_CHANNEL_4
2281 * @arg @ref LL_DMA_CHANNEL_5
2282 * @arg @ref LL_DMA_CHANNEL_6
2283 * @arg @ref LL_DMA_CHANNEL_7
2284 * @retval None
2285 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2286 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2287 {
2288 uint32_t dma_base_addr = (uint32_t)DMAx;
2289 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
2290 }
2291
2292 /**
2293 * @brief Disable Half transfer interrupt.
2294 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
2295 * @param DMAx DMAx Instance
2296 * @param Channel This parameter can be one of the following values:
2297 * @arg @ref LL_DMA_CHANNEL_1
2298 * @arg @ref LL_DMA_CHANNEL_2
2299 * @arg @ref LL_DMA_CHANNEL_3
2300 * @arg @ref LL_DMA_CHANNEL_4
2301 * @arg @ref LL_DMA_CHANNEL_5
2302 * @arg @ref LL_DMA_CHANNEL_6
2303 * @arg @ref LL_DMA_CHANNEL_7
2304 * @retval None
2305 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2306 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2307 {
2308 uint32_t dma_base_addr = (uint32_t)DMAx;
2309 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
2310 }
2311
2312 /**
2313 * @brief Disable Transfer error interrupt.
2314 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
2315 * @param DMAx DMAx Instance
2316 * @param Channel This parameter can be one of the following values:
2317 * @arg @ref LL_DMA_CHANNEL_1
2318 * @arg @ref LL_DMA_CHANNEL_2
2319 * @arg @ref LL_DMA_CHANNEL_3
2320 * @arg @ref LL_DMA_CHANNEL_4
2321 * @arg @ref LL_DMA_CHANNEL_5
2322 * @arg @ref LL_DMA_CHANNEL_6
2323 * @arg @ref LL_DMA_CHANNEL_7
2324 * @retval None
2325 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2326 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2327 {
2328 uint32_t dma_base_addr = (uint32_t)DMAx;
2329 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE);
2330 }
2331
2332 /**
2333 * @brief Check if Transfer complete Interrupt is enabled.
2334 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
2335 * @param DMAx DMAx Instance
2336 * @param Channel This parameter can be one of the following values:
2337 * @arg @ref LL_DMA_CHANNEL_1
2338 * @arg @ref LL_DMA_CHANNEL_2
2339 * @arg @ref LL_DMA_CHANNEL_3
2340 * @arg @ref LL_DMA_CHANNEL_4
2341 * @arg @ref LL_DMA_CHANNEL_5
2342 * @arg @ref LL_DMA_CHANNEL_6
2343 * @arg @ref LL_DMA_CHANNEL_7
2344 * @retval State of bit (1 or 0).
2345 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2346 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2347 {
2348 uint32_t dma_base_addr = (uint32_t)DMAx;
2349 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
2350 DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
2351 }
2352
2353 /**
2354 * @brief Check if Half transfer Interrupt is enabled.
2355 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
2356 * @param DMAx DMAx Instance
2357 * @param Channel This parameter can be one of the following values:
2358 * @arg @ref LL_DMA_CHANNEL_1
2359 * @arg @ref LL_DMA_CHANNEL_2
2360 * @arg @ref LL_DMA_CHANNEL_3
2361 * @arg @ref LL_DMA_CHANNEL_4
2362 * @arg @ref LL_DMA_CHANNEL_5
2363 * @arg @ref LL_DMA_CHANNEL_6
2364 * @arg @ref LL_DMA_CHANNEL_7
2365 * @retval State of bit (1 or 0).
2366 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2367 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2368 {
2369 uint32_t dma_base_addr = (uint32_t)DMAx;
2370 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
2371 DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
2372 }
2373
2374 /**
2375 * @brief Check if Transfer error Interrupt is enabled.
2376 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
2377 * @param DMAx DMAx Instance
2378 * @param Channel This parameter can be one of the following values:
2379 * @arg @ref LL_DMA_CHANNEL_1
2380 * @arg @ref LL_DMA_CHANNEL_2
2381 * @arg @ref LL_DMA_CHANNEL_3
2382 * @arg @ref LL_DMA_CHANNEL_4
2383 * @arg @ref LL_DMA_CHANNEL_5
2384 * @arg @ref LL_DMA_CHANNEL_6
2385 * @arg @ref LL_DMA_CHANNEL_7
2386 * @retval State of bit (1 or 0).
2387 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2388 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2389 {
2390 uint32_t dma_base_addr = (uint32_t)DMAx;
2391 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
2392 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
2393 }
2394
2395 /**
2396 * @}
2397 */
2398
2399 #if defined(USE_FULL_LL_DRIVER)
2400 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2401 * @{
2402 */
2403 ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
2404 ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
2405 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2406
2407 /**
2408 * @}
2409 */
2410 #endif /* USE_FULL_LL_DRIVER */
2411
2412 /**
2413 * @}
2414 */
2415
2416 /**
2417 * @}
2418 */
2419
2420 #endif /* DMA1 || DMA2 */
2421
2422 /**
2423 * @}
2424 */
2425
2426 #ifdef __cplusplus
2427 }
2428 #endif
2429
2430 #endif /* STM32L4xx_LL_DMA_H */
2431
