1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L4xx_LL_DAC_H
21 #define STM32L4xx_LL_DAC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l4xx.h"
29
30 /** @addtogroup STM32L4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DAC1)
35
36 /** @defgroup DAC_LL DAC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
45 * @{
46 */
47
48 /* Internal masks for DAC channels definition */
49 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
50 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
51 /* - channel bits position into register SWTRIG */
52 /* - channel register offset of data holding register DHRx */
53 /* - channel register offset of data output register DORx */
54 /* - channel register offset of sample-and-hold sample time register SHSRx */
55 #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
56 #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
57 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
58
59 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
60 #if defined(DAC_CHANNEL2_SUPPORT)
61 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
62 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
63 #else
64 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
65 #endif /* DAC_CHANNEL2_SUPPORT */
66
67 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
68 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
69 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
70 #if defined(DAC_CHANNEL2_SUPPORT)
71 #define DAC_REG_DHR12R2_REGOFFSET 0x30000000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
72 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
73 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
74 #endif /* DAC_CHANNEL2_SUPPORT */
75 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000U
76 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
77 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
78 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
79
80 #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
81 #if defined(DAC_CHANNEL2_SUPPORT)
82 #define DAC_REG_DOR2_REGOFFSET 0x00000020U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */
83 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
84 #else
85 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
86 #endif /* DAC_CHANNEL2_SUPPORT */
87
88 #define DAC_REG_SHSR1_REGOFFSET 0x00000000U /* Register SHSRx channel 1 taken as reference */
89 #if defined(DAC_CHANNEL2_SUPPORT)
90 #define DAC_REG_SHSR2_REGOFFSET 0x00000040U /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */
91 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
92 #else
93 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET)
94 #endif /* DAC_CHANNEL2_SUPPORT */
95
96 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
97 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of DORx registers offset when shifted to position 0 */
98 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of SHSRx registers offset when shifted to position 0 */
99
100 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
101 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
102 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
103 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */
104 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6U /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */
105
106 /* DAC registers bits positions */
107 #if defined(DAC_CHANNEL2_SUPPORT)
108 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
109 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
110 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
111 #endif /* DAC_CHANNEL2_SUPPORT */
112
113 /* Miscellaneous data */
114 #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
115
116 /**
117 * @}
118 */
119
120
121 /* Private macros ------------------------------------------------------------*/
122 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
123 * @{
124 */
125
126 /**
127 * @brief Driver macro reserved for internal use: set a pointer to
128 * a register from a register basis from which an offset
129 * is applied.
130 * @param __REG__ Register basis from which the offset is applied.
131 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
132 * @retval Pointer to register address
133 */
134 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
135 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
136
137 /**
138 * @}
139 */
140
141
142 /* Exported types ------------------------------------------------------------*/
143 #if defined(USE_FULL_LL_DRIVER)
144 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
145 * @{
146 */
147
148 /**
149 * @brief Structure definition of some features of DAC instance.
150 */
151 typedef struct
152 {
153 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line).
154 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
155
156 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
157
158 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
159 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
160
161 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
162
163 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
164 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
165 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
166 @note If waveform automatic generation mode is disabled, this parameter is discarded.
167
168 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR(), @ref LL_DAC_SetWaveTriangleAmplitude()
169 depending on the wave automatic generation selected. */
170
171 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
172 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
173
174 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
175
176 uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
177 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
178
179 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */
180
181 uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC channel.
182 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
183
184 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */
185 } LL_DAC_InitTypeDef;
186
187 /**
188 * @}
189 */
190 #endif /* USE_FULL_LL_DRIVER */
191
192 /* Exported constants --------------------------------------------------------*/
193 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
194 * @{
195 */
196
197 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
198 * @brief Flags defines which can be used with LL_DAC_ReadReg function
199 * @{
200 */
201 /* DAC channel 1 flags */
202 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
203 #define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
204 #define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */
205
206 #if defined(DAC_CHANNEL2_SUPPORT)
207 /* DAC channel 2 flags */
208 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
209 #define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
210 #define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */
211 #endif /* DAC_CHANNEL2_SUPPORT */
212 /**
213 * @}
214 */
215
216 /** @defgroup DAC_LL_EC_IT DAC interruptions
217 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
218 * @{
219 */
220 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
221 #if defined(DAC_CHANNEL2_SUPPORT)
222 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
223 #endif /* DAC_CHANNEL2_SUPPORT */
224 /**
225 * @}
226 */
227
228 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
229 * @{
230 */
231 #define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
232 #if defined(DAC_CHANNEL2_SUPPORT)
233 #define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
234 #endif /* DAC_CHANNEL2_SUPPORT */
235 /**
236 * @}
237 */
238 #if defined (DAC_CR_HFSEL) /* High frequency interface mode */
239
240 /** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode
241 * @brief High frequency interface mode defines that can be used with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode
242 * @{
243 */
244 #define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000U /*!< High frequency interface mode disabled */
245 #define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_CR_HFSEL) /*!< High frequency interface mode compatible to AHB>80MHz enabled */
246 /**
247 * @}
248 */
249 #endif /* High frequency interface mode */
250
251 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
252 * @{
253 */
254 #define LL_DAC_MODE_NORMAL_OPERATION 0x00000000U /*!< DAC channel in mode normal operation */
255 #define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */
256 /**
257 * @}
258 */
259
260 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
261 * @{
262 */
263 #if defined (DAC_CR_TSEL1_3)
264 #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM1 TRGO. */
265 #define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
266 #define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
267 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
268 #define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
269 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
270 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
271 #define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */
272 #define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: LPTIM1 TRGO. */
273 #define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: LPTIM2 TRGO. */
274 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
275 #define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC channel conversion trigger internal (SW start) */
276 #else
277 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
278 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
279 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
280 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
281 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
282 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
283 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
284 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
285 #endif
286
287 /**
288 * @}
289 */
290
291 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
292 * @{
293 */
294 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
295 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
296 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
297 /**
298 * @}
299 */
300
301 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
302 * @{
303 */
304 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
305 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
306 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
307 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
308 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
309 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
310 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
311 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
312 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
313 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
314 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
315 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
316 /**
317 * @}
318 */
319
320 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
321 * @{
322 */
323 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
324 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
325 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
326 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
327 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
328 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
329 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
330 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
331 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
332 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
333 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
334 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
335 /**
336 * @}
337 */
338
339 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
340 * @{
341 */
342 #define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000U /*!< The selected DAC channel output is on mode normal. */
343 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
344 /**
345 * @}
346 */
347
348 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
349 * @{
350 */
351 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
352 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
353 /**
354 * @}
355 */
356
357 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
358 * @{
359 */
360 #define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000U /*!< The selected DAC channel output is connected to external pin */
361 #define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
362 /**
363 * @}
364 */
365
366 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
367 * @{
368 */
369 #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
370 #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
371 /**
372 * @}
373 */
374
375 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
376 * @{
377 */
378 /* List of DAC registers intended to be used (most commonly) with */
379 /* DMA transfer. */
380 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
381 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
382 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
383 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
384 /**
385 * @}
386 */
387
388 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
389 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
390 * not timeout values.
391 * For details on delays values, refer to descriptions in source code
392 * above each literal definition.
393 * @{
394 */
395
396 /* Delay for DAC channel voltage settling time from DAC channel startup */
397 /* (transition from disable to enable). */
398 /* Note: DAC channel startup time depends on board application environment: */
399 /* impedance connected to DAC channel output. */
400 /* The delay below is specified under conditions: */
401 /* - voltage maximum transition (lowest to highest value) */
402 /* - until voltage reaches final value +-1LSB */
403 /* - DAC channel output buffer enabled */
404 /* - load impedance of 5kOhm (min), 50pF (max) */
405 /* Literal set to maximum value (refer to device datasheet, */
406 /* parameter "tWAKEUP"). */
407 /* Unit: us */
408 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
409
410
411 /* Delay for DAC channel voltage settling time. */
412 /* Note: DAC channel startup time depends on board application environment: */
413 /* impedance connected to DAC channel output. */
414 /* The delay below is specified under conditions: */
415 /* - voltage maximum transition (lowest to highest value) */
416 /* - until voltage reaches final value +-1LSB */
417 /* - DAC channel output buffer enabled */
418 /* - load impedance of 5kOhm min, 50pF max */
419 /* Literal set to maximum value (refer to device datasheet, */
420 /* parameter "tSETTLING"). */
421 /* Unit: us */
422 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3U /*!< Delay for DAC channel voltage settling time */
423
424 /**
425 * @}
426 */
427
428 /**
429 * @}
430 */
431
432 /* Exported macro ------------------------------------------------------------*/
433 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
434 * @{
435 */
436
437 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
438 * @{
439 */
440
441 /**
442 * @brief Write a value in DAC register
443 * @param __INSTANCE__ DAC Instance
444 * @param __REG__ Register to be written
445 * @param __VALUE__ Value to be written in the register
446 * @retval None
447 */
448 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
449
450 /**
451 * @brief Read a value in DAC register
452 * @param __INSTANCE__ DAC Instance
453 * @param __REG__ Register to be read
454 * @retval Register value
455 */
456 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
457
458 /**
459 * @}
460 */
461
462 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
463 * @{
464 */
465
466 /**
467 * @brief Helper macro to get DAC channel number in decimal format
468 * from literals LL_DAC_CHANNEL_x.
469 * Example:
470 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
471 * will return decimal number "1".
472 * @note The input can be a value from functions where a channel
473 * number is returned.
474 * @param __CHANNEL__ This parameter can be one of the following values:
475 * @arg @ref LL_DAC_CHANNEL_1
476 * @arg @ref LL_DAC_CHANNEL_2
477 * @retval 1...2
478 */
479 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
480 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
481
482 /**
483 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
484 * from number in decimal format.
485 * Example:
486 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
487 * will return a data equivalent to "LL_DAC_CHANNEL_1".
488 * @note If the input parameter does not correspond to a DAC channel,
489 * this macro returns value '0'.
490 * @param __DECIMAL_NB__ 1...2
491 * @retval Returned value can be one of the following values:
492 * @arg @ref LL_DAC_CHANNEL_1
493 * @arg @ref LL_DAC_CHANNEL_2
494 */
495 #if defined(DAC_CHANNEL2_SUPPORT)
496 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
497 (((__DECIMAL_NB__) == 1U) \
498 ? ( \
499 LL_DAC_CHANNEL_1 \
500 ) \
501 : \
502 (((__DECIMAL_NB__) == 2U) \
503 ? ( \
504 LL_DAC_CHANNEL_2 \
505 ) \
506 : \
507 ( \
508 0U \
509 ) \
510 ) \
511 )
512 #else
513 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
514 (((__DECIMAL_NB__) == 1U) \
515 ? ( \
516 LL_DAC_CHANNEL_1 \
517 ) \
518 : \
519 ( \
520 0U \
521 ) \
522 )
523 #endif /* DAC_CHANNEL2_SUPPORT */
524
525 /**
526 * @brief Helper macro to define the DAC conversion data full-scale digital
527 * value corresponding to the selected DAC resolution.
528 * @note DAC conversion data full-scale corresponds to voltage range
529 * determined by analog voltage references Vref+ and Vref-
530 * (refer to reference manual).
531 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
532 * @arg @ref LL_DAC_RESOLUTION_12B
533 * @arg @ref LL_DAC_RESOLUTION_8B
534 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
535 */
536 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
537 ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
538
539 /**
540 * @brief Helper macro to calculate the DAC conversion data (unit: digital
541 * value) corresponding to a voltage (unit: mVolt).
542 * @note This helper macro is intended to provide input data in voltage
543 * rather than digital value,
544 * to be used with LL DAC functions such as
545 * @ref LL_DAC_ConvertData12RightAligned().
546 * @note Analog reference voltage (Vref+) must be either known from
547 * user board environment or can be calculated using ADC measurement
548 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
549 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
550 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
551 * (unit: mVolt).
552 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
553 * @arg @ref LL_DAC_RESOLUTION_12B
554 * @arg @ref LL_DAC_RESOLUTION_8B
555 * @retval DAC conversion data (unit: digital value)
556 */
557 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
558 __DAC_VOLTAGE__,\
559 __DAC_RESOLUTION__) \
560 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
561 / (__VREFANALOG_VOLTAGE__) \
562 )
563
564 /**
565 * @}
566 */
567
568 /**
569 * @}
570 */
571
572
573 /* Exported functions --------------------------------------------------------*/
574 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
575 * @{
576 */
577
578 #if defined (DAC_CR_HFSEL) /* High frequency interface mode */
579
580 /** @defgroup DAC_LL_EF_High_Frequency_Configuration High Frequency Configuration of DAC instance
581 * @{
582 */
583 /**
584 * @brief Set the high frequency interface mode for the selected DAC instance
585 * @rmtoll CR HFSEL LL_DAC_SetHighFrequencyMode
586 * @param DACx DAC instance
587 * @param HighFreqMode This parameter can be one of the following values:
588 * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
589 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
590 * @retval None
591 */
LL_DAC_SetHighFrequencyMode(DAC_TypeDef * DACx,uint32_t HighFreqMode)592 __STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *DACx, uint32_t HighFreqMode)
593 {
594 MODIFY_REG(DACx->CR, DAC_CR_HFSEL, HighFreqMode);
595 }
596
597 /**
598 * @brief Get the high frequency interface mode for the selected DAC instance
599 * @rmtoll CR HFSEL LL_DAC_GetHighFrequencyMode
600 * @param DACx DAC instance
601 * @retval Returned value can be one of the following values:
602 * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
603 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
604 */
LL_DAC_GetHighFrequencyMode(DAC_TypeDef * DACx)605 __STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(DAC_TypeDef *DACx)
606 {
607 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_HFSEL));
608 }
609 /**
610 * @}
611 */
612
613 #endif /* High frequency interface mode */
614
615 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
616 * @{
617 */
618
619 /**
620 * @brief Set the operating mode for the selected DAC channel:
621 * calibration or normal operating mode.
622 * @rmtoll CR CEN1 LL_DAC_SetMode\n
623 * CR CEN2 LL_DAC_SetMode
624 * @param DACx DAC instance
625 * @param DAC_Channel This parameter can be one of the following values:
626 * @arg @ref LL_DAC_CHANNEL_1
627 * @arg @ref LL_DAC_CHANNEL_2
628 * @param ChannelMode This parameter can be one of the following values:
629 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
630 * @arg @ref LL_DAC_MODE_CALIBRATION
631 * @retval None
632 */
LL_DAC_SetMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t ChannelMode)633 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
634 {
635 MODIFY_REG(DACx->CR,
636 DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
637 ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
638 }
639
640 /**
641 * @brief Get the operating mode for the selected DAC channel:
642 * calibration or normal operating mode.
643 * @rmtoll CR CEN1 LL_DAC_GetMode\n
644 * CR CEN2 LL_DAC_GetMode
645 * @param DACx DAC instance
646 * @param DAC_Channel This parameter can be one of the following values:
647 * @arg @ref LL_DAC_CHANNEL_1
648 * @arg @ref LL_DAC_CHANNEL_2
649 * @retval Returned value can be one of the following values:
650 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
651 * @arg @ref LL_DAC_MODE_CALIBRATION
652 */
LL_DAC_GetMode(DAC_TypeDef * DACx,uint32_t DAC_Channel)653 __STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
654 {
655 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
656 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
657 );
658 }
659
660 /**
661 * @brief Set the offset trimming value for the selected DAC channel.
662 * Trimming has an impact when output buffer is enabled
663 * and is intended to replace factory calibration default values.
664 * @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n
665 * CCR OTRIM2 LL_DAC_SetTrimmingValue
666 * @param DACx DAC instance
667 * @param DAC_Channel This parameter can be one of the following values:
668 * @arg @ref LL_DAC_CHANNEL_1
669 * @arg @ref LL_DAC_CHANNEL_2
670 * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
671 * @retval None
672 */
LL_DAC_SetTrimmingValue(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TrimmingValue)673 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
674 {
675 MODIFY_REG(DACx->CCR,
676 DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
677 TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
678 }
679
680 /**
681 * @brief Get the offset trimming value for the selected DAC channel.
682 * Trimming has an impact when output buffer is enabled
683 * and is intended to replace factory calibration default values.
684 * @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n
685 * CCR OTRIM2 LL_DAC_GetTrimmingValue
686 * @param DACx DAC instance
687 * @param DAC_Channel This parameter can be one of the following values:
688 * @arg @ref LL_DAC_CHANNEL_1
689 * @arg @ref LL_DAC_CHANNEL_2
690 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
691 */
LL_DAC_GetTrimmingValue(DAC_TypeDef * DACx,uint32_t DAC_Channel)692 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
693 {
694 return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
695 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
696 );
697 }
698
699 /**
700 * @brief Set the conversion trigger source for the selected DAC channel.
701 * @note For conversion trigger source to be effective, DAC trigger
702 * must be enabled using function @ref LL_DAC_EnableTrigger().
703 * @note To set conversion trigger source, DAC channel must be disabled.
704 * Otherwise, the setting is discarded.
705 * @note Availability of parameters of trigger sources from timer
706 * depends on timers availability on the selected device.
707 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
708 * CR TSEL2 LL_DAC_SetTriggerSource
709 * @param DACx DAC instance
710 * @param DAC_Channel This parameter can be one of the following values:
711 * @arg @ref LL_DAC_CHANNEL_1
712 * @arg @ref LL_DAC_CHANNEL_2
713 * @param TriggerSource This parameter can be one of the following values:
714 * @arg @ref LL_DAC_TRIG_SOFTWARE
715 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
716 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
717 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
718 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
719 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
720 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
721 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
722 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
723 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
724 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
725 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
726 * @retval None
727 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)728 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
729 {
730 MODIFY_REG(DACx->CR,
731 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
732 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
733 }
734
735 /**
736 * @brief Get the conversion trigger source for the selected DAC channel.
737 * @note For conversion trigger source to be effective, DAC trigger
738 * must be enabled using function @ref LL_DAC_EnableTrigger().
739 * @note Availability of parameters of trigger sources from timer
740 * depends on timers availability on the selected device.
741 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
742 * CR TSEL2 LL_DAC_GetTriggerSource
743 * @param DACx DAC instance
744 * @param DAC_Channel This parameter can be one of the following values:
745 * @arg @ref LL_DAC_CHANNEL_1
746 * @arg @ref LL_DAC_CHANNEL_2 (1)
747 *
748 * (1) On this STM32 serie, parameter not available on all devices.
749 * Refer to device datasheet for channels availability.
750 * @retval Returned value can be one of the following values:
751 * @arg @ref LL_DAC_TRIG_SOFTWARE
752 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
753 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
754 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
755 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
756 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
757 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
758 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
759 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
760 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
761 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
762 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
763 */
LL_DAC_GetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel)764 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
765 {
766 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
767 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
768 );
769 }
770
771 /**
772 * @brief Set the waveform automatic generation mode
773 * for the selected DAC channel.
774 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
775 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
776 * @param DACx DAC instance
777 * @param DAC_Channel This parameter can be one of the following values:
778 * @arg @ref LL_DAC_CHANNEL_1
779 * @arg @ref LL_DAC_CHANNEL_2 (1)
780 *
781 * (1) On this STM32 serie, parameter not available on all devices.
782 * Refer to device datasheet for channels availability.
783 * @param WaveAutoGeneration This parameter can be one of the following values:
784 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
785 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
786 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
787 * @retval None
788 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)789 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
790 {
791 MODIFY_REG(DACx->CR,
792 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
793 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
794 }
795
796 /**
797 * @brief Get the waveform automatic generation mode
798 * for the selected DAC channel.
799 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
800 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
801 * @param DACx DAC instance
802 * @param DAC_Channel This parameter can be one of the following values:
803 * @arg @ref LL_DAC_CHANNEL_1
804 * @arg @ref LL_DAC_CHANNEL_2 (1)
805 *
806 * (1) On this STM32 serie, parameter not available on all devices.
807 * Refer to device datasheet for channels availability.
808 * @retval Returned value can be one of the following values:
809 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
810 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
811 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
812 */
LL_DAC_GetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel)813 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
814 {
815 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
816 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
817 );
818 }
819
820 /**
821 * @brief Set the noise waveform generation for the selected DAC channel:
822 * Noise mode and parameters LFSR (linear feedback shift register).
823 * @note For wave generation to be effective, DAC channel
824 * wave generation mode must be enabled using
825 * function @ref LL_DAC_SetWaveAutoGeneration().
826 * @note This setting can be set when the selected DAC channel is disabled
827 * (otherwise, the setting operation is ignored).
828 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
829 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
830 * @param DACx DAC instance
831 * @param DAC_Channel This parameter can be one of the following values:
832 * @arg @ref LL_DAC_CHANNEL_1
833 * @arg @ref LL_DAC_CHANNEL_2 (1)
834 *
835 * (1) On this STM32 serie, parameter not available on all devices.
836 * Refer to device datasheet for channels availability.
837 * @param NoiseLFSRMask This parameter can be one of the following values:
838 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
839 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
840 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
841 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
842 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
843 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
844 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
845 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
846 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
847 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
848 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
849 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
850 * @retval None
851 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)852 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
853 {
854 MODIFY_REG(DACx->CR,
855 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
856 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
857 }
858
859 /**
860 * @brief Get the noise waveform generation for the selected DAC channel:
861 * Noise mode and parameters LFSR (linear feedback shift register).
862 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
863 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
864 * @param DACx DAC instance
865 * @param DAC_Channel This parameter can be one of the following values:
866 * @arg @ref LL_DAC_CHANNEL_1
867 * @arg @ref LL_DAC_CHANNEL_2 (1)
868 *
869 * (1) On this STM32 serie, parameter not available on all devices.
870 * Refer to device datasheet for channels availability.
871 * @retval Returned value can be one of the following values:
872 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
873 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
874 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
875 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
876 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
877 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
878 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
879 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
880 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
881 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
882 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
883 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
884 */
LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel)885 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
886 {
887 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
888 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
889 );
890 }
891
892 /**
893 * @brief Set the triangle waveform generation for the selected DAC channel:
894 * triangle mode and amplitude.
895 * @note For wave generation to be effective, DAC channel
896 * wave generation mode must be enabled using
897 * function @ref LL_DAC_SetWaveAutoGeneration().
898 * @note This setting can be set when the selected DAC channel is disabled
899 * (otherwise, the setting operation is ignored).
900 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
901 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
902 * @param DACx DAC instance
903 * @param DAC_Channel This parameter can be one of the following values:
904 * @arg @ref LL_DAC_CHANNEL_1
905 * @arg @ref LL_DAC_CHANNEL_2 (1)
906 *
907 * (1) On this STM32 serie, parameter not available on all devices.
908 * Refer to device datasheet for channels availability.
909 * @param TriangleAmplitude This parameter can be one of the following values:
910 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
911 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
912 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
913 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
914 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
915 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
916 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
917 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
918 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
919 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
920 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
921 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
922 * @retval None
923 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)924 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
925 uint32_t TriangleAmplitude)
926 {
927 MODIFY_REG(DACx->CR,
928 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
929 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
930 }
931
932 /**
933 * @brief Get the triangle waveform generation for the selected DAC channel:
934 * triangle mode and amplitude.
935 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
936 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
937 * @param DACx DAC instance
938 * @param DAC_Channel This parameter can be one of the following values:
939 * @arg @ref LL_DAC_CHANNEL_1
940 * @arg @ref LL_DAC_CHANNEL_2 (1)
941 *
942 * (1) On this STM32 serie, parameter not available on all devices.
943 * Refer to device datasheet for channels availability.
944 * @retval Returned value can be one of the following values:
945 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
946 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
947 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
948 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
949 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
950 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
951 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
952 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
953 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
954 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
955 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
956 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
957 */
LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel)958 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
959 {
960 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
961 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
962 );
963 }
964
965 /**
966 * @brief Set the output for the selected DAC channel.
967 * @note This function set several features:
968 * - mode normal or sample-and-hold
969 * - buffer
970 * - connection to GPIO or internal path.
971 * These features can also be set individually using
972 * dedicated functions:
973 * - @ref LL_DAC_SetOutputBuffer()
974 * - @ref LL_DAC_SetOutputMode()
975 * - @ref LL_DAC_SetOutputConnection()
976 * @note On this STM32 serie, output connection depends on output mode
977 * (normal or sample and hold) and output buffer state.
978 * - if output connection is set to internal path and output buffer
979 * is enabled (whatever output mode):
980 * output connection is also connected to GPIO pin
981 * (both connections to GPIO pin and internal path).
982 * - if output connection is set to GPIO pin, output buffer
983 * is disabled, output mode set to sample and hold:
984 * output connection is also connected to internal path
985 * (both connections to GPIO pin and internal path).
986 * @note Mode sample-and-hold requires an external capacitor
987 * to be connected between DAC channel output and ground.
988 * Capacitor value depends on load on DAC channel output and
989 * sample-and-hold timings configured.
990 * As indication, capacitor typical value is 100nF
991 * (refer to device datasheet, parameter "CSH").
992 * @rmtoll CR MODE1 LL_DAC_ConfigOutput\n
993 * CR MODE2 LL_DAC_ConfigOutput
994 * @param DACx DAC instance
995 * @param DAC_Channel This parameter can be one of the following values:
996 * @arg @ref LL_DAC_CHANNEL_1
997 * @arg @ref LL_DAC_CHANNEL_2 (1)
998 *
999 * (1) On this STM32 serie, parameter not available on all devices.
1000 * Refer to device datasheet for channels availability.
1001 * @param OutputMode This parameter can be one of the following values:
1002 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1003 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1004 * @param OutputBuffer This parameter can be one of the following values:
1005 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1006 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1007 * @param OutputConnection This parameter can be one of the following values:
1008 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1009 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1010 * @retval None
1011 */
LL_DAC_ConfigOutput(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode,uint32_t OutputBuffer,uint32_t OutputConnection)1012 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
1013 uint32_t OutputBuffer, uint32_t OutputConnection)
1014 {
1015 MODIFY_REG(DACx->MCR,
1016 (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1017 (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1018 }
1019
1020 /**
1021 * @brief Set the output mode normal or sample-and-hold
1022 * for the selected DAC channel.
1023 * @note Mode sample-and-hold requires an external capacitor
1024 * to be connected between DAC channel output and ground.
1025 * Capacitor value depends on load on DAC channel output and
1026 * sample-and-hold timings configured.
1027 * As indication, capacitor typical value is 100nF
1028 * (refer to device datasheet, parameter "CSH").
1029 * @rmtoll CR MODE1 LL_DAC_SetOutputMode\n
1030 * CR MODE2 LL_DAC_SetOutputMode
1031 * @param DACx DAC instance
1032 * @param DAC_Channel This parameter can be one of the following values:
1033 * @arg @ref LL_DAC_CHANNEL_1
1034 * @arg @ref LL_DAC_CHANNEL_2 (1)
1035 *
1036 * (1) On this STM32 serie, parameter not available on all devices.
1037 * Refer to device datasheet for channels availability.
1038 * @param OutputMode This parameter can be one of the following values:
1039 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1040 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1041 * @retval None
1042 */
LL_DAC_SetOutputMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode)1043 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
1044 {
1045 MODIFY_REG(DACx->MCR,
1046 (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1047 OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1048 }
1049
1050 /**
1051 * @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
1052 * @rmtoll CR MODE1 LL_DAC_GetOutputMode\n
1053 * CR MODE2 LL_DAC_GetOutputMode
1054 * @param DACx DAC instance
1055 * @param DAC_Channel This parameter can be one of the following values:
1056 * @arg @ref LL_DAC_CHANNEL_1
1057 * @arg @ref LL_DAC_CHANNEL_2 (1)
1058 *
1059 * (1) On this STM32 serie, parameter not available on all devices.
1060 * Refer to device datasheet for channels availability.
1061 * @retval Returned value can be one of the following values:
1062 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1063 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1064 */
LL_DAC_GetOutputMode(DAC_TypeDef * DACx,uint32_t DAC_Channel)1065 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1066 {
1067 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1068 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1069 );
1070 }
1071
1072 /**
1073 * @brief Set the output buffer for the selected DAC channel.
1074 * @note On this STM32 serie, when buffer is enabled, its offset can be
1075 * trimmed: factory calibration default values can be
1076 * replaced by user trimming values, using function
1077 * @ref LL_DAC_SetTrimmingValue().
1078 * @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n
1079 * CR MODE2 LL_DAC_SetOutputBuffer
1080 * @param DACx DAC instance
1081 * @param DAC_Channel This parameter can be one of the following values:
1082 * @arg @ref LL_DAC_CHANNEL_1
1083 * @arg @ref LL_DAC_CHANNEL_2 (1)
1084 *
1085 * (1) On this STM32 serie, parameter not available on all devices.
1086 * Refer to device datasheet for channels availability.
1087 * @param OutputBuffer This parameter can be one of the following values:
1088 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1089 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1090 * @retval None
1091 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)1092 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
1093 {
1094 MODIFY_REG(DACx->MCR,
1095 (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1096 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1097 }
1098
1099 /**
1100 * @brief Get the output buffer state for the selected DAC channel.
1101 * @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n
1102 * CR MODE2 LL_DAC_GetOutputBuffer
1103 * @param DACx DAC instance
1104 * @param DAC_Channel This parameter can be one of the following values:
1105 * @arg @ref LL_DAC_CHANNEL_1
1106 * @arg @ref LL_DAC_CHANNEL_2 (1)
1107 *
1108 * (1) On this STM32 serie, parameter not available on all devices.
1109 * Refer to device datasheet for channels availability.
1110 * @retval Returned value can be one of the following values:
1111 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1112 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1113 */
LL_DAC_GetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel)1114 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1115 {
1116 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1117 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1118 );
1119 }
1120
1121 /**
1122 * @brief Set the output connection for the selected DAC channel.
1123 * @note On this STM32 serie, output connection depends on output mode (normal or
1124 * sample and hold) and output buffer state.
1125 * - if output connection is set to internal path and output buffer
1126 * is enabled (whatever output mode):
1127 * output connection is also connected to GPIO pin
1128 * (both connections to GPIO pin and internal path).
1129 * - if output connection is set to GPIO pin, output buffer
1130 * is disabled, output mode set to sample and hold:
1131 * output connection is also connected to internal path
1132 * (both connections to GPIO pin and internal path).
1133 * @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n
1134 * CR MODE2 LL_DAC_SetOutputConnection
1135 * @param DACx DAC instance
1136 * @param DAC_Channel This parameter can be one of the following values:
1137 * @arg @ref LL_DAC_CHANNEL_1
1138 * @arg @ref LL_DAC_CHANNEL_2 (1)
1139 *
1140 * (1) On this STM32 serie, parameter not available on all devices.
1141 * Refer to device datasheet for channels availability.
1142 * @param OutputConnection This parameter can be one of the following values:
1143 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1144 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1145 * @retval None
1146 */
LL_DAC_SetOutputConnection(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputConnection)1147 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
1148 {
1149 MODIFY_REG(DACx->MCR,
1150 (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1151 OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1152 }
1153
1154 /**
1155 * @brief Get the output connection for the selected DAC channel.
1156 * @note On this STM32 serie, output connection depends on output mode (normal or
1157 * sample and hold) and output buffer state.
1158 * - if output connection is set to internal path and output buffer
1159 * is enabled (whatever output mode):
1160 * output connection is also connected to GPIO pin
1161 * (both connections to GPIO pin and internal path).
1162 * - if output connection is set to GPIO pin, output buffer
1163 * is disabled, output mode set to sample and hold:
1164 * output connection is also connected to internal path
1165 * (both connections to GPIO pin and internal path).
1166 * @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n
1167 * CR MODE2 LL_DAC_GetOutputConnection
1168 * @param DACx DAC instance
1169 * @param DAC_Channel This parameter can be one of the following values:
1170 * @arg @ref LL_DAC_CHANNEL_1
1171 * @arg @ref LL_DAC_CHANNEL_2 (1)
1172 *
1173 * (1) On this STM32 serie, parameter not available on all devices.
1174 * Refer to device datasheet for channels availability.
1175 * @retval Returned value can be one of the following values:
1176 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1177 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1178 */
LL_DAC_GetOutputConnection(DAC_TypeDef * DACx,uint32_t DAC_Channel)1179 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1180 {
1181 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1182 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1183 );
1184 }
1185
1186 /**
1187 * @brief Set the sample-and-hold timing for the selected DAC channel:
1188 * sample time
1189 * @note Sample time must be set when DAC channel is disabled
1190 * or during DAC operation when DAC channel flag BWSTx is reset,
1191 * otherwise the setting is ignored.
1192 * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
1193 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n
1194 * SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
1195 * @param DACx DAC instance
1196 * @param DAC_Channel This parameter can be one of the following values:
1197 * @arg @ref LL_DAC_CHANNEL_1
1198 * @arg @ref LL_DAC_CHANNEL_2 (1)
1199 *
1200 * (1) On this STM32 serie, parameter not available on all devices.
1201 * Refer to device datasheet for channels availability.
1202 * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
1203 * @retval None
1204 */
LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t SampleTime)1205 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
1206 {
1207 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1208
1209 MODIFY_REG(*preg,
1210 DAC_SHSR1_TSAMPLE1,
1211 SampleTime);
1212 }
1213
1214 /**
1215 * @brief Get the sample-and-hold timing for the selected DAC channel:
1216 * sample time
1217 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n
1218 * SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
1219 * @param DACx DAC instance
1220 * @param DAC_Channel This parameter can be one of the following values:
1221 * @arg @ref LL_DAC_CHANNEL_1
1222 * @arg @ref LL_DAC_CHANNEL_2 (1)
1223 *
1224 * (1) On this STM32 serie, parameter not available on all devices.
1225 * Refer to device datasheet for channels availability.
1226 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1227 */
LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef * DACx,uint32_t DAC_Channel)1228 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1229 {
1230 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1231
1232 return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
1233 }
1234
1235 /**
1236 * @brief Set the sample-and-hold timing for the selected DAC channel:
1237 * hold time
1238 * @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n
1239 * SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
1240 * @param DACx DAC instance
1241 * @param DAC_Channel This parameter can be one of the following values:
1242 * @arg @ref LL_DAC_CHANNEL_1
1243 * @arg @ref LL_DAC_CHANNEL_2 (1)
1244 *
1245 * (1) On this STM32 serie, parameter not available on all devices.
1246 * Refer to device datasheet for channels availability.
1247 * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
1248 * @retval None
1249 */
LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t HoldTime)1250 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
1251 {
1252 MODIFY_REG(DACx->SHHR,
1253 DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1254 HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1255 }
1256
1257 /**
1258 * @brief Get the sample-and-hold timing for the selected DAC channel:
1259 * hold time
1260 * @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n
1261 * SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
1262 * @param DACx DAC instance
1263 * @param DAC_Channel This parameter can be one of the following values:
1264 * @arg @ref LL_DAC_CHANNEL_1
1265 * @arg @ref LL_DAC_CHANNEL_2 (1)
1266 *
1267 * (1) On this STM32 serie, parameter not available on all devices.
1268 * Refer to device datasheet for channels availability.
1269 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1270 */
LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef * DACx,uint32_t DAC_Channel)1271 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1272 {
1273 return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1274 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1275 );
1276 }
1277
1278 /**
1279 * @brief Set the sample-and-hold timing for the selected DAC channel:
1280 * refresh time
1281 * @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n
1282 * SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
1283 * @param DACx DAC instance
1284 * @param DAC_Channel This parameter can be one of the following values:
1285 * @arg @ref LL_DAC_CHANNEL_1
1286 * @arg @ref LL_DAC_CHANNEL_2 (1)
1287 *
1288 * (1) On this STM32 serie, parameter not available on all devices.
1289 * Refer to device datasheet for channels availability.
1290 * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
1291 * @retval None
1292 */
LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t RefreshTime)1293 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
1294 {
1295 MODIFY_REG(DACx->SHRR,
1296 DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1297 RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1298 }
1299
1300 /**
1301 * @brief Get the sample-and-hold timing for the selected DAC channel:
1302 * refresh time
1303 * @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n
1304 * SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
1305 * @param DACx DAC instance
1306 * @param DAC_Channel This parameter can be one of the following values:
1307 * @arg @ref LL_DAC_CHANNEL_1
1308 * @arg @ref LL_DAC_CHANNEL_2 (1)
1309 *
1310 * (1) On this STM32 serie, parameter not available on all devices.
1311 * Refer to device datasheet for channels availability.
1312 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1313 */
LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef * DACx,uint32_t DAC_Channel)1314 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1315 {
1316 return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1317 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1318 );
1319 }
1320
1321 /**
1322 * @}
1323 */
1324
1325 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
1326 * @{
1327 */
1328
1329 /**
1330 * @brief Enable DAC DMA transfer request of the selected channel.
1331 * @note To configure DMA source address (peripheral address),
1332 * use function @ref LL_DAC_DMA_GetRegAddr().
1333 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
1334 * CR DMAEN2 LL_DAC_EnableDMAReq
1335 * @param DACx DAC instance
1336 * @param DAC_Channel This parameter can be one of the following values:
1337 * @arg @ref LL_DAC_CHANNEL_1
1338 * @arg @ref LL_DAC_CHANNEL_2 (1)
1339 *
1340 * (1) On this STM32 serie, parameter not available on all devices.
1341 * Refer to device datasheet for channels availability.
1342 * @retval None
1343 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1344 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1345 {
1346 SET_BIT(DACx->CR,
1347 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1348 }
1349
1350 /**
1351 * @brief Disable DAC DMA transfer request of the selected channel.
1352 * @note To configure DMA source address (peripheral address),
1353 * use function @ref LL_DAC_DMA_GetRegAddr().
1354 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
1355 * CR DMAEN2 LL_DAC_DisableDMAReq
1356 * @param DACx DAC instance
1357 * @param DAC_Channel This parameter can be one of the following values:
1358 * @arg @ref LL_DAC_CHANNEL_1
1359 * @arg @ref LL_DAC_CHANNEL_2 (1)
1360 *
1361 * (1) On this STM32 serie, parameter not available on all devices.
1362 * Refer to device datasheet for channels availability.
1363 * @retval None
1364 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1365 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1366 {
1367 CLEAR_BIT(DACx->CR,
1368 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1369 }
1370
1371 /**
1372 * @brief Get DAC DMA transfer request state of the selected channel.
1373 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
1374 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
1375 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
1376 * @param DACx DAC instance
1377 * @param DAC_Channel This parameter can be one of the following values:
1378 * @arg @ref LL_DAC_CHANNEL_1
1379 * @arg @ref LL_DAC_CHANNEL_2 (1)
1380 *
1381 * (1) On this STM32 serie, parameter not available on all devices.
1382 * Refer to device datasheet for channels availability.
1383 * @retval State of bit (1 or 0).
1384 */
LL_DAC_IsDMAReqEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1385 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1386 {
1387 return ((READ_BIT(DACx->CR,
1388 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1389 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1390 }
1391
1392 /**
1393 * @brief Function to help to configure DMA transfer to DAC: retrieve the
1394 * DAC register address from DAC instance and a list of DAC registers
1395 * intended to be used (most commonly) with DMA transfer.
1396 * @note These DAC registers are data holding registers:
1397 * when DAC conversion is requested, DAC generates a DMA transfer
1398 * request to have data available in DAC data holding registers.
1399 * @note This macro is intended to be used with LL DMA driver, refer to
1400 * function "LL_DMA_ConfigAddresses()".
1401 * Example:
1402 * LL_DMA_ConfigAddresses(DMA1,
1403 * LL_DMA_CHANNEL_1,
1404 * (uint32_t)&< array or variable >,
1405 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
1406 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
1407 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1408 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1409 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1410 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1411 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1412 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
1413 * @param DACx DAC instance
1414 * @param DAC_Channel This parameter can be one of the following values:
1415 * @arg @ref LL_DAC_CHANNEL_1
1416 * @arg @ref LL_DAC_CHANNEL_2 (1)
1417 *
1418 * (1) On this STM32 serie, parameter not available on all devices.
1419 * Refer to device datasheet for channels availability.
1420 * @param Register This parameter can be one of the following values:
1421 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
1422 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
1423 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
1424 * @retval DAC register address
1425 */
LL_DAC_DMA_GetRegAddr(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)1426 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
1427 {
1428 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
1429 /* DAC channel selected. */
1430 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1,
1431 ((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
1432 }
1433 /**
1434 * @}
1435 */
1436
1437 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
1438 * @{
1439 */
1440
1441 /**
1442 * @brief Enable DAC selected channel.
1443 * @rmtoll CR EN1 LL_DAC_Enable\n
1444 * CR EN2 LL_DAC_Enable
1445 * @note After enable from off state, DAC channel requires a delay
1446 * for output voltage to reach accuracy +/- 1 LSB.
1447 * Refer to device datasheet, parameter "tWAKEUP".
1448 * @param DACx DAC instance
1449 * @param DAC_Channel This parameter can be one of the following values:
1450 * @arg @ref LL_DAC_CHANNEL_1
1451 * @arg @ref LL_DAC_CHANNEL_2 (1)
1452 *
1453 * (1) On this STM32 serie, parameter not available on all devices.
1454 * Refer to device datasheet for channels availability.
1455 * @retval None
1456 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1457 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1458 {
1459 SET_BIT(DACx->CR,
1460 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1461 }
1462
1463 /**
1464 * @brief Disable DAC selected channel.
1465 * @rmtoll CR EN1 LL_DAC_Disable\n
1466 * CR EN2 LL_DAC_Disable
1467 * @param DACx DAC instance
1468 * @param DAC_Channel This parameter can be one of the following values:
1469 * @arg @ref LL_DAC_CHANNEL_1
1470 * @arg @ref LL_DAC_CHANNEL_2 (1)
1471 *
1472 * (1) On this STM32 serie, parameter not available on all devices.
1473 * Refer to device datasheet for channels availability.
1474 * @retval None
1475 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1476 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1477 {
1478 CLEAR_BIT(DACx->CR,
1479 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1480 }
1481
1482 /**
1483 * @brief Get DAC enable state of the selected channel.
1484 * (0: DAC channel is disabled, 1: DAC channel is enabled)
1485 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
1486 * CR EN2 LL_DAC_IsEnabled
1487 * @param DACx DAC instance
1488 * @param DAC_Channel This parameter can be one of the following values:
1489 * @arg @ref LL_DAC_CHANNEL_1
1490 * @arg @ref LL_DAC_CHANNEL_2 (1)
1491 *
1492 * (1) On this STM32 serie, parameter not available on all devices.
1493 * Refer to device datasheet for channels availability.
1494 * @retval State of bit (1 or 0).
1495 */
LL_DAC_IsEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1496 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1497 {
1498 return ((READ_BIT(DACx->CR,
1499 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1500 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1501 }
1502
1503 /**
1504 * @brief Enable DAC trigger of the selected channel.
1505 * @note - If DAC trigger is disabled, DAC conversion is performed
1506 * automatically once the data holding register is updated,
1507 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1508 * @ref LL_DAC_ConvertData12RightAligned(), ...
1509 * - If DAC trigger is enabled, DAC conversion is performed
1510 * only when a hardware of software trigger event is occurring.
1511 * Select trigger source using
1512 * function @ref LL_DAC_SetTriggerSource().
1513 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1514 * CR TEN2 LL_DAC_EnableTrigger
1515 * @param DACx DAC instance
1516 * @param DAC_Channel This parameter can be one of the following values:
1517 * @arg @ref LL_DAC_CHANNEL_1
1518 * @arg @ref LL_DAC_CHANNEL_2 (1)
1519 *
1520 * (1) On this STM32 serie, parameter not available on all devices.
1521 * Refer to device datasheet for channels availability.
1522 * @retval None
1523 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1524 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1525 {
1526 SET_BIT(DACx->CR,
1527 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1528 }
1529
1530 /**
1531 * @brief Disable DAC trigger of the selected channel.
1532 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1533 * CR TEN2 LL_DAC_DisableTrigger
1534 * @param DACx DAC instance
1535 * @param DAC_Channel This parameter can be one of the following values:
1536 * @arg @ref LL_DAC_CHANNEL_1
1537 * @arg @ref LL_DAC_CHANNEL_2 (1)
1538 *
1539 * (1) On this STM32 serie, parameter not available on all devices.
1540 * Refer to device datasheet for channels availability.
1541 * @retval None
1542 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1543 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1544 {
1545 CLEAR_BIT(DACx->CR,
1546 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1547 }
1548
1549 /**
1550 * @brief Get DAC trigger state of the selected channel.
1551 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1552 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1553 * CR TEN2 LL_DAC_IsTriggerEnabled
1554 * @param DACx DAC instance
1555 * @param DAC_Channel This parameter can be one of the following values:
1556 * @arg @ref LL_DAC_CHANNEL_1
1557 * @arg @ref LL_DAC_CHANNEL_2 (1)
1558 *
1559 * (1) On this STM32 serie, parameter not available on all devices.
1560 * Refer to device datasheet for channels availability.
1561 * @retval State of bit (1 or 0).
1562 */
LL_DAC_IsTriggerEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1563 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1564 {
1565 return ((READ_BIT(DACx->CR,
1566 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1567 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1568 }
1569
1570 /**
1571 * @brief Trig DAC conversion by software for the selected DAC channel.
1572 * @note Preliminarily, DAC trigger must be set to software trigger
1573 * using function
1574 * @ref LL_DAC_Init()
1575 * @ref LL_DAC_SetTriggerSource()
1576 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1577 * and DAC trigger must be enabled using
1578 * function @ref LL_DAC_EnableTrigger().
1579 * @note For devices featuring DAC with 2 channels: this function
1580 * can perform a SW start of both DAC channels simultaneously.
1581 * Two channels can be selected as parameter.
1582 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1583 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1584 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1585 * @param DACx DAC instance
1586 * @param DAC_Channel This parameter can a combination of the following values:
1587 * @arg @ref LL_DAC_CHANNEL_1
1588 * @arg @ref LL_DAC_CHANNEL_2 (1)
1589 *
1590 * (1) On this STM32 serie, parameter not available on all devices.
1591 * Refer to device datasheet for channels availability.
1592 * @retval None
1593 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1594 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1595 {
1596 SET_BIT(DACx->SWTRIGR,
1597 (DAC_Channel & DAC_SWTR_CHX_MASK));
1598 }
1599
1600 /**
1601 * @brief Set the data to be loaded in the data holding register
1602 * in format 12 bits left alignment (LSB aligned on bit 0),
1603 * for the selected DAC channel.
1604 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1605 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1606 * @param DACx DAC instance
1607 * @param DAC_Channel This parameter can be one of the following values:
1608 * @arg @ref LL_DAC_CHANNEL_1
1609 * @arg @ref LL_DAC_CHANNEL_2 (1)
1610 *
1611 * (1) On this STM32 serie, parameter not available on all devices.
1612 * Refer to device datasheet for channels availability.
1613 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1614 * @retval None
1615 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1616 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1617 {
1618 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1619
1620 MODIFY_REG(*preg,
1621 DAC_DHR12R1_DACC1DHR,
1622 Data);
1623 }
1624
1625 /**
1626 * @brief Set the data to be loaded in the data holding register
1627 * in format 12 bits left alignment (MSB aligned on bit 15),
1628 * for the selected DAC channel.
1629 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1630 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1631 * @param DACx DAC instance
1632 * @param DAC_Channel This parameter can be one of the following values:
1633 * @arg @ref LL_DAC_CHANNEL_1
1634 * @arg @ref LL_DAC_CHANNEL_2 (1)
1635 *
1636 * (1) On this STM32 serie, parameter not available on all devices.
1637 * Refer to device datasheet for channels availability.
1638 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1639 * @retval None
1640 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1641 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1642 {
1643 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1644
1645 MODIFY_REG(*preg,
1646 DAC_DHR12L1_DACC1DHR,
1647 Data);
1648 }
1649
1650 /**
1651 * @brief Set the data to be loaded in the data holding register
1652 * in format 8 bits left alignment (LSB aligned on bit 0),
1653 * for the selected DAC channel.
1654 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1655 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1656 * @param DACx DAC instance
1657 * @param DAC_Channel This parameter can be one of the following values:
1658 * @arg @ref LL_DAC_CHANNEL_1
1659 * @arg @ref LL_DAC_CHANNEL_2 (1)
1660 *
1661 * (1) On this STM32 serie, parameter not available on all devices.
1662 * Refer to device datasheet for channels availability.
1663 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1664 * @retval None
1665 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1666 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1667 {
1668 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1669
1670 MODIFY_REG(*preg,
1671 DAC_DHR8R1_DACC1DHR,
1672 Data);
1673 }
1674
1675 #if defined(DAC_CHANNEL2_SUPPORT)
1676 /**
1677 * @brief Set the data to be loaded in the data holding register
1678 * in format 12 bits left alignment (LSB aligned on bit 0),
1679 * for both DAC channels.
1680 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1681 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1682 * @param DACx DAC instance
1683 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1684 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1685 * @retval None
1686 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1687 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1688 uint32_t DataChannel2)
1689 {
1690 MODIFY_REG(DACx->DHR12RD,
1691 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1692 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1693 }
1694
1695 /**
1696 * @brief Set the data to be loaded in the data holding register
1697 * in format 12 bits left alignment (MSB aligned on bit 15),
1698 * for both DAC channels.
1699 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1700 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1701 * @param DACx DAC instance
1702 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1703 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1704 * @retval None
1705 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1706 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1707 {
1708 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1709 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1710 /* the 4 LSB must be taken into account for the shift value. */
1711 MODIFY_REG(DACx->DHR12LD,
1712 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1713 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1714 }
1715
1716 /**
1717 * @brief Set the data to be loaded in the data holding register
1718 * in format 8 bits left alignment (LSB aligned on bit 0),
1719 * for both DAC channels.
1720 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1721 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1722 * @param DACx DAC instance
1723 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1724 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1725 * @retval None
1726 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1727 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1728 {
1729 MODIFY_REG(DACx->DHR8RD,
1730 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1731 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1732 }
1733
1734 #endif /* DAC_CHANNEL2_SUPPORT */
1735 /**
1736 * @brief Retrieve output data currently generated for the selected DAC channel.
1737 * @note Whatever alignment and resolution settings
1738 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1739 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1740 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1741 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1742 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1743 * @param DACx DAC instance
1744 * @param DAC_Channel This parameter can be one of the following values:
1745 * @arg @ref LL_DAC_CHANNEL_1
1746 * @arg @ref LL_DAC_CHANNEL_2 (1)
1747 *
1748 * (1) On this STM32 serie, parameter not available on all devices.
1749 * Refer to device datasheet for channels availability.
1750 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1751 */
LL_DAC_RetrieveOutputData(DAC_TypeDef * DACx,uint32_t DAC_Channel)1752 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1753 {
1754 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1755
1756 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1757 }
1758
1759 /**
1760 * @}
1761 */
1762
1763 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1764 * @{
1765 */
1766 /**
1767 * @brief Get DAC calibration offset flag for DAC channel 1
1768 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
1769 * @param DACx DAC instance
1770 * @retval State of bit (1 or 0).
1771 */
LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef * DACx)1772 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
1773 {
1774 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
1775 }
1776
1777 #if defined(DAC_CHANNEL2_SUPPORT)
1778 /**
1779 * @brief Get DAC calibration offset flag for DAC channel 2
1780 * @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
1781 * @param DACx DAC instance
1782 * @retval State of bit (1 or 0).
1783 */
LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef * DACx)1784 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
1785 {
1786 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
1787 }
1788
1789 #endif /* DAC_CHANNEL2_SUPPORT */
1790 /**
1791 * @brief Get DAC busy writing sample time flag for DAC channel 1
1792 * @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
1793 * @param DACx DAC instance
1794 * @retval State of bit (1 or 0).
1795 */
LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef * DACx)1796 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
1797 {
1798 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
1799 }
1800
1801 #if defined(DAC_CHANNEL2_SUPPORT)
1802 /**
1803 * @brief Get DAC busy writing sample time flag for DAC channel 2
1804 * @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
1805 * @param DACx DAC instance
1806 * @retval State of bit (1 or 0).
1807 */
LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef * DACx)1808 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
1809 {
1810 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
1811 }
1812
1813 #endif /* DAC_CHANNEL2_SUPPORT */
1814 /**
1815 * @brief Get DAC underrun flag for DAC channel 1
1816 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1817 * @param DACx DAC instance
1818 * @retval State of bit (1 or 0).
1819 */
LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef * DACx)1820 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1821 {
1822 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1823 }
1824
1825 #if defined(DAC_CHANNEL2_SUPPORT)
1826 /**
1827 * @brief Get DAC underrun flag for DAC channel 2
1828 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1829 * @param DACx DAC instance
1830 * @retval State of bit (1 or 0).
1831 */
LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef * DACx)1832 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1833 {
1834 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
1835 }
1836 #endif /* DAC_CHANNEL2_SUPPORT */
1837
1838 /**
1839 * @brief Clear DAC underrun flag for DAC channel 1
1840 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1841 * @param DACx DAC instance
1842 * @retval None
1843 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1844 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1845 {
1846 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1847 }
1848
1849 #if defined(DAC_CHANNEL2_SUPPORT)
1850 /**
1851 * @brief Clear DAC underrun flag for DAC channel 2
1852 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1853 * @param DACx DAC instance
1854 * @retval None
1855 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)1856 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1857 {
1858 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1859 }
1860 #endif /* DAC_CHANNEL2_SUPPORT */
1861
1862 /**
1863 * @}
1864 */
1865
1866 /** @defgroup DAC_LL_EF_IT_Management IT management
1867 * @{
1868 */
1869
1870 /**
1871 * @brief Enable DMA underrun interrupt for DAC channel 1
1872 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1873 * @param DACx DAC instance
1874 * @retval None
1875 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1876 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1877 {
1878 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1879 }
1880
1881 #if defined(DAC_CHANNEL2_SUPPORT)
1882 /**
1883 * @brief Enable DMA underrun interrupt for DAC channel 2
1884 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1885 * @param DACx DAC instance
1886 * @retval None
1887 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)1888 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1889 {
1890 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1891 }
1892 #endif /* DAC_CHANNEL2_SUPPORT */
1893
1894 /**
1895 * @brief Disable DMA underrun interrupt for DAC channel 1
1896 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1897 * @param DACx DAC instance
1898 * @retval None
1899 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1900 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1901 {
1902 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1903 }
1904
1905 #if defined(DAC_CHANNEL2_SUPPORT)
1906 /**
1907 * @brief Disable DMA underrun interrupt for DAC channel 2
1908 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1909 * @param DACx DAC instance
1910 * @retval None
1911 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)1912 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1913 {
1914 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1915 }
1916 #endif /* DAC_CHANNEL2_SUPPORT */
1917
1918 /**
1919 * @brief Get DMA underrun interrupt for DAC channel 1
1920 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1921 * @param DACx DAC instance
1922 * @retval State of bit (1 or 0).
1923 */
LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef * DACx)1924 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1925 {
1926 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1927 }
1928
1929 #if defined(DAC_CHANNEL2_SUPPORT)
1930 /**
1931 * @brief Get DMA underrun interrupt for DAC channel 2
1932 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1933 * @param DACx DAC instance
1934 * @retval State of bit (1 or 0).
1935 */
LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef * DACx)1936 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1937 {
1938 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
1939 }
1940 #endif /* DAC_CHANNEL2_SUPPORT */
1941
1942 /**
1943 * @}
1944 */
1945
1946 #if defined(USE_FULL_LL_DRIVER)
1947 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1948 * @{
1949 */
1950
1951 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
1952 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
1953 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
1954
1955 /**
1956 * @}
1957 */
1958 #endif /* USE_FULL_LL_DRIVER */
1959
1960 /**
1961 * @}
1962 */
1963
1964 /**
1965 * @}
1966 */
1967
1968 #endif /* DAC1 */
1969
1970 /**
1971 * @}
1972 */
1973
1974 #ifdef __cplusplus
1975 }
1976 #endif
1977
1978 #endif /* STM32L4xx_LL_DAC_H */
1979
1980
