1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_pwr_ex.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L4xx_HAL_PWR_EX_H 21 #define STM32L4xx_HAL_PWR_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l4xx_hal_def.h" 29 30 /** @addtogroup STM32L4xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup PWREx 35 * @{ 36 */ 37 38 39 /* Exported types ------------------------------------------------------------*/ 40 41 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types 42 * @{ 43 */ 44 45 46 /** 47 * @brief PWR PVM configuration structure definition 48 */ 49 typedef struct 50 { 51 uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. 52 This parameter can be a value of @ref PWREx_PVM_Type. 53 @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). 54 @if STM32L486xx 55 @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device). 56 @endif 57 @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. 58 @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */ 59 60 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. 61 This parameter can be a value of @ref PWREx_PVM_Mode. */ 62 }PWR_PVMTypeDef; 63 64 /** 65 * @} 66 */ 67 68 /* Exported constants --------------------------------------------------------*/ 69 70 /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants 71 * @{ 72 */ 73 74 /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants 75 * @{ 76 */ 77 #define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polariry */ 78 /** 79 * @} 80 */ 81 82 83 /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins 84 * @{ 85 */ 86 #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 87 #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 88 #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 89 #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ 90 #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ 91 #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 92 #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 93 #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 94 #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ 95 #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ 96 #define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */ 97 #define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */ 98 #define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */ 99 #define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */ 100 #define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */ 101 /** 102 * @} 103 */ 104 105 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type 106 * @{ 107 */ 108 #if defined(PWR_CR2_PVME1) 109 #define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */ 110 #endif /* PWR_CR2_PVME1 */ 111 #if defined(PWR_CR2_PVME2) 112 #define PWR_PVM_2 PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */ 113 #endif /* PWR_CR2_PVME2 */ 114 #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */ 115 #define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V */ 116 /** 117 * @} 118 */ 119 120 /** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode 121 * @{ 122 */ 123 #define PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ 124 #define PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ 125 #define PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ 126 #define PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 127 #define PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ 128 #define PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ 129 #define PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ 130 /** 131 * @} 132 */ 133 134 135 136 /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale 137 * @{ 138 */ 139 #if defined(PWR_CR5_R1MODE) 140 #define PWR_REGULATOR_VOLTAGE_SCALE1_BOOST ((uint32_t)0x00000000) /*!< Voltage scaling range 1 boost mode */ 141 #endif 142 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 normal mode */ 143 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */ 144 /** 145 * @} 146 */ 147 148 149 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection 150 * @{ 151 */ 152 #define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor */ 153 #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ 154 /** 155 * @} 156 */ 157 158 /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging 159 * @{ 160 */ 161 #define PWR_BATTERY_CHARGING_DISABLE ((uint32_t)0x00000000) 162 #define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE 163 /** 164 * @} 165 */ 166 167 /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode 168 * @{ 169 */ 170 #define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /*!< GPIO port I/O pin 0 */ 171 #define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /*!< GPIO port I/O pin 1 */ 172 #define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /*!< GPIO port I/O pin 2 */ 173 #define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /*!< GPIO port I/O pin 3 */ 174 #define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /*!< GPIO port I/O pin 4 */ 175 #define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /*!< GPIO port I/O pin 5 */ 176 #define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /*!< GPIO port I/O pin 6 */ 177 #define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /*!< GPIO port I/O pin 7 */ 178 #define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /*!< GPIO port I/O pin 8 */ 179 #define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /*!< GPIO port I/O pin 9 */ 180 #define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /*!< GPIO port I/O pin 10 */ 181 #define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /*!< GPIO port I/O pin 11 */ 182 #define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /*!< GPIO port I/O pin 12 */ 183 #define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /*!< GPIO port I/O pin 13 */ 184 #define PWR_GPIO_BIT_14 PWR_PDCRA_PA14 /*!< GPIO port I/O pin 14 */ 185 #define PWR_GPIO_BIT_15 PWR_PUCRA_PA15 /*!< GPIO port I/O pin 15 */ 186 /** 187 * @} 188 */ 189 190 /** @defgroup PWREx_GPIO GPIO port 191 * @{ 192 */ 193 #define PWR_GPIO_A 0x00000000U /*!< GPIO port A */ 194 #define PWR_GPIO_B 0x00000001U /*!< GPIO port B */ 195 #define PWR_GPIO_C 0x00000002U /*!< GPIO port C */ 196 #if defined(GPIOD_BASE) 197 #define PWR_GPIO_D 0x00000003U /*!< GPIO port D */ 198 #endif 199 #if defined(GPIOE_BASE) 200 #define PWR_GPIO_E 0x00000004U /*!< GPIO port E */ 201 #endif 202 #if defined(GPIOF_BASE) 203 #define PWR_GPIO_F 0x00000005U /*!< GPIO port F */ 204 #endif 205 #if defined(GPIOG_BASE) 206 #define PWR_GPIO_G 0x00000006U /*!< GPIO port G */ 207 #endif 208 #define PWR_GPIO_H 0x00000007U /*!< GPIO port H */ 209 #if defined(GPIOI_BASE) 210 #define PWR_GPIO_I 0x00000008U /*!< GPIO port I */ 211 #endif 212 /** 213 * @} 214 */ 215 216 /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines 217 * @{ 218 */ 219 #if defined(PWR_CR2_PVME1) 220 #define PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008) /*!< External interrupt line 35 Connected to the PVM1 EXTI Line */ 221 #endif /* PWR_CR2_PVME1 */ 222 #if defined(PWR_CR2_PVME2) 223 #define PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010) /*!< External interrupt line 36 Connected to the PVM2 EXTI Line */ 224 #endif /* PWR_CR2_PVME2 */ 225 #define PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020) /*!< External interrupt line 37 Connected to the PVM3 EXTI Line */ 226 #define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040) /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */ 227 /** 228 * @} 229 */ 230 231 /** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines 232 * @{ 233 */ 234 #if defined(PWR_CR2_PVME1) 235 #define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008) /*!< Event line 35 Connected to the PVM1 EXTI Line */ 236 #endif /* PWR_CR2_PVME1 */ 237 #if defined(PWR_CR2_PVME2) 238 #define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010) /*!< Event line 36 Connected to the PVM2 EXTI Line */ 239 #endif /* PWR_CR2_PVME2 */ 240 #define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020) /*!< Event line 37 Connected to the PVM3 EXTI Line */ 241 #define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040) /*!< Event line 38 Connected to the PVM4 EXTI Line */ 242 /** 243 * @} 244 */ 245 246 /** @defgroup PWREx_Flag PWR Status Flags 247 * Elements values convention: 0000 0000 0XXY YYYYb 248 * - Y YYYY : Flag position in the XX register (5 bits) 249 * - XX : Status register (2 bits) 250 * - 01: SR1 register 251 * - 10: SR2 register 252 * The only exception is PWR_FLAG_WU, encompassing all 253 * wake-up flags and set to PWR_SR1_WUF. 254 * @{ 255 */ 256 #define PWR_FLAG_WUF1 ((uint32_t)0x0020) /*!< Wakeup event on wakeup pin 1 */ 257 #define PWR_FLAG_WUF2 ((uint32_t)0x0021) /*!< Wakeup event on wakeup pin 2 */ 258 #define PWR_FLAG_WUF3 ((uint32_t)0x0022) /*!< Wakeup event on wakeup pin 3 */ 259 #define PWR_FLAG_WUF4 ((uint32_t)0x0023) /*!< Wakeup event on wakeup pin 4 */ 260 #define PWR_FLAG_WUF5 ((uint32_t)0x0024) /*!< Wakeup event on wakeup pin 5 */ 261 #define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */ 262 #define PWR_FLAG_SB ((uint32_t)0x0028) /*!< Standby flag */ 263 #if defined(PWR_SR1_EXT_SMPS_RDY) 264 #define PWR_FLAG_EXT_SMPS ((uint32_t)0x002D) /*!< Switching to external SMPS ready flag */ 265 #endif /* PWR_SR1_EXT_SMPS_RDY */ 266 #define PWR_FLAG_WUFI ((uint32_t)0x002F) /*!< Wakeup on internal wakeup line */ 267 268 #define PWR_FLAG_REGLPS ((uint32_t)0x0048) /*!< Low-power regulator start flag */ 269 #define PWR_FLAG_REGLPF ((uint32_t)0x0049) /*!< Low-power regulator flag */ 270 #define PWR_FLAG_VOSF ((uint32_t)0x004A) /*!< Voltage scaling flag */ 271 #define PWR_FLAG_PVDO ((uint32_t)0x004B) /*!< Power Voltage Detector output flag */ 272 #if defined(PWR_CR2_PVME1) 273 #define PWR_FLAG_PVMO1 ((uint32_t)0x004C) /*!< Power Voltage Monitoring 1 output flag */ 274 #endif /* PWR_CR2_PVME1 */ 275 #if defined(PWR_CR2_PVME2) 276 #define PWR_FLAG_PVMO2 ((uint32_t)0x004D) /*!< Power Voltage Monitoring 2 output flag */ 277 #endif /* PWR_CR2_PVME2 */ 278 #define PWR_FLAG_PVMO3 ((uint32_t)0x004E) /*!< Power Voltage Monitoring 3 output flag */ 279 #define PWR_FLAG_PVMO4 ((uint32_t)0x004F) /*!< Power Voltage Monitoring 4 output flag */ 280 /** 281 * @} 282 */ 283 284 /** @defgroup PWREx_SRAM2_Retention PWR SRAM2 Retention in Standby mode 285 * @{ 286 */ 287 #define PWR_NO_SRAM2_RETENTION ((uint32_t)0x00000000) /*!< SRAM2 is powered off in Standby mode (SRAM2 content is lost) */ 288 #if defined(PWR_CR3_RRS_1) 289 #define PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS_0 /*!< Full SRAM2 is powered by the low-power regulator in Standby mode */ 290 #define PWR_4KBYTES_SRAM2_RETENTION PWR_CR3_RRS_1 /*!< Only 4 Kbytes of SRAM2 is powered by the low-power regulator in Standby mode */ 291 #else 292 #define PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS /*!< Full SRAM2 is powered by the low-power regulator in Standby mode */ 293 #endif /* PWR_CR3_RRS_1 */ 294 /** 295 * @} 296 */ 297 298 /** 299 * @} 300 */ 301 302 /* Exported macros -----------------------------------------------------------*/ 303 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros 304 * @{ 305 */ 306 307 #if defined(PWR_CR2_PVME1) 308 /** 309 * @brief Enable the PVM1 Extended Interrupt Line. 310 * @retval None 311 */ 312 #define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) 313 314 /** 315 * @brief Disable the PVM1 Extended Interrupt Line. 316 * @retval None 317 */ 318 #define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) 319 320 /** 321 * @brief Enable the PVM1 Event Line. 322 * @retval None 323 */ 324 #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) 325 326 /** 327 * @brief Disable the PVM1 Event Line. 328 * @retval None 329 */ 330 #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) 331 332 /** 333 * @brief Enable the PVM1 Extended Interrupt Rising Trigger. 334 * @retval None 335 */ 336 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) 337 338 /** 339 * @brief Disable the PVM1 Extended Interrupt Rising Trigger. 340 * @retval None 341 */ 342 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) 343 344 /** 345 * @brief Enable the PVM1 Extended Interrupt Falling Trigger. 346 * @retval None 347 */ 348 #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) 349 350 351 /** 352 * @brief Disable the PVM1 Extended Interrupt Falling Trigger. 353 * @retval None 354 */ 355 #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) 356 357 358 /** 359 * @brief PVM1 EXTI line configuration: set rising & falling edge trigger. 360 * @retval None 361 */ 362 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ 363 do { \ 364 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \ 365 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \ 366 } while(0) 367 368 /** 369 * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger. 370 * @retval None 371 */ 372 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ 373 do { \ 374 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \ 375 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \ 376 } while(0) 377 378 /** 379 * @brief Generate a Software interrupt on selected EXTI line. 380 * @retval None 381 */ 382 #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1) 383 384 /** 385 * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not. 386 * @retval EXTI PVM1 Line Status. 387 */ 388 #define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1) 389 390 /** 391 * @brief Clear the PVM1 EXTI flag. 392 * @retval None 393 */ 394 #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1) 395 396 #endif /* PWR_CR2_PVME1 */ 397 398 399 #if defined(PWR_CR2_PVME2) 400 /** 401 * @brief Enable the PVM2 Extended Interrupt Line. 402 * @retval None 403 */ 404 #define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) 405 406 /** 407 * @brief Disable the PVM2 Extended Interrupt Line. 408 * @retval None 409 */ 410 #define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) 411 412 /** 413 * @brief Enable the PVM2 Event Line. 414 * @retval None 415 */ 416 #define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) 417 418 /** 419 * @brief Disable the PVM2 Event Line. 420 * @retval None 421 */ 422 #define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) 423 424 /** 425 * @brief Enable the PVM2 Extended Interrupt Rising Trigger. 426 * @retval None 427 */ 428 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) 429 430 /** 431 * @brief Disable the PVM2 Extended Interrupt Rising Trigger. 432 * @retval None 433 */ 434 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) 435 436 /** 437 * @brief Enable the PVM2 Extended Interrupt Falling Trigger. 438 * @retval None 439 */ 440 #define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) 441 442 443 /** 444 * @brief Disable the PVM2 Extended Interrupt Falling Trigger. 445 * @retval None 446 */ 447 #define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) 448 449 450 /** 451 * @brief PVM2 EXTI line configuration: set rising & falling edge trigger. 452 * @retval None 453 */ 454 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \ 455 do { \ 456 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \ 457 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \ 458 } while(0) 459 460 /** 461 * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger. 462 * @retval None 463 */ 464 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \ 465 do { \ 466 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \ 467 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \ 468 } while(0) 469 470 /** 471 * @brief Generate a Software interrupt on selected EXTI line. 472 * @retval None 473 */ 474 #define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2) 475 476 /** 477 * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not. 478 * @retval EXTI PVM2 Line Status. 479 */ 480 #define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2) 481 482 /** 483 * @brief Clear the PVM2 EXTI flag. 484 * @retval None 485 */ 486 #define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2) 487 488 #endif /* PWR_CR2_PVME2 */ 489 490 491 /** 492 * @brief Enable the PVM3 Extended Interrupt Line. 493 * @retval None 494 */ 495 #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) 496 497 /** 498 * @brief Disable the PVM3 Extended Interrupt Line. 499 * @retval None 500 */ 501 #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) 502 503 /** 504 * @brief Enable the PVM3 Event Line. 505 * @retval None 506 */ 507 #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) 508 509 /** 510 * @brief Disable the PVM3 Event Line. 511 * @retval None 512 */ 513 #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) 514 515 /** 516 * @brief Enable the PVM3 Extended Interrupt Rising Trigger. 517 * @retval None 518 */ 519 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) 520 521 /** 522 * @brief Disable the PVM3 Extended Interrupt Rising Trigger. 523 * @retval None 524 */ 525 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) 526 527 /** 528 * @brief Enable the PVM3 Extended Interrupt Falling Trigger. 529 * @retval None 530 */ 531 #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) 532 533 534 /** 535 * @brief Disable the PVM3 Extended Interrupt Falling Trigger. 536 * @retval None 537 */ 538 #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) 539 540 541 /** 542 * @brief PVM3 EXTI line configuration: set rising & falling edge trigger. 543 * @retval None 544 */ 545 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \ 546 do { \ 547 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \ 548 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \ 549 } while(0) 550 551 /** 552 * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger. 553 * @retval None 554 */ 555 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \ 556 do { \ 557 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \ 558 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \ 559 } while(0) 560 561 /** 562 * @brief Generate a Software interrupt on selected EXTI line. 563 * @retval None 564 */ 565 #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3) 566 567 /** 568 * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not. 569 * @retval EXTI PVM3 Line Status. 570 */ 571 #define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3) 572 573 /** 574 * @brief Clear the PVM3 EXTI flag. 575 * @retval None 576 */ 577 #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3) 578 579 580 581 582 /** 583 * @brief Enable the PVM4 Extended Interrupt Line. 584 * @retval None 585 */ 586 #define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) 587 588 /** 589 * @brief Disable the PVM4 Extended Interrupt Line. 590 * @retval None 591 */ 592 #define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) 593 594 /** 595 * @brief Enable the PVM4 Event Line. 596 * @retval None 597 */ 598 #define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) 599 600 /** 601 * @brief Disable the PVM4 Event Line. 602 * @retval None 603 */ 604 #define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) 605 606 /** 607 * @brief Enable the PVM4 Extended Interrupt Rising Trigger. 608 * @retval None 609 */ 610 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) 611 612 /** 613 * @brief Disable the PVM4 Extended Interrupt Rising Trigger. 614 * @retval None 615 */ 616 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) 617 618 /** 619 * @brief Enable the PVM4 Extended Interrupt Falling Trigger. 620 * @retval None 621 */ 622 #define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) 623 624 625 /** 626 * @brief Disable the PVM4 Extended Interrupt Falling Trigger. 627 * @retval None 628 */ 629 #define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) 630 631 632 /** 633 * @brief PVM4 EXTI line configuration: set rising & falling edge trigger. 634 * @retval None 635 */ 636 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \ 637 do { \ 638 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \ 639 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \ 640 } while(0) 641 642 /** 643 * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger. 644 * @retval None 645 */ 646 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \ 647 do { \ 648 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \ 649 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \ 650 } while(0) 651 652 /** 653 * @brief Generate a Software interrupt on selected EXTI line. 654 * @retval None 655 */ 656 #define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4) 657 658 /** 659 * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set. 660 * @retval EXTI PVM4 Line Status. 661 */ 662 #define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4) 663 664 /** 665 * @brief Clear the PVM4 EXTI flag. 666 * @retval None 667 */ 668 #define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4) 669 670 671 /** 672 * @brief Configure the main internal regulator output voltage. 673 * @param __REGULATOR__ specifies the regulator output voltage to achieve 674 * a tradeoff between performance and power consumption. 675 * This parameter can be one of the following values: 676 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, 677 * typical output voltage at 1.2 V, 678 * system frequency up to 80 MHz. 679 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, 680 * typical output voltage at 1.0 V, 681 * system frequency up to 26 MHz. 682 * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check 683 * whether or not VOSF flag is cleared when moving from range 2 to range 1. User 684 * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. 685 * @retval None 686 */ 687 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ 688 __IO uint32_t tmpreg; \ 689 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ 690 /* Delay after an RCC peripheral clock enabling */ \ 691 tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ 692 UNUSED(tmpreg); \ 693 } while(0) 694 695 /** 696 * @} 697 */ 698 699 /* Private macros --------------------------------------------------------*/ 700 /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros 701 * @{ 702 */ 703 704 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ 705 ((PIN) == PWR_WAKEUP_PIN2) || \ 706 ((PIN) == PWR_WAKEUP_PIN3) || \ 707 ((PIN) == PWR_WAKEUP_PIN4) || \ 708 ((PIN) == PWR_WAKEUP_PIN5) || \ 709 ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ 710 ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ 711 ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ 712 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ 713 ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \ 714 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ 715 ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ 716 ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ 717 ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ 718 ((PIN) == PWR_WAKEUP_PIN5_LOW)) 719 720 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 721 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 722 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ 723 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 724 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ 725 ((TYPE) == PWR_PVM_2) ||\ 726 ((TYPE) == PWR_PVM_3) ||\ 727 ((TYPE) == PWR_PVM_4)) 728 #elif defined (STM32L471xx) 729 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\ 730 ((TYPE) == PWR_PVM_3) ||\ 731 ((TYPE) == PWR_PVM_4)) 732 #endif 733 734 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx) 735 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ 736 ((TYPE) == PWR_PVM_3) ||\ 737 ((TYPE) == PWR_PVM_4)) 738 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L442xx) || defined (STM32L451xx) 739 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\ 740 ((TYPE) == PWR_PVM_4)) 741 #endif 742 743 #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ 744 ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ 745 ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ 746 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ 747 ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ 748 ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ 749 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) 750 751 #if defined(PWR_CR5_R1MODE) 752 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \ 753 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ 754 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) 755 #else 756 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ 757 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) 758 #endif 759 760 761 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ 762 ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) 763 764 #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ 765 ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) 766 767 #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00) 768 769 770 #if defined (STM32L412xx) || defined (STM32L422xx) 771 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 772 ((GPIO) == PWR_GPIO_B) ||\ 773 ((GPIO) == PWR_GPIO_C) ||\ 774 ((GPIO) == PWR_GPIO_D) ||\ 775 ((GPIO) == PWR_GPIO_H)) 776 #elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \ 777 defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 778 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 779 ((GPIO) == PWR_GPIO_B) ||\ 780 ((GPIO) == PWR_GPIO_C) ||\ 781 ((GPIO) == PWR_GPIO_D) ||\ 782 ((GPIO) == PWR_GPIO_E) ||\ 783 ((GPIO) == PWR_GPIO_H)) 784 #elif defined (STM32L432xx) || defined (STM32L442xx) 785 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 786 ((GPIO) == PWR_GPIO_B) ||\ 787 ((GPIO) == PWR_GPIO_C) ||\ 788 ((GPIO) == PWR_GPIO_H)) 789 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 790 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 791 ((GPIO) == PWR_GPIO_B) ||\ 792 ((GPIO) == PWR_GPIO_C) ||\ 793 ((GPIO) == PWR_GPIO_D) ||\ 794 ((GPIO) == PWR_GPIO_E) ||\ 795 ((GPIO) == PWR_GPIO_F) ||\ 796 ((GPIO) == PWR_GPIO_G) ||\ 797 ((GPIO) == PWR_GPIO_H)) 798 #elif defined (STM32L496xx) || defined (STM32L4A6xx) || \ 799 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ 800 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 801 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 802 ((GPIO) == PWR_GPIO_B) ||\ 803 ((GPIO) == PWR_GPIO_C) ||\ 804 ((GPIO) == PWR_GPIO_D) ||\ 805 ((GPIO) == PWR_GPIO_E) ||\ 806 ((GPIO) == PWR_GPIO_F) ||\ 807 ((GPIO) == PWR_GPIO_G) ||\ 808 ((GPIO) == PWR_GPIO_H) ||\ 809 ((GPIO) == PWR_GPIO_I)) 810 #endif 811 812 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) 813 #define IS_PWR_SRAM2_RETENTION(SRAM2) (((SRAM2) == PWR_NO_SRAM2_RETENTION) ||\ 814 ((SRAM2) == PWR_FULL_SRAM2_RETENTION) ||\ 815 ((SRAM2) == PWR_4KBYTES_SRAM2_RETENTION)) 816 #else 817 #define IS_PWR_SRAM2_RETENTION(SRAM2) (((SRAM2) == PWR_NO_SRAM2_RETENTION) ||\ 818 ((SRAM2) == PWR_FULL_SRAM2_RETENTION)) 819 #endif 820 821 /** 822 * @} 823 */ 824 825 826 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions 827 * @{ 828 */ 829 830 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions 831 * @{ 832 */ 833 834 835 /* Peripheral Control functions **********************************************/ 836 uint32_t HAL_PWREx_GetVoltageRange(void); 837 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); 838 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); 839 void HAL_PWREx_DisableBatteryCharging(void); 840 #if defined(PWR_CR2_USV) 841 void HAL_PWREx_EnableVddUSB(void); 842 void HAL_PWREx_DisableVddUSB(void); 843 #endif /* PWR_CR2_USV */ 844 #if defined(PWR_CR2_IOSV) 845 void HAL_PWREx_EnableVddIO2(void); 846 void HAL_PWREx_DisableVddIO2(void); 847 #endif /* PWR_CR2_IOSV */ 848 void HAL_PWREx_EnableInternalWakeUpLine(void); 849 void HAL_PWREx_DisableInternalWakeUpLine(void); 850 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); 851 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); 852 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); 853 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); 854 void HAL_PWREx_EnablePullUpPullDownConfig(void); 855 void HAL_PWREx_DisablePullUpPullDownConfig(void); 856 void HAL_PWREx_EnableSRAM2ContentRetention(void); 857 void HAL_PWREx_DisableSRAM2ContentRetention(void); 858 HAL_StatusTypeDef HAL_PWREx_SetSRAM2ContentRetention(uint32_t SRAM2Size); 859 #if defined(PWR_CR1_RRSTP) 860 void HAL_PWREx_EnableSRAM3ContentRetention(void); 861 void HAL_PWREx_DisableSRAM3ContentRetention(void); 862 #endif /* PWR_CR1_RRSTP */ 863 #if defined(PWR_CR3_DSIPDEN) 864 void HAL_PWREx_EnableDSIPinsPDActivation(void); 865 void HAL_PWREx_DisableDSIPinsPDActivation(void); 866 #endif /* PWR_CR3_DSIPDEN */ 867 #if defined(PWR_CR2_PVME1) 868 void HAL_PWREx_EnablePVM1(void); 869 void HAL_PWREx_DisablePVM1(void); 870 #endif /* PWR_CR2_PVME1 */ 871 #if defined(PWR_CR2_PVME2) 872 void HAL_PWREx_EnablePVM2(void); 873 void HAL_PWREx_DisablePVM2(void); 874 #endif /* PWR_CR2_PVME2 */ 875 void HAL_PWREx_EnablePVM3(void); 876 void HAL_PWREx_DisablePVM3(void); 877 void HAL_PWREx_EnablePVM4(void); 878 void HAL_PWREx_DisablePVM4(void); 879 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); 880 #if defined(PWR_CR3_ENULP) 881 void HAL_PWREx_EnableBORPVD_ULP(void); 882 void HAL_PWREx_DisableBORPVD_ULP(void); 883 #endif /* PWR_CR3_ENULP */ 884 #if defined(PWR_CR4_EXT_SMPS_ON) 885 void HAL_PWREx_EnableExtSMPS_0V95(void); 886 void HAL_PWREx_DisableExtSMPS_0V95(void); 887 #endif /* PWR_CR4_EXT_SMPS_ON */ 888 889 890 /* Low Power modes configuration functions ************************************/ 891 void HAL_PWREx_EnableLowPowerRunMode(void); 892 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); 893 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry); 894 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); 895 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); 896 void HAL_PWREx_EnterSHUTDOWNMode(void); 897 898 void HAL_PWREx_PVD_PVM_IRQHandler(void); 899 #if defined(PWR_CR2_PVME1) 900 void HAL_PWREx_PVM1Callback(void); 901 #endif /* PWR_CR2_PVME1 */ 902 #if defined(PWR_CR2_PVME2) 903 void HAL_PWREx_PVM2Callback(void); 904 #endif /* PWR_CR2_PVME2 */ 905 void HAL_PWREx_PVM3Callback(void); 906 void HAL_PWREx_PVM4Callback(void); 907 908 /** 909 * @} 910 */ 911 912 /** 913 * @} 914 */ 915 916 /** 917 * @} 918 */ 919 920 /** 921 * @} 922 */ 923 924 #ifdef __cplusplus 925 } 926 #endif 927 928 929 #endif /* STM32L4xx_HAL_PWR_EX_H */ 930
