1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_flash.h 4 * @author MCD Application Team 5 * @brief Header file of FLASH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32L4xx_HAL_FLASH_H 20 #define STM32L4xx_HAL_FLASH_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32l4xx_hal_def.h" 28 29 /** @addtogroup STM32L4xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup FLASH 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 /** @defgroup FLASH_Exported_Types FLASH Exported Types 39 * @{ 40 */ 41 42 /** 43 * @brief FLASH Erase structure definition 44 */ 45 typedef struct 46 { 47 uint32_t TypeErase; /*!< Mass erase or page erase. 48 This parameter can be a value of @ref FLASH_Type_Erase */ 49 uint32_t Banks; /*!< Select bank to erase. 50 This parameter must be a value of @ref FLASH_Banks 51 (FLASH_BANK_BOTH should be used only for mass erase) */ 52 uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled 53 This parameter must be a value between 0 and (max number of pages in the bank - 1) 54 (eg : 255 for 1MB dual bank) */ 55 uint32_t NbPages; /*!< Number of pages to be erased. 56 This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/ 57 } FLASH_EraseInitTypeDef; 58 59 /** 60 * @brief FLASH Option Bytes Program structure definition 61 */ 62 typedef struct 63 { 64 uint32_t OptionType; /*!< Option byte to be configured. 65 This parameter can be a combination of the values of @ref FLASH_OB_Type */ 66 uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). 67 Only one WRP area could be programmed at the same time. 68 This parameter can be value of @ref FLASH_OB_WRP_Area */ 69 uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). 70 This parameter must be a value between 0 and (max number of pages in the bank - 1) 71 (eg : 25 for 1MB dual bank) */ 72 uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). 73 This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */ 74 uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP). 75 This parameter can be a value of @ref FLASH_OB_Read_Protection */ 76 uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). 77 This parameter can be a combination of @ref FLASH_OB_USER_Type */ 78 uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). 79 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, 80 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, 81 @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, 82 @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, 83 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2, 84 @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1, 85 @ref FLASH_OB_USER_SRAM2_PE, @ref FLASH_OB_USER_SRAM2_RST, 86 @ref FLASH_OB_USER_nSWBOOT0 and @ref FLASH_OB_USER_nBOOT0 */ 87 uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). 88 This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH) 89 and @ref FLASH_OB_PCROP_RDP */ 90 uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). 91 This parameter must be a value between begin and end of bank 92 => Be careful of the bank swapping for the address */ 93 uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). 94 This parameter must be a value between PCROP Start address and end of bank */ 95 } FLASH_OBProgramInitTypeDef; 96 97 /** 98 * @brief FLASH Procedure structure definition 99 */ 100 typedef enum 101 { 102 FLASH_PROC_NONE = 0, 103 FLASH_PROC_PAGE_ERASE, 104 FLASH_PROC_MASS_ERASE, 105 FLASH_PROC_PROGRAM, 106 FLASH_PROC_PROGRAM_LAST 107 } FLASH_ProcedureTypeDef; 108 109 /** 110 * @brief FLASH Cache structure definition 111 */ 112 typedef enum 113 { 114 FLASH_CACHE_DISABLED = 0, 115 FLASH_CACHE_ICACHE_ENABLED, 116 FLASH_CACHE_DCACHE_ENABLED, 117 FLASH_CACHE_ICACHE_DCACHE_ENABLED 118 } FLASH_CacheTypeDef; 119 120 /** 121 * @brief FLASH handle Structure definition 122 */ 123 typedef struct 124 { 125 HAL_LockTypeDef Lock; /* FLASH locking object */ 126 __IO uint32_t ErrorCode; /* FLASH error code */ 127 __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ 128 __IO uint32_t Address; /* Internal variable to save address selected for program in IT context */ 129 __IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */ 130 __IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ 131 __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ 132 __IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */ 133 }FLASH_ProcessTypeDef; 134 135 /** 136 * @} 137 */ 138 139 /* Exported constants --------------------------------------------------------*/ 140 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 141 * @{ 142 */ 143 144 /** @defgroup FLASH_Error FLASH Error 145 * @{ 146 */ 147 #define HAL_FLASH_ERROR_NONE 0x00000000U 148 #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR 149 #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR 150 #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR 151 #define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR 152 #define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR 153 #define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR 154 #define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR 155 #define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR 156 #define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR 157 #define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR 158 #define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC 159 #define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD 160 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ 161 defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ 162 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || \ 163 defined (STM32L4S7xx) || defined (STM32L4S9xx) 164 #define HAL_FLASH_ERROR_PEMPTY FLASH_FLAG_PEMPTY 165 #endif 166 /** 167 * @} 168 */ 169 170 /** @defgroup FLASH_Type_Erase FLASH Erase Type 171 * @{ 172 */ 173 #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/ 174 #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01) /*!<Flash mass erase activation*/ 175 /** 176 * @} 177 */ 178 179 /** @defgroup FLASH_Banks FLASH Banks 180 * @{ 181 */ 182 #define FLASH_BANK_1 ((uint32_t)0x01) /*!< Bank 1 */ 183 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 184 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 185 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 186 #define FLASH_BANK_2 ((uint32_t)0x02) /*!< Bank 2 */ 187 #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */ 188 #else 189 #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1)) /*!< Bank 1 */ 190 #endif 191 /** 192 * @} 193 */ 194 195 196 /** @defgroup FLASH_Type_Program FLASH Program Type 197 * @{ 198 */ 199 #define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x00) /*!<Program a double-word (64-bit) at a specified address.*/ 200 #define FLASH_TYPEPROGRAM_FAST ((uint32_t)0x01) /*!<Fast program a 32 row double-word (64-bit) at a specified address. 201 And another 32 row double-word (64-bit) will be programmed */ 202 #define FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02) /*!<Fast program a 32 row double-word (64-bit) at a specified address. 203 And this is the last 32 row double-word (64-bit) programmed */ 204 /** 205 * @} 206 */ 207 208 /** @defgroup FLASH_OB_Type FLASH Option Bytes Type 209 * @{ 210 */ 211 #define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */ 212 #define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */ 213 #define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */ 214 #define OPTIONBYTE_PCROP ((uint32_t)0x08) /*!< PCROP option byte configuration */ 215 /** 216 * @} 217 */ 218 219 /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area 220 * @{ 221 */ 222 #define OB_WRPAREA_BANK1_AREAA ((uint32_t)0x00) /*!< Flash Bank 1 Area A */ 223 #define OB_WRPAREA_BANK1_AREAB ((uint32_t)0x01) /*!< Flash Bank 1 Area B */ 224 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 225 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 226 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 227 #define OB_WRPAREA_BANK2_AREAA ((uint32_t)0x02) /*!< Flash Bank 2 Area A */ 228 #define OB_WRPAREA_BANK2_AREAB ((uint32_t)0x04) /*!< Flash Bank 2 Area B */ 229 #endif 230 /** 231 * @} 232 */ 233 234 /** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection 235 * @{ 236 */ 237 #define OB_RDP_LEVEL_0 ((uint32_t)0xAA) 238 #define OB_RDP_LEVEL_1 ((uint32_t)0xBB) 239 #define OB_RDP_LEVEL_2 ((uint32_t)0xCC) /*!< Warning: When enabling read protection level 2 240 it's no more possible to go back to level 1 or 0 */ 241 /** 242 * @} 243 */ 244 245 /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type 246 * @{ 247 */ 248 #define OB_USER_BOR_LEV ((uint32_t)0x0001) /*!< BOR reset Level */ 249 #define OB_USER_nRST_STOP ((uint32_t)0x0002) /*!< Reset generated when entering the stop mode */ 250 #define OB_USER_nRST_STDBY ((uint32_t)0x0004) /*!< Reset generated when entering the standby mode */ 251 #define OB_USER_IWDG_SW ((uint32_t)0x0008) /*!< Independent watchdog selection */ 252 #define OB_USER_IWDG_STOP ((uint32_t)0x0010) /*!< Independent watchdog counter freeze in stop mode */ 253 #define OB_USER_IWDG_STDBY ((uint32_t)0x0020) /*!< Independent watchdog counter freeze in standby mode */ 254 #define OB_USER_WWDG_SW ((uint32_t)0x0040) /*!< Window watchdog selection */ 255 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 256 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 257 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 258 #define OB_USER_BFB2 ((uint32_t)0x0080) /*!< Dual-bank boot */ 259 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 260 #define OB_USER_DUALBANK ((uint32_t)0x0100) /*!< Dual-Bank on 1MB or 512kB Flash memory devices */ 261 #else 262 #define OB_USER_DUALBANK ((uint32_t)0x0100) /*!< Dual-Bank on 512KB or 256KB Flash memory devices */ 263 #endif 264 #endif 265 #define OB_USER_nBOOT1 ((uint32_t)0x0200) /*!< Boot configuration */ 266 #define OB_USER_SRAM2_PE ((uint32_t)0x0400) /*!< SRAM2 parity check enable */ 267 #define OB_USER_SRAM2_RST ((uint32_t)0x0800) /*!< SRAM2 Erase when system reset */ 268 #define OB_USER_nRST_SHDW ((uint32_t)0x1000) /*!< Reset generated when entering the shutdown mode */ 269 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \ 270 defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ 271 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 272 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 273 #define OB_USER_nSWBOOT0 ((uint32_t)0x2000) /*!< Software BOOT0 */ 274 #define OB_USER_nBOOT0 ((uint32_t)0x4000) /*!< nBOOT0 option bit */ 275 #endif 276 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 277 #define OB_USER_DBANK ((uint32_t)0x8000) /*!< Single bank with 128-bits data or two banks with 64-bits data */ 278 #endif 279 /** 280 * @} 281 */ 282 283 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level 284 * @{ 285 */ 286 #define OB_BOR_LEVEL_0 ((uint32_t)FLASH_OPTR_BOR_LEV_0) /*!< Reset level threshold is around 1.7V */ 287 #define OB_BOR_LEVEL_1 ((uint32_t)FLASH_OPTR_BOR_LEV_1) /*!< Reset level threshold is around 2.0V */ 288 #define OB_BOR_LEVEL_2 ((uint32_t)FLASH_OPTR_BOR_LEV_2) /*!< Reset level threshold is around 2.2V */ 289 #define OB_BOR_LEVEL_3 ((uint32_t)FLASH_OPTR_BOR_LEV_3) /*!< Reset level threshold is around 2.5V */ 290 #define OB_BOR_LEVEL_4 ((uint32_t)FLASH_OPTR_BOR_LEV_4) /*!< Reset level threshold is around 2.8V */ 291 /** 292 * @} 293 */ 294 295 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop 296 * @{ 297 */ 298 #define OB_STOP_RST ((uint32_t)0x0000) /*!< Reset generated when entering the stop mode */ 299 #define OB_STOP_NORST ((uint32_t)FLASH_OPTR_nRST_STOP) /*!< No reset generated when entering the stop mode */ 300 /** 301 * @} 302 */ 303 304 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby 305 * @{ 306 */ 307 #define OB_STANDBY_RST ((uint32_t)0x0000) /*!< Reset generated when entering the standby mode */ 308 #define OB_STANDBY_NORST ((uint32_t)FLASH_OPTR_nRST_STDBY) /*!< No reset generated when entering the standby mode */ 309 /** 310 * @} 311 */ 312 313 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown 314 * @{ 315 */ 316 #define OB_SHUTDOWN_RST ((uint32_t)0x0000) /*!< Reset generated when entering the shutdown mode */ 317 #define OB_SHUTDOWN_NORST ((uint32_t)FLASH_OPTR_nRST_SHDW) /*!< No reset generated when entering the shutdown mode */ 318 /** 319 * @} 320 */ 321 322 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type 323 * @{ 324 */ 325 #define OB_IWDG_HW ((uint32_t)0x00000) /*!< Hardware independent watchdog */ 326 #define OB_IWDG_SW ((uint32_t)FLASH_OPTR_IWDG_SW) /*!< Software independent watchdog */ 327 /** 328 * @} 329 */ 330 331 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop 332 * @{ 333 */ 334 #define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000) /*!< Independent watchdog counter is frozen in Stop mode */ 335 #define OB_IWDG_STOP_RUN ((uint32_t)FLASH_OPTR_IWDG_STOP) /*!< Independent watchdog counter is running in Stop mode */ 336 /** 337 * @} 338 */ 339 340 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby 341 * @{ 342 */ 343 #define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000) /*!< Independent watchdog counter is frozen in Standby mode */ 344 #define OB_IWDG_STDBY_RUN ((uint32_t)FLASH_OPTR_IWDG_STDBY) /*!< Independent watchdog counter is running in Standby mode */ 345 /** 346 * @} 347 */ 348 349 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type 350 * @{ 351 */ 352 #define OB_WWDG_HW ((uint32_t)0x00000) /*!< Hardware window watchdog */ 353 #define OB_WWDG_SW ((uint32_t)FLASH_OPTR_WWDG_SW) /*!< Software window watchdog */ 354 /** 355 * @} 356 */ 357 358 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 359 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 360 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 361 /** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode 362 * @{ 363 */ 364 #define OB_BFB2_DISABLE ((uint32_t)0x000000) /*!< Dual-bank boot disable */ 365 #define OB_BFB2_ENABLE ((uint32_t)FLASH_OPTR_BFB2) /*!< Dual-bank boot enable */ 366 /** 367 * @} 368 */ 369 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 370 /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type 371 * @{ 372 */ 373 #define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /*!< 1 MB/512 kB Single-bank Flash */ 374 #define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DB1M) /*!< 1 MB/512 kB Dual-bank Flash */ 375 /** 376 * @} 377 */ 378 #else 379 /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type 380 * @{ 381 */ 382 #define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /*!< 256 KB/512 KB Single-bank Flash */ 383 #define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DUALBANK) /*!< 256 KB/512 KB Dual-bank Flash */ 384 /** 385 * @} 386 */ 387 #endif 388 #endif 389 390 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 391 /** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type 392 * @{ 393 */ 394 #define OB_DBANK_128_BITS ((uint32_t)0x000000) /*!< Single-bank with 128-bits data */ 395 #define OB_DBANK_64_BITS ((uint32_t)FLASH_OPTR_DBANK) /*!< Dual-bank with 64-bits data */ 396 #endif 397 /** 398 * @} 399 */ 400 /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type 401 * @{ 402 */ 403 #define OB_BOOT1_SRAM ((uint32_t)0x000000) /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */ 404 #define OB_BOOT1_SYSTEM ((uint32_t)FLASH_OPTR_nBOOT1) /*!< System memory is selected as boot space (if BOOT0=1) */ 405 /** 406 * @} 407 */ 408 409 /** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes User SRAM2 Parity Check Type 410 * @{ 411 */ 412 #define OB_SRAM2_PARITY_ENABLE ((uint32_t)0x0000000) /*!< SRAM2 parity check enable */ 413 #define OB_SRAM2_PARITY_DISABLE ((uint32_t)FLASH_OPTR_SRAM2_PE) /*!< SRAM2 parity check disable */ 414 /** 415 * @} 416 */ 417 418 /** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type 419 * @{ 420 */ 421 #define OB_SRAM2_RST_ERASE ((uint32_t)0x0000000) /*!< SRAM2 erased when a system reset occurs */ 422 #define OB_SRAM2_RST_NOT_ERASE ((uint32_t)FLASH_OPTR_SRAM2_RST) /*!< SRAM2 is not erased when a system reset occurs */ 423 /** 424 * @} 425 */ 426 427 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \ 428 defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ 429 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 430 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 431 /** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0 432 * @{ 433 */ 434 #define OB_BOOT0_FROM_OB ((uint32_t)0x0000000) /*!< BOOT0 taken from the option bit nBOOT0 */ 435 #define OB_BOOT0_FROM_PIN ((uint32_t)FLASH_OPTR_nSWBOOT0) /*!< BOOT0 taken from PH3/BOOT0 pin */ 436 /** 437 * @} 438 */ 439 440 /** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit 441 * @{ 442 */ 443 #define OB_BOOT0_RESET ((uint32_t)0x0000000) /*!< nBOOT0 = 0 */ 444 #define OB_BOOT0_SET ((uint32_t)FLASH_OPTR_nBOOT0) /*!< nBOOT0 = 1 */ 445 /** 446 * @} 447 */ 448 #endif 449 450 /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type 451 * @{ 452 */ 453 #define OB_PCROP_RDP_NOT_ERASE ((uint32_t)0x00000000) /*!< PCROP area is not erased when the RDP level 454 is decreased from Level 1 to Level 0 */ 455 #define OB_PCROP_RDP_ERASE ((uint32_t)FLASH_PCROP1ER_PCROP_RDP) /*!< PCROP area is erased when the RDP level is 456 decreased from Level 1 to Level 0 (full mass erase) */ 457 /** 458 * @} 459 */ 460 461 /** @defgroup FLASH_Latency FLASH Latency 462 * @{ 463 */ 464 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ 465 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ 466 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ 467 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ 468 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ 469 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 470 #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait state */ 471 #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait state */ 472 #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */ 473 #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */ 474 #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait states */ 475 #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait state */ 476 #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait state */ 477 #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait states */ 478 #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait states */ 479 #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait states */ 480 #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait states */ 481 #endif 482 /** 483 * @} 484 */ 485 486 /** @defgroup FLASH_Keys FLASH Keys 487 * @{ 488 */ 489 #define FLASH_KEY1 0x45670123U /*!< Flash key1 */ 490 #define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 491 to unlock the FLASH registers access */ 492 493 #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */ 494 #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 495 to unlock the RUN_PD bit in FLASH_ACR */ 496 497 #define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ 498 #define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 499 to allow option bytes operations */ 500 /** 501 * @} 502 */ 503 504 /** @defgroup FLASH_Flags FLASH Flags Definition 505 * @{ 506 */ 507 #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */ 508 #define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */ 509 #define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /*!< FLASH Programming error flag */ 510 #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protection error flag */ 511 #define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */ 512 #define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */ 513 #define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */ 514 #define FLASH_FLAG_MISERR FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */ 515 #define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */ 516 #define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */ 517 #define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */ 518 #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ 519 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ 520 defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ 521 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || \ 522 defined (STM32L4S7xx) || defined (STM32L4S9xx) 523 #define FLASH_FLAG_PEMPTY FLASH_SR_PEMPTY /*!< FLASH Program empty */ 524 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 525 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 526 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ 527 FLASH_FLAG_OPTVERR | FLASH_FLAG_PEMPTY) 528 #else 529 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 530 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 531 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ 532 FLASH_FLAG_OPTVERR) 533 #endif 534 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || \ 535 defined (STM32L4S7xx) || defined (STM32L4S9xx) 536 #define FLASH_FLAG_ECCC (FLASH_ECCR_ECCC | FLASH_ECCR_ECCC2) /*!< FLASH ECC correction */ 537 #define FLASH_FLAG_ECCD (FLASH_ECCR_ECCD | FLASH_ECCR_ECCD2) /*!< FLASH ECC detection */ 538 #else 539 #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ 540 #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ 541 #endif 542 #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCD | FLASH_FLAG_ECCC) 543 544 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 545 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 546 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ 547 FLASH_FLAG_OPTVERR | FLASH_FLAG_ECCR_ERRORS) 548 /** 549 * @} 550 */ 551 552 /** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition 553 * @brief FLASH Interrupt definition 554 * @{ 555 */ 556 #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ 557 #define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */ 558 #define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source*/ 559 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */ 560 /** 561 * @} 562 */ 563 564 /* Exported macros -----------------------------------------------------------*/ 565 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros 566 * @brief macros to control FLASH features 567 * @{ 568 */ 569 570 /** 571 * @brief Set the FLASH Latency. 572 * @param __LATENCY__ FLASH Latency 573 * This parameter can be one of the following values : 574 * @arg FLASH_LATENCY_0: FLASH Zero wait state 575 * @arg FLASH_LATENCY_1: FLASH One wait state 576 * @arg FLASH_LATENCY_2: FLASH Two wait states 577 * @arg FLASH_LATENCY_3: FLASH Three wait states 578 * @arg FLASH_LATENCY_4: FLASH Four wait states 579 * @retval None 580 */ 581 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))) 582 583 /** 584 * @brief Get the FLASH Latency. 585 * @retval FLASH Latency 586 * This parameter can be one of the following values : 587 * @arg FLASH_LATENCY_0: FLASH Zero wait state 588 * @arg FLASH_LATENCY_1: FLASH One wait state 589 * @arg FLASH_LATENCY_2: FLASH Two wait states 590 * @arg FLASH_LATENCY_3: FLASH Three wait states 591 * @arg FLASH_LATENCY_4: FLASH Four wait states 592 */ 593 #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) 594 595 /** 596 * @brief Enable the FLASH prefetch buffer. 597 * @retval None 598 */ 599 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 600 601 /** 602 * @brief Disable the FLASH prefetch buffer. 603 * @retval None 604 */ 605 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 606 607 /** 608 * @brief Enable the FLASH instruction cache. 609 * @retval none 610 */ 611 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) 612 613 /** 614 * @brief Disable the FLASH instruction cache. 615 * @retval none 616 */ 617 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) 618 619 /** 620 * @brief Enable the FLASH data cache. 621 * @retval none 622 */ 623 #define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN) 624 625 /** 626 * @brief Disable the FLASH data cache. 627 * @retval none 628 */ 629 #define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN) 630 631 /** 632 * @brief Reset the FLASH instruction Cache. 633 * @note This function must be used only when the Instruction Cache is disabled. 634 * @retval None 635 */ 636 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ 637 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ 638 } while (0) 639 640 /** 641 * @brief Reset the FLASH data Cache. 642 * @note This function must be used only when the data Cache is disabled. 643 * @retval None 644 */ 645 #define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ 646 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ 647 } while (0) 648 649 /** 650 * @brief Enable the FLASH power down during Low-power run mode. 651 * @note Writing this bit to 0 this bit, automatically the keys are 652 * loss and a new unlock sequence is necessary to re-write it to 1. 653 */ 654 #define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ 655 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ 656 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ 657 } while (0) 658 659 /** 660 * @brief Disable the FLASH power down during Low-power run mode. 661 * @note Writing this bit to 0 this bit, automatically the keys are 662 * loss and a new unlock sequence is necessary to re-write it to 1. 663 */ 664 #define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ 665 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ 666 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ 667 } while (0) 668 669 /** 670 * @brief Enable the FLASH power down during Low-Power sleep mode 671 * @retval none 672 */ 673 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 674 675 /** 676 * @brief Disable the FLASH power down during Low-Power sleep mode 677 * @retval none 678 */ 679 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 680 681 /** 682 * @} 683 */ 684 685 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros 686 * @brief macros to handle FLASH interrupts 687 * @{ 688 */ 689 690 /** 691 * @brief Enable the specified FLASH interrupt. 692 * @param __INTERRUPT__ FLASH interrupt 693 * This parameter can be any combination of the following values: 694 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 695 * @arg FLASH_IT_OPERR: Error Interrupt 696 * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt 697 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 698 * @retval none 699 */ 700 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 701 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 702 } while(0) 703 704 /** 705 * @brief Disable the specified FLASH interrupt. 706 * @param __INTERRUPT__ FLASH interrupt 707 * This parameter can be any combination of the following values: 708 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 709 * @arg FLASH_IT_OPERR: Error Interrupt 710 * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt 711 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 712 * @retval none 713 */ 714 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 715 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 716 } while(0) 717 718 /** 719 * @brief Check whether the specified FLASH flag is set or not. 720 * @param __FLAG__ specifies the FLASH flag to check. 721 * This parameter can be one of the following values: 722 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 723 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 724 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 725 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 726 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 727 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 728 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 729 * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag 730 * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag 731 * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag 732 * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag 733 * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 734 * @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices) 735 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 736 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 737 * @retval The new state of FLASH_FLAG (SET or RESET). 738 */ 739 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \ 740 (READ_BIT(FLASH->ECCR, (__FLAG__)) != 0U) : \ 741 (READ_BIT(FLASH->SR, (__FLAG__)) != 0U)) 742 743 /** 744 * @brief Clear the FLASH's pending flags. 745 * @param __FLAG__ specifies the FLASH flags to clear. 746 * This parameter can be any combination of the following values: 747 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 748 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 749 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 750 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 751 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 752 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 753 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 754 * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag 755 * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag 756 * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag 757 * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag 758 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 759 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 760 * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags 761 * @retval None 762 */ 763 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ 764 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ 765 } while(0) 766 /** 767 * @} 768 */ 769 770 /* Include FLASH HAL Extended module */ 771 #include "stm32l4xx_hal_flash_ex.h" 772 #include "stm32l4xx_hal_flash_ramfunc.h" 773 774 /* Exported functions --------------------------------------------------------*/ 775 /** @addtogroup FLASH_Exported_Functions 776 * @{ 777 */ 778 779 /* Program operation functions ***********************************************/ 780 /** @addtogroup FLASH_Exported_Functions_Group1 781 * @{ 782 */ 783 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 784 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 785 /* FLASH IRQ handler method */ 786 void HAL_FLASH_IRQHandler(void); 787 /* Callbacks in non blocking modes */ 788 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 789 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 790 /** 791 * @} 792 */ 793 794 /* Peripheral Control functions **********************************************/ 795 /** @addtogroup FLASH_Exported_Functions_Group2 796 * @{ 797 */ 798 HAL_StatusTypeDef HAL_FLASH_Unlock(void); 799 HAL_StatusTypeDef HAL_FLASH_Lock(void); 800 /* Option bytes control */ 801 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 802 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 803 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); 804 /** 805 * @} 806 */ 807 808 /* Peripheral State functions ************************************************/ 809 /** @addtogroup FLASH_Exported_Functions_Group3 810 * @{ 811 */ 812 uint32_t HAL_FLASH_GetError(void); 813 /** 814 * @} 815 */ 816 817 /** 818 * @} 819 */ 820 821 /* Private variables ---------------------------------------------------------*/ 822 /** @addtogroup FLASH_Private_Variables FLASH Private Variables 823 * @{ 824 */ 825 extern FLASH_ProcessTypeDef pFlash; 826 /** 827 * @} 828 */ 829 830 /* Private function ----------------------------------------------------------*/ 831 /** @addtogroup FLASH_Private_Functions FLASH Private Functions 832 * @{ 833 */ 834 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); 835 /** 836 * @} 837 */ 838 839 /* Private constants --------------------------------------------------------*/ 840 /** @defgroup FLASH_Private_Constants FLASH Private Constants 841 * @{ 842 */ 843 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 844 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 845 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 846 #define FLASH_BANK_SIZE (FLASH_SIZE >> 1U) 847 #else 848 #define FLASH_BANK_SIZE (FLASH_SIZE) 849 #endif 850 851 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 852 #define FLASH_PAGE_SIZE ((uint32_t)0x1000) 853 #define FLASH_PAGE_SIZE_128_BITS ((uint32_t)0x2000) 854 #else 855 #define FLASH_PAGE_SIZE ((uint32_t)0x800) 856 #endif 857 858 #define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ 859 /** 860 * @} 861 */ 862 863 /* Private macros ------------------------------------------------------------*/ 864 /** @defgroup FLASH_Private_Macros FLASH Private Macros 865 * @{ 866 */ 867 868 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ 869 ((VALUE) == FLASH_TYPEERASE_MASSERASE)) 870 871 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 872 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 873 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 874 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ 875 ((BANK) == FLASH_BANK_2) || \ 876 ((BANK) == FLASH_BANK_BOTH)) 877 878 #define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ 879 ((BANK) == FLASH_BANK_2)) 880 #else 881 #define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1) 882 883 #define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1) 884 #endif 885 886 #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ 887 ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \ 888 ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST)) 889 890 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 891 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((ADDRESS) <= (FLASH_BASE+0x1FFFFFU))) 892 #else 893 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? \ 894 ((ADDRESS) <= (FLASH_BASE+0xFFFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? \ 895 ((ADDRESS) <= (FLASH_BASE+0x7FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? \ 896 ((ADDRESS) <= (FLASH_BASE+0x3FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? \ 897 ((ADDRESS) <= (FLASH_BASE+0x1FFFFU)) : ((ADDRESS) <= (FLASH_BASE+0xFFFFFU))))))) 898 #endif 899 900 #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU)) 901 902 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS))) 903 904 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 905 #define IS_FLASH_PAGE(PAGE) ((PAGE) < 256U) 906 #elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) 907 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? ((PAGE) < 256U) : \ 908 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 128U) : \ 909 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 64U) : \ 910 ((PAGE) < 256U))))) 911 #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 912 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 256U) : \ 913 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \ 914 ((PAGE) < 256U)))) 915 #else 916 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \ 917 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? ((PAGE) < 64U) : \ 918 ((PAGE) < 128U)))) 919 #endif 920 921 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP))) 922 923 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 924 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 925 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 926 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ 927 ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) 928 #else 929 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB)) 930 #endif 931 932 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ 933 ((LEVEL) == OB_RDP_LEVEL_1)/* ||\ 934 ((LEVEL) == OB_RDP_LEVEL_2)*/) 935 936 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 937 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFFFU) && ((TYPE) != 0U)) 938 #elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 939 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFFU) && ((TYPE) != 0U)) 940 #else 941 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7FU) && ((TYPE) != 0U) && (((TYPE)&0x0180U) == 0U)) 942 #endif 943 944 #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ 945 ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \ 946 ((LEVEL) == OB_BOR_LEVEL_4)) 947 948 #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) 949 950 #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) 951 952 #define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST)) 953 954 #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) 955 956 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) 957 958 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) 959 960 #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) 961 962 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 963 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 964 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 965 #define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE)) 966 967 #define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL)) 968 #endif 969 970 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 971 #define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS)) 972 #endif 973 974 #define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM)) 975 976 #define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE)) 977 978 #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) 979 980 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \ 981 defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ 982 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 983 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 984 #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) 985 986 #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET)) 987 #endif 988 989 #define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE)) 990 991 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 992 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ 993 ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ 994 ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ 995 ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ 996 ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ 997 ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ 998 ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ 999 ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) 1000 #else 1001 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ 1002 ((LATENCY) == FLASH_LATENCY_1) || \ 1003 ((LATENCY) == FLASH_LATENCY_2) || \ 1004 ((LATENCY) == FLASH_LATENCY_3) || \ 1005 ((LATENCY) == FLASH_LATENCY_4)) 1006 #endif 1007 /** 1008 * @} 1009 */ 1010 1011 /** 1012 * @} 1013 */ 1014 1015 /** 1016 * @} 1017 */ 1018 1019 /** 1020 * @} 1021 */ 1022 1023 #ifdef __cplusplus 1024 } 1025 #endif 1026 1027 #endif /* STM32L4xx_HAL_FLASH_H */ 1028 1029
