1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_dma2d.h 4 * @author MCD Application Team 5 * @brief Header file of DMA2D HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L4xx_HAL_DMA2D_H 21 #define STM32L4xx_HAL_DMA2D_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l4xx_hal_def.h" 29 30 /** @addtogroup STM32L4xx_HAL_Driver 31 * @{ 32 */ 33 34 #if defined (DMA2D) 35 36 /** @addtogroup DMA2D DMA2D 37 * @brief DMA2D HAL module driver 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types 43 * @{ 44 */ 45 #define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */ 46 47 /** 48 * @brief DMA2D CLUT Structure definition 49 */ 50 typedef struct 51 { 52 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ 53 54 uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. 55 This parameter can be one value of @ref DMA2D_CLUT_CM. */ 56 57 uint32_t Size; /*!< Configures the DMA2D CLUT size. 58 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ 59 } DMA2D_CLUTCfgTypeDef; 60 61 /** 62 * @brief DMA2D Init structure definition 63 */ 64 typedef struct 65 { 66 uint32_t Mode; /*!< Configures the DMA2D transfer mode. 67 This parameter can be one value of @ref DMA2D_Mode. */ 68 69 uint32_t ColorMode; /*!< Configures the color format of the output image. 70 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ 71 72 uint32_t OutputOffset; /*!< Specifies the Offset value. 73 This parameter must be a number between 74 Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 75 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter. 76 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ 77 78 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) 79 for the output pixel format converter. 80 This parameter can be one value of @ref DMA2D_RB_Swap. */ 81 82 83 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) 84 uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two). 85 This parameter can be one value of @ref DMA2D_Bytes_Swap. */ 86 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ 87 88 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) 89 uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset 90 for the foreground, background and output. 91 This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */ 92 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ 93 94 } DMA2D_InitTypeDef; 95 96 97 /** 98 * @brief DMA2D Layer structure definition 99 */ 100 typedef struct 101 { 102 uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. 103 This parameter must be a number between 104 Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 105 106 uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. 107 This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ 108 109 uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. 110 This parameter can be one value of @ref DMA2D_Alpha_Mode. */ 111 112 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value 113 in case of A8 or A4 color mode. 114 This parameter must be a number between Min_Data = 0x00 115 and Max_Data = 0xFF except for the color modes detailed below. 116 @note In case of A8 or A4 color mode (ARGB), 117 this parameter must be a number between 118 Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where 119 - InputAlpha[24:31] is the alpha value ALPHA[0:7] 120 - InputAlpha[16:23] is the red value RED[0:7] 121 - InputAlpha[8:15] is the green value GREEN[0:7] 122 - InputAlpha[0:7] is the blue value BLUE[0:7]. */ 123 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value. 124 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ 125 126 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). 127 This parameter can be one value of @ref DMA2D_RB_Swap. */ 128 129 130 } DMA2D_LayerCfgTypeDef; 131 132 /** 133 * @brief HAL DMA2D State structures definition 134 */ 135 typedef enum 136 { 137 HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ 138 HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 139 HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 140 HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 141 HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ 142 HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ 143 } HAL_DMA2D_StateTypeDef; 144 145 /** 146 * @brief DMA2D handle Structure definition 147 */ 148 typedef struct __DMA2D_HandleTypeDef 149 { 150 DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ 151 152 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ 153 154 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */ 155 156 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */ 157 158 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 159 void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */ 160 161 void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */ 162 163 void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */ 164 165 void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */ 166 167 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ 168 169 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ 170 171 HAL_LockTypeDef Lock; /*!< DMA2D lock. */ 172 173 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ 174 175 __IO uint32_t ErrorCode; /*!< DMA2D error code. */ 176 } DMA2D_HandleTypeDef; 177 178 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 179 /** 180 * @brief HAL DMA2D Callback pointer definition 181 */ 182 typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */ 183 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 184 /** 185 * @} 186 */ 187 188 /* Exported constants --------------------------------------------------------*/ 189 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants 190 * @{ 191 */ 192 193 /** @defgroup DMA2D_Error_Code DMA2D Error Code 194 * @{ 195 */ 196 #define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ 197 #define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ 198 #define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ 199 #define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ 200 #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 201 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 202 #define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */ 203 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ 204 205 /** 206 * @} 207 */ 208 209 /** @defgroup DMA2D_Mode DMA2D Mode 210 * @{ 211 */ 212 #define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ 213 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ 214 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ 215 #define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */ 216 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT) 217 #define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */ 218 #define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */ 219 #endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */ 220 /** 221 * @} 222 */ 223 224 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode 225 * @{ 226 */ 227 #define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ 228 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ 229 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ 230 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ 231 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ 232 /** 233 * @} 234 */ 235 236 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode 237 * @{ 238 */ 239 #define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ 240 #define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ 241 #define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ 242 #define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ 243 #define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ 244 #define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ 245 #define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ 246 #define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ 247 #define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ 248 #define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ 249 #define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ 250 /** 251 * @} 252 */ 253 254 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode 255 * @{ 256 */ 257 #define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 258 #define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ 259 #define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value 260 with original alpha channel value */ 261 /** 262 * @} 263 */ 264 265 /** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion 266 * @{ 267 */ 268 #define DMA2D_REGULAR_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 269 #define DMA2D_INVERTED_ALPHA 0x00000001U /*!< Invert the alpha channel value */ 270 /** 271 * @} 272 */ 273 274 /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap 275 * @{ 276 */ 277 #define DMA2D_RB_REGULAR 0x00000000U /*!< Select regular mode (RGB or ARGB) */ 278 #define DMA2D_RB_SWAP 0x00000001U /*!< Select swap mode (BGR or ABGR) */ 279 /** 280 * @} 281 */ 282 283 284 285 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) 286 /** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode 287 * @{ 288 */ 289 #define DMA2D_LOM_PIXELS 0x00000000U /*!< Line offsets expressed in pixels */ 290 #define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */ 291 /** 292 * @} 293 */ 294 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ 295 296 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) 297 /** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap 298 * @{ 299 */ 300 #define DMA2D_BYTES_REGULAR 0x00000000U /*!< Bytes in regular order in output FIFO */ 301 #define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */ 302 /** 303 * @} 304 */ 305 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ 306 307 308 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode 309 * @{ 310 */ 311 #define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ 312 #define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ 313 /** 314 * @} 315 */ 316 317 /** @defgroup DMA2D_Interrupts DMA2D Interrupts 318 * @{ 319 */ 320 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ 321 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ 322 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ 323 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ 324 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ 325 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ 326 /** 327 * @} 328 */ 329 330 /** @defgroup DMA2D_Flags DMA2D Flags 331 * @{ 332 */ 333 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ 334 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ 335 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ 336 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ 337 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ 338 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ 339 /** 340 * @} 341 */ 342 343 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 344 /** 345 * @brief HAL DMA2D common Callback ID enumeration definition 346 */ 347 typedef enum 348 { 349 HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */ 350 HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */ 351 HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */ 352 HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ 353 HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ 354 HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ 355 } HAL_DMA2D_CallbackIDTypeDef; 356 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 357 358 359 /** 360 * @} 361 */ 362 /* Exported macros ------------------------------------------------------------*/ 363 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros 364 * @{ 365 */ 366 367 /** @brief Reset DMA2D handle state 368 * @param __HANDLE__ specifies the DMA2D handle. 369 * @retval None 370 */ 371 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 372 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ 373 (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ 374 (__HANDLE__)->MspInitCallback = NULL; \ 375 (__HANDLE__)->MspDeInitCallback = NULL; \ 376 }while(0) 377 #else 378 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) 379 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 380 381 382 /** 383 * @brief Enable the DMA2D. 384 * @param __HANDLE__ DMA2D handle 385 * @retval None. 386 */ 387 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) 388 389 390 /* Interrupt & Flag management */ 391 /** 392 * @brief Get the DMA2D pending flags. 393 * @param __HANDLE__ DMA2D handle 394 * @param __FLAG__ flag to check. 395 * This parameter can be any combination of the following values: 396 * @arg DMA2D_FLAG_CE: Configuration error flag 397 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 398 * @arg DMA2D_FLAG_CAE: CLUT access error flag 399 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 400 * @arg DMA2D_FLAG_TC: Transfer complete flag 401 * @arg DMA2D_FLAG_TE: Transfer error flag 402 * @retval The state of FLAG. 403 */ 404 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 405 406 /** 407 * @brief Clear the DMA2D pending flags. 408 * @param __HANDLE__ DMA2D handle 409 * @param __FLAG__ specifies the flag to clear. 410 * This parameter can be any combination of the following values: 411 * @arg DMA2D_FLAG_CE: Configuration error flag 412 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 413 * @arg DMA2D_FLAG_CAE: CLUT access error flag 414 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 415 * @arg DMA2D_FLAG_TC: Transfer complete flag 416 * @arg DMA2D_FLAG_TE: Transfer error flag 417 * @retval None 418 */ 419 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) 420 421 /** 422 * @brief Enable the specified DMA2D interrupts. 423 * @param __HANDLE__ DMA2D handle 424 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. 425 * This parameter can be any combination of the following values: 426 * @arg DMA2D_IT_CE: Configuration error interrupt mask 427 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 428 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 429 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 430 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 431 * @arg DMA2D_IT_TE: Transfer error interrupt mask 432 * @retval None 433 */ 434 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) 435 436 /** 437 * @brief Disable the specified DMA2D interrupts. 438 * @param __HANDLE__ DMA2D handle 439 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. 440 * This parameter can be any combination of the following values: 441 * @arg DMA2D_IT_CE: Configuration error interrupt mask 442 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 443 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 444 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 445 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 446 * @arg DMA2D_IT_TE: Transfer error interrupt mask 447 * @retval None 448 */ 449 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) 450 451 /** 452 * @brief Check whether the specified DMA2D interrupt source is enabled or not. 453 * @param __HANDLE__ DMA2D handle 454 * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. 455 * This parameter can be one of the following values: 456 * @arg DMA2D_IT_CE: Configuration error interrupt mask 457 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 458 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 459 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 460 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 461 * @arg DMA2D_IT_TE: Transfer error interrupt mask 462 * @retval The state of INTERRUPT source. 463 */ 464 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) 465 466 /** 467 * @} 468 */ 469 470 /* Exported functions --------------------------------------------------------*/ 471 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions 472 * @{ 473 */ 474 475 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions 476 * @{ 477 */ 478 479 /* Initialization and de-initialization functions *******************************/ 480 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); 481 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d); 482 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d); 483 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d); 484 /* Callbacks Register/UnRegister functions ***********************************/ 485 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 486 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, 487 pDMA2D_CallbackTypeDef pCallback); 488 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); 489 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 490 491 /** 492 * @} 493 */ 494 495 496 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions 497 * @{ 498 */ 499 500 /* IO operation functions *******************************************************/ 501 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, 502 uint32_t Height); 503 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, 504 uint32_t DstAddress, uint32_t Width, uint32_t Height); 505 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, 506 uint32_t Height); 507 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, 508 uint32_t DstAddress, uint32_t Width, uint32_t Height); 509 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); 510 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); 511 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); 512 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 513 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, 514 uint32_t LayerIdx); 515 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, 516 uint32_t LayerIdx); 517 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 518 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 519 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 520 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 521 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 522 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); 523 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); 524 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); 525 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); 526 527 /** 528 * @} 529 */ 530 531 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions 532 * @{ 533 */ 534 535 /* Peripheral Control functions *************************************************/ 536 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 537 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 538 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); 539 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); 540 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); 541 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); 542 543 /** 544 * @} 545 */ 546 547 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions 548 * @{ 549 */ 550 551 /* Peripheral State functions ***************************************************/ 552 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); 553 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); 554 555 /** 556 * @} 557 */ 558 559 /** 560 * @} 561 */ 562 563 /* Private constants ---------------------------------------------------------*/ 564 565 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants 566 * @{ 567 */ 568 569 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark 570 * @{ 571 */ 572 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ 573 /** 574 * @} 575 */ 576 577 /** @defgroup DMA2D_Color_Value DMA2D Color Value 578 * @{ 579 */ 580 #define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ 581 /** 582 * @} 583 */ 584 585 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers 586 * @{ 587 */ 588 #define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ 589 /** 590 * @} 591 */ 592 593 /** @defgroup DMA2D_Layers DMA2D Layers 594 * @{ 595 */ 596 #define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */ 597 #define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */ 598 /** 599 * @} 600 */ 601 602 /** @defgroup DMA2D_Offset DMA2D Offset 603 * @{ 604 */ 605 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */ 606 /** 607 * @} 608 */ 609 610 /** @defgroup DMA2D_Size DMA2D Size 611 * @{ 612 */ 613 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */ 614 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */ 615 /** 616 * @} 617 */ 618 619 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size 620 * @{ 621 */ 622 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */ 623 /** 624 * @} 625 */ 626 627 /** 628 * @} 629 */ 630 631 632 /* Private macros ------------------------------------------------------------*/ 633 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros 634 * @{ 635 */ 636 #define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\ 637 || ((LAYER) == DMA2D_FOREGROUND_LAYER)) 638 639 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT) 640 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ 641 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \ 642 ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG)) 643 #else 644 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ 645 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) 646 #endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */ 647 648 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \ 649 ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ 650 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \ 651 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ 652 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) 653 654 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) 655 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) 656 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) 657 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) 658 659 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \ 660 ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ 661 ((INPUT_CM) == DMA2D_INPUT_RGB565) || \ 662 ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ 663 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \ 664 ((INPUT_CM) == DMA2D_INPUT_L8) || \ 665 ((INPUT_CM) == DMA2D_INPUT_AL44) || \ 666 ((INPUT_CM) == DMA2D_INPUT_AL88) || \ 667 ((INPUT_CM) == DMA2D_INPUT_L4) || \ 668 ((INPUT_CM) == DMA2D_INPUT_A8) || \ 669 ((INPUT_CM) == DMA2D_INPUT_A4)) 670 671 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ 672 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ 673 ((AlphaMode) == DMA2D_COMBINE_ALPHA)) 674 675 #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \ 676 ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA)) 677 678 #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ 679 ((RB_Swap) == DMA2D_RB_SWAP)) 680 681 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) 682 #define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \ 683 ((LOM) == DMA2D_LOM_BYTES)) 684 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ 685 686 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) 687 #define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \ 688 ((BYTES_SWAP) == DMA2D_BYTES_SWAP)) 689 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ 690 691 692 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) 693 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) 694 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) 695 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ 696 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ 697 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) 698 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ 699 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ 700 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) 701 /** 702 * @} 703 */ 704 705 /** 706 * @} 707 */ 708 709 #endif /* defined (DMA2D) */ 710 711 /** 712 * @} 713 */ 714 715 #ifdef __cplusplus 716 } 717 #endif 718 719 #endif /* STM32L4xx_HAL_DMA2D_H */ 720
