1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L4xx_HAL_DMA_H 21 #define STM32L4xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l4xx_hal_def.h" 29 30 /** @addtogroup STM32L4xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup DMA_Exported_Types DMA Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief DMA Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Request; /*!< Specifies the request selected for the specified channel. 49 This parameter can be a value of @ref DMA_request */ 50 51 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 52 from memory to memory or from peripheral to memory. 53 This parameter can be a value of @ref DMA_Data_transfer_direction */ 54 55 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 56 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 57 58 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 59 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 60 61 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 62 This parameter can be a value of @ref DMA_Peripheral_data_size */ 63 64 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 65 This parameter can be a value of @ref DMA_Memory_data_size */ 66 67 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 68 This parameter can be a value of @ref DMA_mode 69 @note The circular buffer mode cannot be used if the memory-to-memory 70 data transfer is configured on the selected Channel */ 71 72 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 73 This parameter can be a value of @ref DMA_Priority_level */ 74 } DMA_InitTypeDef; 75 76 /** 77 * @brief HAL DMA State structures definition 78 */ 79 typedef enum 80 { 81 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 82 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 83 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 84 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 85 }HAL_DMA_StateTypeDef; 86 87 /** 88 * @brief HAL DMA Error Code structure definition 89 */ 90 typedef enum 91 { 92 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 93 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 94 }HAL_DMA_LevelCompleteTypeDef; 95 96 97 /** 98 * @brief HAL DMA Callback ID structure definition 99 */ 100 typedef enum 101 { 102 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 103 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 104 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 105 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 106 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 107 }HAL_DMA_CallbackIDTypeDef; 108 109 /** 110 * @brief DMA handle Structure definition 111 */ 112 typedef struct __DMA_HandleTypeDef 113 { 114 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 115 116 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 117 118 HAL_LockTypeDef Lock; /*!< DMA locking object */ 119 120 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 121 122 void *Parent; /*!< Parent object state */ 123 124 void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 125 126 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 127 128 void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 129 130 void (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ 131 132 __IO uint32_t ErrorCode; /*!< DMA Error code */ 133 134 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 135 136 uint32_t ChannelIndex; /*!< DMA Channel Index */ 137 138 #if defined(DMAMUX1) 139 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ 140 141 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ 142 143 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ 144 145 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ 146 147 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ 148 149 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ 150 151 #endif /* DMAMUX1 */ 152 153 }DMA_HandleTypeDef; 154 /** 155 * @} 156 */ 157 158 /* Exported constants --------------------------------------------------------*/ 159 160 /** @defgroup DMA_Exported_Constants DMA Exported Constants 161 * @{ 162 */ 163 164 /** @defgroup DMA_Error_Code DMA Error Code 165 * @{ 166 */ 167 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 168 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 169 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ 170 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 171 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 172 #define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ 173 #define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ 174 175 /** 176 * @} 177 */ 178 179 /** @defgroup DMA_request DMA request 180 * @{ 181 */ 182 #if !defined (DMAMUX1) 183 184 #define DMA_REQUEST_0 0U 185 #define DMA_REQUEST_1 1U 186 #define DMA_REQUEST_2 2U 187 #define DMA_REQUEST_3 3U 188 #define DMA_REQUEST_4 4U 189 #define DMA_REQUEST_5 5U 190 #define DMA_REQUEST_6 6U 191 #define DMA_REQUEST_7 7U 192 193 #endif 194 195 #if defined(DMAMUX1) 196 197 #define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ 198 199 #define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ 200 #define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ 201 #define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ 202 #define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ 203 204 #define DMA_REQUEST_ADC1 5U /*!< DMAMUX1 ADC1 request */ 205 206 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) 207 208 #define DMA_REQUEST_ADC2 6U /*!< DMAMUX1 ADC1 request */ 209 210 #define DMA_REQUEST_DAC1_CH1 7U /*!< DMAMUX1 DAC1 CH1 request */ 211 #define DMA_REQUEST_DAC1_CH2 8U /*!< DMAMUX1 DAC1 CH2 request */ 212 213 #define DMA_REQUEST_TIM6_UP 9U /*!< DMAMUX1 TIM6 UP request */ 214 #define DMA_REQUEST_TIM7_UP 10U /*!< DMAMUX1 TIM7 UP request */ 215 216 #define DMA_REQUEST_SPI1_RX 11U /*!< DMAMUX1 SPI1 RX request */ 217 #define DMA_REQUEST_SPI1_TX 12U /*!< DMAMUX1 SPI1 TX request */ 218 #define DMA_REQUEST_SPI2_RX 13U /*!< DMAMUX1 SPI2 RX request */ 219 #define DMA_REQUEST_SPI2_TX 14U /*!< DMAMUX1 SPI2 TX request */ 220 #define DMA_REQUEST_SPI3_RX 15U /*!< DMAMUX1 SPI3 RX request */ 221 #define DMA_REQUEST_SPI3_TX 16U /*!< DMAMUX1 SPI3 TX request */ 222 223 #define DMA_REQUEST_I2C1_RX 17U /*!< DMAMUX1 I2C1 RX request */ 224 #define DMA_REQUEST_I2C1_TX 18U /*!< DMAMUX1 I2C1 TX request */ 225 #define DMA_REQUEST_I2C2_RX 19U /*!< DMAMUX1 I2C2 RX request */ 226 #define DMA_REQUEST_I2C2_TX 20U /*!< DMAMUX1 I2C2 TX request */ 227 #define DMA_REQUEST_I2C3_RX 21U /*!< DMAMUX1 I2C3 RX request */ 228 #define DMA_REQUEST_I2C3_TX 22U /*!< DMAMUX1 I2C3 TX request */ 229 #define DMA_REQUEST_I2C4_RX 23U /*!< DMAMUX1 I2C4 RX request */ 230 #define DMA_REQUEST_I2C4_TX 24U /*!< DMAMUX1 I2C4 TX request */ 231 232 #define DMA_REQUEST_USART1_RX 25U /*!< DMAMUX1 USART1 RX request */ 233 #define DMA_REQUEST_USART1_TX 26U /*!< DMAMUX1 USART1 TX request */ 234 #define DMA_REQUEST_USART2_RX 27U /*!< DMAMUX1 USART2 RX request */ 235 #define DMA_REQUEST_USART2_TX 28U /*!< DMAMUX1 USART2 TX request */ 236 #define DMA_REQUEST_USART3_RX 29U /*!< DMAMUX1 USART3 RX request */ 237 #define DMA_REQUEST_USART3_TX 30U /*!< DMAMUX1 USART3 TX request */ 238 239 #define DMA_REQUEST_UART4_RX 31U /*!< DMAMUX1 UART4 RX request */ 240 #define DMA_REQUEST_UART4_TX 32U /*!< DMAMUX1 UART4 TX request */ 241 #define DMA_REQUEST_UART5_RX 33U /*!< DMAMUX1 UART5 RX request */ 242 #define DMA_REQUEST_UART5_TX 34U /*!< DMAMUX1 UART5 TX request */ 243 244 #define DMA_REQUEST_LPUART1_RX 35U /*!< DMAMUX1 LP_UART1_RX request */ 245 #define DMA_REQUEST_LPUART1_TX 36U /*!< DMAMUX1 LP_UART1_RX request */ 246 247 #define DMA_REQUEST_SAI1_A 37U /*!< DMAMUX1 SAI1 A request */ 248 #define DMA_REQUEST_SAI1_B 38U /*!< DMAMUX1 SAI1 B request */ 249 #define DMA_REQUEST_SAI2_A 39U /*!< DMAMUX1 SAI2 A request */ 250 #define DMA_REQUEST_SAI2_B 40U /*!< DMAMUX1 SAI2 B request */ 251 252 #define DMA_REQUEST_OCTOSPI1 41U /*!< DMAMUX1 OCTOSPI1 request */ 253 #define DMA_REQUEST_OCTOSPI2 42U /*!< DMAMUX1 OCTOSPI2 request */ 254 255 #define DMA_REQUEST_TIM1_CH1 43U /*!< DMAMUX1 TIM1 CH1 request */ 256 #define DMA_REQUEST_TIM1_CH2 44U /*!< DMAMUX1 TIM1 CH2 request */ 257 #define DMA_REQUEST_TIM1_CH3 45U /*!< DMAMUX1 TIM1 CH3 request */ 258 #define DMA_REQUEST_TIM1_CH4 46U /*!< DMAMUX1 TIM1 CH4 request */ 259 #define DMA_REQUEST_TIM1_UP 47U /*!< DMAMUX1 TIM1 UP request */ 260 #define DMA_REQUEST_TIM1_TRIG 48U /*!< DMAMUX1 TIM1 TRIG request */ 261 #define DMA_REQUEST_TIM1_COM 49U /*!< DMAMUX1 TIM1 COM request */ 262 263 #define DMA_REQUEST_TIM8_CH1 50U /*!< DMAMUX1 TIM8 CH1 request */ 264 #define DMA_REQUEST_TIM8_CH2 51U /*!< DMAMUX1 TIM8 CH2 request */ 265 #define DMA_REQUEST_TIM8_CH3 52U /*!< DMAMUX1 TIM8 CH3 request */ 266 #define DMA_REQUEST_TIM8_CH4 53U /*!< DMAMUX1 TIM8 CH4 request */ 267 #define DMA_REQUEST_TIM8_UP 54U /*!< DMAMUX1 TIM8 UP request */ 268 #define DMA_REQUEST_TIM8_TRIG 55U /*!< DMAMUX1 TIM8 TRIG request */ 269 #define DMA_REQUEST_TIM8_COM 56U /*!< DMAMUX1 TIM8 COM request */ 270 271 #define DMA_REQUEST_TIM2_CH1 57U /*!< DMAMUX1 TIM2 CH1 request */ 272 #define DMA_REQUEST_TIM2_CH2 58U /*!< DMAMUX1 TIM2 CH2 request */ 273 #define DMA_REQUEST_TIM2_CH3 59U /*!< DMAMUX1 TIM2 CH3 request */ 274 #define DMA_REQUEST_TIM2_CH4 60U /*!< DMAMUX1 TIM2 CH4 request */ 275 #define DMA_REQUEST_TIM2_UP 61U /*!< DMAMUX1 TIM2 UP request */ 276 277 #define DMA_REQUEST_TIM3_CH1 62U /*!< DMAMUX1 TIM3 CH1 request */ 278 #define DMA_REQUEST_TIM3_CH2 63U /*!< DMAMUX1 TIM3 CH2 request */ 279 #define DMA_REQUEST_TIM3_CH3 64U /*!< DMAMUX1 TIM3 CH3 request */ 280 #define DMA_REQUEST_TIM3_CH4 65U /*!< DMAMUX1 TIM3 CH4 request */ 281 #define DMA_REQUEST_TIM3_UP 66U /*!< DMAMUX1 TIM3 UP request */ 282 #define DMA_REQUEST_TIM3_TRIG 67U /*!< DMAMUX1 TIM3 TRIG request */ 283 284 #define DMA_REQUEST_TIM4_CH1 68U /*!< DMAMUX1 TIM4 CH1 request */ 285 #define DMA_REQUEST_TIM4_CH2 69U /*!< DMAMUX1 TIM4 CH2 request */ 286 #define DMA_REQUEST_TIM4_CH3 70U /*!< DMAMUX1 TIM4 CH3 request */ 287 #define DMA_REQUEST_TIM4_CH4 71U /*!< DMAMUX1 TIM4 CH4 request */ 288 #define DMA_REQUEST_TIM4_UP 72U /*!< DMAMUX1 TIM4 UP request */ 289 290 #define DMA_REQUEST_TIM5_CH1 73U /*!< DMAMUX1 TIM5 CH1 request */ 291 #define DMA_REQUEST_TIM5_CH2 74U /*!< DMAMUX1 TIM5 CH2 request */ 292 #define DMA_REQUEST_TIM5_CH3 75U /*!< DMAMUX1 TIM5 CH3 request */ 293 #define DMA_REQUEST_TIM5_CH4 76U /*!< DMAMUX1 TIM5 CH4 request */ 294 #define DMA_REQUEST_TIM5_UP 77U /*!< DMAMUX1 TIM5 UP request */ 295 #define DMA_REQUEST_TIM5_TRIG 78U /*!< DMAMUX1 TIM5 TRIG request */ 296 297 #define DMA_REQUEST_TIM15_CH1 79U /*!< DMAMUX1 TIM15 CH1 request */ 298 #define DMA_REQUEST_TIM15_UP 80U /*!< DMAMUX1 TIM15 UP request */ 299 #define DMA_REQUEST_TIM15_TRIG 81U /*!< DMAMUX1 TIM15 TRIG request */ 300 #define DMA_REQUEST_TIM15_COM 82U /*!< DMAMUX1 TIM15 COM request */ 301 302 #define DMA_REQUEST_TIM16_CH1 83U /*!< DMAMUX1 TIM16 CH1 request */ 303 #define DMA_REQUEST_TIM16_UP 84U /*!< DMAMUX1 TIM16 UP request */ 304 #define DMA_REQUEST_TIM17_CH1 85U /*!< DMAMUX1 TIM17 CH1 request */ 305 #define DMA_REQUEST_TIM17_UP 86U /*!< DMAMUX1 TIM17 UP request */ 306 307 #define DMA_REQUEST_DFSDM1_FLT0 87U /*!< DMAMUX1 DFSDM1 Filter0 request */ 308 #define DMA_REQUEST_DFSDM1_FLT1 88U /*!< DMAMUX1 DFSDM1 Filter1 request */ 309 310 #define DMA_REQUEST_DCMI 91U /*!< DMAMUX1 DCMI request */ 311 #define DMA_REQUEST_DCMI_PSSI 91U /*!< DMAMUX1 DCMI/PSSI request */ 312 313 #define DMA_REQUEST_AES_IN 92U /*!< DMAMUX1 AES IN request */ 314 #define DMA_REQUEST_AES_OUT 93U /*!< DMAMUX1 AES OUT request */ 315 316 #define DMA_REQUEST_HASH_IN 94U /*!< DMAMUX1 HASH IN request */ 317 318 #else 319 320 #define DMA_REQUEST_DAC1_CH1 6U /*!< DMAMUX1 DAC1 CH1 request */ 321 #define DMA_REQUEST_DAC1_CH2 7U /*!< DMAMUX1 DAC1 CH2 request */ 322 323 #define DMA_REQUEST_TIM6_UP 8U /*!< DMAMUX1 TIM6 UP request */ 324 #define DMA_REQUEST_TIM7_UP 9U /*!< DMAMUX1 TIM7 UP request */ 325 326 #define DMA_REQUEST_SPI1_RX 10U /*!< DMAMUX1 SPI1 RX request */ 327 #define DMA_REQUEST_SPI1_TX 11U /*!< DMAMUX1 SPI1 TX request */ 328 #define DMA_REQUEST_SPI2_RX 12U /*!< DMAMUX1 SPI2 RX request */ 329 #define DMA_REQUEST_SPI2_TX 13U /*!< DMAMUX1 SPI2 TX request */ 330 #define DMA_REQUEST_SPI3_RX 14U /*!< DMAMUX1 SPI3 RX request */ 331 #define DMA_REQUEST_SPI3_TX 15U /*!< DMAMUX1 SPI3 TX request */ 332 333 #define DMA_REQUEST_I2C1_RX 16U /*!< DMAMUX1 I2C1 RX request */ 334 #define DMA_REQUEST_I2C1_TX 17U /*!< DMAMUX1 I2C1 TX request */ 335 #define DMA_REQUEST_I2C2_RX 18U /*!< DMAMUX1 I2C2 RX request */ 336 #define DMA_REQUEST_I2C2_TX 19U /*!< DMAMUX1 I2C2 TX request */ 337 #define DMA_REQUEST_I2C3_RX 20U /*!< DMAMUX1 I2C3 RX request */ 338 #define DMA_REQUEST_I2C3_TX 21U /*!< DMAMUX1 I2C3 TX request */ 339 #define DMA_REQUEST_I2C4_RX 22U /*!< DMAMUX1 I2C4 RX request */ 340 #define DMA_REQUEST_I2C4_TX 23U /*!< DMAMUX1 I2C4 TX request */ 341 342 #define DMA_REQUEST_USART1_RX 24U /*!< DMAMUX1 USART1 RX request */ 343 #define DMA_REQUEST_USART1_TX 25U /*!< DMAMUX1 USART1 TX request */ 344 #define DMA_REQUEST_USART2_RX 26U /*!< DMAMUX1 USART2 RX request */ 345 #define DMA_REQUEST_USART2_TX 27U /*!< DMAMUX1 USART2 TX request */ 346 #define DMA_REQUEST_USART3_RX 28U /*!< DMAMUX1 USART3 RX request */ 347 #define DMA_REQUEST_USART3_TX 29U /*!< DMAMUX1 USART3 TX request */ 348 349 #define DMA_REQUEST_UART4_RX 30U /*!< DMAMUX1 UART4 RX request */ 350 #define DMA_REQUEST_UART4_TX 31U /*!< DMAMUX1 UART4 TX request */ 351 #define DMA_REQUEST_UART5_RX 32U /*!< DMAMUX1 UART5 RX request */ 352 #define DMA_REQUEST_UART5_TX 33U /*!< DMAMUX1 UART5 TX request */ 353 354 #define DMA_REQUEST_LPUART1_RX 34U /*!< DMAMUX1 LP_UART1_RX request */ 355 #define DMA_REQUEST_LPUART1_TX 35U /*!< DMAMUX1 LP_UART1_RX request */ 356 357 #define DMA_REQUEST_SAI1_A 36U /*!< DMAMUX1 SAI1 A request */ 358 #define DMA_REQUEST_SAI1_B 37U /*!< DMAMUX1 SAI1 B request */ 359 #define DMA_REQUEST_SAI2_A 38U /*!< DMAMUX1 SAI2 A request */ 360 #define DMA_REQUEST_SAI2_B 39U /*!< DMAMUX1 SAI2 B request */ 361 362 #define DMA_REQUEST_OCTOSPI1 40U /*!< DMAMUX1 OCTOSPI1 request */ 363 #define DMA_REQUEST_OCTOSPI2 41U /*!< DMAMUX1 OCTOSPI2 request */ 364 365 #define DMA_REQUEST_TIM1_CH1 42U /*!< DMAMUX1 TIM1 CH1 request */ 366 #define DMA_REQUEST_TIM1_CH2 43U /*!< DMAMUX1 TIM1 CH2 request */ 367 #define DMA_REQUEST_TIM1_CH3 44U /*!< DMAMUX1 TIM1 CH3 request */ 368 #define DMA_REQUEST_TIM1_CH4 45U /*!< DMAMUX1 TIM1 CH4 request */ 369 #define DMA_REQUEST_TIM1_UP 46U /*!< DMAMUX1 TIM1 UP request */ 370 #define DMA_REQUEST_TIM1_TRIG 47U /*!< DMAMUX1 TIM1 TRIG request */ 371 #define DMA_REQUEST_TIM1_COM 48U /*!< DMAMUX1 TIM1 COM request */ 372 373 #define DMA_REQUEST_TIM8_CH1 49U /*!< DMAMUX1 TIM8 CH1 request */ 374 #define DMA_REQUEST_TIM8_CH2 50U /*!< DMAMUX1 TIM8 CH2 request */ 375 #define DMA_REQUEST_TIM8_CH3 51U /*!< DMAMUX1 TIM8 CH3 request */ 376 #define DMA_REQUEST_TIM8_CH4 52U /*!< DMAMUX1 TIM8 CH4 request */ 377 #define DMA_REQUEST_TIM8_UP 53U /*!< DMAMUX1 TIM8 UP request */ 378 #define DMA_REQUEST_TIM8_TRIG 54U /*!< DMAMUX1 TIM8 TRIG request */ 379 #define DMA_REQUEST_TIM8_COM 55U /*!< DMAMUX1 TIM8 COM request */ 380 381 #define DMA_REQUEST_TIM2_CH1 56U /*!< DMAMUX1 TIM2 CH1 request */ 382 #define DMA_REQUEST_TIM2_CH2 57U /*!< DMAMUX1 TIM2 CH2 request */ 383 #define DMA_REQUEST_TIM2_CH3 58U /*!< DMAMUX1 TIM2 CH3 request */ 384 #define DMA_REQUEST_TIM2_CH4 59U /*!< DMAMUX1 TIM2 CH4 request */ 385 #define DMA_REQUEST_TIM2_UP 60U /*!< DMAMUX1 TIM2 UP request */ 386 387 #define DMA_REQUEST_TIM3_CH1 61U /*!< DMAMUX1 TIM3 CH1 request */ 388 #define DMA_REQUEST_TIM3_CH2 62U /*!< DMAMUX1 TIM3 CH2 request */ 389 #define DMA_REQUEST_TIM3_CH3 63U /*!< DMAMUX1 TIM3 CH3 request */ 390 #define DMA_REQUEST_TIM3_CH4 64U /*!< DMAMUX1 TIM3 CH4 request */ 391 #define DMA_REQUEST_TIM3_UP 65U /*!< DMAMUX1 TIM3 UP request */ 392 #define DMA_REQUEST_TIM3_TRIG 66U /*!< DMAMUX1 TIM3 TRIG request */ 393 394 #define DMA_REQUEST_TIM4_CH1 67U /*!< DMAMUX1 TIM4 CH1 request */ 395 #define DMA_REQUEST_TIM4_CH2 68U /*!< DMAMUX1 TIM4 CH2 request */ 396 #define DMA_REQUEST_TIM4_CH3 69U /*!< DMAMUX1 TIM4 CH3 request */ 397 #define DMA_REQUEST_TIM4_CH4 70U /*!< DMAMUX1 TIM4 CH4 request */ 398 #define DMA_REQUEST_TIM4_UP 71U /*!< DMAMUX1 TIM4 UP request */ 399 400 #define DMA_REQUEST_TIM5_CH1 72U /*!< DMAMUX1 TIM5 CH1 request */ 401 #define DMA_REQUEST_TIM5_CH2 73U /*!< DMAMUX1 TIM5 CH2 request */ 402 #define DMA_REQUEST_TIM5_CH3 74U /*!< DMAMUX1 TIM5 CH3 request */ 403 #define DMA_REQUEST_TIM5_CH4 75U /*!< DMAMUX1 TIM5 CH4 request */ 404 #define DMA_REQUEST_TIM5_UP 76U /*!< DMAMUX1 TIM5 UP request */ 405 #define DMA_REQUEST_TIM5_TRIG 77U /*!< DMAMUX1 TIM5 TRIG request */ 406 407 #define DMA_REQUEST_TIM15_CH1 78U /*!< DMAMUX1 TIM15 CH1 request */ 408 #define DMA_REQUEST_TIM15_UP 79U /*!< DMAMUX1 TIM15 UP request */ 409 #define DMA_REQUEST_TIM15_TRIG 80U /*!< DMAMUX1 TIM15 TRIG request */ 410 #define DMA_REQUEST_TIM15_COM 81U /*!< DMAMUX1 TIM15 COM request */ 411 412 #define DMA_REQUEST_TIM16_CH1 82U /*!< DMAMUX1 TIM16 CH1 request */ 413 #define DMA_REQUEST_TIM16_UP 83U /*!< DMAMUX1 TIM16 UP request */ 414 #define DMA_REQUEST_TIM17_CH1 84U /*!< DMAMUX1 TIM17 CH1 request */ 415 #define DMA_REQUEST_TIM17_UP 85U /*!< DMAMUX1 TIM17 UP request */ 416 417 #define DMA_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX1 DFSDM1 Filter0 request */ 418 #define DMA_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX1 DFSDM1 Filter1 request */ 419 #define DMA_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX1 DFSDM1 Filter2 request */ 420 #define DMA_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX1 DFSDM1 Filter3 request */ 421 422 #define DMA_REQUEST_DCMI 90U /*!< DMAMUX1 DCMI request */ 423 424 #define DMA_REQUEST_AES_IN 91U /*!< DMAMUX1 AES IN request */ 425 #define DMA_REQUEST_AES_OUT 92U /*!< DMAMUX1 AES OUT request */ 426 427 #define DMA_REQUEST_HASH_IN 93U /*!< DMAMUX1 HASH IN request */ 428 #endif /* STM32L4P5xx || STM32L4Q5xx */ 429 430 #endif /* DMAMUX1 */ 431 432 /** 433 * @} 434 */ 435 436 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 437 * @{ 438 */ 439 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 440 #define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ 441 #define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ 442 /** 443 * @} 444 */ 445 446 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 447 * @{ 448 */ 449 #define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ 450 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ 451 /** 452 * @} 453 */ 454 455 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 456 * @{ 457 */ 458 #define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ 459 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ 460 /** 461 * @} 462 */ 463 464 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 465 * @{ 466 */ 467 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 468 #define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 469 #define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 470 /** 471 * @} 472 */ 473 474 /** @defgroup DMA_Memory_data_size DMA Memory data size 475 * @{ 476 */ 477 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 478 #define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 479 #define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ 480 /** 481 * @} 482 */ 483 484 /** @defgroup DMA_mode DMA mode 485 * @{ 486 */ 487 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 488 #define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */ 489 /** 490 * @} 491 */ 492 493 /** @defgroup DMA_Priority_level DMA Priority level 494 * @{ 495 */ 496 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 497 #define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ 498 #define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ 499 #define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */ 500 /** 501 * @} 502 */ 503 504 505 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 506 * @{ 507 */ 508 #define DMA_IT_TC DMA_CCR_TCIE 509 #define DMA_IT_HT DMA_CCR_HTIE 510 #define DMA_IT_TE DMA_CCR_TEIE 511 /** 512 * @} 513 */ 514 515 /** @defgroup DMA_flag_definitions DMA flag definitions 516 * @{ 517 */ 518 #define DMA_FLAG_GL1 DMA_ISR_GIF1 519 #define DMA_FLAG_TC1 DMA_ISR_TCIF1 520 #define DMA_FLAG_HT1 DMA_ISR_HTIF1 521 #define DMA_FLAG_TE1 DMA_ISR_TEIF1 522 #define DMA_FLAG_GL2 DMA_ISR_GIF2 523 #define DMA_FLAG_TC2 DMA_ISR_TCIF2 524 #define DMA_FLAG_HT2 DMA_ISR_HTIF2 525 #define DMA_FLAG_TE2 DMA_ISR_TEIF2 526 #define DMA_FLAG_GL3 DMA_ISR_GIF3 527 #define DMA_FLAG_TC3 DMA_ISR_TCIF3 528 #define DMA_FLAG_HT3 DMA_ISR_HTIF3 529 #define DMA_FLAG_TE3 DMA_ISR_TEIF3 530 #define DMA_FLAG_GL4 DMA_ISR_GIF4 531 #define DMA_FLAG_TC4 DMA_ISR_TCIF4 532 #define DMA_FLAG_HT4 DMA_ISR_HTIF4 533 #define DMA_FLAG_TE4 DMA_ISR_TEIF4 534 #define DMA_FLAG_GL5 DMA_ISR_GIF5 535 #define DMA_FLAG_TC5 DMA_ISR_TCIF5 536 #define DMA_FLAG_HT5 DMA_ISR_HTIF5 537 #define DMA_FLAG_TE5 DMA_ISR_TEIF5 538 #define DMA_FLAG_GL6 DMA_ISR_GIF6 539 #define DMA_FLAG_TC6 DMA_ISR_TCIF6 540 #define DMA_FLAG_HT6 DMA_ISR_HTIF6 541 #define DMA_FLAG_TE6 DMA_ISR_TEIF6 542 #define DMA_FLAG_GL7 DMA_ISR_GIF7 543 #define DMA_FLAG_TC7 DMA_ISR_TCIF7 544 #define DMA_FLAG_HT7 DMA_ISR_HTIF7 545 #define DMA_FLAG_TE7 DMA_ISR_TEIF7 546 /** 547 * @} 548 */ 549 550 /** 551 * @} 552 */ 553 554 /* Exported macros -----------------------------------------------------------*/ 555 /** @defgroup DMA_Exported_Macros DMA Exported Macros 556 * @{ 557 */ 558 559 /** @brief Reset DMA handle state. 560 * @param __HANDLE__ DMA handle 561 * @retval None 562 */ 563 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 564 565 /** 566 * @brief Enable the specified DMA Channel. 567 * @param __HANDLE__ DMA handle 568 * @retval None 569 */ 570 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 571 572 /** 573 * @brief Disable the specified DMA Channel. 574 * @param __HANDLE__ DMA handle 575 * @retval None 576 */ 577 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 578 579 580 /* Interrupt & Flag management */ 581 582 /** 583 * @brief Return the current DMA Channel transfer complete flag. 584 * @param __HANDLE__ DMA handle 585 * @retval The specified transfer complete flag index. 586 */ 587 588 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 589 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 590 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ 591 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 592 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ 593 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 594 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ 595 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 596 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ 597 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 598 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ 599 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 600 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ 601 DMA_FLAG_TC7) 602 603 /** 604 * @brief Return the current DMA Channel half transfer complete flag. 605 * @param __HANDLE__ DMA handle 606 * @retval The specified half transfer complete flag index. 607 */ 608 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 609 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 610 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ 611 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 612 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ 613 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 614 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ 615 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 616 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ 617 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 618 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ 619 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 620 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ 621 DMA_FLAG_HT7) 622 623 /** 624 * @brief Return the current DMA Channel transfer error flag. 625 * @param __HANDLE__ DMA handle 626 * @retval The specified transfer error flag index. 627 */ 628 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 629 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 630 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ 631 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 632 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ 633 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 634 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ 635 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 636 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ 637 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 638 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ 639 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 640 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ 641 DMA_FLAG_TE7) 642 643 /** 644 * @brief Return the current DMA Channel Global interrupt flag. 645 * @param __HANDLE__ DMA handle 646 * @retval The specified transfer error flag index. 647 */ 648 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 649 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 650 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ 651 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 652 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ 653 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 654 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ 655 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 656 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ 657 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ 658 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ 659 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ 660 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\ 661 DMA_ISR_GIF7) 662 663 /** 664 * @brief Get the DMA Channel pending flags. 665 * @param __HANDLE__ DMA handle 666 * @param __FLAG__ Get the specified flag. 667 * This parameter can be any combination of the following values: 668 * @arg DMA_FLAG_TCx: Transfer complete flag 669 * @arg DMA_FLAG_HTx: Half transfer complete flag 670 * @arg DMA_FLAG_TEx: Transfer error flag 671 * @arg DMA_FLAG_GLx: Global interrupt flag 672 * Where x can be from 1 to 7 to select the DMA Channel x flag. 673 * @retval The state of FLAG (SET or RESET). 674 */ 675 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 676 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) 677 678 /** 679 * @brief Clear the DMA Channel pending flags. 680 * @param __HANDLE__ DMA handle 681 * @param __FLAG__ specifies the flag to clear. 682 * This parameter can be any combination of the following values: 683 * @arg DMA_FLAG_TCx: Transfer complete flag 684 * @arg DMA_FLAG_HTx: Half transfer complete flag 685 * @arg DMA_FLAG_TEx: Transfer error flag 686 * @arg DMA_FLAG_GLx: Global interrupt flag 687 * Where x can be from 1 to 7 to select the DMA Channel x flag. 688 * @retval None 689 */ 690 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 691 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) 692 693 /** 694 * @brief Enable the specified DMA Channel interrupts. 695 * @param __HANDLE__ DMA handle 696 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 697 * This parameter can be any combination of the following values: 698 * @arg DMA_IT_TC: Transfer complete interrupt mask 699 * @arg DMA_IT_HT: Half transfer complete interrupt mask 700 * @arg DMA_IT_TE: Transfer error interrupt mask 701 * @retval None 702 */ 703 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 704 705 /** 706 * @brief Disable the specified DMA Channel interrupts. 707 * @param __HANDLE__ DMA handle 708 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 709 * This parameter can be any combination of the following values: 710 * @arg DMA_IT_TC: Transfer complete interrupt mask 711 * @arg DMA_IT_HT: Half transfer complete interrupt mask 712 * @arg DMA_IT_TE: Transfer error interrupt mask 713 * @retval None 714 */ 715 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 716 717 /** 718 * @brief Check whether the specified DMA Channel interrupt is enabled or not. 719 * @param __HANDLE__ DMA handle 720 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 721 * This parameter can be one of the following values: 722 * @arg DMA_IT_TC: Transfer complete interrupt mask 723 * @arg DMA_IT_HT: Half transfer complete interrupt mask 724 * @arg DMA_IT_TE: Transfer error interrupt mask 725 * @retval The state of DMA_IT (SET or RESET). 726 */ 727 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 728 729 /** 730 * @brief Return the number of remaining data units in the current DMA Channel transfer. 731 * @param __HANDLE__ DMA handle 732 * @retval The number of remaining data units in the current DMA Channel transfer. 733 */ 734 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 735 736 /** 737 * @} 738 */ 739 740 #if defined(DMAMUX1) 741 /* Include DMA HAL Extension module */ 742 #include "stm32l4xx_hal_dma_ex.h" 743 #endif /* DMAMUX1 */ 744 745 /* Exported functions --------------------------------------------------------*/ 746 747 /** @addtogroup DMA_Exported_Functions 748 * @{ 749 */ 750 751 /** @addtogroup DMA_Exported_Functions_Group1 752 * @{ 753 */ 754 /* Initialization and de-initialization functions *****************************/ 755 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 756 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); 757 /** 758 * @} 759 */ 760 761 /** @addtogroup DMA_Exported_Functions_Group2 762 * @{ 763 */ 764 /* IO operation functions *****************************************************/ 765 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 766 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 767 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 768 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 769 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 770 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 771 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); 772 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 773 774 /** 775 * @} 776 */ 777 778 /** @addtogroup DMA_Exported_Functions_Group3 779 * @{ 780 */ 781 /* Peripheral State and Error functions ***************************************/ 782 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 783 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 784 /** 785 * @} 786 */ 787 788 /** 789 * @} 790 */ 791 792 /* Private macros ------------------------------------------------------------*/ 793 /** @defgroup DMA_Private_Macros DMA Private Macros 794 * @{ 795 */ 796 797 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 798 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 799 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 800 801 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) 802 803 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 804 ((STATE) == DMA_PINC_DISABLE)) 805 806 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 807 ((STATE) == DMA_MINC_DISABLE)) 808 809 #if !defined (DMAMUX1) 810 811 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ 812 ((REQUEST) == DMA_REQUEST_1) || \ 813 ((REQUEST) == DMA_REQUEST_2) || \ 814 ((REQUEST) == DMA_REQUEST_3) || \ 815 ((REQUEST) == DMA_REQUEST_4) || \ 816 ((REQUEST) == DMA_REQUEST_5) || \ 817 ((REQUEST) == DMA_REQUEST_6) || \ 818 ((REQUEST) == DMA_REQUEST_7)) 819 #endif 820 821 #if defined(DMAMUX1) 822 823 #define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_HASH_IN) 824 825 #endif /* DMAMUX1 */ 826 827 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 828 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 829 ((SIZE) == DMA_PDATAALIGN_WORD)) 830 831 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 832 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 833 ((SIZE) == DMA_MDATAALIGN_WORD )) 834 835 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 836 ((MODE) == DMA_CIRCULAR)) 837 838 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 839 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 840 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 841 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 842 843 /** 844 * @} 845 */ 846 847 /* Private functions ---------------------------------------------------------*/ 848 849 /** 850 * @} 851 */ 852 853 /** 854 * @} 855 */ 856 857 #ifdef __cplusplus 858 } 859 #endif 860 861 #endif /* STM32L4xx_HAL_DMA_H */ 862
