1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_dfsdm.h 4 * @author MCD Application Team 5 * @brief Header file of DFSDM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L4xx_HAL_DFSDM_H 21 #define STM32L4xx_HAL_DFSDM_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ 28 defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ 29 defined(STM32L496xx) || defined(STM32L4A6xx) || \ 30 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 31 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 32 33 /* Includes ------------------------------------------------------------------*/ 34 #include "stm32l4xx_hal_def.h" 35 36 /** @addtogroup STM32L4xx_HAL_Driver 37 * @{ 38 */ 39 40 /** @addtogroup DFSDM 41 * @{ 42 */ 43 44 /* Exported types ------------------------------------------------------------*/ 45 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types 46 * @{ 47 */ 48 49 /** 50 * @brief HAL DFSDM Channel states definition 51 */ 52 typedef enum 53 { 54 HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */ 55 HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */ 56 HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */ 57 } HAL_DFSDM_Channel_StateTypeDef; 58 59 /** 60 * @brief DFSDM channel output clock structure definition 61 */ 62 typedef struct 63 { 64 FunctionalState Activation; /*!< Output clock enable/disable */ 65 uint32_t Selection; /*!< Output clock is system clock or audio clock. 66 This parameter can be a value of @ref DFSDM_Channel_OuputClock */ 67 uint32_t Divider; /*!< Output clock divider. 68 This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ 69 } DFSDM_Channel_OutputClockTypeDef; 70 71 /** 72 * @brief DFSDM channel input structure definition 73 */ 74 typedef struct 75 { 76 uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output. 77 ADC output is available only on STM32L451xx, STM32L452xx, STM32L462xx, 78 STM32L496xx, STM32L4A6xx, STM32L4R5xx, STM32L4R7xx, STM32L4R9xx, 79 STM32L4S5xx, STM32L4S7xx, STM32L4S9xx, STM32L4P5xx and STM32L4Q5xx products. 80 This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ 81 uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. 82 This parameter can be a value of @ref DFSDM_Channel_DataPacking */ 83 uint32_t Pins; /*!< Input pins are taken from same or following channel. 84 This parameter can be a value of @ref DFSDM_Channel_InputPins */ 85 } DFSDM_Channel_InputTypeDef; 86 87 /** 88 * @brief DFSDM channel serial interface structure definition 89 */ 90 typedef struct 91 { 92 uint32_t Type; /*!< SPI or Manchester modes. 93 This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */ 94 uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point). 95 This parameter can be a value of @ref DFSDM_Channel_SpiClock */ 96 } DFSDM_Channel_SerialInterfaceTypeDef; 97 98 /** 99 * @brief DFSDM channel analog watchdog structure definition 100 */ 101 typedef struct 102 { 103 uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. 104 This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */ 105 uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio. 106 This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ 107 } DFSDM_Channel_AwdTypeDef; 108 109 /** 110 * @brief DFSDM channel init structure definition 111 */ 112 typedef struct 113 { 114 DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ 115 DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */ 116 DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */ 117 DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */ 118 int32_t Offset; /*!< DFSDM channel offset. 119 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 120 uint32_t RightBitShift; /*!< DFSDM channel right bit shift. 121 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 122 } DFSDM_Channel_InitTypeDef; 123 124 /** 125 * @brief DFSDM channel handle structure definition 126 */ 127 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 128 typedef struct __DFSDM_Channel_HandleTypeDef 129 #else 130 typedef struct 131 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ 132 { 133 DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ 134 DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ 135 HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ 136 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 137 void (*CkabCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */ 138 void (*ScdCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */ 139 void (*MspInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */ 140 void (*MspDeInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */ 141 #endif 142 } DFSDM_Channel_HandleTypeDef; 143 144 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 145 /** 146 * @brief DFSDM channel callback ID enumeration definition 147 */ 148 typedef enum 149 { 150 HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U, /*!< DFSDM channel clock absence detection callback ID */ 151 HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U, /*!< DFSDM channel short circuit detection callback ID */ 152 HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U, /*!< DFSDM channel MSP init callback ID */ 153 HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U /*!< DFSDM channel MSP de-init callback ID */ 154 } HAL_DFSDM_Channel_CallbackIDTypeDef; 155 156 /** 157 * @brief DFSDM channel callback pointer definition 158 */ 159 typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 160 #endif 161 162 /** 163 * @brief HAL DFSDM Filter states definition 164 */ 165 typedef enum 166 { 167 HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */ 168 HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */ 169 HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */ 170 HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */ 171 HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */ 172 HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */ 173 } HAL_DFSDM_Filter_StateTypeDef; 174 175 /** 176 * @brief DFSDM filter regular conversion parameters structure definition 177 */ 178 typedef struct 179 { 180 uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. 181 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 182 FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */ 183 FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ 184 } DFSDM_Filter_RegularParamTypeDef; 185 186 /** 187 * @brief DFSDM filter injected conversion parameters structure definition 188 */ 189 typedef struct 190 { 191 uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. 192 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 193 FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */ 194 FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */ 195 uint32_t ExtTrigger; /*!< External trigger. 196 This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */ 197 uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both. 198 This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ 199 } DFSDM_Filter_InjectedParamTypeDef; 200 201 /** 202 * @brief DFSDM filter parameters structure definition 203 */ 204 typedef struct 205 { 206 uint32_t SincOrder; /*!< Sinc filter order. 207 This parameter can be a value of @ref DFSDM_Filter_SincOrder */ 208 uint32_t Oversampling; /*!< Filter oversampling ratio. 209 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ 210 uint32_t IntOversampling; /*!< Integrator oversampling ratio. 211 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ 212 } DFSDM_Filter_FilterParamTypeDef; 213 214 /** 215 * @brief DFSDM filter init structure definition 216 */ 217 typedef struct 218 { 219 DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ 220 DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */ 221 DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ 222 } DFSDM_Filter_InitTypeDef; 223 224 /** 225 * @brief DFSDM filter handle structure definition 226 */ 227 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 228 typedef struct __DFSDM_Filter_HandleTypeDef 229 #else 230 typedef struct 231 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ 232 { 233 DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ 234 DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ 235 DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */ 236 DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */ 237 uint32_t RegularContMode; /*!< Regular conversion continuous mode */ 238 uint32_t RegularTrigger; /*!< Trigger used for regular conversion */ 239 uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */ 240 uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */ 241 FunctionalState InjectedScanMode; /*!< Injected scanning mode */ 242 uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ 243 uint32_t InjConvRemaining; /*!< Injected conversions remaining */ 244 HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ 245 uint32_t ErrorCode; /*!< DFSDM filter error code */ 246 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 247 void (*AwdCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 248 uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */ 249 void (*RegConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */ 250 void (*RegConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half regular conversion complete callback */ 251 void (*InjConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter injected conversion complete callback */ 252 void (*InjConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half injected conversion complete callback */ 253 void (*ErrorCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter error callback */ 254 void (*MspInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP init callback */ 255 void (*MspDeInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP de-init callback */ 256 #endif 257 } DFSDM_Filter_HandleTypeDef; 258 259 /** 260 * @brief DFSDM filter analog watchdog parameters structure definition 261 */ 262 typedef struct 263 { 264 uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. 265 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */ 266 uint32_t Channel; /*!< Analog watchdog channel selection. 267 This parameter can be a values combination of @ref DFSDM_Channel_Selection */ 268 int32_t HighThreshold; /*!< High threshold for the analog watchdog. 269 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 270 int32_t LowThreshold; /*!< Low threshold for the analog watchdog. 271 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 272 uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event. 273 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 274 uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event. 275 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 276 } DFSDM_Filter_AwdParamTypeDef; 277 278 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 279 /** 280 * @brief DFSDM filter callback ID enumeration definition 281 */ 282 typedef enum 283 { 284 HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */ 285 HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */ 286 HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */ 287 HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */ 288 HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U, /*!< DFSDM filter error callback ID */ 289 HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U, /*!< DFSDM filter MSP init callback ID */ 290 HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U /*!< DFSDM filter MSP de-init callback ID */ 291 } HAL_DFSDM_Filter_CallbackIDTypeDef; 292 293 /** 294 * @brief DFSDM filter callback pointer definition 295 */ 296 typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 297 typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); 298 #endif 299 300 /** 301 * @} 302 */ 303 /* End of exported types -----------------------------------------------------*/ 304 305 /* Exported constants --------------------------------------------------------*/ 306 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants 307 * @{ 308 */ 309 310 /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection 311 * @{ 312 */ 313 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for output clock is system clock */ 314 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for output clock is audio clock */ 315 /** 316 * @} 317 */ 318 319 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer 320 * @{ 321 */ 322 #define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U /*!< Data are taken from external inputs */ 323 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ 324 defined(STM32L496xx) || defined(STM32L4A6xx) || \ 325 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 326 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 327 #define DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0 /*!< Data are taken from ADC output */ 328 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || STM32L4P5xx || STM32L4Q5xx */ 329 #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ 330 /** 331 * @} 332 */ 333 334 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing 335 * @{ 336 */ 337 #define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U /*!< Standard data packing mode */ 338 #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ 339 #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ 340 /** 341 * @} 342 */ 343 344 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins 345 * @{ 346 */ 347 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U /*!< Input from pins on same channel */ 348 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ 349 /** 350 * @} 351 */ 352 353 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type 354 * @{ 355 */ 356 #define DFSDM_CHANNEL_SPI_RISING 0x00000000U /*!< SPI with rising edge */ 357 #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ 358 #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ 359 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ 360 /** 361 * @} 362 */ 363 364 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection 365 * @{ 366 */ 367 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U /*!< External SPI clock */ 368 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ 369 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ 370 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ 371 /** 372 * @} 373 */ 374 375 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order 376 * @{ 377 */ 378 #define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ 379 #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ 380 #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ 381 #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */ 382 /** 383 * @} 384 */ 385 386 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger 387 * @{ 388 */ 389 #define DFSDM_FILTER_SW_TRIGGER 0x00000000U /*!< Software trigger */ 390 #define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */ 391 #define DFSDM_FILTER_EXT_TRIGGER 0x00000002U /*!< External trigger (only for injected conversion) */ 392 /** 393 * @} 394 */ 395 396 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger 397 * @{ 398 */ 399 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) 400 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM filter 0, 1, 2 and 3 */ 401 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ 402 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ 403 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */ 404 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */ 405 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ 406 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */ 407 #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 408 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 409 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For all DFSDM filters */ 410 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For all DFSDM filters */ 411 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For all DFSDM filters */ 412 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */ 413 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For all DFSDM filters */ 414 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ 415 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ 416 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \ 417 DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ 418 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For all DFSDM filters */ 419 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 420 #define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \ 421 DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 422 #define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \ 423 DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 424 #else 425 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM filter 0, 1, 2 and 3 */ 426 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ 427 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ 428 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */ 429 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 3 */ 430 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 0, 1 and 2 */ 431 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 3 */ 432 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */ 433 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 2 and 3 */ 434 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ 435 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */ 436 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ 437 /** 438 * @} 439 */ 440 441 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge 442 * @{ 443 */ 444 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */ 445 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */ 446 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */ 447 /** 448 * @} 449 */ 450 451 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order 452 * @{ 453 */ 454 #define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ 455 #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */ 456 #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */ 457 #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */ 458 #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */ 459 #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */ 460 /** 461 * @} 462 */ 463 464 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source 465 * @{ 466 */ 467 #define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U /*!< From digital filter */ 468 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */ 469 /** 470 * @} 471 */ 472 473 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code 474 * @{ 475 */ 476 #define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */ 477 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */ 478 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */ 479 #define DFSDM_FILTER_ERROR_DMA 0x00000003U /*!< DMA error occurs */ 480 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 481 #define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */ 482 #endif 483 /** 484 * @} 485 */ 486 487 /** @defgroup DFSDM_BreakSignals DFSDM break signals 488 * @{ 489 */ 490 #define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */ 491 #define DFSDM_BREAK_SIGNAL_0 0x00000001U /*!< Break signal 0 */ 492 #define DFSDM_BREAK_SIGNAL_1 0x00000002U /*!< Break signal 1 */ 493 #define DFSDM_BREAK_SIGNAL_2 0x00000004U /*!< Break signal 2 */ 494 #define DFSDM_BREAK_SIGNAL_3 0x00000008U /*!< Break signal 3 */ 495 /** 496 * @} 497 */ 498 499 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection 500 * @{ 501 */ 502 /* DFSDM Channels ------------------------------------------------------------*/ 503 /* The DFSDM channels are defined as follows: 504 - in 16-bit LSB the channel mask is set 505 - in 16-bit MSB the channel number is set 506 e.g. for channel 5 definition: 507 - the channel mask is 0x00000020 (bit 5 is set) 508 - the channel number 5 is 0x00050000 509 --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ 510 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ 511 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 512 #define DFSDM_CHANNEL_0 0x00000001U 513 #define DFSDM_CHANNEL_1 0x00010002U 514 #define DFSDM_CHANNEL_2 0x00020004U 515 #define DFSDM_CHANNEL_3 0x00030008U 516 #else 517 #define DFSDM_CHANNEL_0 0x00000001U 518 #define DFSDM_CHANNEL_1 0x00010002U 519 #define DFSDM_CHANNEL_2 0x00020004U 520 #define DFSDM_CHANNEL_3 0x00030008U 521 #define DFSDM_CHANNEL_4 0x00040010U 522 #define DFSDM_CHANNEL_5 0x00050020U 523 #define DFSDM_CHANNEL_6 0x00060040U 524 #define DFSDM_CHANNEL_7 0x00070080U 525 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L4P5xx || STM32L4Q5xx */ 526 /** 527 * @} 528 */ 529 530 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode 531 * @{ 532 */ 533 #define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U /*!< Conversion are not continuous */ 534 #define DFSDM_CONTINUOUS_CONV_ON 0x00000001U /*!< Conversion are continuous */ 535 /** 536 * @} 537 */ 538 539 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold 540 * @{ 541 */ 542 #define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U /*!< Analog watchdog high threshold */ 543 #define DFSDM_AWD_LOW_THRESHOLD 0x00000001U /*!< Analog watchdog low threshold */ 544 /** 545 * @} 546 */ 547 548 /** 549 * @} 550 */ 551 /* End of exported constants -------------------------------------------------*/ 552 553 /* Exported macros -----------------------------------------------------------*/ 554 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros 555 * @{ 556 */ 557 558 /** @brief Reset DFSDM channel handle state. 559 * @param __HANDLE__ DFSDM channel handle. 560 * @retval None 561 */ 562 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 563 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \ 564 (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \ 565 (__HANDLE__)->MspInitCallback = NULL; \ 566 (__HANDLE__)->MspDeInitCallback = NULL; \ 567 } while(0) 568 #else 569 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) 570 #endif 571 572 /** @brief Reset DFSDM filter handle state. 573 * @param __HANDLE__ DFSDM filter handle. 574 * @retval None 575 */ 576 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 577 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \ 578 (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \ 579 (__HANDLE__)->MspInitCallback = NULL; \ 580 (__HANDLE__)->MspDeInitCallback = NULL; \ 581 } while(0) 582 #else 583 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) 584 #endif 585 586 /** 587 * @} 588 */ 589 /* End of exported macros ----------------------------------------------------*/ 590 591 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 592 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 593 /* Include DFSDM HAL Extension module */ 594 #include "stm32l4xx_hal_dfsdm_ex.h" 595 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || STM32L4P5xx || STM32L4Q5xx */ 596 597 /* Exported functions --------------------------------------------------------*/ 598 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions 599 * @{ 600 */ 601 602 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions 603 * @{ 604 */ 605 /* Channel initialization and de-initialization functions *********************/ 606 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 607 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 608 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 609 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 610 611 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 612 /* Channel callbacks register/unregister functions ****************************/ 613 HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 614 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, 615 pDFSDM_Channel_CallbackTypeDef pCallback); 616 HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 617 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID); 618 #endif 619 /** 620 * @} 621 */ 622 623 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions 624 * @{ 625 */ 626 /* Channel operation functions ************************************************/ 627 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 628 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 629 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 630 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 631 632 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 633 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 634 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 635 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 636 637 int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 638 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); 639 640 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 641 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 642 643 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 644 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 645 /** 646 * @} 647 */ 648 649 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function 650 * @{ 651 */ 652 /* Channel state function *****************************************************/ 653 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 654 /** 655 * @} 656 */ 657 658 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions 659 * @{ 660 */ 661 /* Filter initialization and de-initialization functions *********************/ 662 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 663 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 664 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 665 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 666 667 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 668 /* Filter callbacks register/unregister functions ****************************/ 669 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 670 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, 671 pDFSDM_Filter_CallbackTypeDef pCallback); 672 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 673 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID); 674 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 675 pDFSDM_Filter_AwdCallbackTypeDef pCallback); 676 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 677 #endif 678 /** 679 * @} 680 */ 681 682 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions 683 * @{ 684 */ 685 /* Filter control functions *********************/ 686 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 687 uint32_t Channel, 688 uint32_t ContinuousMode); 689 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 690 uint32_t Channel); 691 /** 692 * @} 693 */ 694 695 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions 696 * @{ 697 */ 698 /* Filter operation functions *********************/ 699 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 700 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 701 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 702 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 703 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 704 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 705 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 706 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 707 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 708 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 709 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 710 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 711 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 712 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 713 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 714 const DFSDM_Filter_AwdParamTypeDef *awdParam); 715 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 716 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); 717 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 718 719 int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); 720 int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); 721 int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); 722 int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); 723 uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 724 725 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 726 727 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 728 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 729 730 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 731 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 732 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 733 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 734 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); 735 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 736 /** 737 * @} 738 */ 739 740 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions 741 * @{ 742 */ 743 /* Filter state functions *****************************************************/ 744 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 745 uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 746 /** 747 * @} 748 */ 749 750 /** 751 * @} 752 */ 753 /* End of exported functions -------------------------------------------------*/ 754 755 /* Private macros ------------------------------------------------------------*/ 756 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros 757 * @{ 758 */ 759 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ 760 ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) 761 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U)) 762 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ 763 defined(STM32L496xx) || defined(STM32L4A6xx) || \ 764 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 765 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 766 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ 767 ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \ 768 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) 769 #else 770 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ 771 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) 772 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ 773 /* STM32L496xx || STM32L4A6xx || */ 774 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || */ 775 /* STM32L4P5xx || STM32L4Q5xx || */ 776 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ 777 ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ 778 ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) 779 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \ 780 ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS)) 781 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \ 782 ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \ 783 ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \ 784 ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING)) 785 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \ 786 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \ 787 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \ 788 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING)) 789 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \ 790 ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ 791 ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ 792 ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) 793 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U)) 794 #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 795 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU) 796 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU) 797 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 798 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) 799 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 800 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \ 801 ((TRIG) == DFSDM_FILTER_EXT_TRIGGER)) 802 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) 803 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 804 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ 805 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 806 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ 807 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 808 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 809 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) 810 #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 811 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 812 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 813 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ 814 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ 815 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \ 816 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 817 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ 818 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ 819 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 820 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ 821 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 822 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \ 823 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT)) 824 #else 825 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 826 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ 827 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ 828 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \ 829 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 830 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ 831 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ 832 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 833 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ 834 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 835 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) 836 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ 837 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \ 838 ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \ 839 ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES)) 840 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \ 841 ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \ 842 ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \ 843 ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ 844 ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ 845 ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) 846 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U)) 847 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U)) 848 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ 849 ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) 850 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 851 #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU) 852 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ 853 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 854 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ 855 ((CHANNEL) == DFSDM_CHANNEL_1) || \ 856 ((CHANNEL) == DFSDM_CHANNEL_2) || \ 857 ((CHANNEL) == DFSDM_CHANNEL_3)) 858 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU)) 859 #else 860 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ 861 ((CHANNEL) == DFSDM_CHANNEL_1) || \ 862 ((CHANNEL) == DFSDM_CHANNEL_2) || \ 863 ((CHANNEL) == DFSDM_CHANNEL_3) || \ 864 ((CHANNEL) == DFSDM_CHANNEL_4) || \ 865 ((CHANNEL) == DFSDM_CHANNEL_5) || \ 866 ((CHANNEL) == DFSDM_CHANNEL_6) || \ 867 ((CHANNEL) == DFSDM_CHANNEL_7)) 868 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU)) 869 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L4P5xx || STM32L4Q5xx */ 870 #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ 871 ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) 872 /** 873 * @} 874 */ 875 /* End of private macros -----------------------------------------------------*/ 876 877 /** 878 * @} 879 */ 880 881 /** 882 * @} 883 */ 884 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ 885 /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ 886 /* STM32L496xx || STM32L4A6xx || */ 887 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || */ 888 /* STM32L4P5xx || STM32L4Q5xx */ 889 890 #ifdef __cplusplus 891 } 892 #endif 893 894 #endif /* STM32L4xx_HAL_DFSDM_H */ 895
