1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_adc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L4xx_HAL_ADC_EX_H 21 #define STM32L4xx_HAL_ADC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l4xx_hal_def.h" 29 30 /** @addtogroup STM32L4xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup ADCEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief ADC Injected Conversion Oversampling structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Ratio; /*!< Configures the oversampling ratio. 49 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 50 51 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 52 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 53 } ADC_InjOversamplingTypeDef; 54 55 /** 56 * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected 57 * @note Parameters of this structure are shared within 2 scopes: 58 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset 59 * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, 60 * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling. 61 * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 62 * ADC state can be either: 63 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') 64 * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group. 65 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. 66 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going 67 * on ADC groups regular and injected. 68 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 69 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 70 */ 71 typedef struct 72 { 73 uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. 74 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 75 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 76 77 uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. 78 This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. 79 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 80 the new channel setting (or parameter number of conversions adjusted) */ 81 82 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 83 Unit: ADC clock cycles. 84 Conversion time is the addition of sampling time and processing time 85 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 86 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. 87 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 88 It overwrites the last setting. 89 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 90 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 91 Refer to device datasheet for timings values. */ 92 93 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. 94 In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 95 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 96 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. 97 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 98 It overwrites the last setting. 99 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 100 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 101 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 102 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 103 of another parameter update on the fly) */ 104 105 uint32_t InjectedOffsetNumber; /*!< Selects the offset number. 106 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. 107 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 108 109 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. 110 Offset value must be a positive number. 111 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 112 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 113 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 114 without continuous mode or external trigger that could launch a conversion). */ 115 116 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer. 117 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 118 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 119 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 120 configure a channel on injected group can impact the configuration of other channels previously set. */ 121 122 FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence 123 (main sequence subdivided in successive parts). 124 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 125 Discontinuous mode can be enabled only if continuous mode is disabled. 126 This parameter can be set to ENABLE or DISABLE. 127 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 128 Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). 129 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 130 configure a channel on injected group can impact the configuration of other channels previously set. */ 131 132 FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one 133 This parameter can be set to ENABLE or DISABLE. 134 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) 135 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) 136 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. 137 To maintain JAUTO always enabled, DMA must be configured in circular mode. 138 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 139 configure a channel on injected group can impact the configuration of other channels previously set. */ 140 141 FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. 142 This parameter can be set to ENABLE or DISABLE. 143 If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a 144 new injected context is set when queue is full, error is triggered by interruption and through function 145 'HAL_ADCEx_InjectedQueueOverflowCallback'. 146 Caution: This feature request that the sequence is fully configured before injected conversion start. 147 Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. 148 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 149 configure a channel on injected group can impact the configuration of other channels previously set. 150 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ 151 152 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. 153 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 154 This parameter can be a value of @ref ADC_injected_external_trigger_source. 155 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 156 configure a channel on injected group can impact the configuration of other channels previously set. */ 157 158 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 159 This parameter can be a value of @ref ADC_injected_external_trigger_edge. 160 If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. 161 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 162 configure a channel on injected group can impact the configuration of other channels previously set. */ 163 164 FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. 165 This parameter can be set to ENABLE or DISABLE. 166 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 167 168 ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. 169 Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. 170 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 171 } ADC_InjectionConfTypeDef; 172 173 #if defined(ADC_MULTIMODE_SUPPORT) 174 /** 175 * @brief Structure definition of ADC multimode 176 * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). 177 * Both Master and Slave ADCs must be disabled. 178 */ 179 typedef struct 180 { 181 uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. 182 This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ 183 184 uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC: 185 selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master) 186 This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */ 187 188 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. 189 This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. 190 Delay range depends on selected resolution: 191 from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits, 192 from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */ 193 } ADC_MultiModeTypeDef; 194 #endif /* ADC_MULTIMODE_SUPPORT */ 195 196 /** 197 * @} 198 */ 199 200 /* Exported constants --------------------------------------------------------*/ 201 202 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants 203 * @{ 204 */ 205 206 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source 207 * @{ 208 */ 209 /* ADC group regular trigger sources for all ADC instances */ 210 #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */ 211 #define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 212 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ 213 #define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 214 #define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 215 #define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 216 #define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 217 #define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 218 #define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 219 #define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 220 #define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 221 #define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ 222 #define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 223 #define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ 224 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ 225 #define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ 226 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */ 227 /** 228 * @} 229 */ 230 231 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) 232 * @{ 233 */ 234 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ 235 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ 236 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ 237 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ 238 /** 239 * @} 240 */ 241 242 /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending 243 * @{ 244 */ 245 #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ 246 #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ 247 /** 248 * @} 249 */ 250 251 /** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number 252 * @{ 253 */ 254 #define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */ 255 #define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 256 #define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 257 #define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 258 #define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 259 /** 260 * @} 261 */ 262 263 /** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 264 * @{ 265 */ 266 #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ 267 #define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ 268 #define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ 269 #define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ 270 /** 271 * @} 272 */ 273 274 #if defined(ADC_MULTIMODE_SUPPORT) 275 /** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode 276 * @{ 277 */ 278 #define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */ 279 #define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */ 280 #define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */ 281 #define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */ 282 #define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 283 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ 284 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 285 #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ 286 287 /** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution 288 * @{ 289 */ 290 #define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ 291 #define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ 292 #define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ 293 /** 294 * @} 295 */ 296 297 /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases 298 * @{ 299 */ 300 #define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ 301 #define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ 302 #define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ 303 #define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ 304 #define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ 305 #define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ 306 #define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ 307 #define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ 308 #define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ 309 #define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ 310 #define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ 311 #define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ 312 /** 313 * @} 314 */ 315 316 /** 317 * @} 318 */ 319 #endif /* ADC_MULTIMODE_SUPPORT */ 320 321 /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups 322 * @{ 323 */ 324 #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ 325 #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/ 326 #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ 327 /** 328 * @} 329 */ 330 331 /** @defgroup ADC_CFGR_fields ADCx CFGR fields 332 * @{ 333 */ 334 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 335 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 336 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 337 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 338 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 339 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ 340 ADC_CFGR_RES | ADC_CFGR_DFSDMCFG | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) 341 #else 342 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 343 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 344 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 345 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 346 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ 347 ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ) 348 #endif /* ADC_CFGR_DFSDMCFG */ 349 /** 350 * @} 351 */ 352 353 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields 354 * @{ 355 */ 356 #if defined(ADC_SMPR1_SMPPLUS) 357 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 358 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 359 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 360 ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS) 361 #else 362 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 363 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 364 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 365 ADC_SMPR1_SMP0) 366 #endif /* ADC_SMPR1_SMPPLUS */ 367 /** 368 * @} 369 */ 370 371 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields 372 * @{ 373 */ 374 /* ADC_CFGR fields of parameters that can be updated when no conversion 375 (neither regular nor injected) is on-going */ 376 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 377 #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY | ADC_CFGR_DFSDMCFG)) 378 #else 379 #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY)) 380 #endif /* ADC_CFGR_DFSDMCFG */ 381 /** 382 * @} 383 */ 384 385 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 386 /** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data 387 * @{ 388 */ 389 #define ADC_DFSDM_MODE_DISABLE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */ 390 #define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transferred to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */ 391 /** 392 * @} 393 */ 394 #endif /* ADC_CFGR_DFSDMCFG */ 395 396 /** 397 * @} 398 */ 399 400 /* Exported macros -----------------------------------------------------------*/ 401 402 #if defined(ADC_MULTIMODE_SUPPORT) 403 /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros 404 * @{ 405 */ 406 407 /** @brief Force ADC instance in multimode mode independent (multimode disable). 408 * @note This macro must be used only in case of transition from multimode 409 * to mode independent and in case of unknown previous state, 410 * to ensure ADC configuration is in mode independent. 411 * @note Standard way of multimode configuration change is done from 412 * HAL ADC handle of ADC master using function 413 * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". 414 * Usage of this macro is not the Standard way of multimode 415 * configuration and can lead to have HAL ADC handles status 416 * misaligned. Usage of this macro must be limited to cases 417 * mentioned above. 418 * @param __HANDLE__ ADC handle. 419 * @retval None 420 */ 421 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ 422 LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) 423 424 /** 425 * @} 426 */ 427 #endif /* ADC_MULTIMODE_SUPPORT */ 428 429 /* Private macros ------------------------------------------------------------*/ 430 431 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros 432 * @{ 433 */ 434 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 435 /* code of final user. */ 436 437 /** 438 * @brief Test if conversion trigger of injected group is software start 439 * or external trigger. 440 * @param __HANDLE__ ADC handle. 441 * @retval SET (software start) or RESET (external trigger). 442 */ 443 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 444 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) 445 446 /** 447 * @brief Check if conversion is on going on regular or injected groups. 448 * @param __HANDLE__ ADC handle. 449 * @retval SET (conversion is on going) or RESET (no conversion is on going). 450 */ 451 #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \ 452 (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \ 453 ) ? RESET : SET) 454 455 /** 456 * @brief Check if conversion is on going on injected group. 457 * @param __HANDLE__ ADC handle. 458 * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) 459 */ 460 #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \ 461 (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance)) 462 463 /** 464 * @brief Check whether or not ADC is independent. 465 * @param __HANDLE__ ADC handle. 466 * @note When multimode feature is not available, the macro always returns SET. 467 * @retval SET (ADC is independent) or RESET (ADC is not). 468 */ 469 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 470 #define ADC_IS_INDEPENDENT(__HANDLE__) \ 471 ( ( ( ((__HANDLE__)->Instance) == ADC3) \ 472 )? \ 473 SET \ 474 : \ 475 RESET \ 476 ) 477 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 478 #define ADC_IS_INDEPENDENT(__HANDLE__) (SET) 479 #elif defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) 480 #define ADC_IS_INDEPENDENT(__HANDLE__) (RESET) 481 #endif /* (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ 482 483 /** 484 * @brief Set the selected injected Channel rank. 485 * @param __CHANNELNB__ Channel number. 486 * @param __RANKNB__ Rank number. 487 * @retval None 488 */ 489 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)\ 490 & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) 491 492 /** 493 * @brief Configure ADC injected context queue 494 * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. 495 * @retval None 496 */ 497 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) 498 499 /** 500 * @brief Configure ADC discontinuous conversion mode for injected group 501 * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. 502 * @retval None 503 */ 504 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) 505 506 /** 507 * @brief Configure ADC discontinuous conversion mode for regular group 508 * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. 509 * @retval None 510 */ 511 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) 512 513 /** 514 * @brief Configure the number of discontinuous conversions for regular group. 515 * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. 516 * @retval None 517 */ 518 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) 519 520 /** 521 * @brief Configure the ADC auto delay mode. 522 * @param __AUTOWAIT__ Auto delay bit enable or disable. 523 * @retval None 524 */ 525 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos) 526 527 /** 528 * @brief Configure ADC continuous conversion mode. 529 * @param __CONTINUOUS_MODE__ Continuous mode. 530 * @retval None 531 */ 532 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) 533 534 /** 535 * @brief Configure the ADC DMA continuous request. 536 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 537 * @retval None 538 */ 539 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos) 540 541 /** 542 * @brief Configure the channel number into offset OFRx register. 543 * @param __CHANNEL__ ADC Channel. 544 * @retval None 545 */ 546 #define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos) 547 548 /** 549 * @brief Configure the channel number into differential mode selection register. 550 * @param __CHANNEL__ ADC Channel. 551 * @retval None 552 */ 553 #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__)) 554 555 /** 556 * @brief Configure calibration factor in differential mode to be set into calibration register. 557 * @param __CALIBRATION_FACTOR__ Calibration factor value. 558 * @retval None 559 */ 560 #define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__)\ 561 & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos) 562 563 /** 564 * @brief Calibration factor in differential mode to be retrieved from calibration register. 565 * @param __CALIBRATION_FACTOR__ Calibration factor value. 566 * @retval None 567 */ 568 #define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos) 569 570 /** 571 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. 572 * @param __THRESHOLD__ Threshold value. 573 * @retval None 574 */ 575 #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL) 576 577 #if defined(ADC_MULTIMODE_SUPPORT) 578 /** 579 * @brief Configure the ADC DMA continuous request for ADC multimode. 580 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 581 * @retval None 582 */ 583 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) 584 #endif /* ADC_MULTIMODE_SUPPORT */ 585 586 /** 587 * @brief Shift the offset with respect to the selected ADC resolution. 588 * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. 589 * If resolution 12 bits, no shift. 590 * If resolution 10 bits, shift of 2 ranks on the left. 591 * If resolution 8 bits, shift of 4 ranks on the left. 592 * If resolution 6 bits, shift of 6 ranks on the left. 593 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). 594 * @param __HANDLE__ ADC handle 595 * @param __OFFSET__ Value to be shifted 596 * @retval None 597 */ 598 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 599 ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) 600 601 /** 602 * @brief Shift the AWD1 threshold with respect to the selected ADC resolution. 603 * @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. 604 * If resolution 12 bits, no shift. 605 * If resolution 10 bits, shift of 2 ranks on the left. 606 * If resolution 8 bits, shift of 4 ranks on the left. 607 * If resolution 6 bits, shift of 6 ranks on the left. 608 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). 609 * @param __HANDLE__ ADC handle 610 * @param __THRESHOLD__ Value to be shifted 611 * @retval None 612 */ 613 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 614 ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) 615 616 /** 617 * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution. 618 * @note Thresholds have to be left-aligned on bit 7. 619 * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded). 620 * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded). 621 * If resolution 8 bits, no shift. 622 * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0). 623 * @param __HANDLE__ ADC handle 624 * @param __THRESHOLD__ Value to be shifted 625 * @retval None 626 */ 627 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 628 ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \ 629 ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \ 630 ((__THRESHOLD__) << 2UL) \ 631 ) 632 633 /** 634 * @brief Clear Common Control Register. 635 * @param __HANDLE__ ADC handle. 636 * @retval None 637 */ 638 #if defined(ADC_MULTIMODE_SUPPORT) 639 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ 640 ADC_CCR_CKMODE | \ 641 ADC_CCR_PRESC | \ 642 ADC_CCR_VBATEN | \ 643 ADC_CCR_TSEN | \ 644 ADC_CCR_VREFEN | \ 645 ADC_CCR_MDMA | \ 646 ADC_CCR_DMACFG | \ 647 ADC_CCR_DELAY | \ 648 ADC_CCR_DUAL) 649 #else 650 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ 651 ADC_CCR_CKMODE | \ 652 ADC_CCR_PRESC | \ 653 ADC_CCR_VBATEN | \ 654 ADC_CCR_TSEN | \ 655 ADC_CCR_VREFEN) 656 657 #endif /* ADC_MULTIMODE_SUPPORT */ 658 659 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) 660 /** 661 * @brief Set handle instance of the ADC slave associated to the ADC master. 662 * @param __HANDLE_MASTER__ ADC master handle. 663 * @param __HANDLE_SLAVE__ ADC slave handle. 664 * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. 665 * @retval None 666 */ 667 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ 668 ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) ) 669 #endif /* defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 670 671 672 /** 673 * @brief Verify the ADC instance connected to the temperature sensor. 674 * @param __HANDLE__ ADC handle. 675 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 676 */ 677 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 678 /* The temperature sensor measurement path (channel 17) is available on ADC1 */ 679 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 680 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 681 /* The temperature sensor measurement path (channel 17) is available on ADC1 and ADC3 */ 682 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1)\ 683 || (((__HANDLE__)->Instance) == ADC3)) 684 #endif /* (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ 685 686 /** 687 * @brief Verify the ADC instance connected to the battery voltage VBAT. 688 * @param __HANDLE__ ADC handle. 689 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 690 */ 691 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 692 /* The battery voltage measurement path (channel 18) is available on ADC1 */ 693 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 694 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 695 /* The battery voltage measurement path (channel 18) is available on ADC1 and ADC3 */ 696 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1)\ 697 || (((__HANDLE__)->Instance) == ADC3)) 698 #endif /* (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ 699 700 /** 701 * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. 702 * @param __HANDLE__ ADC handle. 703 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 704 */ 705 /* The internal voltage reference VREFINT measurement path (channel 0) is available on ADC1 */ 706 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 707 708 /** 709 * @brief Verify the length of scheduled injected conversions group. 710 * @param __LENGTH__ number of programmed conversions. 711 * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) 712 */ 713 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) 714 715 /** 716 * @brief Calibration factor size verification (7 bits maximum). 717 * @param __CALIBRATION_FACTOR__ Calibration factor value. 718 * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) 719 */ 720 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) 721 722 723 /** 724 * @brief Verify the ADC channel setting. 725 * @param __HANDLE__ ADC handle. 726 * @param __CHANNEL__ programmed ADC channel. 727 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 728 */ 729 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 730 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) && \ 731 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 732 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 733 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 734 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 735 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 736 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 737 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 738 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 739 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 740 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 741 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 742 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 743 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 744 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 745 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 746 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 747 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 748 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 749 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 750 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 751 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 752 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1) || \ 753 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2))) 754 #elif defined (STM32L412xx) || defined (STM32L422xx) 755 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \ 756 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 757 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 758 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 759 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 760 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 761 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 762 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 763 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 764 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 765 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 766 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 767 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 768 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 769 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 770 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 771 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 772 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 773 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 774 ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \ 775 ((((__HANDLE__)->Instance) == ADC2) && \ 776 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 777 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 778 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 779 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 780 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 781 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 782 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 783 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 784 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 785 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 786 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 787 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 788 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 789 ((__CHANNEL__) == ADC_CHANNEL_16) ))) 790 #elif defined (STM32L4P5xx) || defined (STM32L4Q5xx) 791 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \ 792 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 793 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 794 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 795 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 796 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 797 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 798 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 799 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 800 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 801 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 802 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 803 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 804 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 805 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 806 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 807 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 808 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 809 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 810 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 811 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 812 ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \ 813 ((((__HANDLE__)->Instance) == ADC2) && \ 814 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 815 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 816 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 817 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 818 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 819 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 820 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 821 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 822 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 823 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 824 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 825 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 826 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 827 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 828 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 829 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 830 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 831 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 832 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2)|| \ 833 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2) ))) 834 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 835 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \ 836 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 837 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 838 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 839 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 840 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 841 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 842 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 843 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 844 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 845 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 846 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 847 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 848 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 849 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 850 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 851 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 852 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 853 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 854 ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \ 855 ((((__HANDLE__)->Instance) == ADC2) && \ 856 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 857 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 858 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 859 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 860 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 861 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 862 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 863 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 864 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 865 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 866 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 867 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 868 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 869 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 870 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 871 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 872 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 873 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 874 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2) || \ 875 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2))) || \ 876 ((((__HANDLE__)->Instance) == ADC3) && \ 877 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 878 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 879 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 880 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 881 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 882 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 883 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 884 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 885 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 886 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 887 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 888 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 889 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 890 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 891 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 892 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 893 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC3) || \ 894 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC3) ))) 895 #endif /* (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ 896 897 /** 898 * @brief Verify the ADC channel setting in differential mode. 899 * @param __HANDLE__ ADC handle. 900 * @param __CHANNEL__ programmed ADC channel. 901 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 902 */ 903 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 904 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 905 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 906 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 907 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 908 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 909 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 910 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 911 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 912 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 913 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 914 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 915 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 916 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 917 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 918 ((__CHANNEL__) == ADC_CHANNEL_15) ) 919 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 920 /* For ADC1 and ADC2, channels 1 to 15 are available in differential mode, 921 channels 0, 16 to 18 can be only used in single-ended mode. 922 For ADC3, channels 1 to 3 and 6 to 12 are available in differential mode, 923 channels 4, 5 and 13 to 18 can only be used in single-ended mode. */ 924 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ((((((__HANDLE__)->Instance) == ADC1) || \ 925 (((__HANDLE__)->Instance) == ADC2)) && \ 926 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 927 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 928 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 929 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 930 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 931 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 932 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 933 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 934 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 935 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 936 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 937 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 938 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 939 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 940 ((__CHANNEL__) == ADC_CHANNEL_15))) || \ 941 ((((__HANDLE__)->Instance) == ADC3) && \ 942 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 943 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 944 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 945 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 946 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 947 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 948 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 949 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 950 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 951 ((__CHANNEL__) == ADC_CHANNEL_12) ))) 952 #endif /* (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ 953 954 /** 955 * @brief Verify the ADC single-ended input or differential mode setting. 956 * @param __SING_DIFF__ programmed channel setting. 957 * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) 958 */ 959 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ 960 ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) 961 962 /** 963 * @brief Verify the ADC offset management setting. 964 * @param __OFFSET_NUMBER__ ADC offset management. 965 * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) 966 */ 967 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ 968 ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ 969 ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ 970 ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ 971 ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) 972 973 /** 974 * @brief Verify the ADC injected channel setting. 975 * @param __CHANNEL__ programmed ADC injected channel. 976 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 977 */ 978 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ 979 ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ 980 ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ 981 ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) 982 983 /** 984 * @brief Verify the ADC injected conversions external trigger. 985 * @param __HANDLE__ ADC handle. 986 * @param __INJTRIG__ programmed ADC injected conversions external trigger. 987 * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) 988 */ 989 #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 990 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 991 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 992 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 993 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 994 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 995 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ 996 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 997 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 998 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 999 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 1000 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 1001 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 1002 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 1003 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 1004 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 1005 ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) 1006 1007 /** 1008 * @brief Verify the ADC edge trigger setting for injected group. 1009 * @param __EDGE__ programmed ADC edge trigger setting. 1010 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 1011 */ 1012 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 1013 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 1014 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 1015 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 1016 1017 #if defined(ADC_MULTIMODE_SUPPORT) 1018 /** 1019 * @brief Verify the ADC multimode setting. 1020 * @param __MODE__ programmed ADC multimode setting. 1021 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1022 */ 1023 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ 1024 ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ 1025 ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ 1026 ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ 1027 ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ 1028 ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ 1029 ((__MODE__) == ADC_DUALMODE_INTERL) || \ 1030 ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) 1031 1032 /** 1033 * @brief Verify the ADC multimode DMA access setting. 1034 * @param __MODE__ programmed ADC multimode DMA access setting. 1035 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1036 */ 1037 #define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \ 1038 ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \ 1039 ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) ) 1040 1041 /** 1042 * @brief Verify the ADC multimode delay setting. 1043 * @param __DELAY__ programmed ADC multimode delay setting. 1044 * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) 1045 */ 1046 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ 1047 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ 1048 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ 1049 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ 1050 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 1051 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 1052 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 1053 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ 1054 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ 1055 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ 1056 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ 1057 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) ) 1058 #endif /* ADC_MULTIMODE_SUPPORT */ 1059 1060 /** 1061 * @brief Verify the ADC analog watchdog setting. 1062 * @param __WATCHDOG__ programmed ADC analog watchdog setting. 1063 * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) 1064 */ 1065 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ 1066 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ 1067 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) 1068 1069 /** 1070 * @brief Verify the ADC analog watchdog mode setting. 1071 * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. 1072 * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) 1073 */ 1074 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ 1075 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 1076 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 1077 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 1078 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 1079 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 1080 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 1081 1082 /** 1083 * @brief Verify the ADC conversion (regular or injected or both). 1084 * @param __CONVERSION__ ADC conversion group. 1085 * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) 1086 */ 1087 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ 1088 ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ 1089 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) 1090 1091 /** 1092 * @brief Verify the ADC event type. 1093 * @param __EVENT__ ADC event. 1094 * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) 1095 */ 1096 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ 1097 ((__EVENT__) == ADC_AWD_EVENT) || \ 1098 ((__EVENT__) == ADC_AWD2_EVENT) || \ 1099 ((__EVENT__) == ADC_AWD3_EVENT) || \ 1100 ((__EVENT__) == ADC_OVR_EVENT) || \ 1101 ((__EVENT__) == ADC_JQOVF_EVENT) ) 1102 1103 /** 1104 * @brief Verify the ADC oversampling ratio. 1105 * @param __RATIO__ programmed ADC oversampling ratio. 1106 * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) 1107 */ 1108 #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ 1109 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ 1110 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ 1111 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ 1112 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ 1113 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ 1114 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \ 1115 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) 1116 1117 /** 1118 * @brief Verify the ADC oversampling shift. 1119 * @param __SHIFT__ programmed ADC oversampling shift. 1120 * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) 1121 */ 1122 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ 1123 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ 1124 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ 1125 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ 1126 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ 1127 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ 1128 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ 1129 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ 1130 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) 1131 1132 /** 1133 * @brief Verify the ADC oversampling triggered mode. 1134 * @param __MODE__ programmed ADC oversampling triggered mode. 1135 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1136 */ 1137 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ 1138 ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 1139 1140 /** 1141 * @brief Verify the ADC oversampling regular conversion resumed or continued mode. 1142 * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. 1143 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1144 */ 1145 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ 1146 ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) 1147 1148 /** 1149 * @brief Verify the DFSDM mode configuration. 1150 * @param __HANDLE__ ADC handle. 1151 * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For 1152 * this reason, the input parameter is the ADC handle and not the configuration parameter 1153 * directly. 1154 * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) 1155 */ 1156 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 1157 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \ 1158 ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) ) 1159 #else 1160 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) 1161 #endif /* ADC_CFGR_DFSDMCFG */ 1162 1163 /** 1164 * @brief Return the DFSDM configuration mode. 1165 * @param __HANDLE__ ADC handle. 1166 * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). 1167 * For this reason, the input parameter is the ADC handle and not the configuration parameter 1168 * directly. 1169 * @retval DFSDM configuration mode 1170 */ 1171 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 1172 #define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig) 1173 #else 1174 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) 1175 #endif /* ADC_CFGR_DFSDMCFG */ 1176 1177 /** 1178 * @} 1179 */ 1180 1181 1182 /* Exported functions --------------------------------------------------------*/ 1183 /** @addtogroup ADCEx_Exported_Functions 1184 * @{ 1185 */ 1186 1187 /** @addtogroup ADCEx_Exported_Functions_Group1 1188 * @{ 1189 */ 1190 /* IO operation functions *****************************************************/ 1191 1192 /* ADC calibration */ 1193 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 1194 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 1195 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, 1196 uint32_t CalibrationFactor); 1197 1198 /* Blocking mode: Polling */ 1199 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); 1200 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); 1201 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1202 1203 /* Non-blocking mode: Interruption */ 1204 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); 1205 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); 1206 1207 #if defined(ADC_MULTIMODE_SUPPORT) 1208 /* ADC multimode */ 1209 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1210 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1211 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); 1212 #endif /* ADC_MULTIMODE_SUPPORT */ 1213 1214 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1215 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); 1216 1217 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 1218 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); 1219 void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); 1220 void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); 1221 void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); 1222 void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); 1223 1224 /* ADC group regular conversions stop */ 1225 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); 1226 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); 1227 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); 1228 #if defined(ADC_MULTIMODE_SUPPORT) 1229 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1230 #endif /* ADC_MULTIMODE_SUPPORT */ 1231 1232 /** 1233 * @} 1234 */ 1235 1236 /** @addtogroup ADCEx_Exported_Functions_Group2 1237 * @{ 1238 */ 1239 /* Peripheral Control functions ***********************************************/ 1240 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, 1241 ADC_InjectionConfTypeDef *sConfigInjected); 1242 #if defined(ADC_MULTIMODE_SUPPORT) 1243 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); 1244 #endif /* ADC_MULTIMODE_SUPPORT */ 1245 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); 1246 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); 1247 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); 1248 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); 1249 1250 /** 1251 * @} 1252 */ 1253 1254 /** 1255 * @} 1256 */ 1257 1258 /** 1259 * @} 1260 */ 1261 1262 /** 1263 * @} 1264 */ 1265 1266 #ifdef __cplusplus 1267 } 1268 #endif 1269 1270 #endif /* STM32L4xx_HAL_ADC_EX_H */ 1271
