1 /**
2 ******************************************************************************
3 * @file stm32l1xx_ll_utils.h
4 * @author MCD Application Team
5 * @brief Header file of UTILS LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL UTILS driver contains a set of generic APIs that can be
12 used by user:
13 (+) Device electronic signature
14 (+) Timing functions
15 (+) PLL configuration functions
16
17 @endverbatim
18 ******************************************************************************
19 * @attention
20 *
21 * Copyright (c) 2017 STMicroelectronics.
22 * All rights reserved.
23 *
24 * This software is licensed under terms that can be found in the LICENSE file
25 * in the root directory of this software component.
26 * If no LICENSE file comes with this software, it is provided AS-IS.
27 *
28 ******************************************************************************
29 */
30
31 /* Define to prevent recursive inclusion -------------------------------------*/
32 #ifndef __STM32L1xx_LL_UTILS_H
33 #define __STM32L1xx_LL_UTILS_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32l1xx.h"
41
42 /** @addtogroup STM32L1xx_LL_Driver
43 * @{
44 */
45
46 /** @defgroup UTILS_LL UTILS
47 * @{
48 */
49
50 /* Private types -------------------------------------------------------------*/
51 /* Private variables ---------------------------------------------------------*/
52
53 /* Private constants ---------------------------------------------------------*/
54 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
55 * @{
56 */
57
58 /* Max delay can be used in LL_mDelay */
59 #define LL_MAX_DELAY 0xFFFFFFFFU
60
61 /**
62 * @brief Unique device ID register base address
63 */
64 #define UID_BASE_ADDRESS UID_BASE
65
66 /**
67 * @brief Flash size data register base address
68 */
69 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
70
71 /**
72 * @}
73 */
74
75 /* Private macros ------------------------------------------------------------*/
76 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
77 * @{
78 */
79 /**
80 * @}
81 */
82 /* Exported types ------------------------------------------------------------*/
83 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
84 * @{
85 */
86 /**
87 * @brief UTILS PLL structure definition
88 */
89 typedef struct
90 {
91 uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
92 This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
93
94 This feature can be modified afterwards using unitary function
95 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
96
97 uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock.
98 This parameter can be a value of @ref RCC_LL_EC_PLL_DIV
99
100 This feature can be modified afterwards using unitary function
101 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
102 } LL_UTILS_PLLInitTypeDef;
103
104 /**
105 * @brief UTILS System, AHB and APB buses clock configuration structure definition
106 */
107 typedef struct
108 {
109 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
110 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
111
112 This feature can be modified afterwards using unitary function
113 @ref LL_RCC_SetAHBPrescaler(). */
114
115 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
116 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
117
118 This feature can be modified afterwards using unitary function
119 @ref LL_RCC_SetAPB1Prescaler(). */
120
121 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
122 This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
123
124 This feature can be modified afterwards using unitary function
125 @ref LL_RCC_SetAPB2Prescaler(). */
126
127 } LL_UTILS_ClkInitTypeDef;
128
129 /**
130 * @}
131 */
132
133 /* Exported constants --------------------------------------------------------*/
134 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
135 * @{
136 */
137
138 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
139 * @{
140 */
141 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
142 #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
143 /**
144 * @}
145 */
146
147 /**
148 * @}
149 */
150
151 /* Exported macro ------------------------------------------------------------*/
152
153 /* Exported functions --------------------------------------------------------*/
154 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
155 * @{
156 */
157
158 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
159 * @{
160 */
161
162 /**
163 * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
164 * @retval UID[31:0]
165 */
LL_GetUID_Word0(void)166 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
167 {
168 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
169 }
170
171 /**
172 * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
173 * @retval UID[63:32]
174 */
LL_GetUID_Word1(void)175 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
176 {
177 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 0x04U))));
178 }
179
180 /**
181 * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
182 * @retval UID[95:64]
183 */
LL_GetUID_Word2(void)184 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
185 {
186 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 0x14U))));
187 }
188
189 /**
190 * @brief Get Flash memory size
191 * @note For DEV_ID = 0x416 or 0x427 or 0x429 or 0x437, this field value indicates the Flash memory
192 * size of the device in Kbytes.\n
193 * Example: 0x0080 = 128 Kbytes.\n
194 * For DEV_ID = 0x436, the field value can be '0' or '1', with '0' for 384 Kbytes and '1' for 256 Kbytes.
195 * @note For DEV_ID = 0x429, only LSB part of F_SIZE: F_SIZE[7:0] is valid. The MSB part
196 * F_SIZE[15:8] is reserved and must be ignored.
197 * @retval FLASH_SIZE[15:0]: Flash memory size
198 */
LL_GetFlashSize(void)199 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
200 {
201 return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU);
202 }
203
204
205 /**
206 * @}
207 */
208
209 /** @defgroup UTILS_LL_EF_DELAY DELAY
210 * @{
211 */
212
213 /**
214 * @brief This function configures the Cortex-M SysTick source of the time base.
215 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
216 * @note When a RTOS is used, it is recommended to avoid changing the SysTick
217 * configuration by calling this function, for a delay use rather osDelay RTOS service.
218 * @param Ticks Number of ticks
219 * @retval None
220 */
LL_InitTick(uint32_t HCLKFrequency,uint32_t Ticks)221 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
222 {
223 /* Configure the SysTick to have interrupt in 1ms time base */
224 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
225 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
226 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
227 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
228 }
229
230 void LL_Init1msTick(uint32_t HCLKFrequency);
231 void LL_mDelay(uint32_t Delay);
232
233 /**
234 * @}
235 */
236
237 /** @defgroup UTILS_EF_SYSTEM SYSTEM
238 * @{
239 */
240
241 void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
242 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
243 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
244 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
245 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
246 #if defined(FLASH_ACR_LATENCY)
247 ErrorStatus LL_SetFlashLatency(uint32_t Frequency);
248 #endif /* FLASH_ACR_LATENCY */
249
250 /**
251 * @}
252 */
253
254 /**
255 * @}
256 */
257
258 /**
259 * @}
260 */
261
262 /**
263 * @}
264 */
265
266 #ifdef __cplusplus
267 }
268 #endif
269
270 #endif /* __STM32L1xx_LL_UTILS_H */
271
