1 /**
2 ******************************************************************************
3 * @file stm32l1xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32L1xx_LL_DMA_H
21 #define __STM32L1xx_LL_DMA_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l1xx.h"
29
30 /** @addtogroup STM32L1xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DMA1) || defined (DMA2)
35
36 /** @defgroup DMA_LL DMA
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
43 * @{
44 */
45 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
46 static const uint8_t CHANNEL_OFFSET_TAB[] =
47 {
48 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
49 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
55 };
56 /**
57 * @}
58 */
59
60 /* Private constants ---------------------------------------------------------*/
61
62 /* Private macros ------------------------------------------------------------*/
63 #if defined(USE_FULL_LL_DRIVER)
64 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
65 * @{
66 */
67 /**
68 * @}
69 */
70 #endif /*USE_FULL_LL_DRIVER*/
71
72 /* Exported types ------------------------------------------------------------*/
73 #if defined(USE_FULL_LL_DRIVER)
74 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
75 * @{
76 */
77 typedef struct
78 {
79 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
80 or as Source base address in case of memory to memory transfer direction.
81
82 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
83
84 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
85 or as Destination base address in case of memory to memory transfer direction.
86
87 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
88
89 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
90 from memory to memory or from peripheral to memory.
91 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
92
93 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
94
95 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
96 This parameter can be a value of @ref DMA_LL_EC_MODE
97 @note: The circular buffer mode cannot be used if the memory to memory
98 data transfer direction is configured on the selected Channel
99
100 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
101
102 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
103 is incremented or not.
104 This parameter can be a value of @ref DMA_LL_EC_PERIPH
105
106 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
107
108 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
109 is incremented or not.
110 This parameter can be a value of @ref DMA_LL_EC_MEMORY
111
112 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
113
114 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
115 in case of memory to memory transfer direction.
116 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
117
118 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
119
120 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
121 in case of memory to memory transfer direction.
122 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
123
124 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
125
126 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
127 The data unit is equal to the source buffer configuration set in PeripheralSize
128 or MemorySize parameters depending in the transfer direction.
129 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
130
131 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
132
133 uint32_t Priority; /*!< Specifies the channel priority level.
134 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
135
136 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
137
138 } LL_DMA_InitTypeDef;
139 /**
140 * @}
141 */
142 #endif /*USE_FULL_LL_DRIVER*/
143
144 /* Exported constants --------------------------------------------------------*/
145 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
146 * @{
147 */
148 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
149 * @brief Flags defines which can be used with LL_DMA_WriteReg function
150 * @{
151 */
152 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
153 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
154 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
155 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
156 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
157 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
158 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
159 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
160 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
161 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
162 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
163 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
164 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
165 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
166 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
167 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
168 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
169 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
170 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
171 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
172 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
173 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
174 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
175 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
176 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
177 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
178 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
179 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
180 /**
181 * @}
182 */
183
184 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
185 * @brief Flags defines which can be used with LL_DMA_ReadReg function
186 * @{
187 */
188 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
189 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
190 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
191 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
192 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
193 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
194 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
195 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
196 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
197 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
198 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
199 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
200 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
201 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
202 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
203 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
204 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
205 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
206 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
207 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
208 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
209 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
210 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
211 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
212 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
213 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
214 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
215 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
216 /**
217 * @}
218 */
219
220 /** @defgroup DMA_LL_EC_IT IT Defines
221 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
222 * @{
223 */
224 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
225 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
226 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
227 /**
228 * @}
229 */
230
231 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
232 * @{
233 */
234 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
235 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
236 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
237 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
238 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
239 #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
240 #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
241 #if defined(USE_FULL_LL_DRIVER)
242 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
243 #endif /*USE_FULL_LL_DRIVER*/
244 /**
245 * @}
246 */
247
248 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
249 * @{
250 */
251 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
252 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
253 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
254 /**
255 * @}
256 */
257
258 /** @defgroup DMA_LL_EC_MODE Transfer mode
259 * @{
260 */
261 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
262 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
263 /**
264 * @}
265 */
266
267 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
268 * @{
269 */
270 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
271 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
272 /**
273 * @}
274 */
275
276 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
277 * @{
278 */
279 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
280 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
281 /**
282 * @}
283 */
284
285 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
286 * @{
287 */
288 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
289 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
290 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
291 /**
292 * @}
293 */
294
295 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
296 * @{
297 */
298 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
299 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
300 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
301 /**
302 * @}
303 */
304
305 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
306 * @{
307 */
308 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
309 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
310 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
311 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
312 /**
313 * @}
314 */
315
316
317 /**
318 * @}
319 */
320
321 /* Exported macro ------------------------------------------------------------*/
322 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
323 * @{
324 */
325
326 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
327 * @{
328 */
329 /**
330 * @brief Write a value in DMA register
331 * @param __INSTANCE__ DMA Instance
332 * @param __REG__ Register to be written
333 * @param __VALUE__ Value to be written in the register
334 * @retval None
335 */
336 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
337
338 /**
339 * @brief Read a value in DMA register
340 * @param __INSTANCE__ DMA Instance
341 * @param __REG__ Register to be read
342 * @retval Register value
343 */
344 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
345 /**
346 * @}
347 */
348
349 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
350 * @{
351 */
352 /**
353 * @brief Convert DMAx_Channely into DMAx
354 * @param __CHANNEL_INSTANCE__ DMAx_Channely
355 * @retval DMAx
356 */
357 #if defined(DMA2)
358 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
359 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
360 #else
361 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
362 #endif
363
364 /**
365 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
366 * @param __CHANNEL_INSTANCE__ DMAx_Channely
367 * @retval LL_DMA_CHANNEL_y
368 */
369 #if defined (DMA2)
370 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
371 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
372 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
373 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
374 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
375 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
376 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
377 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
378 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
379 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
380 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
381 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
382 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
383 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
384 LL_DMA_CHANNEL_7)
385 #else
386 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
387 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
388 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
389 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
390 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
391 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
392 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
393 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
394 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
395 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
396 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
397 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
398 LL_DMA_CHANNEL_7)
399 #endif
400 #else
401 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
402 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
403 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
404 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
405 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
406 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
407 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
408 LL_DMA_CHANNEL_7)
409 #endif
410
411 /**
412 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
413 * @param __DMA_INSTANCE__ DMAx
414 * @param __CHANNEL__ LL_DMA_CHANNEL_y
415 * @retval DMAx_Channely
416 */
417 #if defined (DMA2)
418 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
419 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
420 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
421 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
422 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
423 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
424 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
425 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
426 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
427 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
428 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
429 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
430 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
431 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
432 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
433 DMA2_Channel7)
434 #else
435 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
436 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
437 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
438 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
439 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
440 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
441 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
442 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
443 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
444 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
445 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
446 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
447 DMA1_Channel7)
448 #endif
449 #else
450 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
451 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
452 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
453 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
456 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
457 DMA1_Channel7)
458 #endif
459
460 /**
461 * @}
462 */
463
464 /**
465 * @}
466 */
467
468 /* Exported functions --------------------------------------------------------*/
469 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
470 * @{
471 */
472
473 /** @defgroup DMA_LL_EF_Configuration Configuration
474 * @{
475 */
476 /**
477 * @brief Enable DMA channel.
478 * @rmtoll CCR EN LL_DMA_EnableChannel
479 * @param DMAx DMAx Instance
480 * @param Channel This parameter can be one of the following values:
481 * @arg @ref LL_DMA_CHANNEL_1
482 * @arg @ref LL_DMA_CHANNEL_2
483 * @arg @ref LL_DMA_CHANNEL_3
484 * @arg @ref LL_DMA_CHANNEL_4
485 * @arg @ref LL_DMA_CHANNEL_5
486 * @arg @ref LL_DMA_CHANNEL_6
487 * @arg @ref LL_DMA_CHANNEL_7
488 * @retval None
489 */
LL_DMA_EnableChannel(DMA_TypeDef * DMAx,uint32_t Channel)490 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
491 {
492 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
493 }
494
495 /**
496 * @brief Disable DMA channel.
497 * @rmtoll CCR EN LL_DMA_DisableChannel
498 * @param DMAx DMAx Instance
499 * @param Channel This parameter can be one of the following values:
500 * @arg @ref LL_DMA_CHANNEL_1
501 * @arg @ref LL_DMA_CHANNEL_2
502 * @arg @ref LL_DMA_CHANNEL_3
503 * @arg @ref LL_DMA_CHANNEL_4
504 * @arg @ref LL_DMA_CHANNEL_5
505 * @arg @ref LL_DMA_CHANNEL_6
506 * @arg @ref LL_DMA_CHANNEL_7
507 * @retval None
508 */
LL_DMA_DisableChannel(DMA_TypeDef * DMAx,uint32_t Channel)509 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
510 {
511 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
512 }
513
514 /**
515 * @brief Check if DMA channel is enabled or disabled.
516 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
517 * @param DMAx DMAx Instance
518 * @param Channel This parameter can be one of the following values:
519 * @arg @ref LL_DMA_CHANNEL_1
520 * @arg @ref LL_DMA_CHANNEL_2
521 * @arg @ref LL_DMA_CHANNEL_3
522 * @arg @ref LL_DMA_CHANNEL_4
523 * @arg @ref LL_DMA_CHANNEL_5
524 * @arg @ref LL_DMA_CHANNEL_6
525 * @arg @ref LL_DMA_CHANNEL_7
526 * @retval State of bit (1 or 0).
527 */
LL_DMA_IsEnabledChannel(DMA_TypeDef * DMAx,uint32_t Channel)528 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
529 {
530 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
531 DMA_CCR_EN) == (DMA_CCR_EN));
532 }
533
534 /**
535 * @brief Configure all parameters link to DMA transfer.
536 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
537 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
538 * CCR CIRC LL_DMA_ConfigTransfer\n
539 * CCR PINC LL_DMA_ConfigTransfer\n
540 * CCR MINC LL_DMA_ConfigTransfer\n
541 * CCR PSIZE LL_DMA_ConfigTransfer\n
542 * CCR MSIZE LL_DMA_ConfigTransfer\n
543 * CCR PL LL_DMA_ConfigTransfer
544 * @param DMAx DMAx Instance
545 * @param Channel This parameter can be one of the following values:
546 * @arg @ref LL_DMA_CHANNEL_1
547 * @arg @ref LL_DMA_CHANNEL_2
548 * @arg @ref LL_DMA_CHANNEL_3
549 * @arg @ref LL_DMA_CHANNEL_4
550 * @arg @ref LL_DMA_CHANNEL_5
551 * @arg @ref LL_DMA_CHANNEL_6
552 * @arg @ref LL_DMA_CHANNEL_7
553 * @param Configuration This parameter must be a combination of all the following values:
554 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
555 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
556 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
557 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
558 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
559 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
560 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
561 * @retval None
562 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)563 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
564 {
565 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
566 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
567 Configuration);
568 }
569
570 /**
571 * @brief Set Data transfer direction (read from peripheral or from memory).
572 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
573 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
574 * @param DMAx DMAx Instance
575 * @param Channel This parameter can be one of the following values:
576 * @arg @ref LL_DMA_CHANNEL_1
577 * @arg @ref LL_DMA_CHANNEL_2
578 * @arg @ref LL_DMA_CHANNEL_3
579 * @arg @ref LL_DMA_CHANNEL_4
580 * @arg @ref LL_DMA_CHANNEL_5
581 * @arg @ref LL_DMA_CHANNEL_6
582 * @arg @ref LL_DMA_CHANNEL_7
583 * @param Direction This parameter can be one of the following values:
584 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
585 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
586 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
587 * @retval None
588 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)589 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
590 {
591 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
592 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
593 }
594
595 /**
596 * @brief Get Data transfer direction (read from peripheral or from memory).
597 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
598 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
599 * @param DMAx DMAx Instance
600 * @param Channel This parameter can be one of the following values:
601 * @arg @ref LL_DMA_CHANNEL_1
602 * @arg @ref LL_DMA_CHANNEL_2
603 * @arg @ref LL_DMA_CHANNEL_3
604 * @arg @ref LL_DMA_CHANNEL_4
605 * @arg @ref LL_DMA_CHANNEL_5
606 * @arg @ref LL_DMA_CHANNEL_6
607 * @arg @ref LL_DMA_CHANNEL_7
608 * @retval Returned value can be one of the following values:
609 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
610 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
611 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
612 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel)613 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
614 {
615 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
616 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
617 }
618
619 /**
620 * @brief Set DMA mode circular or normal.
621 * @note The circular buffer mode cannot be used if the memory-to-memory
622 * data transfer is configured on the selected Channel.
623 * @rmtoll CCR CIRC LL_DMA_SetMode
624 * @param DMAx DMAx Instance
625 * @param Channel This parameter can be one of the following values:
626 * @arg @ref LL_DMA_CHANNEL_1
627 * @arg @ref LL_DMA_CHANNEL_2
628 * @arg @ref LL_DMA_CHANNEL_3
629 * @arg @ref LL_DMA_CHANNEL_4
630 * @arg @ref LL_DMA_CHANNEL_5
631 * @arg @ref LL_DMA_CHANNEL_6
632 * @arg @ref LL_DMA_CHANNEL_7
633 * @param Mode This parameter can be one of the following values:
634 * @arg @ref LL_DMA_MODE_NORMAL
635 * @arg @ref LL_DMA_MODE_CIRCULAR
636 * @retval None
637 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)638 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
639 {
640 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
641 Mode);
642 }
643
644 /**
645 * @brief Get DMA mode circular or normal.
646 * @rmtoll CCR CIRC LL_DMA_GetMode
647 * @param DMAx DMAx Instance
648 * @param Channel This parameter can be one of the following values:
649 * @arg @ref LL_DMA_CHANNEL_1
650 * @arg @ref LL_DMA_CHANNEL_2
651 * @arg @ref LL_DMA_CHANNEL_3
652 * @arg @ref LL_DMA_CHANNEL_4
653 * @arg @ref LL_DMA_CHANNEL_5
654 * @arg @ref LL_DMA_CHANNEL_6
655 * @arg @ref LL_DMA_CHANNEL_7
656 * @retval Returned value can be one of the following values:
657 * @arg @ref LL_DMA_MODE_NORMAL
658 * @arg @ref LL_DMA_MODE_CIRCULAR
659 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Channel)660 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
661 {
662 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
663 DMA_CCR_CIRC));
664 }
665
666 /**
667 * @brief Set Peripheral increment mode.
668 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
669 * @param DMAx DMAx Instance
670 * @param Channel This parameter can be one of the following values:
671 * @arg @ref LL_DMA_CHANNEL_1
672 * @arg @ref LL_DMA_CHANNEL_2
673 * @arg @ref LL_DMA_CHANNEL_3
674 * @arg @ref LL_DMA_CHANNEL_4
675 * @arg @ref LL_DMA_CHANNEL_5
676 * @arg @ref LL_DMA_CHANNEL_6
677 * @arg @ref LL_DMA_CHANNEL_7
678 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
679 * @arg @ref LL_DMA_PERIPH_INCREMENT
680 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
681 * @retval None
682 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcIncMode)683 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
684 {
685 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
686 PeriphOrM2MSrcIncMode);
687 }
688
689 /**
690 * @brief Get Peripheral increment mode.
691 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
692 * @param DMAx DMAx Instance
693 * @param Channel This parameter can be one of the following values:
694 * @arg @ref LL_DMA_CHANNEL_1
695 * @arg @ref LL_DMA_CHANNEL_2
696 * @arg @ref LL_DMA_CHANNEL_3
697 * @arg @ref LL_DMA_CHANNEL_4
698 * @arg @ref LL_DMA_CHANNEL_5
699 * @arg @ref LL_DMA_CHANNEL_6
700 * @arg @ref LL_DMA_CHANNEL_7
701 * @retval Returned value can be one of the following values:
702 * @arg @ref LL_DMA_PERIPH_INCREMENT
703 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
704 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel)705 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
706 {
707 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
708 DMA_CCR_PINC));
709 }
710
711 /**
712 * @brief Set Memory increment mode.
713 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
714 * @param DMAx DMAx Instance
715 * @param Channel This parameter can be one of the following values:
716 * @arg @ref LL_DMA_CHANNEL_1
717 * @arg @ref LL_DMA_CHANNEL_2
718 * @arg @ref LL_DMA_CHANNEL_3
719 * @arg @ref LL_DMA_CHANNEL_4
720 * @arg @ref LL_DMA_CHANNEL_5
721 * @arg @ref LL_DMA_CHANNEL_6
722 * @arg @ref LL_DMA_CHANNEL_7
723 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
724 * @arg @ref LL_DMA_MEMORY_INCREMENT
725 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
726 * @retval None
727 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstIncMode)728 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
729 {
730 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
731 MemoryOrM2MDstIncMode);
732 }
733
734 /**
735 * @brief Get Memory increment mode.
736 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
737 * @param DMAx DMAx Instance
738 * @param Channel This parameter can be one of the following values:
739 * @arg @ref LL_DMA_CHANNEL_1
740 * @arg @ref LL_DMA_CHANNEL_2
741 * @arg @ref LL_DMA_CHANNEL_3
742 * @arg @ref LL_DMA_CHANNEL_4
743 * @arg @ref LL_DMA_CHANNEL_5
744 * @arg @ref LL_DMA_CHANNEL_6
745 * @arg @ref LL_DMA_CHANNEL_7
746 * @retval Returned value can be one of the following values:
747 * @arg @ref LL_DMA_MEMORY_INCREMENT
748 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
749 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel)750 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
751 {
752 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
753 DMA_CCR_MINC));
754 }
755
756 /**
757 * @brief Set Peripheral size.
758 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
759 * @param DMAx DMAx Instance
760 * @param Channel This parameter can be one of the following values:
761 * @arg @ref LL_DMA_CHANNEL_1
762 * @arg @ref LL_DMA_CHANNEL_2
763 * @arg @ref LL_DMA_CHANNEL_3
764 * @arg @ref LL_DMA_CHANNEL_4
765 * @arg @ref LL_DMA_CHANNEL_5
766 * @arg @ref LL_DMA_CHANNEL_6
767 * @arg @ref LL_DMA_CHANNEL_7
768 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
769 * @arg @ref LL_DMA_PDATAALIGN_BYTE
770 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
771 * @arg @ref LL_DMA_PDATAALIGN_WORD
772 * @retval None
773 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcDataSize)774 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
775 {
776 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
777 PeriphOrM2MSrcDataSize);
778 }
779
780 /**
781 * @brief Get Peripheral size.
782 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
783 * @param DMAx DMAx Instance
784 * @param Channel This parameter can be one of the following values:
785 * @arg @ref LL_DMA_CHANNEL_1
786 * @arg @ref LL_DMA_CHANNEL_2
787 * @arg @ref LL_DMA_CHANNEL_3
788 * @arg @ref LL_DMA_CHANNEL_4
789 * @arg @ref LL_DMA_CHANNEL_5
790 * @arg @ref LL_DMA_CHANNEL_6
791 * @arg @ref LL_DMA_CHANNEL_7
792 * @retval Returned value can be one of the following values:
793 * @arg @ref LL_DMA_PDATAALIGN_BYTE
794 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
795 * @arg @ref LL_DMA_PDATAALIGN_WORD
796 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel)797 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
798 {
799 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
800 DMA_CCR_PSIZE));
801 }
802
803 /**
804 * @brief Set Memory size.
805 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
806 * @param DMAx DMAx Instance
807 * @param Channel This parameter can be one of the following values:
808 * @arg @ref LL_DMA_CHANNEL_1
809 * @arg @ref LL_DMA_CHANNEL_2
810 * @arg @ref LL_DMA_CHANNEL_3
811 * @arg @ref LL_DMA_CHANNEL_4
812 * @arg @ref LL_DMA_CHANNEL_5
813 * @arg @ref LL_DMA_CHANNEL_6
814 * @arg @ref LL_DMA_CHANNEL_7
815 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
816 * @arg @ref LL_DMA_MDATAALIGN_BYTE
817 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
818 * @arg @ref LL_DMA_MDATAALIGN_WORD
819 * @retval None
820 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstDataSize)821 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
822 {
823 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
824 MemoryOrM2MDstDataSize);
825 }
826
827 /**
828 * @brief Get Memory size.
829 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
830 * @param DMAx DMAx Instance
831 * @param Channel This parameter can be one of the following values:
832 * @arg @ref LL_DMA_CHANNEL_1
833 * @arg @ref LL_DMA_CHANNEL_2
834 * @arg @ref LL_DMA_CHANNEL_3
835 * @arg @ref LL_DMA_CHANNEL_4
836 * @arg @ref LL_DMA_CHANNEL_5
837 * @arg @ref LL_DMA_CHANNEL_6
838 * @arg @ref LL_DMA_CHANNEL_7
839 * @retval Returned value can be one of the following values:
840 * @arg @ref LL_DMA_MDATAALIGN_BYTE
841 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
842 * @arg @ref LL_DMA_MDATAALIGN_WORD
843 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel)844 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
845 {
846 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
847 DMA_CCR_MSIZE));
848 }
849
850 /**
851 * @brief Set Channel priority level.
852 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
853 * @param DMAx DMAx Instance
854 * @param Channel This parameter can be one of the following values:
855 * @arg @ref LL_DMA_CHANNEL_1
856 * @arg @ref LL_DMA_CHANNEL_2
857 * @arg @ref LL_DMA_CHANNEL_3
858 * @arg @ref LL_DMA_CHANNEL_4
859 * @arg @ref LL_DMA_CHANNEL_5
860 * @arg @ref LL_DMA_CHANNEL_6
861 * @arg @ref LL_DMA_CHANNEL_7
862 * @param Priority This parameter can be one of the following values:
863 * @arg @ref LL_DMA_PRIORITY_LOW
864 * @arg @ref LL_DMA_PRIORITY_MEDIUM
865 * @arg @ref LL_DMA_PRIORITY_HIGH
866 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
867 * @retval None
868 */
LL_DMA_SetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)869 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
870 {
871 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
872 Priority);
873 }
874
875 /**
876 * @brief Get Channel priority level.
877 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
878 * @param DMAx DMAx Instance
879 * @param Channel This parameter can be one of the following values:
880 * @arg @ref LL_DMA_CHANNEL_1
881 * @arg @ref LL_DMA_CHANNEL_2
882 * @arg @ref LL_DMA_CHANNEL_3
883 * @arg @ref LL_DMA_CHANNEL_4
884 * @arg @ref LL_DMA_CHANNEL_5
885 * @arg @ref LL_DMA_CHANNEL_6
886 * @arg @ref LL_DMA_CHANNEL_7
887 * @retval Returned value can be one of the following values:
888 * @arg @ref LL_DMA_PRIORITY_LOW
889 * @arg @ref LL_DMA_PRIORITY_MEDIUM
890 * @arg @ref LL_DMA_PRIORITY_HIGH
891 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
892 */
LL_DMA_GetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel)893 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
894 {
895 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
896 DMA_CCR_PL));
897 }
898
899 /**
900 * @brief Set Number of data to transfer.
901 * @note This action has no effect if
902 * channel is enabled.
903 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
904 * @param DMAx DMAx Instance
905 * @param Channel This parameter can be one of the following values:
906 * @arg @ref LL_DMA_CHANNEL_1
907 * @arg @ref LL_DMA_CHANNEL_2
908 * @arg @ref LL_DMA_CHANNEL_3
909 * @arg @ref LL_DMA_CHANNEL_4
910 * @arg @ref LL_DMA_CHANNEL_5
911 * @arg @ref LL_DMA_CHANNEL_6
912 * @arg @ref LL_DMA_CHANNEL_7
913 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
914 * @retval None
915 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t NbData)916 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
917 {
918 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
919 DMA_CNDTR_NDT, NbData);
920 }
921
922 /**
923 * @brief Get Number of data to transfer.
924 * @note Once the channel is enabled, the return value indicate the
925 * remaining bytes to be transmitted.
926 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
927 * @param DMAx DMAx Instance
928 * @param Channel This parameter can be one of the following values:
929 * @arg @ref LL_DMA_CHANNEL_1
930 * @arg @ref LL_DMA_CHANNEL_2
931 * @arg @ref LL_DMA_CHANNEL_3
932 * @arg @ref LL_DMA_CHANNEL_4
933 * @arg @ref LL_DMA_CHANNEL_5
934 * @arg @ref LL_DMA_CHANNEL_6
935 * @arg @ref LL_DMA_CHANNEL_7
936 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
937 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Channel)938 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
939 {
940 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
941 DMA_CNDTR_NDT));
942 }
943
944 /**
945 * @brief Configure the Source and Destination addresses.
946 * @note This API must not be called when the DMA channel is enabled.
947 * @note Each IP using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
948 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
949 * CMAR MA LL_DMA_ConfigAddresses
950 * @param DMAx DMAx Instance
951 * @param Channel This parameter can be one of the following values:
952 * @arg @ref LL_DMA_CHANNEL_1
953 * @arg @ref LL_DMA_CHANNEL_2
954 * @arg @ref LL_DMA_CHANNEL_3
955 * @arg @ref LL_DMA_CHANNEL_4
956 * @arg @ref LL_DMA_CHANNEL_5
957 * @arg @ref LL_DMA_CHANNEL_6
958 * @arg @ref LL_DMA_CHANNEL_7
959 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
960 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
961 * @param Direction This parameter can be one of the following values:
962 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
963 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
964 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
965 * @retval None
966 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)967 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
968 uint32_t DstAddress, uint32_t Direction)
969 {
970 /* Direction Memory to Periph */
971 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
972 {
973 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
974 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
975 }
976 /* Direction Periph to Memory and Memory to Memory */
977 else
978 {
979 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
980 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
981 }
982 }
983
984 /**
985 * @brief Set the Memory address.
986 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
987 * @note This API must not be called when the DMA channel is enabled.
988 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
989 * @param DMAx DMAx Instance
990 * @param Channel This parameter can be one of the following values:
991 * @arg @ref LL_DMA_CHANNEL_1
992 * @arg @ref LL_DMA_CHANNEL_2
993 * @arg @ref LL_DMA_CHANNEL_3
994 * @arg @ref LL_DMA_CHANNEL_4
995 * @arg @ref LL_DMA_CHANNEL_5
996 * @arg @ref LL_DMA_CHANNEL_6
997 * @arg @ref LL_DMA_CHANNEL_7
998 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
999 * @retval None
1000 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1001 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1002 {
1003 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
1004 }
1005
1006 /**
1007 * @brief Set the Peripheral address.
1008 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1009 * @note This API must not be called when the DMA channel is enabled.
1010 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
1011 * @param DMAx DMAx Instance
1012 * @param Channel This parameter can be one of the following values:
1013 * @arg @ref LL_DMA_CHANNEL_1
1014 * @arg @ref LL_DMA_CHANNEL_2
1015 * @arg @ref LL_DMA_CHANNEL_3
1016 * @arg @ref LL_DMA_CHANNEL_4
1017 * @arg @ref LL_DMA_CHANNEL_5
1018 * @arg @ref LL_DMA_CHANNEL_6
1019 * @arg @ref LL_DMA_CHANNEL_7
1020 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1021 * @retval None
1022 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphAddress)1023 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
1024 {
1025 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
1026 }
1027
1028 /**
1029 * @brief Get Memory address.
1030 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1031 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
1032 * @param DMAx DMAx Instance
1033 * @param Channel This parameter can be one of the following values:
1034 * @arg @ref LL_DMA_CHANNEL_1
1035 * @arg @ref LL_DMA_CHANNEL_2
1036 * @arg @ref LL_DMA_CHANNEL_3
1037 * @arg @ref LL_DMA_CHANNEL_4
1038 * @arg @ref LL_DMA_CHANNEL_5
1039 * @arg @ref LL_DMA_CHANNEL_6
1040 * @arg @ref LL_DMA_CHANNEL_7
1041 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1042 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel)1043 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1044 {
1045 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
1046 }
1047
1048 /**
1049 * @brief Get Peripheral address.
1050 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1051 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
1052 * @param DMAx DMAx Instance
1053 * @param Channel This parameter can be one of the following values:
1054 * @arg @ref LL_DMA_CHANNEL_1
1055 * @arg @ref LL_DMA_CHANNEL_2
1056 * @arg @ref LL_DMA_CHANNEL_3
1057 * @arg @ref LL_DMA_CHANNEL_4
1058 * @arg @ref LL_DMA_CHANNEL_5
1059 * @arg @ref LL_DMA_CHANNEL_6
1060 * @arg @ref LL_DMA_CHANNEL_7
1061 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1062 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel)1063 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1064 {
1065 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
1066 }
1067
1068 /**
1069 * @brief Set the Memory to Memory Source address.
1070 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1071 * @note This API must not be called when the DMA channel is enabled.
1072 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
1073 * @param DMAx DMAx Instance
1074 * @param Channel This parameter can be one of the following values:
1075 * @arg @ref LL_DMA_CHANNEL_1
1076 * @arg @ref LL_DMA_CHANNEL_2
1077 * @arg @ref LL_DMA_CHANNEL_3
1078 * @arg @ref LL_DMA_CHANNEL_4
1079 * @arg @ref LL_DMA_CHANNEL_5
1080 * @arg @ref LL_DMA_CHANNEL_6
1081 * @arg @ref LL_DMA_CHANNEL_7
1082 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1083 * @retval None
1084 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1085 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1086 {
1087 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
1088 }
1089
1090 /**
1091 * @brief Set the Memory to Memory Destination address.
1092 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1093 * @note This API must not be called when the DMA channel is enabled.
1094 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
1095 * @param DMAx DMAx Instance
1096 * @param Channel This parameter can be one of the following values:
1097 * @arg @ref LL_DMA_CHANNEL_1
1098 * @arg @ref LL_DMA_CHANNEL_2
1099 * @arg @ref LL_DMA_CHANNEL_3
1100 * @arg @ref LL_DMA_CHANNEL_4
1101 * @arg @ref LL_DMA_CHANNEL_5
1102 * @arg @ref LL_DMA_CHANNEL_6
1103 * @arg @ref LL_DMA_CHANNEL_7
1104 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1105 * @retval None
1106 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1107 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1108 {
1109 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
1110 }
1111
1112 /**
1113 * @brief Get the Memory to Memory Source address.
1114 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1115 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
1116 * @param DMAx DMAx Instance
1117 * @param Channel This parameter can be one of the following values:
1118 * @arg @ref LL_DMA_CHANNEL_1
1119 * @arg @ref LL_DMA_CHANNEL_2
1120 * @arg @ref LL_DMA_CHANNEL_3
1121 * @arg @ref LL_DMA_CHANNEL_4
1122 * @arg @ref LL_DMA_CHANNEL_5
1123 * @arg @ref LL_DMA_CHANNEL_6
1124 * @arg @ref LL_DMA_CHANNEL_7
1125 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1126 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel)1127 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1128 {
1129 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
1130 }
1131
1132 /**
1133 * @brief Get the Memory to Memory Destination address.
1134 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1135 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
1136 * @param DMAx DMAx Instance
1137 * @param Channel This parameter can be one of the following values:
1138 * @arg @ref LL_DMA_CHANNEL_1
1139 * @arg @ref LL_DMA_CHANNEL_2
1140 * @arg @ref LL_DMA_CHANNEL_3
1141 * @arg @ref LL_DMA_CHANNEL_4
1142 * @arg @ref LL_DMA_CHANNEL_5
1143 * @arg @ref LL_DMA_CHANNEL_6
1144 * @arg @ref LL_DMA_CHANNEL_7
1145 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1146 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel)1147 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1148 {
1149 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
1150 }
1151
1152
1153 /**
1154 * @}
1155 */
1156
1157 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1158 * @{
1159 */
1160
1161 /**
1162 * @brief Get Channel 1 global interrupt flag.
1163 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1164 * @param DMAx DMAx Instance
1165 * @retval State of bit (1 or 0).
1166 */
LL_DMA_IsActiveFlag_GI1(DMA_TypeDef * DMAx)1167 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1168 {
1169 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
1170 }
1171
1172 /**
1173 * @brief Get Channel 2 global interrupt flag.
1174 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1175 * @param DMAx DMAx Instance
1176 * @retval State of bit (1 or 0).
1177 */
LL_DMA_IsActiveFlag_GI2(DMA_TypeDef * DMAx)1178 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1179 {
1180 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
1181 }
1182
1183 /**
1184 * @brief Get Channel 3 global interrupt flag.
1185 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1186 * @param DMAx DMAx Instance
1187 * @retval State of bit (1 or 0).
1188 */
LL_DMA_IsActiveFlag_GI3(DMA_TypeDef * DMAx)1189 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1190 {
1191 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
1192 }
1193
1194 /**
1195 * @brief Get Channel 4 global interrupt flag.
1196 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
1197 * @param DMAx DMAx Instance
1198 * @retval State of bit (1 or 0).
1199 */
LL_DMA_IsActiveFlag_GI4(DMA_TypeDef * DMAx)1200 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
1201 {
1202 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
1203 }
1204
1205 /**
1206 * @brief Get Channel 5 global interrupt flag.
1207 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
1208 * @param DMAx DMAx Instance
1209 * @retval State of bit (1 or 0).
1210 */
LL_DMA_IsActiveFlag_GI5(DMA_TypeDef * DMAx)1211 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
1212 {
1213 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
1214 }
1215
1216 /**
1217 * @brief Get Channel 6 global interrupt flag.
1218 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
1219 * @param DMAx DMAx Instance
1220 * @retval State of bit (1 or 0).
1221 */
LL_DMA_IsActiveFlag_GI6(DMA_TypeDef * DMAx)1222 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
1223 {
1224 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
1225 }
1226
1227 /**
1228 * @brief Get Channel 7 global interrupt flag.
1229 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
1230 * @param DMAx DMAx Instance
1231 * @retval State of bit (1 or 0).
1232 */
LL_DMA_IsActiveFlag_GI7(DMA_TypeDef * DMAx)1233 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
1234 {
1235 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
1236 }
1237
1238 /**
1239 * @brief Get Channel 1 transfer complete flag.
1240 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
1241 * @param DMAx DMAx Instance
1242 * @retval State of bit (1 or 0).
1243 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)1244 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1245 {
1246 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
1247 }
1248
1249 /**
1250 * @brief Get Channel 2 transfer complete flag.
1251 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
1252 * @param DMAx DMAx Instance
1253 * @retval State of bit (1 or 0).
1254 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)1255 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1256 {
1257 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
1258 }
1259
1260 /**
1261 * @brief Get Channel 3 transfer complete flag.
1262 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
1263 * @param DMAx DMAx Instance
1264 * @retval State of bit (1 or 0).
1265 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)1266 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1267 {
1268 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
1269 }
1270
1271 /**
1272 * @brief Get Channel 4 transfer complete flag.
1273 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
1274 * @param DMAx DMAx Instance
1275 * @retval State of bit (1 or 0).
1276 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)1277 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1278 {
1279 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
1280 }
1281
1282 /**
1283 * @brief Get Channel 5 transfer complete flag.
1284 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
1285 * @param DMAx DMAx Instance
1286 * @retval State of bit (1 or 0).
1287 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)1288 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1289 {
1290 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
1291 }
1292
1293 /**
1294 * @brief Get Channel 6 transfer complete flag.
1295 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
1296 * @param DMAx DMAx Instance
1297 * @retval State of bit (1 or 0).
1298 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)1299 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1300 {
1301 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
1302 }
1303
1304 /**
1305 * @brief Get Channel 7 transfer complete flag.
1306 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
1307 * @param DMAx DMAx Instance
1308 * @retval State of bit (1 or 0).
1309 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)1310 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1311 {
1312 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
1313 }
1314
1315 /**
1316 * @brief Get Channel 1 half transfer flag.
1317 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
1318 * @param DMAx DMAx Instance
1319 * @retval State of bit (1 or 0).
1320 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1321 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1322 {
1323 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
1324 }
1325
1326 /**
1327 * @brief Get Channel 2 half transfer flag.
1328 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
1329 * @param DMAx DMAx Instance
1330 * @retval State of bit (1 or 0).
1331 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1332 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1333 {
1334 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
1335 }
1336
1337 /**
1338 * @brief Get Channel 3 half transfer flag.
1339 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
1340 * @param DMAx DMAx Instance
1341 * @retval State of bit (1 or 0).
1342 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1343 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1344 {
1345 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
1346 }
1347
1348 /**
1349 * @brief Get Channel 4 half transfer flag.
1350 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
1351 * @param DMAx DMAx Instance
1352 * @retval State of bit (1 or 0).
1353 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)1354 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1355 {
1356 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
1357 }
1358
1359 /**
1360 * @brief Get Channel 5 half transfer flag.
1361 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
1362 * @param DMAx DMAx Instance
1363 * @retval State of bit (1 or 0).
1364 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)1365 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1366 {
1367 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
1368 }
1369
1370 /**
1371 * @brief Get Channel 6 half transfer flag.
1372 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
1373 * @param DMAx DMAx Instance
1374 * @retval State of bit (1 or 0).
1375 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)1376 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1377 {
1378 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
1379 }
1380
1381 /**
1382 * @brief Get Channel 7 half transfer flag.
1383 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
1384 * @param DMAx DMAx Instance
1385 * @retval State of bit (1 or 0).
1386 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)1387 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1388 {
1389 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
1390 }
1391
1392 /**
1393 * @brief Get Channel 1 transfer error flag.
1394 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
1395 * @param DMAx DMAx Instance
1396 * @retval State of bit (1 or 0).
1397 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)1398 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1399 {
1400 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
1401 }
1402
1403 /**
1404 * @brief Get Channel 2 transfer error flag.
1405 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
1406 * @param DMAx DMAx Instance
1407 * @retval State of bit (1 or 0).
1408 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)1409 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1410 {
1411 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
1412 }
1413
1414 /**
1415 * @brief Get Channel 3 transfer error flag.
1416 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
1417 * @param DMAx DMAx Instance
1418 * @retval State of bit (1 or 0).
1419 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)1420 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1421 {
1422 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
1423 }
1424
1425 /**
1426 * @brief Get Channel 4 transfer error flag.
1427 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
1428 * @param DMAx DMAx Instance
1429 * @retval State of bit (1 or 0).
1430 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)1431 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1432 {
1433 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
1434 }
1435
1436 /**
1437 * @brief Get Channel 5 transfer error flag.
1438 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
1439 * @param DMAx DMAx Instance
1440 * @retval State of bit (1 or 0).
1441 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)1442 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1443 {
1444 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
1445 }
1446
1447 /**
1448 * @brief Get Channel 6 transfer error flag.
1449 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
1450 * @param DMAx DMAx Instance
1451 * @retval State of bit (1 or 0).
1452 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)1453 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1454 {
1455 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
1456 }
1457
1458 /**
1459 * @brief Get Channel 7 transfer error flag.
1460 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
1461 * @param DMAx DMAx Instance
1462 * @retval State of bit (1 or 0).
1463 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)1464 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1465 {
1466 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
1467 }
1468
1469 /**
1470 * @brief Clear Channel 1 global interrupt flag.
1471 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
1472 * @param DMAx DMAx Instance
1473 * @retval None
1474 */
LL_DMA_ClearFlag_GI1(DMA_TypeDef * DMAx)1475 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1476 {
1477 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1);
1478 }
1479
1480 /**
1481 * @brief Clear Channel 2 global interrupt flag.
1482 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
1483 * @param DMAx DMAx Instance
1484 * @retval None
1485 */
LL_DMA_ClearFlag_GI2(DMA_TypeDef * DMAx)1486 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1487 {
1488 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2);
1489 }
1490
1491 /**
1492 * @brief Clear Channel 3 global interrupt flag.
1493 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
1494 * @param DMAx DMAx Instance
1495 * @retval None
1496 */
LL_DMA_ClearFlag_GI3(DMA_TypeDef * DMAx)1497 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1498 {
1499 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3);
1500 }
1501
1502 /**
1503 * @brief Clear Channel 4 global interrupt flag.
1504 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
1505 * @param DMAx DMAx Instance
1506 * @retval None
1507 */
LL_DMA_ClearFlag_GI4(DMA_TypeDef * DMAx)1508 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
1509 {
1510 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4);
1511 }
1512
1513 /**
1514 * @brief Clear Channel 5 global interrupt flag.
1515 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
1516 * @param DMAx DMAx Instance
1517 * @retval None
1518 */
LL_DMA_ClearFlag_GI5(DMA_TypeDef * DMAx)1519 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
1520 {
1521 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5);
1522 }
1523
1524 /**
1525 * @brief Clear Channel 6 global interrupt flag.
1526 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
1527 * @param DMAx DMAx Instance
1528 * @retval None
1529 */
LL_DMA_ClearFlag_GI6(DMA_TypeDef * DMAx)1530 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
1531 {
1532 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6);
1533 }
1534
1535 /**
1536 * @brief Clear Channel 7 global interrupt flag.
1537 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
1538 * @param DMAx DMAx Instance
1539 * @retval None
1540 */
LL_DMA_ClearFlag_GI7(DMA_TypeDef * DMAx)1541 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
1542 {
1543 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7);
1544 }
1545
1546 /**
1547 * @brief Clear Channel 1 transfer complete flag.
1548 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
1549 * @param DMAx DMAx Instance
1550 * @retval None
1551 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)1552 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
1553 {
1554 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1);
1555 }
1556
1557 /**
1558 * @brief Clear Channel 2 transfer complete flag.
1559 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
1560 * @param DMAx DMAx Instance
1561 * @retval None
1562 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)1563 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
1564 {
1565 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2);
1566 }
1567
1568 /**
1569 * @brief Clear Channel 3 transfer complete flag.
1570 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
1571 * @param DMAx DMAx Instance
1572 * @retval None
1573 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)1574 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
1575 {
1576 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3);
1577 }
1578
1579 /**
1580 * @brief Clear Channel 4 transfer complete flag.
1581 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
1582 * @param DMAx DMAx Instance
1583 * @retval None
1584 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)1585 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
1586 {
1587 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4);
1588 }
1589
1590 /**
1591 * @brief Clear Channel 5 transfer complete flag.
1592 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
1593 * @param DMAx DMAx Instance
1594 * @retval None
1595 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)1596 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
1597 {
1598 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5);
1599 }
1600
1601 /**
1602 * @brief Clear Channel 6 transfer complete flag.
1603 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
1604 * @param DMAx DMAx Instance
1605 * @retval None
1606 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)1607 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
1608 {
1609 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6);
1610 }
1611
1612 /**
1613 * @brief Clear Channel 7 transfer complete flag.
1614 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
1615 * @param DMAx DMAx Instance
1616 * @retval None
1617 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)1618 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
1619 {
1620 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7);
1621 }
1622
1623 /**
1624 * @brief Clear Channel 1 half transfer flag.
1625 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
1626 * @param DMAx DMAx Instance
1627 * @retval None
1628 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)1629 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
1630 {
1631 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1);
1632 }
1633
1634 /**
1635 * @brief Clear Channel 2 half transfer flag.
1636 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
1637 * @param DMAx DMAx Instance
1638 * @retval None
1639 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)1640 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
1641 {
1642 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2);
1643 }
1644
1645 /**
1646 * @brief Clear Channel 3 half transfer flag.
1647 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
1648 * @param DMAx DMAx Instance
1649 * @retval None
1650 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)1651 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
1652 {
1653 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3);
1654 }
1655
1656 /**
1657 * @brief Clear Channel 4 half transfer flag.
1658 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
1659 * @param DMAx DMAx Instance
1660 * @retval None
1661 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)1662 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
1663 {
1664 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4);
1665 }
1666
1667 /**
1668 * @brief Clear Channel 5 half transfer flag.
1669 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
1670 * @param DMAx DMAx Instance
1671 * @retval None
1672 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)1673 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
1674 {
1675 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5);
1676 }
1677
1678 /**
1679 * @brief Clear Channel 6 half transfer flag.
1680 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
1681 * @param DMAx DMAx Instance
1682 * @retval None
1683 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)1684 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
1685 {
1686 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6);
1687 }
1688
1689 /**
1690 * @brief Clear Channel 7 half transfer flag.
1691 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
1692 * @param DMAx DMAx Instance
1693 * @retval None
1694 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)1695 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
1696 {
1697 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7);
1698 }
1699
1700 /**
1701 * @brief Clear Channel 1 transfer error flag.
1702 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
1703 * @param DMAx DMAx Instance
1704 * @retval None
1705 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)1706 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
1707 {
1708 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1);
1709 }
1710
1711 /**
1712 * @brief Clear Channel 2 transfer error flag.
1713 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
1714 * @param DMAx DMAx Instance
1715 * @retval None
1716 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)1717 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
1718 {
1719 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2);
1720 }
1721
1722 /**
1723 * @brief Clear Channel 3 transfer error flag.
1724 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
1725 * @param DMAx DMAx Instance
1726 * @retval None
1727 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)1728 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
1729 {
1730 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3);
1731 }
1732
1733 /**
1734 * @brief Clear Channel 4 transfer error flag.
1735 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
1736 * @param DMAx DMAx Instance
1737 * @retval None
1738 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)1739 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
1740 {
1741 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4);
1742 }
1743
1744 /**
1745 * @brief Clear Channel 5 transfer error flag.
1746 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
1747 * @param DMAx DMAx Instance
1748 * @retval None
1749 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)1750 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
1751 {
1752 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5);
1753 }
1754
1755 /**
1756 * @brief Clear Channel 6 transfer error flag.
1757 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
1758 * @param DMAx DMAx Instance
1759 * @retval None
1760 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)1761 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
1762 {
1763 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6);
1764 }
1765
1766 /**
1767 * @brief Clear Channel 7 transfer error flag.
1768 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
1769 * @param DMAx DMAx Instance
1770 * @retval None
1771 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)1772 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
1773 {
1774 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7);
1775 }
1776
1777 /**
1778 * @}
1779 */
1780
1781 /** @defgroup DMA_LL_EF_IT_Management IT_Management
1782 * @{
1783 */
1784 /**
1785 * @brief Enable Transfer complete interrupt.
1786 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
1787 * @param DMAx DMAx Instance
1788 * @param Channel This parameter can be one of the following values:
1789 * @arg @ref LL_DMA_CHANNEL_1
1790 * @arg @ref LL_DMA_CHANNEL_2
1791 * @arg @ref LL_DMA_CHANNEL_3
1792 * @arg @ref LL_DMA_CHANNEL_4
1793 * @arg @ref LL_DMA_CHANNEL_5
1794 * @arg @ref LL_DMA_CHANNEL_6
1795 * @arg @ref LL_DMA_CHANNEL_7
1796 * @retval None
1797 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1798 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1799 {
1800 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
1801 }
1802
1803 /**
1804 * @brief Enable Half transfer interrupt.
1805 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
1806 * @param DMAx DMAx Instance
1807 * @param Channel This parameter can be one of the following values:
1808 * @arg @ref LL_DMA_CHANNEL_1
1809 * @arg @ref LL_DMA_CHANNEL_2
1810 * @arg @ref LL_DMA_CHANNEL_3
1811 * @arg @ref LL_DMA_CHANNEL_4
1812 * @arg @ref LL_DMA_CHANNEL_5
1813 * @arg @ref LL_DMA_CHANNEL_6
1814 * @arg @ref LL_DMA_CHANNEL_7
1815 * @retval None
1816 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1817 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1818 {
1819 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
1820 }
1821
1822 /**
1823 * @brief Enable Transfer error interrupt.
1824 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
1825 * @param DMAx DMAx Instance
1826 * @param Channel This parameter can be one of the following values:
1827 * @arg @ref LL_DMA_CHANNEL_1
1828 * @arg @ref LL_DMA_CHANNEL_2
1829 * @arg @ref LL_DMA_CHANNEL_3
1830 * @arg @ref LL_DMA_CHANNEL_4
1831 * @arg @ref LL_DMA_CHANNEL_5
1832 * @arg @ref LL_DMA_CHANNEL_6
1833 * @arg @ref LL_DMA_CHANNEL_7
1834 * @retval None
1835 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1836 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1837 {
1838 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
1839 }
1840
1841 /**
1842 * @brief Disable Transfer complete interrupt.
1843 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
1844 * @param DMAx DMAx Instance
1845 * @param Channel This parameter can be one of the following values:
1846 * @arg @ref LL_DMA_CHANNEL_1
1847 * @arg @ref LL_DMA_CHANNEL_2
1848 * @arg @ref LL_DMA_CHANNEL_3
1849 * @arg @ref LL_DMA_CHANNEL_4
1850 * @arg @ref LL_DMA_CHANNEL_5
1851 * @arg @ref LL_DMA_CHANNEL_6
1852 * @arg @ref LL_DMA_CHANNEL_7
1853 * @retval None
1854 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1855 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1856 {
1857 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
1858 }
1859
1860 /**
1861 * @brief Disable Half transfer interrupt.
1862 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
1863 * @param DMAx DMAx Instance
1864 * @param Channel This parameter can be one of the following values:
1865 * @arg @ref LL_DMA_CHANNEL_1
1866 * @arg @ref LL_DMA_CHANNEL_2
1867 * @arg @ref LL_DMA_CHANNEL_3
1868 * @arg @ref LL_DMA_CHANNEL_4
1869 * @arg @ref LL_DMA_CHANNEL_5
1870 * @arg @ref LL_DMA_CHANNEL_6
1871 * @arg @ref LL_DMA_CHANNEL_7
1872 * @retval None
1873 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1874 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1875 {
1876 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
1877 }
1878
1879 /**
1880 * @brief Disable Transfer error interrupt.
1881 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
1882 * @param DMAx DMAx Instance
1883 * @param Channel This parameter can be one of the following values:
1884 * @arg @ref LL_DMA_CHANNEL_1
1885 * @arg @ref LL_DMA_CHANNEL_2
1886 * @arg @ref LL_DMA_CHANNEL_3
1887 * @arg @ref LL_DMA_CHANNEL_4
1888 * @arg @ref LL_DMA_CHANNEL_5
1889 * @arg @ref LL_DMA_CHANNEL_6
1890 * @arg @ref LL_DMA_CHANNEL_7
1891 * @retval None
1892 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1893 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1894 {
1895 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
1896 }
1897
1898 /**
1899 * @brief Check if Transfer complete Interrupt is enabled.
1900 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
1901 * @param DMAx DMAx Instance
1902 * @param Channel This parameter can be one of the following values:
1903 * @arg @ref LL_DMA_CHANNEL_1
1904 * @arg @ref LL_DMA_CHANNEL_2
1905 * @arg @ref LL_DMA_CHANNEL_3
1906 * @arg @ref LL_DMA_CHANNEL_4
1907 * @arg @ref LL_DMA_CHANNEL_5
1908 * @arg @ref LL_DMA_CHANNEL_6
1909 * @arg @ref LL_DMA_CHANNEL_7
1910 * @retval State of bit (1 or 0).
1911 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1912 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1913 {
1914 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1915 DMA_CCR_TCIE) == (DMA_CCR_TCIE));
1916 }
1917
1918 /**
1919 * @brief Check if Half transfer Interrupt is enabled.
1920 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
1921 * @param DMAx DMAx Instance
1922 * @param Channel This parameter can be one of the following values:
1923 * @arg @ref LL_DMA_CHANNEL_1
1924 * @arg @ref LL_DMA_CHANNEL_2
1925 * @arg @ref LL_DMA_CHANNEL_3
1926 * @arg @ref LL_DMA_CHANNEL_4
1927 * @arg @ref LL_DMA_CHANNEL_5
1928 * @arg @ref LL_DMA_CHANNEL_6
1929 * @arg @ref LL_DMA_CHANNEL_7
1930 * @retval State of bit (1 or 0).
1931 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1932 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1933 {
1934 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1935 DMA_CCR_HTIE) == (DMA_CCR_HTIE));
1936 }
1937
1938 /**
1939 * @brief Check if Transfer error Interrupt is enabled.
1940 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
1941 * @param DMAx DMAx Instance
1942 * @param Channel This parameter can be one of the following values:
1943 * @arg @ref LL_DMA_CHANNEL_1
1944 * @arg @ref LL_DMA_CHANNEL_2
1945 * @arg @ref LL_DMA_CHANNEL_3
1946 * @arg @ref LL_DMA_CHANNEL_4
1947 * @arg @ref LL_DMA_CHANNEL_5
1948 * @arg @ref LL_DMA_CHANNEL_6
1949 * @arg @ref LL_DMA_CHANNEL_7
1950 * @retval State of bit (1 or 0).
1951 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1952 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1953 {
1954 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1955 DMA_CCR_TEIE) == (DMA_CCR_TEIE));
1956 }
1957
1958 /**
1959 * @}
1960 */
1961
1962 #if defined(USE_FULL_LL_DRIVER)
1963 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
1964 * @{
1965 */
1966
1967 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
1968 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
1969 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
1970
1971 /**
1972 * @}
1973 */
1974 #endif /* USE_FULL_LL_DRIVER */
1975
1976 /**
1977 * @}
1978 */
1979
1980 /**
1981 * @}
1982 */
1983
1984 #endif /* DMA1 || DMA2 */
1985
1986 /**
1987 * @}
1988 */
1989
1990 #ifdef __cplusplus
1991 }
1992 #endif
1993
1994 #endif /* __STM32L1xx_LL_DMA_H */
1995
1996
