1 /** 2 ****************************************************************************** 3 * @file stm32l1xx_hal_flash_ex.h 4 * @author MCD Application Team 5 * @brief Header file of Flash HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32L1xx_HAL_FLASH_EX_H 20 #define __STM32L1xx_HAL_FLASH_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32l1xx_hal_def.h" 28 29 /** @addtogroup STM32L1xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup FLASHEx 34 * @{ 35 */ 36 37 /** @addtogroup FLASHEx_Private_Constants 38 * @{ 39 */ 40 #if defined(FLASH_SR_RDERR) && defined(FLASH_SR_OPTVERRUSR) 41 42 #define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ 43 FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ 44 FLASH_FLAG_OPTVERRUSR | FLASH_FLAG_RDERR) 45 46 #elif defined(FLASH_SR_RDERR) 47 48 #define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ 49 FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ 50 FLASH_FLAG_RDERR) 51 52 #elif defined(FLASH_SR_OPTVERRUSR) 53 54 #define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ 55 FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ 56 FLASH_FLAG_OPTVERRUSR) 57 58 #else 59 60 #define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ 61 FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR) 62 63 #endif /* FLASH_SR_RDERR & FLASH_SR_OPTVERRUSR */ 64 65 #if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \ 66 || defined(STM32L151xBA) || defined(STM32L152xBA) 67 68 /******* Devices with FLASH 128K *******/ 69 #define FLASH_NBPAGES_MAX 512U /* 512 pages from page 0 to page 511U */ 70 71 #elif defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ 72 || defined(STM32L151xCA) || defined(STM32L152xCA) || defined(STM32L162xCA) 73 74 /******* Devices with FLASH 256K *******/ 75 #define FLASH_NBPAGES_MAX 1024U /* 1024 pages from page 0 to page 1023U */ 76 77 #elif defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ 78 || defined(STM32L162xD) || defined(STM32L162xDX) 79 80 /******* Devices with FLASH 384K *******/ 81 #define FLASH_NBPAGES_MAX 1536U /* 1536 pages from page 0 to page 1535U */ 82 83 #elif defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) 84 85 /******* Devices with FLASH 512K *******/ 86 #define FLASH_NBPAGES_MAX 2048U /* 2048 pages from page 0 to page 2047U */ 87 88 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */ 89 90 #define WRP_MASK_LOW (0x0000FFFFU) 91 #define WRP_MASK_HIGH (0xFFFF0000U) 92 93 /** 94 * @} 95 */ 96 97 /** @addtogroup FLASHEx_Private_Macros 98 * @{ 99 */ 100 101 #define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES)) 102 103 #define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR))) 104 105 #define IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || \ 106 ((__VALUE__) == OB_WRPSTATE_ENABLE)) 107 108 #define IS_OB_WRP(__PAGE__) (((__PAGE__) != 0x0000000U)) 109 110 #define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) ||\ 111 ((__LEVEL__) == OB_RDP_LEVEL_1) ||\ 112 ((__LEVEL__) == OB_RDP_LEVEL_2)) 113 114 #define IS_OB_BOR_LEVEL(__LEVEL__) (((__LEVEL__) == OB_BOR_OFF) || \ 115 ((__LEVEL__) == OB_BOR_LEVEL1) || \ 116 ((__LEVEL__) == OB_BOR_LEVEL2) || \ 117 ((__LEVEL__) == OB_BOR_LEVEL3) || \ 118 ((__LEVEL__) == OB_BOR_LEVEL4) || \ 119 ((__LEVEL__) == OB_BOR_LEVEL5)) 120 121 #define IS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW)) 122 123 #define IS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST)) 124 125 #define IS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST)) 126 127 #if defined(FLASH_OBR_SPRMOD) && defined(FLASH_OBR_nRST_BFB2) 128 129 #define IS_OBEX(__VALUE__) (((__VALUE__) == OPTIONBYTE_PCROP) || ((__VALUE__) == OPTIONBYTE_BOOTCONFIG)) 130 131 #elif defined(FLASH_OBR_SPRMOD) && !defined(FLASH_OBR_nRST_BFB2) 132 133 #define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_PCROP) 134 135 #elif !defined(FLASH_OBR_SPRMOD) && defined(FLASH_OBR_nRST_BFB2) 136 137 #define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_BOOTCONFIG) 138 139 #endif /* FLASH_OBR_SPRMOD && FLASH_OBR_nRST_BFB2 */ 140 141 #if defined(FLASH_OBR_SPRMOD) 142 143 #define IS_PCROPSTATE(__VALUE__) (((__VALUE__) == OB_PCROP_STATE_DISABLE) || \ 144 ((__VALUE__) == OB_PCROP_STATE_ENABLE)) 145 146 #define IS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000U)) 147 #endif /* FLASH_OBR_SPRMOD */ 148 149 #if defined(FLASH_OBR_nRST_BFB2) 150 151 #define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1)) 152 153 #endif /* FLASH_OBR_nRST_BFB2 */ 154 155 #define IS_TYPEERASEDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEERASEDATA_BYTE) || \ 156 ((__VALUE__) == FLASH_TYPEERASEDATA_HALFWORD) || \ 157 ((__VALUE__) == FLASH_TYPEERASEDATA_WORD)) 158 #define IS_TYPEPROGRAMDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || \ 159 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \ 160 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD) || \ 161 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTBYTE) || \ 162 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTHALFWORD) || \ 163 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTWORD)) 164 165 166 /** @defgroup FLASHEx_Address FLASHEx Address 167 * @{ 168 */ 169 170 #define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_EEPROM_BASE) && ((__ADDRESS__) <= FLASH_EEPROM_END)) 171 172 #if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \ 173 || defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L100xC) || defined(STM32L151xC) \ 174 || defined(STM32L152xC) || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L152xCA) \ 175 || defined(STM32L162xCA) 176 177 #define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_END)) 178 179 #else /*STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ 180 181 #define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END)) 182 #define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK1_END)) 183 #define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END)) 184 185 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || (...) || STM32L151xCA || STM32L152xCA || STM32L162xCA */ 186 187 #define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1U) && ((__PAGES__) <= FLASH_NBPAGES_MAX)) 188 189 /** 190 * @} 191 */ 192 193 /** 194 * @} 195 */ 196 /* Exported types ------------------------------------------------------------*/ 197 198 /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types 199 * @{ 200 */ 201 202 /** 203 * @brief FLASH Erase structure definition 204 */ 205 typedef struct 206 { 207 uint32_t TypeErase; /*!< TypeErase: Page Erase only. 208 This parameter can be a value of @ref FLASHEx_Type_Erase */ 209 210 uint32_t PageAddress; /*!< PageAddress: Initial FLASH address to be erased 211 This parameter must be a value belonging to FLASH Program address (depending on the devices) */ 212 213 uint32_t NbPages; /*!< NbPages: Number of pages to be erased. 214 This parameter must be a value between 1 and (max number of pages - value of Initial page)*/ 215 216 } FLASH_EraseInitTypeDef; 217 218 /** 219 * @brief FLASH Option Bytes PROGRAM structure definition 220 */ 221 typedef struct 222 { 223 uint32_t OptionType; /*!< OptionType: Option byte to be configured. 224 This parameter can be a value of @ref FLASHEx_Option_Type */ 225 226 uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. 227 This parameter can be a value of @ref FLASHEx_WRP_State */ 228 229 uint32_t WRPSector0To31; /*!< WRPSector0To31: specifies the sector(s) which are write protected between Sector 0 to 31 230 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection1 */ 231 232 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ 233 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \ 234 || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \ 235 || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) 236 uint32_t WRPSector32To63; /*!< WRPSector32To63: specifies the sector(s) which are write protected between Sector 32 to 63 237 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */ 238 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */ 239 240 #if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ 241 || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ 242 || defined(STM32L162xE) 243 uint32_t WRPSector64To95; /*!< WRPSector64to95: specifies the sector(s) which are write protected between Sector 64 to 95 244 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection3 */ 245 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ 246 247 #if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \ 248 || defined(STM32L152xDX) || defined(STM32L162xDX) 249 uint32_t WRPSector96To127; /*!< WRPSector96To127: specifies the sector(s) which are write protected between Sector 96 to 127 or 250 Sectors 96 to 111 for STM32L1xxxDX devices. 251 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4 */ 252 #endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */ 253 254 uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level. 255 This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ 256 257 uint8_t BORLevel; /*!< BORLevel: Set the BOR Level. 258 This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */ 259 260 uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. 261 This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog, 262 @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/ 263 } FLASH_OBProgramInitTypeDef; 264 265 #if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2) 266 /** 267 * @brief FLASH Advanced Option Bytes Program structure definition 268 */ 269 typedef struct 270 { 271 uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension . 272 This parameter can be a value of @ref FLASHEx_OptionAdv_Type */ 273 274 #if defined(FLASH_OBR_SPRMOD) 275 uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation. 276 This parameter can be a value of @ref FLASHEx_PCROP_State */ 277 278 uint32_t PCROPSector0To31; /*!< PCROPSector0To31: specifies the sector(s) set for PCROP 279 This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 */ 280 281 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) 282 uint32_t PCROPSector32To63; /*!< PCROPSector32To63: specifies the sector(s) set for PCROP 283 This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */ 284 #endif /* STM32L151xC || STM32L152xC || STM32L162xC */ 285 #endif /* FLASH_OBR_SPRMOD */ 286 287 #if defined(FLASH_OBR_nRST_BFB2) 288 uint16_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config 289 This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */ 290 #endif /* FLASH_OBR_nRST_BFB2*/ 291 } FLASH_AdvOBProgramInitTypeDef; 292 293 /** 294 * @} 295 */ 296 #endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */ 297 298 /* Exported constants --------------------------------------------------------*/ 299 300 301 /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants 302 * @{ 303 */ 304 305 /** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase 306 * @{ 307 */ 308 #define FLASH_TYPEERASE_PAGES (0x00U) /*!<Page erase only*/ 309 310 /** 311 * @} 312 */ 313 314 /** @defgroup FLASHEx_Option_Type FLASHEx Option Type 315 * @{ 316 */ 317 #define OPTIONBYTE_WRP (0x01U) /*!<WRP option byte configuration*/ 318 #define OPTIONBYTE_RDP (0x02U) /*!<RDP option byte configuration*/ 319 #define OPTIONBYTE_USER (0x04U) /*!<USER option byte configuration*/ 320 #define OPTIONBYTE_BOR (0x08U) /*!<BOR option byte configuration*/ 321 322 /** 323 * @} 324 */ 325 326 /** @defgroup FLASHEx_WRP_State FLASHEx WRP State 327 * @{ 328 */ 329 #define OB_WRPSTATE_DISABLE (0x00U) /*!<Disable the write protection of the desired sectors*/ 330 #define OB_WRPSTATE_ENABLE (0x01U) /*!<Enable the write protection of the desired sectors*/ 331 332 /** 333 * @} 334 */ 335 336 /** @defgroup FLASHEx_Option_Bytes_Write_Protection1 FLASHEx Option Bytes Write Protection1 337 * @{ 338 */ 339 340 /* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */ 341 #define OB_WRP1_PAGES0TO15 (0x00000001U) /* Write protection of Sector0 */ 342 #define OB_WRP1_PAGES16TO31 (0x00000002U) /* Write protection of Sector1 */ 343 #define OB_WRP1_PAGES32TO47 (0x00000004U) /* Write protection of Sector2 */ 344 #define OB_WRP1_PAGES48TO63 (0x00000008U) /* Write protection of Sector3 */ 345 #define OB_WRP1_PAGES64TO79 (0x00000010U) /* Write protection of Sector4 */ 346 #define OB_WRP1_PAGES80TO95 (0x00000020U) /* Write protection of Sector5 */ 347 #define OB_WRP1_PAGES96TO111 (0x00000040U) /* Write protection of Sector6 */ 348 #define OB_WRP1_PAGES112TO127 (0x00000080U) /* Write protection of Sector7 */ 349 #define OB_WRP1_PAGES128TO143 (0x00000100U) /* Write protection of Sector8 */ 350 #define OB_WRP1_PAGES144TO159 (0x00000200U) /* Write protection of Sector9 */ 351 #define OB_WRP1_PAGES160TO175 (0x00000400U) /* Write protection of Sector10 */ 352 #define OB_WRP1_PAGES176TO191 (0x00000800U) /* Write protection of Sector11 */ 353 #define OB_WRP1_PAGES192TO207 (0x00001000U) /* Write protection of Sector12 */ 354 #define OB_WRP1_PAGES208TO223 (0x00002000U) /* Write protection of Sector13 */ 355 #define OB_WRP1_PAGES224TO239 (0x00004000U) /* Write protection of Sector14 */ 356 #define OB_WRP1_PAGES240TO255 (0x00008000U) /* Write protection of Sector15 */ 357 #define OB_WRP1_PAGES256TO271 (0x00010000U) /* Write protection of Sector16 */ 358 #define OB_WRP1_PAGES272TO287 (0x00020000U) /* Write protection of Sector17 */ 359 #define OB_WRP1_PAGES288TO303 (0x00040000U) /* Write protection of Sector18 */ 360 #define OB_WRP1_PAGES304TO319 (0x00080000U) /* Write protection of Sector19 */ 361 #define OB_WRP1_PAGES320TO335 (0x00100000U) /* Write protection of Sector20 */ 362 #define OB_WRP1_PAGES336TO351 (0x00200000U) /* Write protection of Sector21 */ 363 #define OB_WRP1_PAGES352TO367 (0x00400000U) /* Write protection of Sector22 */ 364 #define OB_WRP1_PAGES368TO383 (0x00800000U) /* Write protection of Sector23 */ 365 #define OB_WRP1_PAGES384TO399 (0x01000000U) /* Write protection of Sector24 */ 366 #define OB_WRP1_PAGES400TO415 (0x02000000U) /* Write protection of Sector25 */ 367 #define OB_WRP1_PAGES416TO431 (0x04000000U) /* Write protection of Sector26 */ 368 #define OB_WRP1_PAGES432TO447 (0x08000000U) /* Write protection of Sector27 */ 369 #define OB_WRP1_PAGES448TO463 (0x10000000U) /* Write protection of Sector28 */ 370 #define OB_WRP1_PAGES464TO479 (0x20000000U) /* Write protection of Sector29 */ 371 #define OB_WRP1_PAGES480TO495 (0x40000000U) /* Write protection of Sector30 */ 372 #define OB_WRP1_PAGES496TO511 (0x80000000U) /* Write protection of Sector31 */ 373 374 #define OB_WRP1_ALLPAGES ((uint32_t)FLASH_WRPR1_WRP) /*!< Write protection of all Sectors */ 375 376 /** 377 * @} 378 */ 379 380 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ 381 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \ 382 || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \ 383 || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) 384 385 /** @defgroup FLASHEx_Option_Bytes_Write_Protection2 FLASHEx Option Bytes Write Protection2 386 * @{ 387 */ 388 389 /* Pages for Cat3, Cat4 & Cat5 devices*/ 390 #define OB_WRP2_PAGES512TO527 (0x00000001U) /* Write protection of Sector32 */ 391 #define OB_WRP2_PAGES528TO543 (0x00000002U) /* Write protection of Sector33 */ 392 #define OB_WRP2_PAGES544TO559 (0x00000004U) /* Write protection of Sector34 */ 393 #define OB_WRP2_PAGES560TO575 (0x00000008U) /* Write protection of Sector35 */ 394 #define OB_WRP2_PAGES576TO591 (0x00000010U) /* Write protection of Sector36 */ 395 #define OB_WRP2_PAGES592TO607 (0x00000020U) /* Write protection of Sector37 */ 396 #define OB_WRP2_PAGES608TO623 (0x00000040U) /* Write protection of Sector38 */ 397 #define OB_WRP2_PAGES624TO639 (0x00000080U) /* Write protection of Sector39 */ 398 #define OB_WRP2_PAGES640TO655 (0x00000100U) /* Write protection of Sector40 */ 399 #define OB_WRP2_PAGES656TO671 (0x00000200U) /* Write protection of Sector41 */ 400 #define OB_WRP2_PAGES672TO687 (0x00000400U) /* Write protection of Sector42 */ 401 #define OB_WRP2_PAGES688TO703 (0x00000800U) /* Write protection of Sector43 */ 402 #define OB_WRP2_PAGES704TO719 (0x00001000U) /* Write protection of Sector44 */ 403 #define OB_WRP2_PAGES720TO735 (0x00002000U) /* Write protection of Sector45 */ 404 #define OB_WRP2_PAGES736TO751 (0x00004000U) /* Write protection of Sector46 */ 405 #define OB_WRP2_PAGES752TO767 (0x00008000U) /* Write protection of Sector47 */ 406 407 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ 408 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA) || defined(STM32L152xD) \ 409 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L152xE) \ 410 || defined(STM32L162xE) 411 412 #define OB_WRP2_PAGES768TO783 (0x00010000U) /* Write protection of Sector48 */ 413 #define OB_WRP2_PAGES784TO799 (0x00020000U) /* Write protection of Sector49 */ 414 #define OB_WRP2_PAGES800TO815 (0x00040000U) /* Write protection of Sector50 */ 415 #define OB_WRP2_PAGES816TO831 (0x00080000U) /* Write protection of Sector51 */ 416 #define OB_WRP2_PAGES832TO847 (0x00100000U) /* Write protection of Sector52 */ 417 #define OB_WRP2_PAGES848TO863 (0x00200000U) /* Write protection of Sector53 */ 418 #define OB_WRP2_PAGES864TO879 (0x00400000U) /* Write protection of Sector54 */ 419 #define OB_WRP2_PAGES880TO895 (0x00800000U) /* Write protection of Sector55 */ 420 #define OB_WRP2_PAGES896TO911 (0x01000000U) /* Write protection of Sector56 */ 421 #define OB_WRP2_PAGES912TO927 (0x02000000U) /* Write protection of Sector57 */ 422 #define OB_WRP2_PAGES928TO943 (0x04000000U) /* Write protection of Sector58 */ 423 #define OB_WRP2_PAGES944TO959 (0x08000000U) /* Write protection of Sector59 */ 424 #define OB_WRP2_PAGES960TO975 (0x10000000U) /* Write protection of Sector60 */ 425 #define OB_WRP2_PAGES976TO991 (0x20000000U) /* Write protection of Sector61 */ 426 #define OB_WRP2_PAGES992TO1007 (0x40000000U) /* Write protection of Sector62 */ 427 #define OB_WRP2_PAGES1008TO1023 (0x80000000U) /* Write protection of Sector63 */ 428 429 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ 430 431 #define OB_WRP2_ALLPAGES ((uint32_t)FLASH_WRPR2_WRP) /*!< Write protection of all Sectors */ 432 433 /** 434 * @} 435 */ 436 437 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L162xD || STM32L151xDX || STM32L152xE || STM32L162xE */ 438 439 #if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ 440 || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ 441 || defined(STM32L162xE) 442 443 /** @defgroup FLASHEx_Option_Bytes_Write_Protection3 FLASHEx Option Bytes Write Protection3 444 * @{ 445 */ 446 447 /* Pages for devices with FLASH >= 256KB*/ 448 #define OB_WRP3_PAGES1024TO1039 (0x00000001U) /* Write protection of Sector64 */ 449 #define OB_WRP3_PAGES1040TO1055 (0x00000002U) /* Write protection of Sector65 */ 450 #define OB_WRP3_PAGES1056TO1071 (0x00000004U) /* Write protection of Sector66 */ 451 #define OB_WRP3_PAGES1072TO1087 (0x00000008U) /* Write protection of Sector67 */ 452 #define OB_WRP3_PAGES1088TO1103 (0x00000010U) /* Write protection of Sector68 */ 453 #define OB_WRP3_PAGES1104TO1119 (0x00000020U) /* Write protection of Sector69 */ 454 #define OB_WRP3_PAGES1120TO1135 (0x00000040U) /* Write protection of Sector70 */ 455 #define OB_WRP3_PAGES1136TO1151 (0x00000080U) /* Write protection of Sector71 */ 456 #define OB_WRP3_PAGES1152TO1167 (0x00000100U) /* Write protection of Sector72 */ 457 #define OB_WRP3_PAGES1168TO1183 (0x00000200U) /* Write protection of Sector73 */ 458 #define OB_WRP3_PAGES1184TO1199 (0x00000400U) /* Write protection of Sector74 */ 459 #define OB_WRP3_PAGES1200TO1215 (0x00000800U) /* Write protection of Sector75 */ 460 #define OB_WRP3_PAGES1216TO1231 (0x00001000U) /* Write protection of Sector76 */ 461 #define OB_WRP3_PAGES1232TO1247 (0x00002000U) /* Write protection of Sector77 */ 462 #define OB_WRP3_PAGES1248TO1263 (0x00004000U) /* Write protection of Sector78 */ 463 #define OB_WRP3_PAGES1264TO1279 (0x00008000U) /* Write protection of Sector79 */ 464 #define OB_WRP3_PAGES1280TO1295 (0x00010000U) /* Write protection of Sector80 */ 465 #define OB_WRP3_PAGES1296TO1311 (0x00020000U) /* Write protection of Sector81 */ 466 #define OB_WRP3_PAGES1312TO1327 (0x00040000U) /* Write protection of Sector82 */ 467 #define OB_WRP3_PAGES1328TO1343 (0x00080000U) /* Write protection of Sector83 */ 468 #define OB_WRP3_PAGES1344TO1359 (0x00100000U) /* Write protection of Sector84 */ 469 #define OB_WRP3_PAGES1360TO1375 (0x00200000U) /* Write protection of Sector85 */ 470 #define OB_WRP3_PAGES1376TO1391 (0x00400000U) /* Write protection of Sector86 */ 471 #define OB_WRP3_PAGES1392TO1407 (0x00800000U) /* Write protection of Sector87 */ 472 #define OB_WRP3_PAGES1408TO1423 (0x01000000U) /* Write protection of Sector88 */ 473 #define OB_WRP3_PAGES1424TO1439 (0x02000000U) /* Write protection of Sector89 */ 474 #define OB_WRP3_PAGES1440TO1455 (0x04000000U) /* Write protection of Sector90 */ 475 #define OB_WRP3_PAGES1456TO1471 (0x08000000U) /* Write protection of Sector91 */ 476 #define OB_WRP3_PAGES1472TO1487 (0x10000000U) /* Write protection of Sector92 */ 477 #define OB_WRP3_PAGES1488TO1503 (0x20000000U) /* Write protection of Sector93 */ 478 #define OB_WRP3_PAGES1504TO1519 (0x40000000U) /* Write protection of Sector94 */ 479 #define OB_WRP3_PAGES1520TO1535 (0x80000000U) /* Write protection of Sector95 */ 480 481 #define OB_WRP3_ALLPAGES ((uint32_t)FLASH_WRPR3_WRP) /*!< Write protection of all Sectors */ 482 483 /** 484 * @} 485 */ 486 487 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/ 488 489 #if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \ 490 || defined(STM32L152xDX) || defined(STM32L162xDX) 491 492 /** @defgroup FLASHEx_Option_Bytes_Write_Protection4 FLASHEx Option Bytes Write Protection4 493 * @{ 494 */ 495 496 /* Pages for Cat5 devices*/ 497 #define OB_WRP4_PAGES1536TO1551 (0x00000001U)/* Write protection of Sector96*/ 498 #define OB_WRP4_PAGES1552TO1567 (0x00000002U)/* Write protection of Sector97*/ 499 #define OB_WRP4_PAGES1568TO1583 (0x00000004U)/* Write protection of Sector98*/ 500 #define OB_WRP4_PAGES1584TO1599 (0x00000008U)/* Write protection of Sector99*/ 501 #define OB_WRP4_PAGES1600TO1615 (0x00000010U) /* Write protection of Sector100*/ 502 #define OB_WRP4_PAGES1616TO1631 (0x00000020U) /* Write protection of Sector101*/ 503 #define OB_WRP4_PAGES1632TO1647 (0x00000040U) /* Write protection of Sector102*/ 504 #define OB_WRP4_PAGES1648TO1663 (0x00000080U) /* Write protection of Sector103*/ 505 #define OB_WRP4_PAGES1664TO1679 (0x00000100U) /* Write protection of Sector104*/ 506 #define OB_WRP4_PAGES1680TO1695 (0x00000200U) /* Write protection of Sector105*/ 507 #define OB_WRP4_PAGES1696TO1711 (0x00000400U) /* Write protection of Sector106*/ 508 #define OB_WRP4_PAGES1712TO1727 (0x00000800U) /* Write protection of Sector107*/ 509 #define OB_WRP4_PAGES1728TO1743 (0x00001000U) /* Write protection of Sector108*/ 510 #define OB_WRP4_PAGES1744TO1759 (0x00002000U) /* Write protection of Sector109*/ 511 #define OB_WRP4_PAGES1760TO1775 (0x00004000U) /* Write protection of Sector110*/ 512 #define OB_WRP4_PAGES1776TO1791 (0x00008000U) /* Write protection of Sector111*/ 513 514 #if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) 515 516 #define OB_WRP4_PAGES1792TO1807 (0x00010000U) /* Write protection of Sector112*/ 517 #define OB_WRP4_PAGES1808TO1823 (0x00020000U) /* Write protection of Sector113*/ 518 #define OB_WRP4_PAGES1824TO1839 (0x00040000U) /* Write protection of Sector114*/ 519 #define OB_WRP4_PAGES1840TO1855 (0x00080000U) /* Write protection of Sector115*/ 520 #define OB_WRP4_PAGES1856TO1871 (0x00100000U) /* Write protection of Sector116*/ 521 #define OB_WRP4_PAGES1872TO1887 (0x00200000U) /* Write protection of Sector117*/ 522 #define OB_WRP4_PAGES1888TO1903 (0x00400000U) /* Write protection of Sector118*/ 523 #define OB_WRP4_PAGES1904TO1919 (0x00800000U) /* Write protection of Sector119*/ 524 #define OB_WRP4_PAGES1920TO1935 (0x01000000U) /* Write protection of Sector120*/ 525 #define OB_WRP4_PAGES1936TO1951 (0x02000000U) /* Write protection of Sector121*/ 526 #define OB_WRP4_PAGES1952TO1967 (0x04000000U) /* Write protection of Sector122*/ 527 #define OB_WRP4_PAGES1968TO1983 (0x08000000U) /* Write protection of Sector123*/ 528 #define OB_WRP4_PAGES1984TO1999 (0x10000000U) /* Write protection of Sector124*/ 529 #define OB_WRP4_PAGES2000TO2015 (0x20000000U) /* Write protection of Sector125*/ 530 #define OB_WRP4_PAGES2016TO2031 (0x40000000U) /* Write protection of Sector126*/ 531 #define OB_WRP4_PAGES2032TO2047 (0x80000000U) /* Write protection of Sector127*/ 532 533 #endif /* STM32L151xE || STM32L152xE || STM32L162xE */ 534 535 #define OB_WRP4_ALLPAGES ((uint32_t)FLASH_WRPR4_WRP) /*!< Write protection of all Sectors */ 536 537 /** 538 * @} 539 */ 540 541 #endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */ 542 543 /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASHEx Option Bytes Read Protection 544 * @{ 545 */ 546 #define OB_RDP_LEVEL_0 ((uint8_t)0xAAU) 547 #define OB_RDP_LEVEL_1 ((uint8_t)0xBBU) 548 #define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /* Warning: When enabling read protection level 2 549 it is no more possible to go back to level 1 or 0 */ 550 551 /** 552 * @} 553 */ 554 555 /** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASHEx Option Bytes BOR Level 556 * @{ 557 */ 558 559 #define OB_BOR_OFF ((uint8_t)0x00U) /*!< BOR is disabled at power down, the reset is asserted when the VDD 560 power supply reaches the PDR(Power Down Reset) threshold (1.5V) */ 561 #define OB_BOR_LEVEL1 ((uint8_t)0x08U) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */ 562 #define OB_BOR_LEVEL2 ((uint8_t)0x09U) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */ 563 #define OB_BOR_LEVEL3 ((uint8_t)0x0AU) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */ 564 #define OB_BOR_LEVEL4 ((uint8_t)0x0BU) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */ 565 #define OB_BOR_LEVEL5 ((uint8_t)0x0CU) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */ 566 567 /** 568 * @} 569 */ 570 571 /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASHEx Option Bytes IWatchdog 572 * @{ 573 */ 574 575 #define OB_IWDG_SW ((uint8_t)0x10U) /*!< Software WDG selected */ 576 #define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware WDG selected */ 577 578 /** 579 * @} 580 */ 581 582 /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASHEx Option Bytes nRST_STOP 583 * @{ 584 */ 585 586 #define OB_STOP_NORST ((uint8_t)0x20U) /*!< No reset generated when entering in STOP */ 587 #define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */ 588 /** 589 * @} 590 */ 591 592 /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASHEx Option Bytes nRST_STDBY 593 * @{ 594 */ 595 596 #define OB_STDBY_NORST ((uint8_t)0x40U) /*!< No reset generated when entering in STANDBY */ 597 #define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */ 598 599 /** 600 * @} 601 */ 602 603 #if defined(FLASH_OBR_SPRMOD) 604 605 /** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type 606 * @{ 607 */ 608 609 #define OPTIONBYTE_PCROP (0x01U) /*!<PCROP option byte configuration*/ 610 611 /** 612 * @} 613 */ 614 615 #endif /* FLASH_OBR_SPRMOD */ 616 617 #if defined(FLASH_OBR_nRST_BFB2) 618 619 /** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type 620 * @{ 621 */ 622 623 #define OPTIONBYTE_BOOTCONFIG (0x02U) /*!<BOOTConfig option byte configuration*/ 624 625 /** 626 * @} 627 */ 628 629 #endif /* FLASH_OBR_nRST_BFB2 */ 630 631 #if defined(FLASH_OBR_SPRMOD) 632 633 /** @defgroup FLASHEx_PCROP_State FLASHEx PCROP State 634 * @{ 635 */ 636 #define OB_PCROP_STATE_DISABLE (0x00U) /*!<Disable PCROP for selected sectors */ 637 #define OB_PCROP_STATE_ENABLE (0x01U) /*!<Enable PCROP for selected sectors */ 638 639 /** 640 * @} 641 */ 642 643 /** @defgroup FLASHEx_Selection_Protection_Mode FLASHEx Selection Protection Mode 644 * @{ 645 */ 646 #define OB_PCROP_DESELECTED ((uint16_t)0x0000U) /*!< Disabled PCROP, nWPRi bits used for Write Protection on sector i */ 647 #define OB_PCROP_SELECTED ((uint16_t)FLASH_OBR_SPRMOD) /*!< Enable PCROP, nWPRi bits used for PCRoP Protection on sector i */ 648 649 /** 650 * @} 651 */ 652 #endif /* FLASH_OBR_SPRMOD */ 653 654 #if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \ 655 || defined(STM32L162xC) 656 /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 FLASHEx Option Bytes PC ReadWrite Protection 1 657 * @{ 658 */ 659 660 /* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */ 661 #define OB_PCROP1_PAGES0TO15 (0x00000001U) /* PC Read/Write protection of Sector0 */ 662 #define OB_PCROP1_PAGES16TO31 (0x00000002U) /* PC Read/Write protection of Sector1 */ 663 #define OB_PCROP1_PAGES32TO47 (0x00000004U) /* PC Read/Write protection of Sector2 */ 664 #define OB_PCROP1_PAGES48TO63 (0x00000008U) /* PC Read/Write protection of Sector3 */ 665 #define OB_PCROP1_PAGES64TO79 (0x00000010U) /* PC Read/Write protection of Sector4 */ 666 #define OB_PCROP1_PAGES80TO95 (0x00000020U) /* PC Read/Write protection of Sector5 */ 667 #define OB_PCROP1_PAGES96TO111 (0x00000040U) /* PC Read/Write protection of Sector6 */ 668 #define OB_PCROP1_PAGES112TO127 (0x00000080U) /* PC Read/Write protection of Sector7 */ 669 #define OB_PCROP1_PAGES128TO143 (0x00000100U) /* PC Read/Write protection of Sector8 */ 670 #define OB_PCROP1_PAGES144TO159 (0x00000200U) /* PC Read/Write protection of Sector9 */ 671 #define OB_PCROP1_PAGES160TO175 (0x00000400U) /* PC Read/Write protection of Sector10 */ 672 #define OB_PCROP1_PAGES176TO191 (0x00000800U) /* PC Read/Write protection of Sector11 */ 673 #define OB_PCROP1_PAGES192TO207 (0x00001000U) /* PC Read/Write protection of Sector12 */ 674 #define OB_PCROP1_PAGES208TO223 (0x00002000U) /* PC Read/Write protection of Sector13 */ 675 #define OB_PCROP1_PAGES224TO239 (0x00004000U) /* PC Read/Write protection of Sector14 */ 676 #define OB_PCROP1_PAGES240TO255 (0x00008000U) /* PC Read/Write protection of Sector15 */ 677 #define OB_PCROP1_PAGES256TO271 (0x00010000U) /* PC Read/Write protection of Sector16 */ 678 #define OB_PCROP1_PAGES272TO287 (0x00020000U) /* PC Read/Write protection of Sector17 */ 679 #define OB_PCROP1_PAGES288TO303 (0x00040000U) /* PC Read/Write protection of Sector18 */ 680 #define OB_PCROP1_PAGES304TO319 (0x00080000U) /* PC Read/Write protection of Sector19 */ 681 #define OB_PCROP1_PAGES320TO335 (0x00100000U) /* PC Read/Write protection of Sector20 */ 682 #define OB_PCROP1_PAGES336TO351 (0x00200000U) /* PC Read/Write protection of Sector21 */ 683 #define OB_PCROP1_PAGES352TO367 (0x00400000U) /* PC Read/Write protection of Sector22 */ 684 #define OB_PCROP1_PAGES368TO383 (0x00800000U) /* PC Read/Write protection of Sector23 */ 685 #define OB_PCROP1_PAGES384TO399 (0x01000000U) /* PC Read/Write protection of Sector24 */ 686 #define OB_PCROP1_PAGES400TO415 (0x02000000U) /* PC Read/Write protection of Sector25 */ 687 #define OB_PCROP1_PAGES416TO431 (0x04000000U) /* PC Read/Write protection of Sector26 */ 688 #define OB_PCROP1_PAGES432TO447 (0x08000000U) /* PC Read/Write protection of Sector27 */ 689 #define OB_PCROP1_PAGES448TO463 (0x10000000U) /* PC Read/Write protection of Sector28 */ 690 #define OB_PCROP1_PAGES464TO479 (0x20000000U) /* PC Read/Write protection of Sector29 */ 691 #define OB_PCROP1_PAGES480TO495 (0x40000000U) /* PC Read/Write protection of Sector30 */ 692 #define OB_PCROP1_PAGES496TO511 (0x80000000U) /* PC Read/Write protection of Sector31 */ 693 694 #define OB_PCROP1_ALLPAGES (0xFFFFFFFFU) /*!< PC Read/Write protection of all Sectors */ 695 696 /** 697 * @} 698 */ 699 #endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ 700 701 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) 702 703 /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 FLASHEx Option Bytes PC ReadWrite Protection 2 704 * @{ 705 */ 706 707 /* Pages for Cat3, Cat4 & Cat5 devices*/ 708 #define OB_PCROP2_PAGES512TO527 (0x00000001U) /* PC Read/Write protection of Sector32 */ 709 #define OB_PCROP2_PAGES528TO543 (0x00000002U) /* PC Read/Write protection of Sector33 */ 710 #define OB_PCROP2_PAGES544TO559 (0x00000004U) /* PC Read/Write protection of Sector34 */ 711 #define OB_PCROP2_PAGES560TO575 (0x00000008U) /* PC Read/Write protection of Sector35 */ 712 #define OB_PCROP2_PAGES576TO591 (0x00000010U) /* PC Read/Write protection of Sector36 */ 713 #define OB_PCROP2_PAGES592TO607 (0x00000020U) /* PC Read/Write protection of Sector37 */ 714 #define OB_PCROP2_PAGES608TO623 (0x00000040U) /* PC Read/Write protection of Sector38 */ 715 #define OB_PCROP2_PAGES624TO639 (0x00000080U) /* PC Read/Write protection of Sector39 */ 716 #define OB_PCROP2_PAGES640TO655 (0x00000100U) /* PC Read/Write protection of Sector40 */ 717 #define OB_PCROP2_PAGES656TO671 (0x00000200U) /* PC Read/Write protection of Sector41 */ 718 #define OB_PCROP2_PAGES672TO687 (0x00000400U) /* PC Read/Write protection of Sector42 */ 719 #define OB_PCROP2_PAGES688TO703 (0x00000800U) /* PC Read/Write protection of Sector43 */ 720 #define OB_PCROP2_PAGES704TO719 (0x00001000U) /* PC Read/Write protection of Sector44 */ 721 #define OB_PCROP2_PAGES720TO735 (0x00002000U) /* PC Read/Write protection of Sector45 */ 722 #define OB_PCROP2_PAGES736TO751 (0x00004000U) /* PC Read/Write protection of Sector46 */ 723 #define OB_PCROP2_PAGES752TO767 (0x00008000U) /* PC Read/Write protection of Sector47 */ 724 #define OB_PCROP2_PAGES768TO783 (0x00010000U) /* PC Read/Write protection of Sector48 */ 725 #define OB_PCROP2_PAGES784TO799 (0x00020000U) /* PC Read/Write protection of Sector49 */ 726 #define OB_PCROP2_PAGES800TO815 (0x00040000U) /* PC Read/Write protection of Sector50 */ 727 #define OB_PCROP2_PAGES816TO831 (0x00080000U) /* PC Read/Write protection of Sector51 */ 728 #define OB_PCROP2_PAGES832TO847 (0x00100000U) /* PC Read/Write protection of Sector52 */ 729 #define OB_PCROP2_PAGES848TO863 (0x00200000U) /* PC Read/Write protection of Sector53 */ 730 #define OB_PCROP2_PAGES864TO879 (0x00400000U) /* PC Read/Write protection of Sector54 */ 731 #define OB_PCROP2_PAGES880TO895 (0x00800000U) /* PC Read/Write protection of Sector55 */ 732 #define OB_PCROP2_PAGES896TO911 (0x01000000U) /* PC Read/Write protection of Sector56 */ 733 #define OB_PCROP2_PAGES912TO927 (0x02000000U) /* PC Read/Write protection of Sector57 */ 734 #define OB_PCROP2_PAGES928TO943 (0x04000000U) /* PC Read/Write protection of Sector58 */ 735 #define OB_PCROP2_PAGES944TO959 (0x08000000U) /* PC Read/Write protection of Sector59 */ 736 #define OB_PCROP2_PAGES960TO975 (0x10000000U) /* PC Read/Write protection of Sector60 */ 737 #define OB_PCROP2_PAGES976TO991 (0x20000000U) /* PC Read/Write protection of Sector61 */ 738 #define OB_PCROP2_PAGES992TO1007 (0x40000000U) /* PC Read/Write protection of Sector62 */ 739 #define OB_PCROP2_PAGES1008TO1023 (0x80000000U) /* PC Read/Write protection of Sector63 */ 740 741 #define OB_PCROP2_ALLPAGES (0xFFFFFFFFU) /*!< PC Read/Write protection of all Sectors */ 742 743 /** 744 * @} 745 */ 746 #endif /* STM32L151xC || STM32L152xC || STM32L162xC */ 747 748 /** @defgroup FLASHEx_Type_Erase_Data FLASHEx Type Erase Data 749 * @{ 750 */ 751 #define FLASH_TYPEERASEDATA_BYTE (0x00U) /*!<Erase byte (8-bit) at a specified address.*/ 752 #define FLASH_TYPEERASEDATA_HALFWORD (0x01U) /*!<Erase a half-word (16-bit) at a specified address.*/ 753 #define FLASH_TYPEERASEDATA_WORD (0x02U) /*!<Erase a word (32-bit) at a specified address.*/ 754 755 /** 756 * @} 757 */ 758 759 /** @defgroup FLASHEx_Type_Program_Data FLASHEx Type Program Data 760 * @{ 761 */ 762 #define FLASH_TYPEPROGRAMDATA_BYTE (0x00U) /*!<Program byte (8-bit) at a specified address.*/ 763 #define FLASH_TYPEPROGRAMDATA_HALFWORD (0x01U) /*!<Program a half-word (16-bit) at a specified address.*/ 764 #define FLASH_TYPEPROGRAMDATA_WORD (0x02U) /*!<Program a word (32-bit) at a specified address.*/ 765 #define FLASH_TYPEPROGRAMDATA_FASTBYTE (0x04U) /*!<Fast Program byte (8-bit) at a specified address.*/ 766 #define FLASH_TYPEPROGRAMDATA_FASTHALFWORD (0x08U) /*!<Fast Program a half-word (16-bit) at a specified address.*/ 767 #define FLASH_TYPEPROGRAMDATA_FASTWORD (0x10U) /*!<Fast Program a word (32-bit) at a specified address.*/ 768 769 /** 770 * @} 771 */ 772 773 #if defined(FLASH_OBR_nRST_BFB2) 774 775 /** @defgroup FLASHEx_Option_Bytes_BOOT FLASHEx Option Bytes BOOT 776 * @{ 777 */ 778 779 #define OB_BOOT_BANK2 ((uint8_t)0x00U) /*!< At startup, if boot pins are set in boot from user Flash position 780 and this parameter is selected the device will boot from Bank 2 781 or Bank 1, depending on the activation of the bank */ 782 #define OB_BOOT_BANK1 ((uint8_t)(FLASH_OBR_nRST_BFB2 >> 16U)) /*!< At startup, if boot pins are set in boot from user Flash position 783 and this parameter is selected the device will boot from Bank1(Default) */ 784 785 /** 786 * @} 787 */ 788 #endif /* FLASH_OBR_nRST_BFB2 */ 789 790 /** 791 * @} 792 */ 793 794 /* Exported macro ------------------------------------------------------------*/ 795 796 /** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros 797 * @{ 798 */ 799 800 /** 801 * @brief Set the FLASH Latency. 802 * @param __LATENCY__ FLASH Latency 803 * This parameter can be one of the following values: 804 * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle 805 * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle 806 * @retval none 807 */ 808 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) do { \ 809 if ((__LATENCY__) == FLASH_LATENCY_1) {__HAL_FLASH_ACC64_ENABLE();} \ 810 MODIFY_REG((FLASH->ACR), FLASH_ACR_LATENCY, (__LATENCY__)); \ 811 } while(0U) 812 813 /** 814 * @brief Get the FLASH Latency. 815 * @retval FLASH Latency 816 * This parameter can be one of the following values: 817 * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle 818 * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle 819 */ 820 #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) 821 822 /** 823 * @brief Enable the FLASH 64-bit access. 824 * @note Read access 64 bit is used. 825 * @note This bit cannot be written at the same time as the LATENCY and 826 * PRFTEN bits. 827 * @retval none 828 */ 829 #define __HAL_FLASH_ACC64_ENABLE() (SET_BIT((FLASH->ACR), FLASH_ACR_ACC64)) 830 831 /** 832 * @brief Disable the FLASH 64-bit access. 833 * @note Read access 32 bit is used 834 * @note To reset this bit, the LATENCY should be zero wait state and the 835 * prefetch off. 836 * @retval none 837 */ 838 #define __HAL_FLASH_ACC64_DISABLE() (CLEAR_BIT((FLASH->ACR), FLASH_ACR_ACC64)) 839 840 /** 841 * @brief Enable the FLASH prefetch buffer. 842 * @retval none 843 */ 844 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() do { __HAL_FLASH_ACC64_ENABLE(); \ 845 SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN); \ 846 } while(0U) 847 848 /** 849 * @brief Disable the FLASH prefetch buffer. 850 * @retval none 851 */ 852 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN) 853 854 /** 855 * @brief Enable the FLASH power down during Sleep mode 856 * @retval none 857 */ 858 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 859 860 /** 861 * @brief Disable the FLASH power down during Sleep mode 862 * @retval none 863 */ 864 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 865 866 /** 867 * @brief Enable the Flash Run power down mode. 868 * @note Writing this bit to 0 this bit, automatically the keys are 869 * loss and a new unlock sequence is necessary to re-write it to 1. 870 */ 871 #define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \ 872 FLASH->PDKEYR = FLASH_PDKEY2; \ 873 SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \ 874 } while (0U) 875 876 /** 877 * @brief Disable the Flash Run power down mode. 878 * @note Writing this bit to 0 this bit, automatically the keys are 879 * loss and a new unlock sequence is necessary to re-write it to 1. 880 */ 881 #define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \ 882 FLASH->PDKEYR = FLASH_PDKEY2; \ 883 CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \ 884 } while (0U) 885 886 /** 887 * @} 888 */ 889 890 /* Exported functions --------------------------------------------------------*/ 891 892 /** @addtogroup FLASHEx_Exported_Functions 893 * @{ 894 */ 895 896 /** @addtogroup FLASHEx_Exported_Functions_Group1 897 * @{ 898 */ 899 900 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); 901 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); 902 903 /** 904 * @} 905 */ 906 907 /** @addtogroup FLASHEx_Exported_Functions_Group2 908 * @{ 909 */ 910 911 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); 912 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); 913 914 #if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2) 915 916 HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); 917 void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); 918 919 #endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */ 920 921 #if defined(FLASH_OBR_SPRMOD) 922 923 HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void); 924 HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void); 925 926 #endif /* FLASH_OBR_SPRMOD */ 927 928 /** 929 * @} 930 */ 931 932 /** @addtogroup FLASHEx_Exported_Functions_Group3 933 * @{ 934 */ 935 936 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void); 937 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void); 938 939 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address); 940 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data); 941 void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void); 942 void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void); 943 944 /** 945 * @} 946 */ 947 948 /** 949 * @} 950 */ 951 952 /** 953 * @} 954 */ 955 956 /** 957 * @} 958 */ 959 960 #ifdef __cplusplus 961 } 962 #endif 963 964 #endif /* __STM32L1xx_HAL_FLASH_EX_H */ 965 966
