1 /** 2 ****************************************************************************** 3 * @file stm32l1xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L1xx_HAL_DMA_H 21 #define STM32L1xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l1xx_hal_def.h" 29 30 /** @addtogroup STM32L1xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup DMA_Exported_Types DMA Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief DMA Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 49 from memory to memory or from peripheral to memory. 50 This parameter can be a value of @ref DMA_Data_transfer_direction */ 51 52 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 53 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 54 55 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 56 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 57 58 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 59 This parameter can be a value of @ref DMA_Peripheral_data_size */ 60 61 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 62 This parameter can be a value of @ref DMA_Memory_data_size */ 63 64 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 65 This parameter can be a value of @ref DMA_mode 66 @note The circular buffer mode cannot be used if the memory-to-memory 67 data transfer is configured on the selected Channel */ 68 69 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 70 This parameter can be a value of @ref DMA_Priority_level */ 71 } DMA_InitTypeDef; 72 73 /** 74 * @brief HAL DMA State structures definition 75 */ 76 typedef enum 77 { 78 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 79 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 80 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 81 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 82 }HAL_DMA_StateTypeDef; 83 84 /** 85 * @brief HAL DMA Error Code structure definition 86 */ 87 typedef enum 88 { 89 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 90 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 91 }HAL_DMA_LevelCompleteTypeDef; 92 93 94 /** 95 * @brief HAL DMA Callback ID structure definition 96 */ 97 typedef enum 98 { 99 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 100 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 101 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 102 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 103 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 104 }HAL_DMA_CallbackIDTypeDef; 105 106 /** 107 * @brief DMA handle Structure definition 108 */ 109 typedef struct __DMA_HandleTypeDef 110 { 111 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 112 113 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 114 115 HAL_LockTypeDef Lock; /*!< DMA locking object */ 116 117 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 118 119 void *Parent; /*!< Parent object state */ 120 121 void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 122 123 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 124 125 void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 126 127 void (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ 128 129 __IO uint32_t ErrorCode; /*!< DMA Error code */ 130 131 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 132 133 uint32_t ChannelIndex; /*!< DMA Channel Index */ 134 135 }DMA_HandleTypeDef; 136 137 /** 138 * @} 139 */ 140 141 /* Exported constants --------------------------------------------------------*/ 142 143 /** @defgroup DMA_Exported_Constants DMA Exported Constants 144 * @{ 145 */ 146 147 /** @defgroup DMA_Error_Code DMA Error Code 148 * @{ 149 */ 150 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 151 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 152 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ 153 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 154 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 155 156 /** 157 * @} 158 */ 159 160 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 161 * @{ 162 */ 163 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 164 #define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ 165 #define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ 166 /** 167 * @} 168 */ 169 170 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 171 * @{ 172 */ 173 #define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ 174 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ 175 /** 176 * @} 177 */ 178 179 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 180 * @{ 181 */ 182 #define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ 183 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ 184 /** 185 * @} 186 */ 187 188 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 189 * @{ 190 */ 191 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 192 #define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 193 #define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 194 /** 195 * @} 196 */ 197 198 /** @defgroup DMA_Memory_data_size DMA Memory data size 199 * @{ 200 */ 201 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 202 #define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 203 #define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ 204 /** 205 * @} 206 */ 207 208 /** @defgroup DMA_mode DMA mode 209 * @{ 210 */ 211 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 212 #define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */ 213 /** 214 * @} 215 */ 216 217 /** @defgroup DMA_Priority_level DMA Priority level 218 * @{ 219 */ 220 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 221 #define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ 222 #define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ 223 #define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */ 224 /** 225 * @} 226 */ 227 228 229 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 230 * @{ 231 */ 232 #define DMA_IT_TC DMA_CCR_TCIE 233 #define DMA_IT_HT DMA_CCR_HTIE 234 #define DMA_IT_TE DMA_CCR_TEIE 235 /** 236 * @} 237 */ 238 239 /** @defgroup DMA_flag_definitions DMA flag definitions 240 * @{ 241 */ 242 #define DMA_FLAG_GL1 DMA_ISR_GIF1 243 #define DMA_FLAG_TC1 DMA_ISR_TCIF1 244 #define DMA_FLAG_HT1 DMA_ISR_HTIF1 245 #define DMA_FLAG_TE1 DMA_ISR_TEIF1 246 #define DMA_FLAG_GL2 DMA_ISR_GIF2 247 #define DMA_FLAG_TC2 DMA_ISR_TCIF2 248 #define DMA_FLAG_HT2 DMA_ISR_HTIF2 249 #define DMA_FLAG_TE2 DMA_ISR_TEIF2 250 #define DMA_FLAG_GL3 DMA_ISR_GIF3 251 #define DMA_FLAG_TC3 DMA_ISR_TCIF3 252 #define DMA_FLAG_HT3 DMA_ISR_HTIF3 253 #define DMA_FLAG_TE3 DMA_ISR_TEIF3 254 #define DMA_FLAG_GL4 DMA_ISR_GIF4 255 #define DMA_FLAG_TC4 DMA_ISR_TCIF4 256 #define DMA_FLAG_HT4 DMA_ISR_HTIF4 257 #define DMA_FLAG_TE4 DMA_ISR_TEIF4 258 #define DMA_FLAG_GL5 DMA_ISR_GIF5 259 #define DMA_FLAG_TC5 DMA_ISR_TCIF5 260 #define DMA_FLAG_HT5 DMA_ISR_HTIF5 261 #define DMA_FLAG_TE5 DMA_ISR_TEIF5 262 #define DMA_FLAG_GL6 DMA_ISR_GIF6 263 #define DMA_FLAG_TC6 DMA_ISR_TCIF6 264 #define DMA_FLAG_HT6 DMA_ISR_HTIF6 265 #define DMA_FLAG_TE6 DMA_ISR_TEIF6 266 #define DMA_FLAG_GL7 DMA_ISR_GIF7 267 #define DMA_FLAG_TC7 DMA_ISR_TCIF7 268 #define DMA_FLAG_HT7 DMA_ISR_HTIF7 269 #define DMA_FLAG_TE7 DMA_ISR_TEIF7 270 /** 271 * @} 272 */ 273 274 /** 275 * @} 276 */ 277 278 /* Exported macros -----------------------------------------------------------*/ 279 /** @defgroup DMA_Exported_Macros DMA Exported Macros 280 * @{ 281 */ 282 283 /** @brief Reset DMA handle state. 284 * @param __HANDLE__ DMA handle 285 * @retval None 286 */ 287 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 288 289 /** 290 * @brief Enable the specified DMA Channel. 291 * @param __HANDLE__ DMA handle 292 * @retval None 293 */ 294 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 295 296 /** 297 * @brief Disable the specified DMA Channel. 298 * @param __HANDLE__ DMA handle 299 * @retval None 300 */ 301 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 302 303 304 /* Interrupt & Flag management */ 305 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ 306 defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ 307 defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 308 309 /** 310 * @brief Return the current DMA Channel transfer complete flag. 311 * @param __HANDLE__ DMA handle 312 * @retval The specified transfer complete flag index. 313 */ 314 315 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 316 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 317 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ 318 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 319 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ 320 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 321 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ 322 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 323 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ 324 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 325 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ 326 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 327 DMA_FLAG_TC7) 328 329 /** 330 * @brief Return the current DMA Channel half transfer complete flag. 331 * @param __HANDLE__ DMA handle 332 * @retval The specified half transfer complete flag index. 333 */ 334 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 335 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 336 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ 337 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 338 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ 339 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 340 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ 341 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 342 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ 343 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 344 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ 345 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 346 DMA_FLAG_HT7) 347 348 /** 349 * @brief Return the current DMA Channel transfer error flag. 350 * @param __HANDLE__ DMA handle 351 * @retval The specified transfer error flag index. 352 */ 353 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 354 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 355 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ 356 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 357 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ 358 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 359 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ 360 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 361 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ 362 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 363 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ 364 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 365 DMA_FLAG_TE7) 366 367 /** 368 * @brief Return the current DMA Channel Global interrupt flag. 369 * @param __HANDLE__ DMA handle 370 * @retval The specified transfer error flag index. 371 */ 372 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 373 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 374 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ 375 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 376 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ 377 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 378 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ 379 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 380 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ 381 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ 382 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ 383 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ 384 DMA_ISR_GIF7) 385 386 /** 387 * @brief Get the DMA Channel pending flags. 388 * @param __HANDLE__ DMA handle 389 * @param __FLAG__ Get the specified flag. 390 * This parameter can be any combination of the following values: 391 * @arg DMA_FLAG_TCx: Transfer complete flag 392 * @arg DMA_FLAG_HTx: Half transfer complete flag 393 * @arg DMA_FLAG_TEx: Transfer error flag 394 * @arg DMA_FLAG_GLx: Global interrupt flag 395 * Where x can be from 1 to 7 to select the DMA Channel x flag. 396 * @retval The state of FLAG (SET or RESET). 397 */ 398 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 399 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) 400 401 /** 402 * @brief Clear the DMA Channel pending flags. 403 * @param __HANDLE__ DMA handle 404 * @param __FLAG__ specifies the flag to clear. 405 * This parameter can be any combination of the following values: 406 * @arg DMA_FLAG_TCx: Transfer complete flag 407 * @arg DMA_FLAG_HTx: Half transfer complete flag 408 * @arg DMA_FLAG_TEx: Transfer error flag 409 * @arg DMA_FLAG_GLx: Global interrupt flag 410 * Where x can be from 1 to 7 to select the DMA Channel x flag. 411 * @retval None 412 */ 413 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 414 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) 415 416 #else 417 /** 418 * @brief Return the current DMA Channel transfer complete flag. 419 * @param __HANDLE__ DMA handle 420 * @retval The specified transfer complete flag index. 421 */ 422 423 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 424 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 425 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 426 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 427 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 428 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 429 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 430 DMA_FLAG_TC7) 431 432 /** 433 * @brief Return the current DMA Channel half transfer complete flag. 434 * @param __HANDLE__ DMA handle 435 * @retval The specified half transfer complete flag index. 436 */ 437 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 438 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 439 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 440 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 441 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 442 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 443 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 444 DMA_FLAG_HT7) 445 446 /** 447 * @brief Return the current DMA Channel transfer error flag. 448 * @param __HANDLE__ DMA handle 449 * @retval The specified transfer error flag index. 450 */ 451 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 452 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 455 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 458 DMA_FLAG_TE7) 459 460 /** 461 * @brief Return the current DMA Channel Global interrupt flag. 462 * @param __HANDLE__ DMA handle 463 * @retval The specified transfer error flag index. 464 */ 465 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 466 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ 471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ 472 DMA_ISR_GIF7) 473 474 /** 475 * @brief Get the DMA Channel pending flags. 476 * @param __HANDLE__ DMA handle 477 * @param __FLAG__ Get the specified flag. 478 * This parameter can be any combination of the following values: 479 * @arg DMA_FLAG_TCIFx: Transfer complete flag 480 * @arg DMA_FLAG_HTIFx: Half transfer complete flag 481 * @arg DMA_FLAG_TEIFx: Transfer error flag 482 * @arg DMA_ISR_GIFx: Global interrupt flag 483 * Where x can be from 1 to 7 to select the DMA Channel x flag. 484 * @retval The state of FLAG (SET or RESET). 485 */ 486 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) 487 488 /** 489 * @brief Clear the DMA Channel pending flags. 490 * @param __HANDLE__ DMA handle 491 * @param __FLAG__ specifies the flag to clear. 492 * This parameter can be any combination of the following values: 493 * @arg DMA_FLAG_TCx: Transfer complete flag 494 * @arg DMA_FLAG_HTx: Half transfer complete flag 495 * @arg DMA_FLAG_TEx: Transfer error flag 496 * @arg DMA_FLAG_GLx: Global interrupt flag 497 * Where x can be from 1 to 7 to select the DMA Channel x flag. 498 * @retval None 499 */ 500 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) 501 502 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 503 504 /** 505 * @brief Enable the specified DMA Channel interrupts. 506 * @param __HANDLE__ DMA handle 507 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 508 * This parameter can be any combination of the following values: 509 * @arg DMA_IT_TC: Transfer complete interrupt mask 510 * @arg DMA_IT_HT: Half transfer complete interrupt mask 511 * @arg DMA_IT_TE: Transfer error interrupt mask 512 * @retval None 513 */ 514 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 515 516 /** 517 * @brief Disable the specified DMA Channel interrupts. 518 * @param __HANDLE__ DMA handle 519 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 520 * This parameter can be any combination of the following values: 521 * @arg DMA_IT_TC: Transfer complete interrupt mask 522 * @arg DMA_IT_HT: Half transfer complete interrupt mask 523 * @arg DMA_IT_TE: Transfer error interrupt mask 524 * @retval None 525 */ 526 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 527 528 /** 529 * @brief Check whether the specified DMA Channel interrupt is enabled or not. 530 * @param __HANDLE__ DMA handle 531 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 532 * This parameter can be one of the following values: 533 * @arg DMA_IT_TC: Transfer complete interrupt mask 534 * @arg DMA_IT_HT: Half transfer complete interrupt mask 535 * @arg DMA_IT_TE: Transfer error interrupt mask 536 * @retval The state of DMA_IT (SET or RESET). 537 */ 538 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 539 540 /** 541 * @brief Return the number of remaining data units in the current DMA Channel transfer. 542 * @param __HANDLE__ DMA handle 543 * @retval The number of remaining data units in the current DMA Channel transfer. 544 */ 545 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 546 547 /** 548 * @} 549 */ 550 551 /* Exported functions --------------------------------------------------------*/ 552 553 /** @addtogroup DMA_Exported_Functions 554 * @{ 555 */ 556 557 /** @addtogroup DMA_Exported_Functions_Group1 558 * @{ 559 */ 560 /* Initialization and de-initialization functions *****************************/ 561 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 562 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); 563 /** 564 * @} 565 */ 566 567 /** @addtogroup DMA_Exported_Functions_Group2 568 * @{ 569 */ 570 /* IO operation functions *****************************************************/ 571 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 572 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 573 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 574 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 575 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 576 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 577 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); 578 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 579 580 /** 581 * @} 582 */ 583 584 /** @addtogroup DMA_Exported_Functions_Group3 585 * @{ 586 */ 587 /* Peripheral State and Error functions ***************************************/ 588 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 589 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 590 /** 591 * @} 592 */ 593 594 /** 595 * @} 596 */ 597 598 /* Private macros ------------------------------------------------------------*/ 599 /** @defgroup DMA_Private_Macros DMA Private Macros 600 * @{ 601 */ 602 603 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 604 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 605 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 606 607 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) 608 609 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 610 ((STATE) == DMA_PINC_DISABLE)) 611 612 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 613 ((STATE) == DMA_MINC_DISABLE)) 614 615 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 616 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 617 ((SIZE) == DMA_PDATAALIGN_WORD)) 618 619 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 620 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 621 ((SIZE) == DMA_MDATAALIGN_WORD )) 622 623 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 624 ((MODE) == DMA_CIRCULAR)) 625 626 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 627 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 628 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 629 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 630 631 /** 632 * @} 633 */ 634 635 /* Private functions ---------------------------------------------------------*/ 636 637 /** 638 * @} 639 */ 640 641 /** 642 * @} 643 */ 644 645 #ifdef __cplusplus 646 } 647 #endif 648 649 #endif /* STM32L1xx_HAL_DMA_H */ 650 651
