1 /** 2 ****************************************************************************** 3 * @file stm32l1xx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32L1xx_HAL_CORTEX_H 21 #define __STM32L1xx_HAL_CORTEX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l1xx_hal_def.h" 29 30 /** @addtogroup STM32L1xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup CORTEX 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup CORTEX_Exported_Types Cortex Exported Types 40 * @{ 41 */ 42 43 #if (__MPU_PRESENT == 1) 44 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 45 * @brief MPU Region initialization structure 46 * @{ 47 */ 48 typedef struct 49 { 50 uint8_t Enable; /*!< Specifies the status of the region. 51 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 52 uint8_t Number; /*!< Specifies the number of the region to protect. 53 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 54 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 55 uint8_t Size; /*!< Specifies the size of the region to protect. 56 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 57 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. 58 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 59 uint8_t TypeExtField; /*!< Specifies the TEX field level. 60 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ 61 uint8_t AccessPermission; /*!< Specifies the region access permission type. 62 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 63 uint8_t DisableExec; /*!< Specifies the instruction access status. 64 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 65 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 66 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 67 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. 68 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ 69 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. 70 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ 71 }MPU_Region_InitTypeDef; 72 /** 73 * @} 74 */ 75 #endif /* __MPU_PRESENT */ 76 77 /** 78 * @} 79 */ 80 81 /* Exported constants --------------------------------------------------------*/ 82 83 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 84 * @{ 85 */ 86 87 88 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 89 * @{ 90 */ 91 92 #define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bits for pre-emption priority 93 4 bits for subpriority */ 94 #define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bits for pre-emption priority 95 3 bits for subpriority */ 96 #define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority 97 2 bits for subpriority */ 98 #define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority 99 1 bits for subpriority */ 100 #define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority 101 0 bits for subpriority */ 102 /** 103 * @} 104 */ 105 106 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 107 * @{ 108 */ 109 #define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U) 110 #define SYSTICK_CLKSOURCE_HCLK (0x00000004U) 111 112 /** 113 * @} 114 */ 115 116 #if (__MPU_PRESENT == 1) 117 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control 118 * @{ 119 */ 120 #define MPU_HFNMI_PRIVDEF_NONE (0x00000000U) 121 #define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk) 122 #define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk) 123 #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) 124 125 /** 126 * @} 127 */ 128 129 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 130 * @{ 131 */ 132 #define MPU_REGION_ENABLE ((uint8_t)0x01) 133 #define MPU_REGION_DISABLE ((uint8_t)0x00) 134 /** 135 * @} 136 */ 137 138 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 139 * @{ 140 */ 141 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) 142 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) 143 /** 144 * @} 145 */ 146 147 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 148 * @{ 149 */ 150 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) 151 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) 152 /** 153 * @} 154 */ 155 156 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 157 * @{ 158 */ 159 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) 160 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) 161 /** 162 * @} 163 */ 164 165 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 166 * @{ 167 */ 168 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) 169 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) 170 /** 171 * @} 172 */ 173 174 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels 175 * @{ 176 */ 177 #define MPU_TEX_LEVEL0 ((uint8_t)0x00) 178 #define MPU_TEX_LEVEL1 ((uint8_t)0x01) 179 #define MPU_TEX_LEVEL2 ((uint8_t)0x02) 180 /** 181 * @} 182 */ 183 184 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 185 * @{ 186 */ 187 #define MPU_REGION_SIZE_32B ((uint8_t)0x04) 188 #define MPU_REGION_SIZE_64B ((uint8_t)0x05) 189 #define MPU_REGION_SIZE_128B ((uint8_t)0x06) 190 #define MPU_REGION_SIZE_256B ((uint8_t)0x07) 191 #define MPU_REGION_SIZE_512B ((uint8_t)0x08) 192 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) 193 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) 194 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) 195 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) 196 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) 197 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) 198 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) 199 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) 200 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) 201 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) 202 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) 203 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) 204 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) 205 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) 206 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) 207 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) 208 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) 209 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) 210 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) 211 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) 212 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) 213 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) 214 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) 215 /** 216 * @} 217 */ 218 219 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 220 * @{ 221 */ 222 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) 223 #define MPU_REGION_PRIV_RW ((uint8_t)0x01) 224 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) 225 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) 226 #define MPU_REGION_PRIV_RO ((uint8_t)0x05) 227 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) 228 /** 229 * @} 230 */ 231 232 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 233 * @{ 234 */ 235 #define MPU_REGION_NUMBER0 ((uint8_t)0x00) 236 #define MPU_REGION_NUMBER1 ((uint8_t)0x01) 237 #define MPU_REGION_NUMBER2 ((uint8_t)0x02) 238 #define MPU_REGION_NUMBER3 ((uint8_t)0x03) 239 #define MPU_REGION_NUMBER4 ((uint8_t)0x04) 240 #define MPU_REGION_NUMBER5 ((uint8_t)0x05) 241 #define MPU_REGION_NUMBER6 ((uint8_t)0x06) 242 #define MPU_REGION_NUMBER7 ((uint8_t)0x07) 243 /** 244 * @} 245 */ 246 #endif /* __MPU_PRESENT */ 247 /** 248 * @} 249 */ 250 251 /* Exported Macros -----------------------------------------------------------*/ 252 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 253 * @{ 254 */ 255 256 /** @defgroup CORTEX_Preemption_Priority_Group_Macro CORTEX Preemption Priority Group 257 * @{ 258 */ 259 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 260 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 261 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 262 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 263 ((GROUP) == NVIC_PRIORITYGROUP_4)) 264 265 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 266 267 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 268 269 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) 270 271 /** 272 * @} 273 */ 274 275 /** 276 * @} 277 */ 278 279 /* Private macro -------------------------------------------------------------*/ 280 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 281 * @{ 282 */ 283 284 /** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source 285 * @{ 286 */ 287 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ 288 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 289 /** 290 * @} 291 */ 292 293 #if (__MPU_PRESENT == 1) 294 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 295 ((STATE) == MPU_REGION_DISABLE)) 296 297 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 298 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 299 300 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ 301 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 302 303 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ 304 ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) 305 306 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ 307 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) 308 309 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ 310 ((TYPE) == MPU_TEX_LEVEL1) || \ 311 ((TYPE) == MPU_TEX_LEVEL2)) 312 313 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ 314 ((TYPE) == MPU_REGION_PRIV_RW) || \ 315 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ 316 ((TYPE) == MPU_REGION_FULL_ACCESS) || \ 317 ((TYPE) == MPU_REGION_PRIV_RO) || \ 318 ((TYPE) == MPU_REGION_PRIV_RO_URO)) 319 320 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 321 ((NUMBER) == MPU_REGION_NUMBER1) || \ 322 ((NUMBER) == MPU_REGION_NUMBER2) || \ 323 ((NUMBER) == MPU_REGION_NUMBER3) || \ 324 ((NUMBER) == MPU_REGION_NUMBER4) || \ 325 ((NUMBER) == MPU_REGION_NUMBER5) || \ 326 ((NUMBER) == MPU_REGION_NUMBER6) || \ 327 ((NUMBER) == MPU_REGION_NUMBER7)) 328 329 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ 330 ((SIZE) == MPU_REGION_SIZE_64B) || \ 331 ((SIZE) == MPU_REGION_SIZE_128B) || \ 332 ((SIZE) == MPU_REGION_SIZE_256B) || \ 333 ((SIZE) == MPU_REGION_SIZE_512B) || \ 334 ((SIZE) == MPU_REGION_SIZE_1KB) || \ 335 ((SIZE) == MPU_REGION_SIZE_2KB) || \ 336 ((SIZE) == MPU_REGION_SIZE_4KB) || \ 337 ((SIZE) == MPU_REGION_SIZE_8KB) || \ 338 ((SIZE) == MPU_REGION_SIZE_16KB) || \ 339 ((SIZE) == MPU_REGION_SIZE_32KB) || \ 340 ((SIZE) == MPU_REGION_SIZE_64KB) || \ 341 ((SIZE) == MPU_REGION_SIZE_128KB) || \ 342 ((SIZE) == MPU_REGION_SIZE_256KB) || \ 343 ((SIZE) == MPU_REGION_SIZE_512KB) || \ 344 ((SIZE) == MPU_REGION_SIZE_1MB) || \ 345 ((SIZE) == MPU_REGION_SIZE_2MB) || \ 346 ((SIZE) == MPU_REGION_SIZE_4MB) || \ 347 ((SIZE) == MPU_REGION_SIZE_8MB) || \ 348 ((SIZE) == MPU_REGION_SIZE_16MB) || \ 349 ((SIZE) == MPU_REGION_SIZE_32MB) || \ 350 ((SIZE) == MPU_REGION_SIZE_64MB) || \ 351 ((SIZE) == MPU_REGION_SIZE_128MB) || \ 352 ((SIZE) == MPU_REGION_SIZE_256MB) || \ 353 ((SIZE) == MPU_REGION_SIZE_512MB) || \ 354 ((SIZE) == MPU_REGION_SIZE_1GB) || \ 355 ((SIZE) == MPU_REGION_SIZE_2GB) || \ 356 ((SIZE) == MPU_REGION_SIZE_4GB)) 357 358 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) 359 #endif /* __MPU_PRESENT */ 360 361 /** 362 * @} 363 */ 364 365 /* Private functions ---------------------------------------------------------*/ 366 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions 367 * @brief CORTEX private functions 368 * @{ 369 */ 370 371 372 /** 373 * @} 374 */ 375 376 /* Exported functions --------------------------------------------------------*/ 377 /** @addtogroup CORTEX_Exported_Functions 378 * @{ 379 */ 380 381 /** @addtogroup CORTEX_Exported_Functions_Group1 382 * @{ 383 */ 384 /* Initialization and de-initialization functions *****************************/ 385 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 386 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 387 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 388 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 389 void HAL_NVIC_SystemReset(void); 390 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 391 /** 392 * @} 393 */ 394 395 /** @addtogroup CORTEX_Exported_Functions_Group2 396 * @{ 397 */ 398 /* Peripheral Control functions ***********************************************/ 399 #if (__MPU_PRESENT == 1) 400 void HAL_MPU_Enable(uint32_t MPU_Control); 401 void HAL_MPU_Disable(void); 402 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); 403 #endif /* __MPU_PRESENT */ 404 uint32_t HAL_NVIC_GetPriorityGrouping(void); 405 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); 406 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 407 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 408 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 409 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 410 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 411 void HAL_SYSTICK_IRQHandler(void); 412 void HAL_SYSTICK_Callback(void); 413 /** 414 * @} 415 */ 416 417 /** 418 * @} 419 */ 420 421 /** 422 * @} 423 */ 424 425 /** 426 * @} 427 */ 428 429 #ifdef __cplusplus 430 } 431 #endif 432 433 #endif /* __STM32L1xx_HAL_CORTEX_H */ 434 435 436
