1 /** 2 ****************************************************************************** 3 * @file stm32l1xx_hal_adc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32L1xx_HAL_ADC_EX_H 21 #define __STM32L1xx_HAL_ADC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l1xx_hal_def.h" 29 30 /** @addtogroup STM32L1xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup ADCEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup ADCEx_Exported_Types ADCEx Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief ADC Configuration injected Channel structure definition 45 * @note Parameters of this structure are shared within 2 scopes: 46 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset 47 * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, 48 * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. 49 * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 50 * ADC state can be either: 51 * - For all parameters: ADC disabled 52 * - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group. 53 * - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group. 54 */ 55 typedef struct 56 { 57 uint32_t InjectedChannel; /*!< Selection of ADC channel to configure 58 This parameter can be a value of @ref ADC_channels 59 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ 60 uint32_t InjectedRank; /*!< Rank in the injected group sequencer 61 This parameter must be a value of @ref ADCEx_injected_rank 62 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ 63 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 64 Unit: ADC clock cycles 65 Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). 66 This parameter can be a value of @ref ADC_sampling_times 67 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. 68 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. 69 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 70 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 71 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ 72 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). 73 Offset value must be a positive number. 74 Depending of ADC resolution selected (12, 10, 8 or 6 bits), 75 this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ 76 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. 77 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 78 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 79 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 80 configure a channel on injected group can impact the configuration of other channels previously set. */ 81 FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). 82 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 83 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 84 This parameter can be set to ENABLE or DISABLE. 85 Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. 86 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 87 configure a channel on injected group can impact the configuration of other channels previously set. */ 88 FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one 89 This parameter can be set to ENABLE or DISABLE. 90 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) 91 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) 92 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. 93 To maintain JAUTO always enabled, DMA must be configured in circular mode. 94 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 95 configure a channel on injected group can impact the configuration of other channels previously set. */ 96 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. 97 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. 98 If set to external trigger source, triggering is on event rising edge. 99 This parameter can be a value of @ref ADCEx_External_trigger_source_Injected 100 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 101 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) 102 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 103 configure a channel on injected group can impact the configuration of other channels previously set. */ 104 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 105 This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected. 106 If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. 107 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 108 configure a channel on injected group can impact the configuration of other channels previously set. */ 109 }ADC_InjectionConfTypeDef; 110 /** 111 * @} 112 */ 113 114 115 /* Exported constants --------------------------------------------------------*/ 116 117 /** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants 118 * @{ 119 */ 120 121 /** @defgroup ADCEx_injected_rank ADCEx rank into injected group 122 * @{ 123 */ 124 #define ADC_INJECTED_RANK_1 (0x00000001U) 125 #define ADC_INJECTED_RANK_2 (0x00000002U) 126 #define ADC_INJECTED_RANK_3 (0x00000003U) 127 #define ADC_INJECTED_RANK_4 (0x00000004U) 128 /** 129 * @} 130 */ 131 132 /** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group 133 * @{ 134 */ 135 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U) 136 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0) 137 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1) 138 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN) 139 /** 140 * @} 141 */ 142 143 /** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger source Injected 144 * @{ 145 */ 146 /* External triggers for injected groups of ADC1 */ 147 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC_EXTERNALTRIGINJEC_T2_CC1 148 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC_EXTERNALTRIGINJEC_T2_TRGO 149 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC_EXTERNALTRIGINJEC_T3_CC4 150 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC_EXTERNALTRIGINJEC_T4_TRGO 151 #define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ADC_EXTERNALTRIGINJEC_T4_CC1 152 #define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ADC_EXTERNALTRIGINJEC_T4_CC2 153 #define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC_EXTERNALTRIGINJEC_T4_CC3 154 #define ADC_EXTERNALTRIGINJECCONV_T7_TRGO ADC_EXTERNALTRIGINJEC_T7_TRGO 155 #define ADC_EXTERNALTRIGINJECCONV_T9_CC1 ADC_EXTERNALTRIGINJEC_T9_CC1 156 #define ADC_EXTERNALTRIGINJECCONV_T9_TRGO ADC_EXTERNALTRIGINJEC_T9_TRGO 157 #define ADC_EXTERNALTRIGINJECCONV_T10_CC1 ADC_EXTERNALTRIGINJEC_T10_CC1 158 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15 159 #define ADC_INJECTED_SOFTWARE_START (0x00000010U) 160 /** 161 * @} 162 */ 163 164 /** 165 * @} 166 */ 167 168 169 /* Private constants ---------------------------------------------------------*/ 170 171 /** @addtogroup ADCEx_Private_Constants ADCEx Private Constants 172 * @{ 173 */ 174 175 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADCEx Internal HAL driver Ext trig src Injected 176 * @{ 177 */ 178 179 /* List of external triggers of injected group for ADC1: */ 180 /* (used internally by HAL driver. To not use into HAL structure parameters) */ 181 #define ADC_EXTERNALTRIGINJEC_T9_CC1 (0x00000000U) 182 #define ADC_EXTERNALTRIGINJEC_T9_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_0)) 183 #define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 )) 184 #define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) 185 #define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_2 )) 186 #define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) 187 #define ADC_EXTERNALTRIGINJEC_T4_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 )) 188 #define ADC_EXTERNALTRIGINJEC_T4_CC2 ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) 189 #define ADC_EXTERNALTRIGINJEC_T4_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 )) 190 #define ADC_EXTERNALTRIGINJEC_T10_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0)) 191 #define ADC_EXTERNALTRIGINJEC_T7_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 )) 192 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) 193 /** 194 * @} 195 */ 196 197 /** 198 * @} 199 */ 200 201 202 /* Exported macro ------------------------------------------------------------*/ 203 204 /** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros 205 * @{ 206 */ 207 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 208 /* final user. */ 209 210 /** 211 * @brief Selection of channels bank. 212 * Note: Banks availability depends on devices categories. 213 * This macro is intended to change bank selection quickly on the fly, 214 * without going through ADC init structure update and execution of function 215 * 'HAL_ADC_Init()'. 216 * @param __HANDLE__: ADC handle 217 * @param __BANK__: Bank selection. This parameter can be a value of @ref ADC_ChannelsBank. 218 * @retval None 219 */ 220 #define __HAL_ADC_CHANNELS_BANK(__HANDLE__, __BANK__) \ 221 MODIFY_REG((__HANDLE__)->Instance->CR2, ADC_CR2_CFG, (__BANK__)) 222 223 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 224 /** 225 * @brief Configures the ADC channels speed. 226 * Limited to channels 3, 8, 13 and to devices category Cat.3, Cat.4, Cat.5. 227 * - For ADC_CHANNEL_3: Used as ADC direct channel (fast channel) if OPAMP1 is 228 * in power down mode. 229 * - For ADC_CHANNEL_8: Used as ADC direct channel (fast channel) if OPAMP2 is 230 * in power down mode. 231 * - For ADC_CHANNEL_13: Used as ADC re-routed channel if OPAMP3 is in 232 * power down mode. Otherwise, channel 13 is connected to OPAMP3 output and 233 * routed through switches COMP1_SW1 and VCOMP to ADC switch matrix. 234 * (Note: OPAMP3 is available on STM32L1 Cat.4 only). 235 * @param __CHANNEL__: ADC channel 236 * This parameter can be one of the following values: 237 * @arg ADC_CHANNEL_3: Channel 3 is selected. 238 * @arg ADC_CHANNEL_8: Channel 8 is selected. 239 * @arg ADC_CHANNEL_13: Channel 13 is selected. 240 * @retval None 241 */ 242 #define __HAL_ADC_CHANNEL_SPEED_FAST(__CHANNEL__) \ 243 ( ( ((__CHANNEL__) == ADC_CHANNEL_3) \ 244 )? \ 245 (SET_BIT(COMP->CSR, COMP_CSR_FCH3)) \ 246 : \ 247 ( ( ((__CHANNEL__) == ADC_CHANNEL_8) \ 248 )? \ 249 (SET_BIT(COMP->CSR, COMP_CSR_FCH8)) \ 250 : \ 251 ( ( ((__CHANNEL__) == ADC_CHANNEL_13) \ 252 )? \ 253 (SET_BIT(COMP->CSR, COMP_CSR_RCH13)) \ 254 : \ 255 (SET_BIT(COMP->CSR, 0x00000000)) \ 256 ) \ 257 ) \ 258 ) 259 260 #define __HAL_ADC_CHANNEL_SPEED_SLOW(__CHANNEL__) \ 261 ( ( ((__CHANNEL__) == ADC_CHANNEL_3) \ 262 )? \ 263 (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH3)) \ 264 : \ 265 ( ( ((__CHANNEL__) == ADC_CHANNEL_8) \ 266 )? \ 267 (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH8)) \ 268 : \ 269 ( ( ((__CHANNEL__) == ADC_CHANNEL_13) \ 270 )? \ 271 (CLEAR_BIT(COMP->CSR, COMP_CSR_RCH13)) \ 272 : \ 273 (SET_BIT(COMP->CSR, 0x00000000)) \ 274 ) \ 275 ) \ 276 ) 277 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 278 279 /** 280 * @} 281 */ 282 283 /* Private macro ------------------------------------------------------------*/ 284 285 /** @defgroup ADCEx_Private_Macro ADCEx Private Macro 286 * @{ 287 */ 288 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 289 /* code of final user. */ 290 291 /** 292 * @brief Set ADC ranks available in register SQR1. 293 * Register SQR1 bits availability depends on device category. 294 * @param _NbrOfConversion_: Regular channel sequence length 295 * @retval None 296 */ 297 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 298 #define __ADC_SQR1_SQXX (ADC_SQR1_SQ28 | ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25) 299 #else 300 #define __ADC_SQR1_SQXX (ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25) 301 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 302 303 /** 304 * @brief Set the ADC's sample time for channel numbers between 30 and 31. 305 * Register SMPR0 availability depends on device category. If register is not 306 * available on the current device, this macro does nothing. 307 * @retval None 308 * @param _SAMPLETIME_: Sample time parameter. 309 * @param _CHANNELNB_: Channel number. 310 * @retval None 311 */ 312 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 313 #define ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) \ 314 ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 30))) 315 #else 316 #define ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) \ 317 (0x00000000U) 318 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 319 320 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 321 /** 322 * @brief Set the ADC's sample time for channel numbers between 20 and 29. 323 * @param _SAMPLETIME_: Sample time parameter. 324 * @param _CHANNELNB_: Channel number. 325 * @retval None 326 */ 327 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ 328 ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20))) 329 #else 330 /** 331 * @brief Set the ADC's sample time for channel numbers between 20 and 26. 332 * @param _SAMPLETIME_: Sample time parameter. 333 * @param _CHANNELNB_: Channel number. 334 * @retval None 335 */ 336 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ 337 ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20))) 338 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 339 340 /** 341 * @brief Defines the highest channel available in register SMPR1. Channels 342 * availability depends on device category: 343 * Highest channel in register SMPR1 is channel 26 for devices Cat.1, Cat.2, Cat.3 344 * Highest channel in register SMPR1 is channel 29 for devices Cat.4, Cat.5 345 * @param None 346 * @retval None 347 */ 348 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 349 #define ADC_SMPR1_CHANNEL_MAX ADC_CHANNEL_29 350 #else 351 #define ADC_SMPR1_CHANNEL_MAX ADC_CHANNEL_26 352 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 353 354 355 /** 356 * @brief Define mask of configuration bits of ADC and regular group in 357 * register CR2 (bits of ADC enable, conversion start and injected group are 358 * excluded of this mask). 359 * @retval None 360 */ 361 #if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 362 #define ADC_CR2_MASK_ADCINIT() \ 363 (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CFG | ADC_CR2_CONT) 364 #else 365 #define ADC_CR2_MASK_ADCINIT() \ 366 (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CONT) 367 #endif 368 369 370 /** 371 * @brief Get the maximum ADC conversion cycles on all channels. 372 * Returns the selected sampling time + conversion time (12.5 ADC clock cycles) 373 * Approximation of sampling time within 2 ranges, returns the highest value: 374 * below 24 cycles {4 cycles; 9 cycles; 16 cycles; 24 cycles} 375 * between 48 cycles and 384 cycles {48 cycles; 96 cycles; 192 cycles; 384 cycles} 376 * Unit: ADC clock cycles 377 * @param __HANDLE__: ADC handle 378 * @retval ADC conversion cycles on all channels 379 */ 380 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 381 #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ 382 (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET) && \ 383 (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ 384 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) && \ 385 (((__HANDLE__)->Instance->SMPR0 & ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2) == RESET) ) ? \ 386 \ 387 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES \ 388 ) 389 #else 390 #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ 391 (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET) && \ 392 (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ 393 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ 394 \ 395 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES \ 396 ) 397 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 398 399 /** 400 * @brief Get the ADC clock prescaler from ADC common control register 401 * and convert it to its decimal number setting (refer to reference manual) 402 * @retval None 403 */ 404 #define ADC_GET_CLOCK_PRESCALER_DECIMAL(__HANDLE__) \ 405 ((0x01) << ((ADC->CCR & ADC_CCR_ADCPRE) >> POSITION_VAL(ADC_CCR_ADCPRE))) 406 407 /** 408 * @brief Clear register SMPR0. 409 * Register SMPR0 availability depends on device category. If register is not 410 * available on the current device, this macro performs no action. 411 * @param __HANDLE__: ADC handle 412 * @retval None 413 */ 414 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 415 #define ADC_SMPR1_CLEAR(__HANDLE__) \ 416 CLEAR_BIT((__HANDLE__)->Instance->SMPR1, (ADC_SMPR1_SMP29 | ADC_SMPR1_SMP28 | ADC_SMPR1_SMP27 | \ 417 ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 | \ 418 ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 | \ 419 ADC_SMPR1_SMP20 )) 420 421 #define ADC_SMPR0_CLEAR(__HANDLE__) \ 422 (CLEAR_BIT((__HANDLE__)->Instance->SMPR0, (ADC_SMPR0_SMP31 | ADC_SMPR0_SMP30))) 423 #else 424 #define ADC_SMPR1_CLEAR(__HANDLE__) \ 425 CLEAR_BIT((__HANDLE__)->Instance->SMPR1, (ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 | \ 426 ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 | \ 427 ADC_SMPR1_SMP20 )) 428 429 #define ADC_SMPR0_CLEAR(__HANDLE__) __NOP() 430 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 431 432 /** 433 * @brief Clear register CR2. 434 * @param __HANDLE__: ADC handle 435 * @retval None 436 */ 437 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 438 #define ADC_CR2_CLEAR(__HANDLE__) \ 439 (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | \ 440 ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | \ 441 ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | \ 442 ADC_CR2_DMA | ADC_CR2_DELS | ADC_CR2_CFG | \ 443 ADC_CR2_CONT | ADC_CR2_ADON )) \ 444 ) 445 #else 446 #define ADC_CR2_CLEAR(__HANDLE__) \ 447 (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | \ 448 ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | \ 449 ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | \ 450 ADC_CR2_DMA | ADC_CR2_DELS | \ 451 ADC_CR2_CONT | ADC_CR2_ADON )) \ 452 ) 453 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 454 455 /** 456 * @brief Set the sampling time of selected channel on register SMPR0 457 * Register SMPR0 availability depends on device category. If register is not 458 * available on the current device, this macro performs no action. 459 * @param __HANDLE__: ADC handle 460 * @param _SAMPLETIME_: Sample time parameter. 461 * @param __CHANNEL__: Channel number. 462 * @retval None 463 */ 464 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 465 #define ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) \ 466 MODIFY_REG((__HANDLE__)->Instance->SMPR0, \ 467 ADC_SMPR0(ADC_SMPR0_SMP30, (__CHANNEL__)), \ 468 ADC_SMPR0((_SAMPLETIME_), (__CHANNEL__)) ) 469 #else 470 #define ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) __NOP() 471 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 472 473 474 #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ 475 ((CHANNEL) == ADC_INJECTED_RANK_2) || \ 476 ((CHANNEL) == ADC_INJECTED_RANK_3) || \ 477 ((CHANNEL) == ADC_INJECTED_RANK_4) ) 478 479 #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 480 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 481 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 482 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 483 484 #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ 485 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ 486 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ 487 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ 488 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \ 489 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \ 490 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ 491 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \ 492 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_CC1) || \ 493 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_TRGO) || \ 494 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T10_CC1) || \ 495 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ 496 ((REGTRIG) == ADC_SOFTWARE_START) ) 497 498 /** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification 499 * @{ 500 */ 501 #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U))) 502 /** 503 * @} 504 */ 505 506 /** 507 * @} 508 */ 509 510 511 /* Exported functions --------------------------------------------------------*/ 512 /** @addtogroup ADCEx_Exported_Functions 513 * @{ 514 */ 515 516 /* IO operation functions *****************************************************/ 517 /** @addtogroup ADCEx_Exported_Functions_Group1 518 * @{ 519 */ 520 521 /* Blocking mode: Polling */ 522 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); 523 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); 524 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 525 526 /* Non-blocking mode: Interruption */ 527 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); 528 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); 529 530 /* ADC retrieve conversion value intended to be used with polling or interruption */ 531 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); 532 533 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 534 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); 535 /** 536 * @} 537 */ 538 539 540 /* Peripheral Control functions ***********************************************/ 541 /** @addtogroup ADCEx_Exported_Functions_Group2 542 * @{ 543 */ 544 545 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); 546 /** 547 * @} 548 */ 549 550 551 /** 552 * @} 553 */ 554 555 556 /** 557 * @} 558 */ 559 560 /** 561 * @} 562 */ 563 564 #ifdef __cplusplus 565 } 566 #endif 567 568 #endif /* __STM32L1xx_HAL_ADC_EX_H */ 569
