1 /** 2 ****************************************************************************** 3 * @file stm32l1xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2017 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32L1xx_HAL_H 22 #define __STM32L1xx_HAL_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l1xx_hal_conf.h" 30 31 /** @addtogroup STM32L1xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup HAL 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /* Exported constants --------------------------------------------------------*/ 41 42 /** @defgroup HAL_Exported_Constants HAL Exported Constants 43 * @{ 44 */ 45 46 /** @defgroup HAL_TICK_FREQ Tick Frequency 47 * @{ 48 */ 49 #define HAL_TICK_FREQ_10HZ 100U 50 #define HAL_TICK_FREQ_100HZ 10U 51 #define HAL_TICK_FREQ_1KHZ 1U 52 #define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ 53 54 #define IS_TICKFREQ(__FREQ__) (((__FREQ__) == HAL_TICK_FREQ_10HZ) || \ 55 ((__FREQ__) == HAL_TICK_FREQ_100HZ) || \ 56 ((__FREQ__) == HAL_TICK_FREQ_1KHZ)) 57 58 /** 59 * @} 60 */ 61 62 /** 63 * @} 64 */ 65 66 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 67 * @{ 68 */ 69 70 /** @defgroup SYSCFG_Constants SYSCFG: SYStem ConFiG 71 * @{ 72 */ 73 74 /** @defgroup SYSCFG_BootMode Boot Mode 75 * @{ 76 */ 77 78 #define SYSCFG_BOOT_MAINFLASH (0x00000000U) 79 #define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0) 80 #if defined(FSMC_R_BASE) 81 #define SYSCFG_BOOT_FSMC ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1) 82 #endif /* FSMC_R_BASE */ 83 #define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE) 84 85 /** 86 * @} 87 */ 88 89 /** 90 * @} 91 */ 92 93 /** @defgroup RI_Constants RI: Routing Interface 94 * @{ 95 */ 96 97 /** @defgroup RI_InputCapture Input Capture 98 * @{ 99 */ 100 101 #define RI_INPUTCAPTURE_IC1 RI_ICR_IC1 /*!< Input Capture 1 */ 102 #define RI_INPUTCAPTURE_IC2 RI_ICR_IC2 /*!< Input Capture 2 */ 103 #define RI_INPUTCAPTURE_IC3 RI_ICR_IC3 /*!< Input Capture 3 */ 104 #define RI_INPUTCAPTURE_IC4 RI_ICR_IC4 /*!< Input Capture 4 */ 105 106 /** 107 * @} 108 */ 109 110 /** @defgroup TIM_Select TIM Select 111 * @{ 112 */ 113 114 #define TIM_SELECT_NONE (0x00000000U) /*!< None selected */ 115 #define TIM_SELECT_TIM2 ((uint32_t)RI_ICR_TIM_0) /*!< Timer 2 selected */ 116 #define TIM_SELECT_TIM3 ((uint32_t)RI_ICR_TIM_1) /*!< Timer 3 selected */ 117 #define TIM_SELECT_TIM4 ((uint32_t)RI_ICR_TIM) /*!< Timer 4 selected */ 118 119 #define IS_RI_TIM(__TIM__) (((__TIM__) == TIM_SELECT_NONE) || \ 120 ((__TIM__) == TIM_SELECT_TIM2) || \ 121 ((__TIM__) == TIM_SELECT_TIM3) || \ 122 ((__TIM__) == TIM_SELECT_TIM4)) 123 124 /** 125 * @} 126 */ 127 128 /** @defgroup RI_InputCaptureRouting Input Capture Routing 129 * @{ 130 */ 131 /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */ 132 #define RI_INPUTCAPTUREROUTING_0 (0x00000000U) /* PA0 PA1 PA2 PA3 */ 133 #define RI_INPUTCAPTUREROUTING_1 (0x00000001U) /* PA4 PA5 PA6 PA7 */ 134 #define RI_INPUTCAPTUREROUTING_2 (0x00000002U) /* PA8 PA9 PA10 PA11 */ 135 #define RI_INPUTCAPTUREROUTING_3 (0x00000003U) /* PA12 PA13 PA14 PA15 */ 136 #define RI_INPUTCAPTUREROUTING_4 (0x00000004U) /* PC0 PC1 PC2 PC3 */ 137 #define RI_INPUTCAPTUREROUTING_5 (0x00000005U) /* PC4 PC5 PC6 PC7 */ 138 #define RI_INPUTCAPTUREROUTING_6 (0x00000006U) /* PC8 PC9 PC10 PC11 */ 139 #define RI_INPUTCAPTUREROUTING_7 (0x00000007U) /* PC12 PC13 PC14 PC15 */ 140 #define RI_INPUTCAPTUREROUTING_8 (0x00000008U) /* PD0 PD1 PD2 PD3 */ 141 #define RI_INPUTCAPTUREROUTING_9 (0x00000009U) /* PD4 PD5 PD6 PD7 */ 142 #define RI_INPUTCAPTUREROUTING_10 (0x0000000AU) /* PD8 PD9 PD10 PD11 */ 143 #define RI_INPUTCAPTUREROUTING_11 (0x0000000BU) /* PD12 PD13 PD14 PD15 */ 144 #define RI_INPUTCAPTUREROUTING_12 (0x0000000CU) /* PE0 PE1 PE2 PE3 */ 145 #define RI_INPUTCAPTUREROUTING_13 (0x0000000DU) /* PE4 PE5 PE6 PE7 */ 146 #define RI_INPUTCAPTUREROUTING_14 (0x0000000EU) /* PE8 PE9 PE10 PE11 */ 147 #define RI_INPUTCAPTUREROUTING_15 (0x0000000FU) /* PE12 PE13 PE14 PE15 */ 148 149 #define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) || \ 150 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) || \ 151 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_2) || \ 152 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_3) || \ 153 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_4) || \ 154 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_5) || \ 155 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_6) || \ 156 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_7) || \ 157 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_8) || \ 158 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_9) || \ 159 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_10) || \ 160 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_11) || \ 161 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_12) || \ 162 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_13) || \ 163 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_14) || \ 164 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_15)) 165 166 /** 167 * @} 168 */ 169 170 /** @defgroup RI_IOSwitch IO Switch 171 * @{ 172 */ 173 #define RI_ASCR1_REGISTER (0x80000000U) 174 /* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */ 175 #define RI_IOSWITCH_CH0 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_0) 176 #define RI_IOSWITCH_CH1 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_1) 177 #define RI_IOSWITCH_CH2 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_2) 178 #define RI_IOSWITCH_CH3 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_3) 179 #define RI_IOSWITCH_CH4 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_4) 180 #define RI_IOSWITCH_CH5 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_5) 181 #define RI_IOSWITCH_CH6 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_6) 182 #define RI_IOSWITCH_CH7 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_7) 183 #define RI_IOSWITCH_CH8 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_8) 184 #define RI_IOSWITCH_CH9 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_9) 185 #define RI_IOSWITCH_CH10 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_10) 186 #define RI_IOSWITCH_CH11 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_11) 187 #define RI_IOSWITCH_CH12 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_12) 188 #define RI_IOSWITCH_CH13 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_13) 189 #define RI_IOSWITCH_CH14 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_14) 190 #define RI_IOSWITCH_CH15 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_15) 191 #define RI_IOSWITCH_CH18 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_18) 192 #define RI_IOSWITCH_CH19 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_19) 193 #define RI_IOSWITCH_CH20 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_20) 194 #define RI_IOSWITCH_CH21 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_21) 195 #define RI_IOSWITCH_CH22 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_22) 196 #define RI_IOSWITCH_CH23 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_23) 197 #define RI_IOSWITCH_CH24 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_24) 198 #define RI_IOSWITCH_CH25 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_25) 199 #define RI_IOSWITCH_VCOMP ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_VCOMP) /* VCOMP (ADC channel 26) is an internal switch used to connect selected channel to COMP1 non inverting input */ 200 #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ 201 #define RI_IOSWITCH_CH27 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_27) 202 #define RI_IOSWITCH_CH28 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_28) 203 #define RI_IOSWITCH_CH29 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_29) 204 #define RI_IOSWITCH_CH30 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_30) 205 #define RI_IOSWITCH_CH31 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_31) 206 #endif /* RI_ASCR2_CH1b */ 207 208 /* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */ 209 #define RI_IOSWITCH_GR10_1 ((uint32_t)RI_ASCR2_GR10_1) 210 #define RI_IOSWITCH_GR10_2 ((uint32_t)RI_ASCR2_GR10_2) 211 #define RI_IOSWITCH_GR10_3 ((uint32_t)RI_ASCR2_GR10_3) 212 #define RI_IOSWITCH_GR10_4 ((uint32_t)RI_ASCR2_GR10_4) 213 #define RI_IOSWITCH_GR6_1 ((uint32_t)RI_ASCR2_GR6_1) 214 #define RI_IOSWITCH_GR6_2 ((uint32_t)RI_ASCR2_GR6_2) 215 #define RI_IOSWITCH_GR5_1 ((uint32_t)RI_ASCR2_GR5_1) 216 #define RI_IOSWITCH_GR5_2 ((uint32_t)RI_ASCR2_GR5_2) 217 #define RI_IOSWITCH_GR5_3 ((uint32_t)RI_ASCR2_GR5_3) 218 #define RI_IOSWITCH_GR4_1 ((uint32_t)RI_ASCR2_GR4_1) 219 #define RI_IOSWITCH_GR4_2 ((uint32_t)RI_ASCR2_GR4_2) 220 #define RI_IOSWITCH_GR4_3 ((uint32_t)RI_ASCR2_GR4_3) 221 #if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3, Cat.4 and Cat.5 */ 222 #define RI_IOSWITCH_CH0b ((uint32_t)RI_ASCR2_CH0b) 223 #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ 224 #define RI_IOSWITCH_CH1b ((uint32_t)RI_ASCR2_CH1b) 225 #define RI_IOSWITCH_CH2b ((uint32_t)RI_ASCR2_CH2b) 226 #define RI_IOSWITCH_CH3b ((uint32_t)RI_ASCR2_CH3b) 227 #define RI_IOSWITCH_CH6b ((uint32_t)RI_ASCR2_CH6b) 228 #define RI_IOSWITCH_CH7b ((uint32_t)RI_ASCR2_CH7b) 229 #define RI_IOSWITCH_CH8b ((uint32_t)RI_ASCR2_CH8b) 230 #define RI_IOSWITCH_CH9b ((uint32_t)RI_ASCR2_CH9b) 231 #define RI_IOSWITCH_CH10b ((uint32_t)RI_ASCR2_CH10b) 232 #define RI_IOSWITCH_CH11b ((uint32_t)RI_ASCR2_CH11b) 233 #define RI_IOSWITCH_CH12b ((uint32_t)RI_ASCR2_CH12b) 234 #endif /* RI_ASCR2_CH1b */ 235 #define RI_IOSWITCH_GR6_3 ((uint32_t)RI_ASCR2_GR6_3) 236 #define RI_IOSWITCH_GR6_4 ((uint32_t)RI_ASCR2_GR6_4) 237 #endif /* RI_ASCR2_CH0b */ 238 239 240 #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ 241 242 #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ 243 ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ 244 ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ 245 ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ 246 ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ 247 ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ 248 ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ 249 ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ 250 ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ 251 ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ 252 ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ 253 ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ 254 ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_CH27) || \ 255 ((__IOSWITCH__) == RI_IOSWITCH_CH28) || ((__IOSWITCH__) == RI_IOSWITCH_CH29) || \ 256 ((__IOSWITCH__) == RI_IOSWITCH_CH30) || ((__IOSWITCH__) == RI_IOSWITCH_CH31) || \ 257 ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || \ 258 ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || \ 259 ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || \ 260 ((__IOSWITCH__) == RI_IOSWITCH_GR6_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_4) || \ 261 ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || \ 262 ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || \ 263 ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || \ 264 ((__IOSWITCH__) == RI_IOSWITCH_CH0b) || ((__IOSWITCH__) == RI_IOSWITCH_CH1b) || \ 265 ((__IOSWITCH__) == RI_IOSWITCH_CH2b) || ((__IOSWITCH__) == RI_IOSWITCH_CH3b) || \ 266 ((__IOSWITCH__) == RI_IOSWITCH_CH6b) || ((__IOSWITCH__) == RI_IOSWITCH_CH7b) || \ 267 ((__IOSWITCH__) == RI_IOSWITCH_CH8b) || ((__IOSWITCH__) == RI_IOSWITCH_CH9b) || \ 268 ((__IOSWITCH__) == RI_IOSWITCH_CH10b) || ((__IOSWITCH__) == RI_IOSWITCH_CH11b) || \ 269 ((__IOSWITCH__) == RI_IOSWITCH_CH12b)) 270 271 #else /* !RI_ASCR2_CH1b */ 272 273 #if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3 */ 274 275 #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ 276 ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ 277 ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ 278 ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ 279 ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ 280 ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ 281 ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ 282 ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ 283 ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ 284 ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ 285 ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ 286 ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ 287 ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \ 288 ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \ 289 ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \ 290 ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \ 291 ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \ 292 ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \ 293 ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || ((__IOSWITCH__) == RI_IOSWITCH_CH0b)) 294 295 #else /* !RI_ASCR2_CH0b */ /* STM32L1 devices category Cat.1 and Cat.2 */ 296 297 #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ 298 ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ 299 ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ 300 ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ 301 ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ 302 ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ 303 ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ 304 ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ 305 ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ 306 ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ 307 ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ 308 ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ 309 ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \ 310 ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \ 311 ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \ 312 ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \ 313 ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \ 314 ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \ 315 ((__IOSWITCH__) == RI_IOSWITCH_GR4_3)) 316 317 #endif /* RI_ASCR2_CH0b */ 318 #endif /* RI_ASCR2_CH1b */ 319 320 /** 321 * @} 322 */ 323 324 /** @defgroup RI_Pin PIN define 325 * @{ 326 */ 327 #define RI_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ 328 #define RI_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ 329 #define RI_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ 330 #define RI_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ 331 #define RI_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ 332 #define RI_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ 333 #define RI_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ 334 #define RI_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ 335 #define RI_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ 336 #define RI_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ 337 #define RI_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ 338 #define RI_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ 339 #define RI_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ 340 #define RI_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ 341 #define RI_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ 342 #define RI_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ 343 #define RI_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */ 344 345 #define IS_RI_PIN(__PIN__) ((__PIN__) != (uint16_t)0x00) 346 347 /** 348 * @} 349 */ 350 351 /** 352 * @} 353 */ 354 355 /** 356 * @} 357 */ 358 359 /* Exported macros -----------------------------------------------------------*/ 360 361 /** @defgroup HAL_Exported_Macros HAL Exported Macros 362 * @{ 363 */ 364 365 /** @defgroup DBGMCU_Macros DBGMCU: Debug MCU 366 * @{ 367 */ 368 369 /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode 370 * @brief Freeze/Unfreeze Peripherals in Debug mode 371 * @{ 372 */ 373 374 /** 375 * @brief TIM2 Peripherals Debug mode 376 */ 377 #if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP) 378 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP) 379 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP) 380 #endif 381 382 /** 383 * @brief TIM3 Peripherals Debug mode 384 */ 385 #if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP) 386 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP) 387 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP) 388 #endif 389 390 /** 391 * @brief TIM4 Peripherals Debug mode 392 */ 393 #if defined (DBGMCU_APB1_FZ_DBG_TIM4_STOP) 394 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP) 395 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP) 396 #endif 397 398 /** 399 * @brief TIM5 Peripherals Debug mode 400 */ 401 #if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP) 402 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP) 403 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP) 404 #endif 405 406 /** 407 * @brief TIM6 Peripherals Debug mode 408 */ 409 #if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP) 410 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) 411 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) 412 #endif 413 414 /** 415 * @brief TIM7 Peripherals Debug mode 416 */ 417 #if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP) 418 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) 419 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) 420 #endif 421 422 /** 423 * @brief RTC Peripherals Debug mode 424 */ 425 #if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP) 426 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) 427 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) 428 #endif 429 430 /** 431 * @brief WWDG Peripherals Debug mode 432 */ 433 #if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP) 434 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) 435 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) 436 #endif 437 438 /** 439 * @brief IWDG Peripherals Debug mode 440 */ 441 #if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP) 442 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) 443 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) 444 #endif 445 446 /** 447 * @brief I2C1 Peripherals Debug mode 448 */ 449 #if defined (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) 450 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) 451 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) 452 #endif 453 454 /** 455 * @brief I2C2 Peripherals Debug mode 456 */ 457 #if defined (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) 458 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) 459 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) 460 #endif 461 462 /** 463 * @brief TIM9 Peripherals Debug mode 464 */ 465 #if defined (DBGMCU_APB2_FZ_DBG_TIM9_STOP) 466 #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP) 467 #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP) 468 #endif 469 470 /** 471 * @brief TIM10 Peripherals Debug mode 472 */ 473 #if defined (DBGMCU_APB2_FZ_DBG_TIM10_STOP) 474 #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP) 475 #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP) 476 #endif 477 478 /** 479 * @brief TIM11 Peripherals Debug mode 480 */ 481 #if defined (DBGMCU_APB2_FZ_DBG_TIM11_STOP) 482 #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP) 483 #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP) 484 #endif 485 486 487 /** 488 * @} 489 */ 490 491 /** 492 * @} 493 */ 494 495 /** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG 496 * @{ 497 */ 498 499 /** @defgroup SYSCFG_VrefInt VREFINT configuration 500 * @{ 501 */ 502 503 /** 504 * @brief Enables or disables the output of internal reference voltage 505 * (VrefInt) on I/O pin. 506 * @note The VrefInt output can be routed to any I/O in group 3: 507 * - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1). 508 * - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2). 509 * - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2), 510 * CH1b (PF11) or CH2b (PF12). 511 * Note: Comparator peripheral clock must be preliminarily enabled, 512 * either in COMP user function "HAL_COMP_MspInit()" (should be 513 * done if comparators are used) or by direct clock enable: 514 * Refer to macro "__HAL_RCC_COMP_CLK_ENABLE()". 515 * Note: In addition with this macro, VrefInt output buffer must be 516 * connected to the selected I/O pin. Refer to macro 517 * "__HAL_RI_IOSWITCH_CLOSE()". 518 * @note VrefInt output enable: Internal reference voltage connected to I/O group 3 519 * VrefInt output disable: Internal reference voltage disconnected from I/O group 3 520 * @retval None 521 */ 522 #define __HAL_SYSCFG_VREFINT_OUT_ENABLE() SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) 523 #define __HAL_SYSCFG_VREFINT_OUT_DISABLE() CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) 524 525 /** 526 * @} 527 */ 528 529 /** @defgroup SYSCFG_BootModeConfig Boot Mode Configuration 530 * @{ 531 */ 532 533 /** 534 * @brief Main Flash memory mapped at 0x00000000 535 */ 536 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) 537 538 /** @brief System Flash memory mapped at 0x00000000 539 */ 540 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) 541 542 /** @brief Embedded SRAM mapped at 0x00000000 543 */ 544 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1) 545 546 #if defined(FSMC_R_BASE) 547 /** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 548 */ 549 #define __HAL_SYSCFG_REMAPMEMORY_FSMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) 550 551 #endif /* FSMC_R_BASE */ 552 553 /** 554 * @brief Returns the boot mode as configured by user. 555 * @retval The boot mode as configured by user. The returned value can be one 556 * of the following values: 557 * @arg SYSCFG_BOOT_MAINFLASH 558 * @arg SYSCFG_BOOT_SYSTEMFLASH 559 * @arg SYSCFG_BOOT_FSMC (available only for STM32L151xD, STM32L152xD & STM32L162xD) 560 * @arg SYSCFG_BOOT_SRAM 561 */ 562 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE) 563 564 /** 565 * @} 566 */ 567 568 /** @defgroup SYSCFG_USBConfig USB DP line Configuration 569 * @{ 570 */ 571 572 /** 573 * @brief Control the internal pull-up on USB DP line. 574 */ 575 #define __HAL_SYSCFG_USBPULLUP_ENABLE() SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU) 576 577 #define __HAL_SYSCFG_USBPULLUP_DISABLE() CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU) 578 579 /** 580 * @} 581 */ 582 583 /** 584 * @} 585 */ 586 587 /** @defgroup RI_Macris RI: Routing Interface 588 * @{ 589 */ 590 591 /** @defgroup RI_InputCaputureConfig Input Capture configuration 592 * @{ 593 */ 594 595 /** 596 * @brief Configures the routing interface to map Input Capture 1 of TIMx to a selected I/O pin. 597 * @param __TIMSELECT__ Timer select. 598 * This parameter can be one of the following values: 599 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. 600 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. 601 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. 602 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. 603 * @param __INPUT__ selects which pin to be routed to Input Capture. 604 * This parameter must be a value of @ref RI_InputCaptureRouting 605 * e.g. 606 * __HAL_RI_REMAP_INPUTCAPTURE1(TIM_SELECT_TIM2, RI_INPUTCAPTUREROUTING_1) 607 * allows routing of Input capture IC1 of TIM2 to PA4. 608 * For details about correspondence between RI_INPUTCAPTUREROUTING_x 609 * and I/O pins refer to the parameters' description in the header file 610 * or refer to the product reference manual. 611 * @note Input capture selection bits are not reset by this function. 612 * To reset input capture selection bits, use SYSCFG_RIDeInit() function. 613 * @note The I/O should be configured in alternate function mode (AF14) using 614 * GPIO_PinAFConfig() function. 615 * @retval None. 616 */ 617 #define __HAL_RI_REMAP_INPUTCAPTURE1(__TIMSELECT__, __INPUT__) \ 618 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ 619 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ 620 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ 621 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \ 622 MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \ 623 }while(0) 624 625 /** 626 * @brief Configures the routing interface to map Input Capture 2 of TIMx to a selected I/O pin. 627 * @param __TIMSELECT__ Timer select. 628 * This parameter can be one of the following values: 629 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. 630 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. 631 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. 632 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. 633 * @param __INPUT__ selects which pin to be routed to Input Capture. 634 * This parameter must be a value of @ref RI_InputCaptureRouting 635 * @retval None. 636 */ 637 #define __HAL_RI_REMAP_INPUTCAPTURE2(__TIMSELECT__, __INPUT__) \ 638 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ 639 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ 640 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ 641 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \ 642 MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \ 643 }while(0) 644 645 /** 646 * @brief Configures the routing interface to map Input Capture 3 of TIMx to a selected I/O pin. 647 * @param __TIMSELECT__ Timer select. 648 * This parameter can be one of the following values: 649 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. 650 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. 651 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. 652 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. 653 * @param __INPUT__ selects which pin to be routed to Input Capture. 654 * This parameter must be a value of @ref RI_InputCaptureRouting 655 * @retval None. 656 */ 657 #define __HAL_RI_REMAP_INPUTCAPTURE3(__TIMSELECT__, __INPUT__) \ 658 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ 659 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ 660 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ 661 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \ 662 MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \ 663 }while(0) 664 665 /** 666 * @brief Configures the routing interface to map Input Capture 4 of TIMx to a selected I/O pin. 667 * @param __TIMSELECT__ Timer select. 668 * This parameter can be one of the following values: 669 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. 670 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. 671 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. 672 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. 673 * @param __INPUT__ selects which pin to be routed to Input Capture. 674 * This parameter must be a value of @ref RI_InputCaptureRouting 675 * @retval None. 676 */ 677 #define __HAL_RI_REMAP_INPUTCAPTURE4(__TIMSELECT__, __INPUT__) \ 678 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ 679 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ 680 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ 681 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC4); \ 682 MODIFY_REG(RI->ICR, RI_ICR_IC4OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC4OS)); \ 683 }while(0) 684 685 /** 686 * @} 687 */ 688 689 /** @defgroup RI_SwitchControlConfig Switch Control configuration 690 * @{ 691 */ 692 693 /** 694 * @brief Enable or disable the switch control mode. 695 * @note ENABLE: ADC analog switches closed if the corresponding 696 * I/O switch is also closed. 697 * When using COMP1, switch control mode must be enabled. 698 * @note DISABLE: ADC analog switches open or controlled by the ADC interface. 699 * When using the ADC for acquisition, switch control mode 700 * must be disabled. 701 * @note COMP1 comparator and ADC cannot be used at the same time since 702 * they share the ADC switch matrix. 703 * @retval None 704 */ 705 #define __HAL_RI_SWITCHCONTROLMODE_ENABLE() SET_BIT(RI->ASCR1, RI_ASCR1_SCM) 706 707 #define __HAL_RI_SWITCHCONTROLMODE_DISABLE() CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM) 708 709 /* 710 * @brief Close or Open the routing interface Input Output switches. 711 * @param __IOSWITCH__ selects the I/O analog switch number. 712 * This parameter must be a value of @ref RI_IOSwitch 713 * @retval None 714 */ 715 #define __HAL_RI_IOSWITCH_CLOSE(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \ 716 if ((__IOSWITCH__) >> 31 != 0 ) \ 717 { \ 718 SET_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \ 719 } \ 720 else \ 721 { \ 722 SET_BIT(RI->ASCR2, (__IOSWITCH__)); \ 723 } \ 724 }while(0) 725 726 #define __HAL_RI_IOSWITCH_OPEN(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \ 727 if ((__IOSWITCH__) >> 31 != 0 ) \ 728 { \ 729 CLEAR_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \ 730 } \ 731 else \ 732 { \ 733 CLEAR_BIT(RI->ASCR2, (__IOSWITCH__)); \ 734 } \ 735 }while(0) 736 737 #if defined (COMP_CSR_SW1) 738 /** 739 * @brief Close or open the internal switch COMP1_SW1. 740 * This switch connects I/O pin PC3 (can be used as ADC channel 13) 741 * and OPAMP3 output to ADC switch matrix (ADC channel VCOMP, channel 742 * 26) and COMP1 non-inverting input. 743 * Pin PC3 connection depends on another switch setting, refer to 744 * macro "__HAL_ADC_CHANNEL_SPEED_FAST()". 745 * @retval None. 746 */ 747 #define __HAL_RI_SWITCH_COMP1_SW1_CLOSE() SET_BIT(COMP->CSR, COMP_CSR_SW1) 748 749 #define __HAL_RI_SWITCH_COMP1_SW1_OPEN() CLEAR_BIT(COMP->CSR, COMP_CSR_SW1) 750 #endif /* COMP_CSR_SW1 */ 751 752 /** 753 * @} 754 */ 755 756 /** @defgroup RI_HystConfig Hysteresis Activation and Deactivation 757 * @{ 758 */ 759 760 /** 761 * @brief Enable or disable Hysteresis of the input schmitt trigger of Ports A 762 * When the I/Os are programmed in input mode by standard I/O port 763 * registers, the Schmitt trigger and the hysteresis are enabled by default. 764 * When hysteresis is disabled, it is possible to read the 765 * corresponding port with a trigger level of VDDIO/2. 766 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. 767 * This parameter must be a value of @ref RI_Pin 768 * @retval None 769 */ 770 #define __HAL_RI_HYSTERIS_PORTA_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 771 CLEAR_BIT(RI->HYSCR1, (__IOPIN__)); \ 772 } while(0) 773 774 #define __HAL_RI_HYSTERIS_PORTA_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 775 SET_BIT(RI->HYSCR1, (__IOPIN__)); \ 776 } while(0) 777 778 /** 779 * @brief Enable or disable Hysteresis of the input schmitt trigger of Ports B 780 * When the I/Os are programmed in input mode by standard I/O port 781 * registers, the Schmitt trigger and the hysteresis are enabled by default. 782 * When hysteresis is disabled, it is possible to read the 783 * corresponding port with a trigger level of VDDIO/2. 784 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. 785 * This parameter must be a value of @ref RI_Pin 786 * @retval None 787 */ 788 #define __HAL_RI_HYSTERIS_PORTB_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 789 CLEAR_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \ 790 } while(0) 791 792 #define __HAL_RI_HYSTERIS_PORTB_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 793 SET_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \ 794 } while(0) 795 796 /** 797 * @brief Enable or disable Hysteresis of the input schmitt trigger of Ports C 798 * When the I/Os are programmed in input mode by standard I/O port 799 * registers, the Schmitt trigger and the hysteresis are enabled by default. 800 * When hysteresis is disabled, it is possible to read the 801 * corresponding port with a trigger level of VDDIO/2. 802 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. 803 * This parameter must be a value of @ref RI_Pin 804 * @retval None 805 */ 806 #define __HAL_RI_HYSTERIS_PORTC_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 807 CLEAR_BIT(RI->HYSCR2, (__IOPIN__)); \ 808 } while(0) 809 810 #define __HAL_RI_HYSTERIS_PORTC_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 811 SET_BIT(RI->HYSCR2, (__IOPIN__)); \ 812 } while(0) 813 814 /** 815 * @brief Enable or disable Hysteresis of the input schmitt trigger of Ports D 816 * When the I/Os are programmed in input mode by standard I/O port 817 * registers, the Schmitt trigger and the hysteresis are enabled by default. 818 * When hysteresis is disabled, it is possible to read the 819 * corresponding port with a trigger level of VDDIO/2. 820 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. 821 * This parameter must be a value of @ref RI_Pin 822 * @retval None 823 */ 824 #define __HAL_RI_HYSTERIS_PORTD_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 825 CLEAR_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \ 826 } while(0) 827 828 #define __HAL_RI_HYSTERIS_PORTD_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 829 SET_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \ 830 } while(0) 831 832 #if defined (GPIOE_BASE) 833 834 /** 835 * @brief Enable or disable Hysteresis of the input schmitt trigger of Ports E 836 * When the I/Os are programmed in input mode by standard I/O port 837 * registers, the Schmitt trigger and the hysteresis are enabled by default. 838 * When hysteresis is disabled, it is possible to read the 839 * corresponding port with a trigger level of VDDIO/2. 840 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. 841 * This parameter must be a value of @ref RI_Pin 842 * @retval None 843 */ 844 #define __HAL_RI_HYSTERIS_PORTE_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 845 CLEAR_BIT(RI->HYSCR3, (__IOPIN__)); \ 846 } while(0) 847 848 #define __HAL_RI_HYSTERIS_PORTE_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 849 SET_BIT(RI->HYSCR3, (__IOPIN__)); \ 850 } while(0) 851 852 #endif /* GPIOE_BASE */ 853 854 #if defined(GPIOF_BASE) || defined(GPIOG_BASE) 855 856 /** 857 * @brief Enable or disable Hysteresis of the input schmitt trigger of Ports F 858 * When the I/Os are programmed in input mode by standard I/O port 859 * registers, the Schmitt trigger and the hysteresis are enabled by default. 860 * When hysteresis is disabled, it is possible to read the 861 * corresponding port with a trigger level of VDDIO/2. 862 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. 863 * This parameter must be a value of @ref RI_Pin 864 * @retval None 865 */ 866 #define __HAL_RI_HYSTERIS_PORTF_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 867 CLEAR_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \ 868 } while(0) 869 870 #define __HAL_RI_HYSTERIS_PORTF_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 871 SET_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \ 872 } while(0) 873 874 /** 875 * @brief Enable or disable Hysteresis of the input schmitt trigger of Ports G 876 * When the I/Os are programmed in input mode by standard I/O port 877 * registers, the Schmitt trigger and the hysteresis are enabled by default. 878 * When hysteresis is disabled, it is possible to read the 879 * corresponding port with a trigger level of VDDIO/2. 880 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. 881 * This parameter must be a value of @ref RI_Pin 882 * @retval None 883 */ 884 #define __HAL_RI_HYSTERIS_PORTG_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 885 CLEAR_BIT(RI->HYSCR4, (__IOPIN__)); \ 886 } while(0) 887 888 #define __HAL_RI_HYSTERIS_PORTG_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 889 SET_BIT(RI->HYSCR4, (__IOPIN__)); \ 890 } while(0) 891 892 #endif /* GPIOF_BASE || GPIOG_BASE */ 893 894 /** 895 * @} 896 */ 897 898 /** 899 * @} 900 */ 901 902 /** 903 * @} 904 */ 905 906 /* Exported variables --------------------------------------------------------*/ 907 /** @defgroup HAL_Exported_Variables HAL Exported Variables 908 * @{ 909 */ 910 extern __IO uint32_t uwTick; 911 extern uint32_t uwTickPrio; 912 extern uint32_t uwTickFreq; 913 /** 914 * @} 915 */ 916 917 /* Exported functions --------------------------------------------------------*/ 918 /** @addtogroup HAL_Exported_Functions 919 * @{ 920 */ 921 922 /** @addtogroup HAL_Exported_Functions_Group1 923 * @{ 924 */ 925 926 /* Initialization and de-initialization functions ******************************/ 927 HAL_StatusTypeDef HAL_Init(void); 928 HAL_StatusTypeDef HAL_DeInit(void); 929 void HAL_MspInit(void); 930 void HAL_MspDeInit(void); 931 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 932 933 /** 934 * @} 935 */ 936 937 /** @addtogroup HAL_Exported_Functions_Group2 938 * @{ 939 */ 940 941 /* Peripheral Control functions ************************************************/ 942 void HAL_IncTick(void); 943 void HAL_Delay(uint32_t Delay); 944 uint32_t HAL_GetTick(void); 945 uint32_t HAL_GetTickPrio(void); 946 HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq); 947 uint32_t HAL_GetTickFreq(void); 948 void HAL_SuspendTick(void); 949 void HAL_ResumeTick(void); 950 uint32_t HAL_GetHalVersion(void); 951 uint32_t HAL_GetREVID(void); 952 uint32_t HAL_GetDEVID(void); 953 uint32_t HAL_GetUIDw0(void); 954 uint32_t HAL_GetUIDw1(void); 955 uint32_t HAL_GetUIDw2(void); 956 957 /** 958 * @} 959 */ 960 961 /** @addtogroup HAL_Exported_Functions_Group3 962 * @{ 963 */ 964 965 /* DBGMCU Peripheral Control functions *****************************************/ 966 void HAL_DBGMCU_EnableDBGSleepMode(void); 967 void HAL_DBGMCU_DisableDBGSleepMode(void); 968 void HAL_DBGMCU_EnableDBGStopMode(void); 969 void HAL_DBGMCU_DisableDBGStopMode(void); 970 void HAL_DBGMCU_EnableDBGStandbyMode(void); 971 void HAL_DBGMCU_DisableDBGStandbyMode(void); 972 973 /** 974 * @} 975 */ 976 977 /** 978 * @} 979 */ 980 981 /** 982 * @} 983 */ 984 985 /** 986 * @} 987 */ 988 989 #ifdef __cplusplus 990 } 991 #endif 992 993 #endif /* __STM32L1xx_HAL_H */ 994 995
