1 /**
2 ******************************************************************************
3 * @file stm32l0xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 *
7 ******************************************************************************
8 * @attention
9 *
10 * Copyright (c) 2016 STMicroelectronics.
11 * All rights reserved.
12 *
13 * This software is licensed under terms that can be found in the LICENSE file
14 * in the root directory of this software component.
15 * If no LICENSE file comes with this software, it is provided AS-IS.
16 *
17 ******************************************************************************
18 @verbatim
19 ==============================================================================
20 ##### How to use this driver #####
21 ==============================================================================
22 [..]
23 The LL SYSTEM driver contains a set of generic APIs that can be
24 used by user:
25 (+) Some of the FLASH features need to be handled in the SYSTEM file.
26 (+) Access to DBGCMU registers
27 (+) Access to SYSCFG registers
28
29 @endverbatim
30 ******************************************************************************
31 */
32
33 /* Define to prevent recursive inclusion -------------------------------------*/
34 #ifndef __STM32L0xx_LL_SYSTEM_H
35 #define __STM32L0xx_LL_SYSTEM_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32l0xx.h"
43
44 /** @addtogroup STM32L0xx_LL_Driver
45 * @{
46 */
47
48 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
49
50 /** @defgroup SYSTEM_LL SYSTEM
51 * @{
52 */
53
54 /* Private types -------------------------------------------------------------*/
55 /* Private variables ---------------------------------------------------------*/
56
57 /* Private constants ---------------------------------------------------------*/
58 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
59 * @{
60 */
61
62 /**
63 * @brief Power-down in Run mode Flash key
64 */
65 #define FLASH_PDKEY1 (0x04152637U) /*!< Flash power down key1 */
66 #define FLASH_PDKEY2 (0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1
67 to unlock the RUN_PD bit in FLASH_ACR */
68
69 /**
70 * @}
71 */
72
73 /* Private macros ------------------------------------------------------------*/
74
75 /* Exported types ------------------------------------------------------------*/
76 /* Exported constants --------------------------------------------------------*/
77 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
78 * @{
79 */
80
81 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG Memory Remap
82 * @{
83 */
84 #define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */
85 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
86 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< SRAM mapped at 0x00000000 */
87
88 /**
89 * @}
90 */
91
92 #if defined(SYSCFG_CFGR1_UFB)
93 /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG Bank Mode
94 * @{
95 */
96 #define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank1 mapped at 0x08000000 (and aliased at 0x00000000),
97 Flash Bank2 mapped at 0x08018000 (and aliased at 0x00018000),
98 Data EEPROM Bank1 mapped at 0x08080000 (and aliased at 0x00080000),
99 Data EEPROM Bank2 mapped at 0x08080C00 (and aliased at 0x00080C00) */
100 #define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_CFGR1_UFB /*!< Flash Bank2 mapped at 0x08000000 (and aliased at 0x00000000),
101 Flash Bank1 mapped at 0x08018000 (and aliased at 0x00018000),
102 Data EEPROM Bank2 mapped at 0x08080000 (and aliased at 0x00080000),
103 Data EEPROM Bank1 mapped at 0x08080C00 (and aliased at 0x00080C00) */
104 /**
105 * @}
106 */
107
108 #endif /* SYSCFG_CFGR1_UFB */
109
110 /** @defgroup SYSTEM_LL_EC_BOOTMODE SYSCFG Boot Mode
111 * @{
112 */
113 #define LL_SYSCFG_BOOTMODE_FLASH 0x00000000U /*!< Main Flash memory boot mode */
114 #define LL_SYSCFG_BOOTMODE_SYSTEMFLASH SYSCFG_CFGR1_BOOT_MODE_0 /*!< System Flash memory boot mode */
115 #define LL_SYSCFG_BOOTMODE_SRAM (SYSCFG_CFGR1_BOOT_MODE_1 | SYSCFG_CFGR1_BOOT_MODE_0) /*!< SRAM boot mode */
116
117 /**
118 * @}
119 */
120
121 #if defined(SYSCFG_CFGR2_CAPA)
122 /** @defgroup SYSTEM_LL_EC_CFGR2 SYSCFG VLCD Rail Connection
123 * @{
124 */
125
126 #define LL_SYSCFG_CAPA_VLCD2_PB2 SYSCFG_CFGR2_CAPA_0 /*!< Connect PB2 pin to LCD_VLCD2 rails supply voltage */
127 #define LL_SYSCFG_CAPA_VLCD1_PB12 SYSCFG_CFGR2_CAPA_1 /*!< Connect PB12 pin to LCD_VLCD1 rails supply voltage */
128 #define LL_SYSCFG_CAPA_VLCD3_PB0 SYSCFG_CFGR2_CAPA_2 /*!< Connect PB0 pin to LCD_VLCD3 rails supply voltage */
129 #if defined (SYSCFG_CFGR2_CAPA_3)
130 #define LL_SYSCFG_CAPA_VLCD1_PE11 SYSCFG_CFGR2_CAPA_3 /*!< Connect PE11 pin to LCD_VLCD1 rails supply voltage */
131 #endif /* SYSCFG_CFGR2_CAPA_3 */
132 #if defined (SYSCFG_CFGR2_CAPA_4)
133 #define LL_SYSCFG_CAPA_VLCD3_PE12 SYSCFG_CFGR2_CAPA_4 /*!< Connect PE12 pin to LCD_VLCD3 rails supply voltage */
134 #endif /* SYSCFG_CFGR2_CAPA_4 */
135 /**
136 * @}
137 */
138 #endif /* SYSCFG_CFGR2_CAPA */
139
140 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
141 * @{
142 */
143 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR2_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
144 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR2_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
145 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR2_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
146 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR2_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
147 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR2_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
148 #if defined(SYSCFG_CFGR2_I2C2_FMP)
149 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR2_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
150 #endif /* SYSCFG_CFGR2_I2C2_FMP */
151 #if defined(SYSCFG_CFGR2_I2C3_FMP)
152 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR2_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
153 #endif /* SYSCFG_CFGR2_I2C3_FMP */
154 /**
155 * @}
156 */
157
158 /** @defgroup SYSTEM_LL_VREFINT_CONTROL SYSCFG VREFINT Control
159 * @{
160 */
161 #define LL_SYSCFG_VREFINT_CONNECT_NONE 0x00000000U /*!< No pad connected to VREFINT_ADC */
162 #define LL_SYSCFG_VREFINT_CONNECT_IO1 SYSCFG_CFGR3_VREF_OUT_0 /*!< PB0 connected to VREFINT_ADC */
163 #define LL_SYSCFG_VREFINT_CONNECT_IO2 SYSCFG_CFGR3_VREF_OUT_1 /*!< PB1 connected to VREFINT_ADC */
164 #define LL_SYSCFG_VREFINT_CONNECT_IO1_IO2 (SYSCFG_CFGR3_VREF_OUT_0 | SYSCFG_CFGR3_VREF_OUT_1) /*!< PB0 and PB1 connected to VREFINT_ADC */
165 /**
166 * @}
167 */
168
169 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI Port
170 * @{
171 */
172 #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
173 #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
174 #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
175 #if defined(GPIOD_BASE)
176 #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */
177 #endif /*GPIOD_BASE*/
178 #if defined(GPIOE_BASE)
179 #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */
180 #endif /*GPIOE_BASE*/
181 #if defined(GPIOH_BASE)
182 #define LL_SYSCFG_EXTI_PORTH 5U /*!< EXTI PORT H */
183 #endif /*GPIOH_BASE*/
184 /**
185 * @}
186 */
187
188 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI Line
189 * @{
190 */
191 #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0U << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
192 #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(4U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */
193 #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(8U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
194 #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(12U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */
195 #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0U << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
196 #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(4U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */
197 #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(8U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
198 #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(12U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */
199 #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0U << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
200 #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(4U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */
201 #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(8U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
202 #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(12U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */
203 #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0U << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
204 #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(4U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */
205 #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(8U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
206 #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(12U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */
207 /**
208 * @}
209 */
210
211
212
213 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
214 * @{
215 */
216 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
217 #if defined(TIM3)
218 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
219 #endif /*TIM3*/
220 #if defined(TIM6)
221 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
222 #endif /*TIM6*/
223 #if defined(TIM7)
224 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
225 #endif /*TIM7*/
226 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC Calendar frozen when core is halted */
227 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
228 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
229 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
230 #if defined(I2C2)
231 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
232 #endif /*I2C2*/
233 #if defined(I2C3)
234 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
235 #endif /*I2C3*/
236 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP /*!< LPTIM1 counter stopped when core is halted */
237 /**
238 * @}
239 */
240
241 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
242 * @{
243 */
244 #if defined(TIM22)
245 #define LL_DBGMCU_APB2_GRP1_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP /*!< TIM22 counter stopped when core is halted */
246 #endif /*TIM22*/
247 #define LL_DBGMCU_APB2_GRP1_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP /*!< TIM21 counter stopped when core is halted */
248 /**
249 * @}
250 */
251
252 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
253 * @{
254 */
255 #define LL_FLASH_LATENCY_0 (0x00000000U) /*!< FLASH Zero Latency cycle */
256 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */
257 /**
258 * @}
259 */
260
261 /**
262 * @}
263 */
264
265 /* Exported macro ------------------------------------------------------------*/
266
267 /* Exported functions --------------------------------------------------------*/
268 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
269 * @{
270 */
271
272 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
273 * @{
274 */
275
276 /**
277 * @brief Set memory mapping at address 0x00000000
278 * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory
279 * @param Memory This parameter can be one of the following values:
280 * @arg @ref LL_SYSCFG_REMAP_FLASH
281 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
282 * @arg @ref LL_SYSCFG_REMAP_SRAM
283 * @retval None
284 */
LL_SYSCFG_SetRemapMemory(uint32_t Memory)285 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
286 {
287 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
288 }
289
290 /**
291 * @brief Get memory mapping at address 0x00000000
292 * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
293 * @retval Returned value can be one of the following values:
294 * @arg @ref LL_SYSCFG_REMAP_FLASH
295 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
296 * @arg @ref LL_SYSCFG_REMAP_SRAM
297 */
LL_SYSCFG_GetRemapMemory(void)298 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
299 {
300 return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
301 }
302
303 #if defined(SYSCFG_CFGR1_UFB)
304 /**
305 * @brief Select Flash bank mode (Bank flashed at 0x08000000)
306 * @rmtoll SYSCFG_CFGR1 UFB LL_SYSCFG_SetFlashBankMode
307 * @param Bank This parameter can be one of the following values:
308 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
309 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
310 * @retval None
311 */
LL_SYSCFG_SetFlashBankMode(uint32_t Bank)312 __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
313 {
314 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_UFB, Bank);
315 }
316
317 /**
318 * @brief Get Flash bank mode (Bank flashed at 0x08000000)
319 * @rmtoll SYSCFG_CFGR1 UFB LL_SYSCFG_GetFlashBankMode
320 * @retval Returned value can be one of the following values:
321 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
322 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
323 */
LL_SYSCFG_GetFlashBankMode(void)324 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
325 {
326 return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_UFB));
327 }
328 #endif /* SYSCFG_CFGR1_UFB */
329
330 /**
331 * @brief Get Boot mode selected by the boot pins status bits
332 * @note It indicates the boot mode selected by the boot pins. Bit 9
333 * corresponds to the complement of nBOOT1 bit in the FLASH_OPTR register.
334 * Its value is defined in the option bytes. Bit 8 corresponds to the
335 * value sampled on the BOOT0 pin.
336 * @rmtoll SYSCFG_CFGR1 BOOT_MODE LL_SYSCFG_GetBootMode
337 * @retval Returned value can be one of the following values:
338 * @arg @ref LL_SYSCFG_BOOTMODE_FLASH
339 * @arg @ref LL_SYSCFG_BOOTMODE_SYSTEMFLASH
340 * @arg @ref LL_SYSCFG_BOOTMODE_SRAM
341 */
LL_SYSCFG_GetBootMode(void)342 __STATIC_INLINE uint32_t LL_SYSCFG_GetBootMode(void)
343 {
344 return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOT_MODE));
345 }
346
347 /**
348 * @brief Firewall protection enabled
349 * @rmtoll SYSCFG_CFGR2 FWDIS LL_SYSCFG_EnableFirewall
350 * @retval None
351 */
LL_SYSCFG_EnableFirewall(void)352 __STATIC_INLINE void LL_SYSCFG_EnableFirewall(void)
353 {
354 CLEAR_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN);
355 }
356
357 /**
358 * @brief Check if Firewall protection is enabled or not
359 * @rmtoll SYSCFG_CFGR2 FWDIS LL_SYSCFG_IsEnabledFirewall
360 * @retval State of bit (1 or 0).
361 */
LL_SYSCFG_IsEnabledFirewall(void)362 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void)
363 {
364 return !(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN) == SYSCFG_CFGR2_FWDISEN);
365 }
366
367 #if defined(SYSCFG_CFGR2_CAPA)
368 /**
369 * @brief Set VLCD rail connection to optional external capacitor
370 * @note One to three external capacitors can be connected to pads to do
371 * VLCD biasing.
372 * - LCD_VLCD1 rail can be connected to PB12 or PE11(*),
373 * - LCD_VLCD2 rail can be connected to PB2,
374 * - LCD_VLCD3 rail can be connected to PB0 or PE12(*)
375 * @rmtoll SYSCFG_CFGR2 CAPA LL_SYSCFG_SetVLCDRailConnection
376 * @param IoPinConnect This parameter can be a combination of the following values:
377 * @arg @ref LL_SYSCFG_CAPA_VLCD1_PB12
378 * @arg @ref LL_SYSCFG_CAPA_VLCD1_PE11(*)
379 * @arg @ref LL_SYSCFG_CAPA_VLCD2_PB2
380 * @arg @ref LL_SYSCFG_CAPA_VLCD3_PB0
381 * @arg @ref LL_SYSCFG_CAPA_VLCD3_PE12(*)
382 *
383 * (*) value not defined in all devices
384 * @retval None
385 */
LL_SYSCFG_SetVLCDRailConnection(uint32_t IoPinConnect)386 __STATIC_INLINE void LL_SYSCFG_SetVLCDRailConnection(uint32_t IoPinConnect)
387 {
388 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CAPA, IoPinConnect);
389 }
390
391
392 /**
393 * @brief Get VLCD rail connection configuration
394 * @note One to three external capacitors can be connected to pads to do
395 * VLCD biasing.
396 * - LCD_VLCD1 rail can be connected to PB12 or PE11(*),
397 * - LCD_VLCD2 rail can be connected to PB2,
398 * - LCD_VLCD3 rail can be connected to PB0 or PE12(*)
399 * @rmtoll SYSCFG_CFGR2 CAPA LL_SYSCFG_GetVLCDRailConnection
400 * @retval Returned value can be a combination of the following values:
401 * @arg @ref LL_SYSCFG_CAPA_VLCD1_PB12
402 * @arg @ref LL_SYSCFG_CAPA_VLCD1_PE11(*)
403 * @arg @ref LL_SYSCFG_CAPA_VLCD2_PB2
404 * @arg @ref LL_SYSCFG_CAPA_VLCD3_PB0
405 * @arg @ref LL_SYSCFG_CAPA_VLCD3_PE12(*)
406 *
407 * (*) value not defined in all devices
408 */
LL_SYSCFG_GetVLCDRailConnection(void)409 __STATIC_INLINE uint32_t LL_SYSCFG_GetVLCDRailConnection(void)
410 {
411 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CAPA));
412 }
413 #endif
414
415 /**
416 * @brief Enable the I2C fast mode plus driving capability.
417 * @rmtoll SYSCFG_CFGR2 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
418 * SYSCFG_CFGR2 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
419 * @param ConfigFastModePlus This parameter can be a combination of the following values:
420 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
421 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
422 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
423 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
424 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
425 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
426 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
427 *
428 * (*) value not defined in all devices
429 * @retval None
430 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)431 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
432 {
433 SET_BIT(SYSCFG->CFGR2, ConfigFastModePlus);
434 }
435
436 /**
437 * @brief Disable the I2C fast mode plus driving capability.
438 * @rmtoll SYSCFG_CFGR2 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
439 * SYSCFG_CFGR2 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
440 * @param ConfigFastModePlus This parameter can be a combination of the following values:
441 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
442 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
443 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
444 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
445 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
446 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
447 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
448 *
449 * (*) value not defined in all devices
450 * @retval None
451 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)452 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
453 {
454 CLEAR_BIT(SYSCFG->CFGR2, ConfigFastModePlus);
455 }
456
457 /**
458 * @brief Select which pad is connected to VREFINT_ADC
459 * @rmtoll SYSCFG_CFGR3 SEL_VREF_OUT LL_SYSCFG_VREFINT_SetConnection
460 * @param IoPinConnect This parameter can be one of the following values:
461 * @arg @ref LL_SYSCFG_VREFINT_CONNECT_NONE
462 * @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO1
463 * @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO2
464 * @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO1_IO2
465 * @retval None
466 */
LL_SYSCFG_VREFINT_SetConnection(uint32_t IoPinConnect)467 __STATIC_INLINE void LL_SYSCFG_VREFINT_SetConnection(uint32_t IoPinConnect)
468 {
469 MODIFY_REG(SYSCFG->CFGR3, SYSCFG_CFGR3_VREF_OUT, IoPinConnect);
470 }
471
472 /**
473 * @brief Get pad connection to VREFINT_ADC
474 * @rmtoll SYSCFG_CFGR3 SEL_VREF_OUT LL_SYSCFG_VREFINT_GetConnection
475 * @retval Returned value can be one of the following values:
476 * @arg @ref LL_SYSCFG_VREFINT_CONNECT_NONE
477 * @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO1
478 * @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO2
479 * @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO1_IO2
480 */
LL_SYSCFG_VREFINT_GetConnection(void)481 __STATIC_INLINE uint32_t LL_SYSCFG_VREFINT_GetConnection(void)
482 {
483 return (uint32_t)(READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_VREF_OUT));
484 }
485
486 /**
487 * @brief Buffer used to generate VREFINT reference for ADC enable
488 * @note The VrefInit buffer to ADC through internal path is also
489 * enabled using function LL_ADC_SetCommonPathInternalCh()
490 * with parameter LL_ADC_PATH_INTERNAL_VREFINT
491 * @rmtoll SYSCFG_CFGR3 ENBUF_VREFINT_ADC LL_SYSCFG_VREFINT_EnableADC
492 * @retval None
493 */
LL_SYSCFG_VREFINT_EnableADC(void)494 __STATIC_INLINE void LL_SYSCFG_VREFINT_EnableADC(void)
495 {
496 SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC);
497 }
498
499 /**
500 * @brief Buffer used to generate VREFINT reference for ADC disable
501 * @rmtoll SYSCFG_CFGR3 ENBUF_VREFINT_ADC LL_SYSCFG_VREFINT_DisableADC
502 * @retval None
503 */
LL_SYSCFG_VREFINT_DisableADC(void)504 __STATIC_INLINE void LL_SYSCFG_VREFINT_DisableADC(void)
505 {
506 CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC);
507 }
508
509 /**
510 * @brief Buffer used to generate temperature sensor reference for ADC enable
511 * @rmtoll SYSCFG_CFGR3 ENBUF_SENSOR_ADC LL_SYSCFG_TEMPSENSOR_Enable
512 * @retval None
513 */
LL_SYSCFG_TEMPSENSOR_Enable(void)514 __STATIC_INLINE void LL_SYSCFG_TEMPSENSOR_Enable(void)
515 {
516 SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC);
517 }
518
519 /**
520 * @brief Buffer used to generate temperature sensor reference for ADC disable
521 * @rmtoll SYSCFG_CFGR3 ENBUF_SENSOR_ADC LL_SYSCFG_TEMPSENSOR_Disable
522 * @retval None
523 */
LL_SYSCFG_TEMPSENSOR_Disable(void)524 __STATIC_INLINE void LL_SYSCFG_TEMPSENSOR_Disable(void)
525 {
526 CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC);
527 }
528
529 /**
530 * @brief Buffer used to generate VREFINT reference for comparator enable
531 * @rmtoll SYSCFG_CFGR3 ENBUF_VREFINT_COMP LL_SYSCFG_VREFINT_EnableCOMP
532 * @retval None
533 */
LL_SYSCFG_VREFINT_EnableCOMP(void)534 __STATIC_INLINE void LL_SYSCFG_VREFINT_EnableCOMP(void)
535 {
536 SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP);
537 }
538
539 /**
540 * @brief Buffer used to generate VREFINT reference for comparator disable
541 * @rmtoll SYSCFG_CFGR3 ENBUF_VREFINT_COMP LL_SYSCFG_VREFINT_DisableCOMP
542 * @retval None
543 */
LL_SYSCFG_VREFINT_DisableCOMP(void)544 __STATIC_INLINE void LL_SYSCFG_VREFINT_DisableCOMP(void)
545 {
546 CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP);
547 }
548
549 #if defined (RCC_HSI48_SUPPORT)
550 /**
551 * @brief Buffer used to generate VREFINT reference for HSI48 oscillator enable
552 * @rmtoll SYSCFG_CFGR3 ENREF_HSI48 LL_SYSCFG_VREFINT_EnableHSI48
553 * @retval None
554 */
LL_SYSCFG_VREFINT_EnableHSI48(void)555 __STATIC_INLINE void LL_SYSCFG_VREFINT_EnableHSI48(void)
556 {
557 SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48);
558 }
559
560 /**
561 * @brief Buffer used to generate VREFINT reference for HSI48 oscillator disable
562 * @rmtoll SYSCFG_CFGR3 ENREF_HSI48 LL_SYSCFG_VREFINT_DisableHSI48
563 * @retval None
564 */
LL_SYSCFG_VREFINT_DisableHSI48(void)565 __STATIC_INLINE void LL_SYSCFG_VREFINT_DisableHSI48(void)
566 {
567 CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48);
568 }
569 #endif
570
571 /**
572 * @brief Check if VREFINT is ready or not
573 * @note When set, it indicates that VREFINT is available for BOR, PVD and LCD
574 * @rmtoll SYSCFG_CFGR3 VREFINT_RDYF LL_SYSCFG_VREFINT_IsReady
575 * @retval State of bit (1 or 0).
576 */
LL_SYSCFG_VREFINT_IsReady(void)577 __STATIC_INLINE uint32_t LL_SYSCFG_VREFINT_IsReady(void)
578 {
579 return (READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_RDYF) == SYSCFG_CFGR3_VREFINT_RDYF);
580 }
581
582 /**
583 * @brief Lock the whole content of SYSCFG_CFGR3 register
584 * @note After SYSCFG_CFGR3 register lock, only read access available.
585 * Only system hardware reset unlocks SYSCFG_CFGR3 register.
586 * @rmtoll SYSCFG_CFGR3 REF_LOCK LL_SYSCFG_VREFINT_Lock
587 * @retval None
588 */
LL_SYSCFG_VREFINT_Lock(void)589 __STATIC_INLINE void LL_SYSCFG_VREFINT_Lock(void)
590 {
591 SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK);
592 }
593
594 /**
595 * @brief Check if SYSCFG_CFGR3 register is locked (only read access) or not
596 * @note When set, it indicates that SYSCFG_CFGR3 register is locked, only read access available
597 * @rmtoll SYSCFG_CFGR3 REF_LOCK LL_SYSCFG_VREFINT_IsLocked
598 * @retval State of bit (1 or 0).
599 */
LL_SYSCFG_VREFINT_IsLocked(void)600 __STATIC_INLINE uint32_t LL_SYSCFG_VREFINT_IsLocked(void)
601 {
602 return (READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK) == SYSCFG_CFGR3_REF_LOCK);
603 }
604
605 /**
606 * @brief Configure source input for the EXTI external interrupt.
607 * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
608 * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
609 * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
610 * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
611 * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
612 * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
613 * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
614 * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
615 * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
616 * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
617 * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
618 * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
619 * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
620 * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
621 * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
622 * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
623 * @param Port This parameter can be one of the following values:
624 * @arg @ref LL_SYSCFG_EXTI_PORTA
625 * @arg @ref LL_SYSCFG_EXTI_PORTB
626 * @arg @ref LL_SYSCFG_EXTI_PORTC
627 * @arg @ref LL_SYSCFG_EXTI_PORTD (*)
628 * @arg @ref LL_SYSCFG_EXTI_PORTE (*)
629 * @arg @ref LL_SYSCFG_EXTI_PORTH (*)
630 *
631 * (*) value not defined in all devices
632 * @param Line This parameter can be one of the following values:
633 * @arg @ref LL_SYSCFG_EXTI_LINE0
634 * @arg @ref LL_SYSCFG_EXTI_LINE1
635 * @arg @ref LL_SYSCFG_EXTI_LINE2
636 * @arg @ref LL_SYSCFG_EXTI_LINE3
637 * @arg @ref LL_SYSCFG_EXTI_LINE4
638 * @arg @ref LL_SYSCFG_EXTI_LINE5
639 * @arg @ref LL_SYSCFG_EXTI_LINE6
640 * @arg @ref LL_SYSCFG_EXTI_LINE7
641 * @arg @ref LL_SYSCFG_EXTI_LINE8
642 * @arg @ref LL_SYSCFG_EXTI_LINE9
643 * @arg @ref LL_SYSCFG_EXTI_LINE10
644 * @arg @ref LL_SYSCFG_EXTI_LINE11
645 * @arg @ref LL_SYSCFG_EXTI_LINE12
646 * @arg @ref LL_SYSCFG_EXTI_LINE13
647 * @arg @ref LL_SYSCFG_EXTI_LINE14
648 * @arg @ref LL_SYSCFG_EXTI_LINE15
649 * @retval None
650 */
LL_SYSCFG_SetEXTISource(uint32_t Port,uint32_t Line)651 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
652 {
653 MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], SYSCFG_EXTICR1_EXTI0 << (Line >> 16U), Port << (Line >> 16U));
654 }
655
656 /**
657 * @brief Get the configured defined for specific EXTI Line
658 * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
659 * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
660 * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
661 * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
662 * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
663 * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
664 * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
665 * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
666 * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
667 * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
668 * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
669 * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
670 * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
671 * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
672 * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
673 * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
674 * @param Line This parameter can be one of the following values:
675 * @arg @ref LL_SYSCFG_EXTI_LINE0
676 * @arg @ref LL_SYSCFG_EXTI_LINE1
677 * @arg @ref LL_SYSCFG_EXTI_LINE2
678 * @arg @ref LL_SYSCFG_EXTI_LINE3
679 * @arg @ref LL_SYSCFG_EXTI_LINE4
680 * @arg @ref LL_SYSCFG_EXTI_LINE5
681 * @arg @ref LL_SYSCFG_EXTI_LINE6
682 * @arg @ref LL_SYSCFG_EXTI_LINE7
683 * @arg @ref LL_SYSCFG_EXTI_LINE8
684 * @arg @ref LL_SYSCFG_EXTI_LINE9
685 * @arg @ref LL_SYSCFG_EXTI_LINE10
686 * @arg @ref LL_SYSCFG_EXTI_LINE11
687 * @arg @ref LL_SYSCFG_EXTI_LINE12
688 * @arg @ref LL_SYSCFG_EXTI_LINE13
689 * @arg @ref LL_SYSCFG_EXTI_LINE14
690 * @arg @ref LL_SYSCFG_EXTI_LINE15
691 * @retval Returned value can be one of the following values:
692 * @arg @ref LL_SYSCFG_EXTI_PORTA
693 * @arg @ref LL_SYSCFG_EXTI_PORTB
694 * @arg @ref LL_SYSCFG_EXTI_PORTC
695 * @arg @ref LL_SYSCFG_EXTI_PORTD (*)
696 * @arg @ref LL_SYSCFG_EXTI_PORTE (*)
697 * @arg @ref LL_SYSCFG_EXTI_PORTH (*)
698 *
699 * (*) value not defined in all devices
700 */
LL_SYSCFG_GetEXTISource(uint32_t Line)701 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
702 {
703 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (SYSCFG_EXTICR1_EXTI0 << (Line >> 16U))) >> (Line >> 16U));
704 }
705
706
707 /**
708 * @}
709 */
710
711
712 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
713 * @{
714 */
715
716 /**
717 * @brief Return the device identifier
718 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
719 * @retval Values between Min_Data=0x00 and Max_Data=0x7FF (ex: L053 -> 0x417, L073 -> 0x447)
720 */
LL_DBGMCU_GetDeviceID(void)721 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
722 {
723 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
724 }
725
726 /**
727 * @brief Return the device revision identifier
728 * @note This field indicates the revision of the device.
729 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
730 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
731 */
LL_DBGMCU_GetRevisionID(void)732 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
733 {
734 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
735 }
736
737 /**
738 * @brief Enable the Debug Module during SLEEP mode
739 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
740 * @retval None
741 */
LL_DBGMCU_EnableDBGSleepMode(void)742 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
743 {
744 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
745 }
746
747 /**
748 * @brief Disable the Debug Module during SLEEP mode
749 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
750 * @retval None
751 */
LL_DBGMCU_DisableDBGSleepMode(void)752 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
753 {
754 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
755 }
756
757 /**
758 * @brief Enable the Debug Module during STOP mode
759 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
760 * @retval None
761 */
LL_DBGMCU_EnableDBGStopMode(void)762 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
763 {
764 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
765 }
766
767 /**
768 * @brief Disable the Debug Module during STOP mode
769 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
770 * @retval None
771 */
LL_DBGMCU_DisableDBGStopMode(void)772 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
773 {
774 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
775 }
776
777 /**
778 * @brief Enable the Debug Module during STANDBY mode
779 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
780 * @retval None
781 */
LL_DBGMCU_EnableDBGStandbyMode(void)782 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
783 {
784 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
785 }
786
787 /**
788 * @brief Disable the Debug Module during STANDBY mode
789 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
790 * @retval None
791 */
LL_DBGMCU_DisableDBGStandbyMode(void)792 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
793 {
794 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
795 }
796
797 /**
798 * @brief Freeze APB1 peripherals (group1 peripherals)
799 * @rmtoll APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
800 * APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
801 * APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
802 * APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
803 * APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
804 * APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
805 * APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
806 * APB1FZ DBG_I2C1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
807 * APB1FZ DBG_I2C2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
808 * APB1FZ DBG_I2C3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
809 * APB1FZ DBG_LPTIMER_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
810 * @param Periphs This parameter can be a combination of the following values:
811 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
812 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
813 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
814 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
815 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
816 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
817 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
818 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
819 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
820 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
821 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
822 *
823 * (*) value not defined in all devices
824 * @retval None
825 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)826 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
827 {
828 SET_BIT(DBGMCU->APB1FZ, Periphs);
829 }
830
831 /**
832 * @brief Unfreeze APB1 peripherals (group1 peripherals)
833 * @rmtoll APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
834 * APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
835 * APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
836 * APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
837 * APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
838 * APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
839 * APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
840 * APB1FZ DBG_I2C1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
841 * APB1FZ DBG_I2C2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
842 * APB1FZ DBG_I2C3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
843 * APB1FZ DBG_LPTIMER_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
844 * @param Periphs This parameter can be a combination of the following values:
845 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
846 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
847 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
848 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
849 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
850 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
851 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
852 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
853 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
854 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
855 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
856 *
857 * (*) value not defined in all devices
858 * @retval None
859 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)860 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
861 {
862 CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
863 }
864
865 /**
866 * @brief Freeze APB2 peripherals
867 * @rmtoll APB2FZ DBG_TIM22_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
868 * APB2FZ DBG_TIM21_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
869 * @param Periphs This parameter can be a combination of the following values:
870 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM22_STOP (*)
871 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM21_STOP
872 *
873 * (*) value not defined in all devices
874 * @retval None
875 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)876 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
877 {
878 SET_BIT(DBGMCU->APB2FZ, Periphs);
879 }
880
881 /**
882 * @brief Unfreeze APB2 peripherals
883 * @rmtoll APB2FZ DBG_TIM22_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
884 * APB2FZ DBG_TIM21_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
885 * @param Periphs This parameter can be a combination of the following values:
886 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM22_STOP (*)
887 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM21_STOP
888 *
889 * (*) value not defined in all devices
890 * @retval None
891 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)892 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
893 {
894 CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
895 }
896
897 /**
898 * @}
899 */
900
901 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
902 * @{
903 */
904
905 /**
906 * @brief Set FLASH Latency
907 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
908 * @param Latency This parameter can be one of the following values:
909 * @arg @ref LL_FLASH_LATENCY_0
910 * @arg @ref LL_FLASH_LATENCY_1
911 * @retval None
912 */
LL_FLASH_SetLatency(uint32_t Latency)913 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
914 {
915 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
916 }
917
918 /**
919 * @brief Get FLASH Latency
920 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
921 * @retval Returned value can be one of the following values:
922 * @arg @ref LL_FLASH_LATENCY_0
923 * @arg @ref LL_FLASH_LATENCY_1
924 */
LL_FLASH_GetLatency(void)925 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
926 {
927 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
928 }
929
930 /**
931 * @brief Enable Prefetch
932 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
933 * @retval None
934 */
LL_FLASH_EnablePrefetch(void)935 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
936 {
937 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
938 }
939
940 /**
941 * @brief Disable Prefetch
942 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
943 * @retval None
944 */
LL_FLASH_DisablePrefetch(void)945 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
946 {
947 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
948 }
949
950 /**
951 * @brief Check if Prefetch buffer is enabled
952 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
953 * @retval State of bit (1 or 0).
954 */
LL_FLASH_IsPrefetchEnabled(void)955 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
956 {
957 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
958 }
959
960
961 /**
962 * @brief Enable Flash Power-down mode during run mode or Low-power run mode
963 * @note Flash memory can be put in power-down mode only when the code is executed
964 * from RAM
965 * @note Flash must not be accessed when power down is enabled
966 * @note Flash must not be put in power-down while a program or an erase operation
967 * is on-going
968 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
969 * FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n
970 * FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown
971 * @retval None
972 */
LL_FLASH_EnableRunPowerDown(void)973 __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
974 {
975 /* Following values must be written consecutively to unlock the RUN_PD bit in
976 FLASH_ACR */
977 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
978 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
979 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
980 }
981
982 /**
983 * @brief Disable Flash Power-down mode during run mode or Low-power run mode
984 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n
985 * FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n
986 * FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown
987 * @retval None
988 */
LL_FLASH_DisableRunPowerDown(void)989 __STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
990 {
991 /* Following values must be written consecutively to unlock the RUN_PD bit in
992 FLASH_ACR */
993 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
994 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
995 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
996 }
997
998 /**
999 * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
1000 * @note Flash must not be put in power-down while a program or an erase operation
1001 * is on-going
1002 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
1003 * @retval None
1004 */
LL_FLASH_EnableSleepPowerDown(void)1005 __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
1006 {
1007 SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1008 }
1009
1010 /**
1011 * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
1012 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
1013 * @retval None
1014 */
LL_FLASH_DisableSleepPowerDown(void)1015 __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
1016 {
1017 CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1018 }
1019
1020 /**
1021 * @brief Enable buffers used as a cache during read access
1022 * @rmtoll FLASH_ACR DISAB_BUF LL_FLASH_EnableBuffers
1023 * @retval None
1024 */
LL_FLASH_EnableBuffers(void)1025 __STATIC_INLINE void LL_FLASH_EnableBuffers(void)
1026 {
1027 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DISAB_BUF);
1028 }
1029
1030 /**
1031 * @brief Disable buffers used as a cache during read access
1032 * @note When disabled, every read will access the NVM even for
1033 * an address already read (for example, the previous address).
1034 * @rmtoll FLASH_ACR DISAB_BUF LL_FLASH_DisableBuffers
1035 * @retval None
1036 */
LL_FLASH_DisableBuffers(void)1037 __STATIC_INLINE void LL_FLASH_DisableBuffers(void)
1038 {
1039 SET_BIT(FLASH->ACR, FLASH_ACR_DISAB_BUF);
1040 }
1041
1042 /**
1043 * @brief Enable pre-read
1044 * @note When enabled, the memory interface stores the last address
1045 * read as data and tries to read the next one when no other
1046 * read or write or prefetch operation is ongoing.
1047 * It is automatically disabled every time the buffers are disabled.
1048 * @rmtoll FLASH_ACR PRE_READ LL_FLASH_EnablePreRead
1049 * @retval None
1050 */
LL_FLASH_EnablePreRead(void)1051 __STATIC_INLINE void LL_FLASH_EnablePreRead(void)
1052 {
1053 SET_BIT(FLASH->ACR, FLASH_ACR_PRE_READ);
1054 }
1055
1056 /**
1057 * @brief Disable pre-read
1058 * @rmtoll FLASH_ACR PRE_READ LL_FLASH_DisablePreRead
1059 * @retval None
1060 */
LL_FLASH_DisablePreRead(void)1061 __STATIC_INLINE void LL_FLASH_DisablePreRead(void)
1062 {
1063 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRE_READ);
1064 }
1065
1066 /**
1067 * @}
1068 */
1069
1070 /**
1071 * @}
1072 */
1073
1074 /**
1075 * @}
1076 */
1077
1078 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
1079
1080 /**
1081 * @}
1082 */
1083
1084 #ifdef __cplusplus
1085 }
1086 #endif
1087
1088 #endif /* __STM32L0xx_LL_SYSTEM_H */
1089
1090
