1 /**
2 ******************************************************************************
3 * @file stm32l0xx_ll_spi.h
4 * @author MCD Application Team
5 * @brief Header file of SPI LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L0xx_LL_SPI_H
21 #define STM32L0xx_LL_SPI_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l0xx.h"
29
30 /** @addtogroup STM32L0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (SPI1) || defined (SPI2)
35
36 /** @defgroup SPI_LL SPI
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43
44 /* Exported types ------------------------------------------------------------*/
45 #if defined(USE_FULL_LL_DRIVER)
46 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
47 * @{
48 */
49
50 /**
51 * @brief SPI Init structures definition
52 */
53 typedef struct
54 {
55 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
56 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
57
58 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
59
60 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
61 This parameter can be a value of @ref SPI_LL_EC_MODE.
62
63 This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
64
65 uint32_t DataWidth; /*!< Specifies the SPI data width.
66 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
67
68 This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
69
70 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
71 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
72
73 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
74
75 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
76 This parameter can be a value of @ref SPI_LL_EC_PHASE.
77
78 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
79
80 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
81 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
82
83 This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
84
85 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
86 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
87 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
88
89 This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
90
91 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
92 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
93
94 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
95
96 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
97 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
98
99 This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
100
101 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
102 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
103
104 This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
105
106 } LL_SPI_InitTypeDef;
107
108 /**
109 * @}
110 */
111 #endif /* USE_FULL_LL_DRIVER */
112
113 /* Exported constants --------------------------------------------------------*/
114 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
115 * @{
116 */
117
118 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
119 * @brief Flags defines which can be used with LL_SPI_ReadReg function
120 * @{
121 */
122 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
123 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
124 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
125 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
126 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
127 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
128 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
129 /**
130 * @}
131 */
132
133 /** @defgroup SPI_LL_EC_IT IT Defines
134 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
135 * @{
136 */
137 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
138 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
139 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
140 /**
141 * @}
142 */
143
144 /** @defgroup SPI_LL_EC_MODE Operation Mode
145 * @{
146 */
147 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
148 #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
149 /**
150 * @}
151 */
152
153 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
154 * @{
155 */
156 #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
157 #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
158 /**
159 * @}
160 */
161
162 /** @defgroup SPI_LL_EC_PHASE Clock Phase
163 * @{
164 */
165 #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
166 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
167 /**
168 * @}
169 */
170
171 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
172 * @{
173 */
174 #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
175 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
176 /**
177 * @}
178 */
179
180 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
181 * @{
182 */
183 #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
184 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
185 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
186 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
187 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
188 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
189 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
190 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
191 /**
192 * @}
193 */
194
195 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
196 * @{
197 */
198 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
199 #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
200 /**
201 * @}
202 */
203
204 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
205 * @{
206 */
207 #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
208 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
209 #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
210 #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
211 /**
212 * @}
213 */
214
215 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
216 * @{
217 */
218 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
219 #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
220 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
221 /**
222 * @}
223 */
224
225 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
226 * @{
227 */
228 #define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */
229 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
230 /**
231 * @}
232 */
233 #if defined(USE_FULL_LL_DRIVER)
234
235 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
236 * @{
237 */
238 #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
239 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
240 /**
241 * @}
242 */
243 #endif /* USE_FULL_LL_DRIVER */
244
245 /**
246 * @}
247 */
248
249 /* Exported macro ------------------------------------------------------------*/
250 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
251 * @{
252 */
253
254 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
255 * @{
256 */
257
258 /**
259 * @brief Write a value in SPI register
260 * @param __INSTANCE__ SPI Instance
261 * @param __REG__ Register to be written
262 * @param __VALUE__ Value to be written in the register
263 * @retval None
264 */
265 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
266
267 /**
268 * @brief Read a value in SPI register
269 * @param __INSTANCE__ SPI Instance
270 * @param __REG__ Register to be read
271 * @retval Register value
272 */
273 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
274 /**
275 * @}
276 */
277
278 /**
279 * @}
280 */
281
282 /* Exported functions --------------------------------------------------------*/
283 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
284 * @{
285 */
286
287 /** @defgroup SPI_LL_EF_Configuration Configuration
288 * @{
289 */
290
291 /**
292 * @brief Enable SPI peripheral
293 * @rmtoll CR1 SPE LL_SPI_Enable
294 * @param SPIx SPI Instance
295 * @retval None
296 */
LL_SPI_Enable(SPI_TypeDef * SPIx)297 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
298 {
299 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
300 }
301
302 /**
303 * @brief Disable SPI peripheral
304 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
305 * @rmtoll CR1 SPE LL_SPI_Disable
306 * @param SPIx SPI Instance
307 * @retval None
308 */
LL_SPI_Disable(SPI_TypeDef * SPIx)309 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
310 {
311 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
312 }
313
314 /**
315 * @brief Check if SPI peripheral is enabled
316 * @rmtoll CR1 SPE LL_SPI_IsEnabled
317 * @param SPIx SPI Instance
318 * @retval State of bit (1 or 0).
319 */
LL_SPI_IsEnabled(SPI_TypeDef * SPIx)320 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
321 {
322 return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
323 }
324
325 /**
326 * @brief Set SPI operation mode to Master or Slave
327 * @note This bit should not be changed when communication is ongoing.
328 * @rmtoll CR1 MSTR LL_SPI_SetMode\n
329 * CR1 SSI LL_SPI_SetMode
330 * @param SPIx SPI Instance
331 * @param Mode This parameter can be one of the following values:
332 * @arg @ref LL_SPI_MODE_MASTER
333 * @arg @ref LL_SPI_MODE_SLAVE
334 * @retval None
335 */
LL_SPI_SetMode(SPI_TypeDef * SPIx,uint32_t Mode)336 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
337 {
338 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
339 }
340
341 /**
342 * @brief Get SPI operation mode (Master or Slave)
343 * @rmtoll CR1 MSTR LL_SPI_GetMode\n
344 * CR1 SSI LL_SPI_GetMode
345 * @param SPIx SPI Instance
346 * @retval Returned value can be one of the following values:
347 * @arg @ref LL_SPI_MODE_MASTER
348 * @arg @ref LL_SPI_MODE_SLAVE
349 */
LL_SPI_GetMode(SPI_TypeDef * SPIx)350 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
351 {
352 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
353 }
354
355 /**
356 * @brief Set serial protocol used
357 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
358 * @rmtoll CR2 FRF LL_SPI_SetStandard
359 * @param SPIx SPI Instance
360 * @param Standard This parameter can be one of the following values:
361 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
362 * @arg @ref LL_SPI_PROTOCOL_TI
363 * @retval None
364 */
LL_SPI_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)365 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
366 {
367 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
368 }
369
370 /**
371 * @brief Get serial protocol used
372 * @rmtoll CR2 FRF LL_SPI_GetStandard
373 * @param SPIx SPI Instance
374 * @retval Returned value can be one of the following values:
375 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
376 * @arg @ref LL_SPI_PROTOCOL_TI
377 */
LL_SPI_GetStandard(SPI_TypeDef * SPIx)378 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
379 {
380 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
381 }
382
383 /**
384 * @brief Set clock phase
385 * @note This bit should not be changed when communication is ongoing.
386 * This bit is not used in SPI TI mode.
387 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
388 * @param SPIx SPI Instance
389 * @param ClockPhase This parameter can be one of the following values:
390 * @arg @ref LL_SPI_PHASE_1EDGE
391 * @arg @ref LL_SPI_PHASE_2EDGE
392 * @retval None
393 */
LL_SPI_SetClockPhase(SPI_TypeDef * SPIx,uint32_t ClockPhase)394 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
395 {
396 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
397 }
398
399 /**
400 * @brief Get clock phase
401 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
402 * @param SPIx SPI Instance
403 * @retval Returned value can be one of the following values:
404 * @arg @ref LL_SPI_PHASE_1EDGE
405 * @arg @ref LL_SPI_PHASE_2EDGE
406 */
LL_SPI_GetClockPhase(SPI_TypeDef * SPIx)407 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
408 {
409 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
410 }
411
412 /**
413 * @brief Set clock polarity
414 * @note This bit should not be changed when communication is ongoing.
415 * This bit is not used in SPI TI mode.
416 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
417 * @param SPIx SPI Instance
418 * @param ClockPolarity This parameter can be one of the following values:
419 * @arg @ref LL_SPI_POLARITY_LOW
420 * @arg @ref LL_SPI_POLARITY_HIGH
421 * @retval None
422 */
LL_SPI_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)423 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
424 {
425 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
426 }
427
428 /**
429 * @brief Get clock polarity
430 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
431 * @param SPIx SPI Instance
432 * @retval Returned value can be one of the following values:
433 * @arg @ref LL_SPI_POLARITY_LOW
434 * @arg @ref LL_SPI_POLARITY_HIGH
435 */
LL_SPI_GetClockPolarity(SPI_TypeDef * SPIx)436 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
437 {
438 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
439 }
440
441 /**
442 * @brief Set baud rate prescaler
443 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
444 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
445 * @param SPIx SPI Instance
446 * @param BaudRate This parameter can be one of the following values:
447 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
448 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
449 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
450 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
451 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
452 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
453 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
454 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
455 * @retval None
456 */
LL_SPI_SetBaudRatePrescaler(SPI_TypeDef * SPIx,uint32_t BaudRate)457 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
458 {
459 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
460 }
461
462 /**
463 * @brief Get baud rate prescaler
464 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
465 * @param SPIx SPI Instance
466 * @retval Returned value can be one of the following values:
467 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
468 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
469 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
470 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
471 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
472 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
473 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
474 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
475 */
LL_SPI_GetBaudRatePrescaler(SPI_TypeDef * SPIx)476 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
477 {
478 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
479 }
480
481 /**
482 * @brief Set transfer bit order
483 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
484 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
485 * @param SPIx SPI Instance
486 * @param BitOrder This parameter can be one of the following values:
487 * @arg @ref LL_SPI_LSB_FIRST
488 * @arg @ref LL_SPI_MSB_FIRST
489 * @retval None
490 */
LL_SPI_SetTransferBitOrder(SPI_TypeDef * SPIx,uint32_t BitOrder)491 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
492 {
493 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
494 }
495
496 /**
497 * @brief Get transfer bit order
498 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
499 * @param SPIx SPI Instance
500 * @retval Returned value can be one of the following values:
501 * @arg @ref LL_SPI_LSB_FIRST
502 * @arg @ref LL_SPI_MSB_FIRST
503 */
LL_SPI_GetTransferBitOrder(SPI_TypeDef * SPIx)504 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
505 {
506 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
507 }
508
509 /**
510 * @brief Set transfer direction mode
511 * @note For Half-Duplex mode, Rx Direction is set by default.
512 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
513 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
514 * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
515 * CR1 BIDIOE LL_SPI_SetTransferDirection
516 * @param SPIx SPI Instance
517 * @param TransferDirection This parameter can be one of the following values:
518 * @arg @ref LL_SPI_FULL_DUPLEX
519 * @arg @ref LL_SPI_SIMPLEX_RX
520 * @arg @ref LL_SPI_HALF_DUPLEX_RX
521 * @arg @ref LL_SPI_HALF_DUPLEX_TX
522 * @retval None
523 */
LL_SPI_SetTransferDirection(SPI_TypeDef * SPIx,uint32_t TransferDirection)524 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
525 {
526 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
527 }
528
529 /**
530 * @brief Get transfer direction mode
531 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
532 * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
533 * CR1 BIDIOE LL_SPI_GetTransferDirection
534 * @param SPIx SPI Instance
535 * @retval Returned value can be one of the following values:
536 * @arg @ref LL_SPI_FULL_DUPLEX
537 * @arg @ref LL_SPI_SIMPLEX_RX
538 * @arg @ref LL_SPI_HALF_DUPLEX_RX
539 * @arg @ref LL_SPI_HALF_DUPLEX_TX
540 */
LL_SPI_GetTransferDirection(SPI_TypeDef * SPIx)541 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
542 {
543 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
544 }
545
546 /**
547 * @brief Set frame data width
548 * @rmtoll CR1 DFF LL_SPI_SetDataWidth
549 * @param SPIx SPI Instance
550 * @param DataWidth This parameter can be one of the following values:
551 * @arg @ref LL_SPI_DATAWIDTH_8BIT
552 * @arg @ref LL_SPI_DATAWIDTH_16BIT
553 * @retval None
554 */
LL_SPI_SetDataWidth(SPI_TypeDef * SPIx,uint32_t DataWidth)555 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
556 {
557 MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
558 }
559
560 /**
561 * @brief Get frame data width
562 * @rmtoll CR1 DFF LL_SPI_GetDataWidth
563 * @param SPIx SPI Instance
564 * @retval Returned value can be one of the following values:
565 * @arg @ref LL_SPI_DATAWIDTH_8BIT
566 * @arg @ref LL_SPI_DATAWIDTH_16BIT
567 */
LL_SPI_GetDataWidth(SPI_TypeDef * SPIx)568 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
569 {
570 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
571 }
572
573 /**
574 * @}
575 */
576
577 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
578 * @{
579 */
580
581 /**
582 * @brief Enable CRC
583 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
584 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
585 * @param SPIx SPI Instance
586 * @retval None
587 */
LL_SPI_EnableCRC(SPI_TypeDef * SPIx)588 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
589 {
590 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
591 }
592
593 /**
594 * @brief Disable CRC
595 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
596 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
597 * @param SPIx SPI Instance
598 * @retval None
599 */
LL_SPI_DisableCRC(SPI_TypeDef * SPIx)600 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
601 {
602 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
603 }
604
605 /**
606 * @brief Check if CRC is enabled
607 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
608 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
609 * @param SPIx SPI Instance
610 * @retval State of bit (1 or 0).
611 */
LL_SPI_IsEnabledCRC(SPI_TypeDef * SPIx)612 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
613 {
614 return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
615 }
616
617 /**
618 * @brief Set CRCNext to transfer CRC on the line
619 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
620 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
621 * @param SPIx SPI Instance
622 * @retval None
623 */
LL_SPI_SetCRCNext(SPI_TypeDef * SPIx)624 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
625 {
626 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
627 }
628
629 /**
630 * @brief Set polynomial for CRC calculation
631 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
632 * @param SPIx SPI Instance
633 * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
634 * @retval None
635 */
LL_SPI_SetCRCPolynomial(SPI_TypeDef * SPIx,uint32_t CRCPoly)636 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
637 {
638 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
639 }
640
641 /**
642 * @brief Get polynomial for CRC calculation
643 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
644 * @param SPIx SPI Instance
645 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
646 */
LL_SPI_GetCRCPolynomial(SPI_TypeDef * SPIx)647 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
648 {
649 return (uint32_t)(READ_REG(SPIx->CRCPR));
650 }
651
652 /**
653 * @brief Get Rx CRC
654 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
655 * @param SPIx SPI Instance
656 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
657 */
LL_SPI_GetRxCRC(SPI_TypeDef * SPIx)658 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
659 {
660 return (uint32_t)(READ_REG(SPIx->RXCRCR));
661 }
662
663 /**
664 * @brief Get Tx CRC
665 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
666 * @param SPIx SPI Instance
667 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
668 */
LL_SPI_GetTxCRC(SPI_TypeDef * SPIx)669 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
670 {
671 return (uint32_t)(READ_REG(SPIx->TXCRCR));
672 }
673
674 /**
675 * @}
676 */
677
678 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
679 * @{
680 */
681
682 /**
683 * @brief Set NSS mode
684 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
685 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
686 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
687 * @param SPIx SPI Instance
688 * @param NSS This parameter can be one of the following values:
689 * @arg @ref LL_SPI_NSS_SOFT
690 * @arg @ref LL_SPI_NSS_HARD_INPUT
691 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
692 * @retval None
693 */
LL_SPI_SetNSSMode(SPI_TypeDef * SPIx,uint32_t NSS)694 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
695 {
696 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
697 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
698 }
699
700 /**
701 * @brief Get NSS mode
702 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
703 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
704 * @param SPIx SPI Instance
705 * @retval Returned value can be one of the following values:
706 * @arg @ref LL_SPI_NSS_SOFT
707 * @arg @ref LL_SPI_NSS_HARD_INPUT
708 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
709 */
LL_SPI_GetNSSMode(SPI_TypeDef * SPIx)710 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
711 {
712 uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
713 uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
714 return (Ssm | Ssoe);
715 }
716
717 /**
718 * @}
719 */
720
721 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
722 * @{
723 */
724
725 /**
726 * @brief Check if Rx buffer is not empty
727 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
728 * @param SPIx SPI Instance
729 * @retval State of bit (1 or 0).
730 */
LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef * SPIx)731 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
732 {
733 return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
734 }
735
736 /**
737 * @brief Check if Tx buffer is empty
738 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
739 * @param SPIx SPI Instance
740 * @retval State of bit (1 or 0).
741 */
LL_SPI_IsActiveFlag_TXE(SPI_TypeDef * SPIx)742 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
743 {
744 return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
745 }
746
747 /**
748 * @brief Get CRC error flag
749 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
750 * @param SPIx SPI Instance
751 * @retval State of bit (1 or 0).
752 */
LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef * SPIx)753 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
754 {
755 return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
756 }
757
758 /**
759 * @brief Get mode fault error flag
760 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
761 * @param SPIx SPI Instance
762 * @retval State of bit (1 or 0).
763 */
LL_SPI_IsActiveFlag_MODF(SPI_TypeDef * SPIx)764 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
765 {
766 return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
767 }
768
769 /**
770 * @brief Get overrun error flag
771 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
772 * @param SPIx SPI Instance
773 * @retval State of bit (1 or 0).
774 */
LL_SPI_IsActiveFlag_OVR(SPI_TypeDef * SPIx)775 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
776 {
777 return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
778 }
779
780 /**
781 * @brief Get busy flag
782 * @note The BSY flag is cleared under any one of the following conditions:
783 * -When the SPI is correctly disabled
784 * -When a fault is detected in Master mode (MODF bit set to 1)
785 * -In Master mode, when it finishes a data transmission and no new data is ready to be
786 * sent
787 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
788 * each data transfer.
789 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
790 * @param SPIx SPI Instance
791 * @retval State of bit (1 or 0).
792 */
LL_SPI_IsActiveFlag_BSY(SPI_TypeDef * SPIx)793 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
794 {
795 return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
796 }
797
798 /**
799 * @brief Get frame format error flag
800 * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
801 * @param SPIx SPI Instance
802 * @retval State of bit (1 or 0).
803 */
LL_SPI_IsActiveFlag_FRE(SPI_TypeDef * SPIx)804 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
805 {
806 return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
807 }
808
809 /**
810 * @brief Clear CRC error flag
811 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
812 * @param SPIx SPI Instance
813 * @retval None
814 */
LL_SPI_ClearFlag_CRCERR(SPI_TypeDef * SPIx)815 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
816 {
817 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
818 }
819
820 /**
821 * @brief Clear mode fault error flag
822 * @note Clearing this flag is done by a read access to the SPIx_SR
823 * register followed by a write access to the SPIx_CR1 register
824 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
825 * @param SPIx SPI Instance
826 * @retval None
827 */
LL_SPI_ClearFlag_MODF(SPI_TypeDef * SPIx)828 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
829 {
830 __IO uint32_t tmpreg_sr;
831 tmpreg_sr = SPIx->SR;
832 (void) tmpreg_sr;
833 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
834 }
835
836 /**
837 * @brief Clear overrun error flag
838 * @note Clearing this flag is done by a read access to the SPIx_DR
839 * register followed by a read access to the SPIx_SR register
840 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
841 * @param SPIx SPI Instance
842 * @retval None
843 */
LL_SPI_ClearFlag_OVR(SPI_TypeDef * SPIx)844 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
845 {
846 __IO uint32_t tmpreg;
847 tmpreg = SPIx->DR;
848 (void) tmpreg;
849 tmpreg = SPIx->SR;
850 (void) tmpreg;
851 }
852
853 /**
854 * @brief Clear frame format error flag
855 * @note Clearing this flag is done by reading SPIx_SR register
856 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
857 * @param SPIx SPI Instance
858 * @retval None
859 */
LL_SPI_ClearFlag_FRE(SPI_TypeDef * SPIx)860 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
861 {
862 __IO uint32_t tmpreg;
863 tmpreg = SPIx->SR;
864 (void) tmpreg;
865 }
866
867 /**
868 * @}
869 */
870
871 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
872 * @{
873 */
874
875 /**
876 * @brief Enable error interrupt
877 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
878 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
879 * @param SPIx SPI Instance
880 * @retval None
881 */
LL_SPI_EnableIT_ERR(SPI_TypeDef * SPIx)882 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
883 {
884 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
885 }
886
887 /**
888 * @brief Enable Rx buffer not empty interrupt
889 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
890 * @param SPIx SPI Instance
891 * @retval None
892 */
LL_SPI_EnableIT_RXNE(SPI_TypeDef * SPIx)893 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
894 {
895 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
896 }
897
898 /**
899 * @brief Enable Tx buffer empty interrupt
900 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
901 * @param SPIx SPI Instance
902 * @retval None
903 */
LL_SPI_EnableIT_TXE(SPI_TypeDef * SPIx)904 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
905 {
906 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
907 }
908
909 /**
910 * @brief Disable error interrupt
911 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
912 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
913 * @param SPIx SPI Instance
914 * @retval None
915 */
LL_SPI_DisableIT_ERR(SPI_TypeDef * SPIx)916 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
917 {
918 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
919 }
920
921 /**
922 * @brief Disable Rx buffer not empty interrupt
923 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
924 * @param SPIx SPI Instance
925 * @retval None
926 */
LL_SPI_DisableIT_RXNE(SPI_TypeDef * SPIx)927 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
928 {
929 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
930 }
931
932 /**
933 * @brief Disable Tx buffer empty interrupt
934 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
935 * @param SPIx SPI Instance
936 * @retval None
937 */
LL_SPI_DisableIT_TXE(SPI_TypeDef * SPIx)938 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
939 {
940 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
941 }
942
943 /**
944 * @brief Check if error interrupt is enabled
945 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
946 * @param SPIx SPI Instance
947 * @retval State of bit (1 or 0).
948 */
LL_SPI_IsEnabledIT_ERR(SPI_TypeDef * SPIx)949 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
950 {
951 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
952 }
953
954 /**
955 * @brief Check if Rx buffer not empty interrupt is enabled
956 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
957 * @param SPIx SPI Instance
958 * @retval State of bit (1 or 0).
959 */
LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef * SPIx)960 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
961 {
962 return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
963 }
964
965 /**
966 * @brief Check if Tx buffer empty interrupt
967 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
968 * @param SPIx SPI Instance
969 * @retval State of bit (1 or 0).
970 */
LL_SPI_IsEnabledIT_TXE(SPI_TypeDef * SPIx)971 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
972 {
973 return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
974 }
975
976 /**
977 * @}
978 */
979
980 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
981 * @{
982 */
983
984 /**
985 * @brief Enable DMA Rx
986 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
987 * @param SPIx SPI Instance
988 * @retval None
989 */
LL_SPI_EnableDMAReq_RX(SPI_TypeDef * SPIx)990 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
991 {
992 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
993 }
994
995 /**
996 * @brief Disable DMA Rx
997 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
998 * @param SPIx SPI Instance
999 * @retval None
1000 */
LL_SPI_DisableDMAReq_RX(SPI_TypeDef * SPIx)1001 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
1002 {
1003 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
1004 }
1005
1006 /**
1007 * @brief Check if DMA Rx is enabled
1008 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
1009 * @param SPIx SPI Instance
1010 * @retval State of bit (1 or 0).
1011 */
LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef * SPIx)1012 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
1013 {
1014 return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
1015 }
1016
1017 /**
1018 * @brief Enable DMA Tx
1019 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
1020 * @param SPIx SPI Instance
1021 * @retval None
1022 */
LL_SPI_EnableDMAReq_TX(SPI_TypeDef * SPIx)1023 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
1024 {
1025 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1026 }
1027
1028 /**
1029 * @brief Disable DMA Tx
1030 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
1031 * @param SPIx SPI Instance
1032 * @retval None
1033 */
LL_SPI_DisableDMAReq_TX(SPI_TypeDef * SPIx)1034 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1035 {
1036 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1037 }
1038
1039 /**
1040 * @brief Check if DMA Tx is enabled
1041 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
1042 * @param SPIx SPI Instance
1043 * @retval State of bit (1 or 0).
1044 */
LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef * SPIx)1045 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
1046 {
1047 return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
1048 }
1049
1050 /**
1051 * @brief Get the data register address used for DMA transfer
1052 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
1053 * @param SPIx SPI Instance
1054 * @retval Address of data register
1055 */
LL_SPI_DMA_GetRegAddr(SPI_TypeDef * SPIx)1056 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
1057 {
1058 return (uint32_t) &(SPIx->DR);
1059 }
1060
1061 /**
1062 * @}
1063 */
1064
1065 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
1066 * @{
1067 */
1068
1069 /**
1070 * @brief Read 8-Bits in the data register
1071 * @rmtoll DR DR LL_SPI_ReceiveData8
1072 * @param SPIx SPI Instance
1073 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
1074 */
LL_SPI_ReceiveData8(SPI_TypeDef * SPIx)1075 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
1076 {
1077 return (*((__IO uint8_t *)&SPIx->DR));
1078 }
1079
1080 /**
1081 * @brief Read 16-Bits in the data register
1082 * @rmtoll DR DR LL_SPI_ReceiveData16
1083 * @param SPIx SPI Instance
1084 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1085 */
LL_SPI_ReceiveData16(SPI_TypeDef * SPIx)1086 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
1087 {
1088 return (uint16_t)(READ_REG(SPIx->DR));
1089 }
1090
1091 /**
1092 * @brief Write 8-Bits in the data register
1093 * @rmtoll DR DR LL_SPI_TransmitData8
1094 * @param SPIx SPI Instance
1095 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
1096 * @retval None
1097 */
LL_SPI_TransmitData8(SPI_TypeDef * SPIx,uint8_t TxData)1098 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
1099 {
1100 #if defined (__GNUC__)
1101 __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
1102 *spidr = TxData;
1103 #else
1104 *((__IO uint8_t *)&SPIx->DR) = TxData;
1105 #endif /* __GNUC__ */
1106 }
1107
1108 /**
1109 * @brief Write 16-Bits in the data register
1110 * @rmtoll DR DR LL_SPI_TransmitData16
1111 * @param SPIx SPI Instance
1112 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1113 * @retval None
1114 */
LL_SPI_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)1115 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1116 {
1117 #if defined (__GNUC__)
1118 __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
1119 *spidr = TxData;
1120 #else
1121 SPIx->DR = TxData;
1122 #endif /* __GNUC__ */
1123 }
1124
1125 /**
1126 * @}
1127 */
1128 #if defined(USE_FULL_LL_DRIVER)
1129 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
1130 * @{
1131 */
1132
1133 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
1134 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
1135 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
1136
1137 /**
1138 * @}
1139 */
1140 #endif /* USE_FULL_LL_DRIVER */
1141 /**
1142 * @}
1143 */
1144
1145 /**
1146 * @}
1147 */
1148
1149 #if defined(SPI_I2S_SUPPORT)
1150 /** @defgroup I2S_LL I2S
1151 * @{
1152 */
1153
1154 /* Private variables ---------------------------------------------------------*/
1155 /* Private constants ---------------------------------------------------------*/
1156 /* Private macros ------------------------------------------------------------*/
1157
1158 /* Exported types ------------------------------------------------------------*/
1159 #if defined(USE_FULL_LL_DRIVER)
1160 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
1161 * @{
1162 */
1163
1164 /**
1165 * @brief I2S Init structure definition
1166 */
1167
1168 typedef struct
1169 {
1170 uint32_t Mode; /*!< Specifies the I2S operating mode.
1171 This parameter can be a value of @ref I2S_LL_EC_MODE
1172
1173 This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
1174
1175 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
1176 This parameter can be a value of @ref I2S_LL_EC_STANDARD
1177
1178 This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
1179
1180
1181 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
1182 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
1183
1184 This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
1185
1186
1187 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
1188 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
1189
1190 This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
1191
1192
1193 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
1194 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
1195
1196 Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
1197 and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
1198
1199
1200 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
1201 This parameter can be a value of @ref I2S_LL_EC_POLARITY
1202
1203 This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
1204
1205 } LL_I2S_InitTypeDef;
1206
1207 /**
1208 * @}
1209 */
1210 #endif /*USE_FULL_LL_DRIVER*/
1211
1212 /* Exported constants --------------------------------------------------------*/
1213 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
1214 * @{
1215 */
1216
1217 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
1218 * @brief Flags defines which can be used with LL_I2S_ReadReg function
1219 * @{
1220 */
1221 #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
1222 #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
1223 #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
1224 #define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
1225 #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
1226 #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
1227 /**
1228 * @}
1229 */
1230
1231 /** @defgroup SPI_LL_EC_IT IT Defines
1232 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
1233 * @{
1234 */
1235 #define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
1236 #define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
1237 #define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
1238 /**
1239 * @}
1240 */
1241
1242 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
1243 * @{
1244 */
1245 #define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */
1246 #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */
1247 #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */
1248 #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */
1249 /**
1250 * @}
1251 */
1252
1253 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
1254 * @{
1255 */
1256 #define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
1257 #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
1258 /**
1259 * @}
1260 */
1261
1262 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
1263 * @{
1264 */
1265 #define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
1266 #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
1267 #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
1268 #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
1269 #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
1270 /**
1271 * @}
1272 */
1273
1274 /** @defgroup I2S_LL_EC_MODE Operation Mode
1275 * @{
1276 */
1277 #define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
1278 #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
1279 #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
1280 #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
1281 /**
1282 * @}
1283 */
1284
1285 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
1286 * @{
1287 */
1288 #define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
1289 #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
1290 /**
1291 * @}
1292 */
1293
1294 #if defined(USE_FULL_LL_DRIVER)
1295
1296 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
1297 * @{
1298 */
1299 #define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
1300 #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
1301 /**
1302 * @}
1303 */
1304
1305 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
1306 * @{
1307 */
1308
1309 #define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
1310 #define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
1311 #define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
1312 #define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
1313 #define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
1314 #define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
1315 #define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
1316 #define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
1317 #define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
1318 #define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
1319 /**
1320 * @}
1321 */
1322 #endif /* USE_FULL_LL_DRIVER */
1323
1324 /**
1325 * @}
1326 */
1327
1328 /* Exported macro ------------------------------------------------------------*/
1329 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
1330 * @{
1331 */
1332
1333 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
1334 * @{
1335 */
1336
1337 /**
1338 * @brief Write a value in I2S register
1339 * @param __INSTANCE__ I2S Instance
1340 * @param __REG__ Register to be written
1341 * @param __VALUE__ Value to be written in the register
1342 * @retval None
1343 */
1344 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1345
1346 /**
1347 * @brief Read a value in I2S register
1348 * @param __INSTANCE__ I2S Instance
1349 * @param __REG__ Register to be read
1350 * @retval Register value
1351 */
1352 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1353 /**
1354 * @}
1355 */
1356
1357 /**
1358 * @}
1359 */
1360
1361
1362 /* Exported functions --------------------------------------------------------*/
1363
1364 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
1365 * @{
1366 */
1367
1368 /** @defgroup I2S_LL_EF_Configuration Configuration
1369 * @{
1370 */
1371
1372 /**
1373 * @brief Select I2S mode and Enable I2S peripheral
1374 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
1375 * I2SCFGR I2SE LL_I2S_Enable
1376 * @param SPIx SPI Instance
1377 * @retval None
1378 */
LL_I2S_Enable(SPI_TypeDef * SPIx)1379 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
1380 {
1381 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1382 }
1383
1384 /**
1385 * @brief Disable I2S peripheral
1386 * @rmtoll I2SCFGR I2SE LL_I2S_Disable
1387 * @param SPIx SPI Instance
1388 * @retval None
1389 */
LL_I2S_Disable(SPI_TypeDef * SPIx)1390 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
1391 {
1392 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1393 }
1394
1395 /**
1396 * @brief Check if I2S peripheral is enabled
1397 * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
1398 * @param SPIx SPI Instance
1399 * @retval State of bit (1 or 0).
1400 */
LL_I2S_IsEnabled(SPI_TypeDef * SPIx)1401 __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
1402 {
1403 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
1404 }
1405
1406 /**
1407 * @brief Set I2S data frame length
1408 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
1409 * I2SCFGR CHLEN LL_I2S_SetDataFormat
1410 * @param SPIx SPI Instance
1411 * @param DataFormat This parameter can be one of the following values:
1412 * @arg @ref LL_I2S_DATAFORMAT_16B
1413 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1414 * @arg @ref LL_I2S_DATAFORMAT_24B
1415 * @arg @ref LL_I2S_DATAFORMAT_32B
1416 * @retval None
1417 */
LL_I2S_SetDataFormat(SPI_TypeDef * SPIx,uint32_t DataFormat)1418 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
1419 {
1420 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
1421 }
1422
1423 /**
1424 * @brief Get I2S data frame length
1425 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
1426 * I2SCFGR CHLEN LL_I2S_GetDataFormat
1427 * @param SPIx SPI Instance
1428 * @retval Returned value can be one of the following values:
1429 * @arg @ref LL_I2S_DATAFORMAT_16B
1430 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1431 * @arg @ref LL_I2S_DATAFORMAT_24B
1432 * @arg @ref LL_I2S_DATAFORMAT_32B
1433 */
LL_I2S_GetDataFormat(SPI_TypeDef * SPIx)1434 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
1435 {
1436 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
1437 }
1438
1439 /**
1440 * @brief Set I2S clock polarity
1441 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
1442 * @param SPIx SPI Instance
1443 * @param ClockPolarity This parameter can be one of the following values:
1444 * @arg @ref LL_I2S_POLARITY_LOW
1445 * @arg @ref LL_I2S_POLARITY_HIGH
1446 * @retval None
1447 */
LL_I2S_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)1448 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1449 {
1450 SET_BIT(SPIx->I2SCFGR, ClockPolarity);
1451 }
1452
1453 /**
1454 * @brief Get I2S clock polarity
1455 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
1456 * @param SPIx SPI Instance
1457 * @retval Returned value can be one of the following values:
1458 * @arg @ref LL_I2S_POLARITY_LOW
1459 * @arg @ref LL_I2S_POLARITY_HIGH
1460 */
LL_I2S_GetClockPolarity(SPI_TypeDef * SPIx)1461 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
1462 {
1463 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
1464 }
1465
1466 /**
1467 * @brief Set I2S standard protocol
1468 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
1469 * I2SCFGR PCMSYNC LL_I2S_SetStandard
1470 * @param SPIx SPI Instance
1471 * @param Standard This parameter can be one of the following values:
1472 * @arg @ref LL_I2S_STANDARD_PHILIPS
1473 * @arg @ref LL_I2S_STANDARD_MSB
1474 * @arg @ref LL_I2S_STANDARD_LSB
1475 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1476 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1477 * @retval None
1478 */
LL_I2S_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)1479 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1480 {
1481 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
1482 }
1483
1484 /**
1485 * @brief Get I2S standard protocol
1486 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
1487 * I2SCFGR PCMSYNC LL_I2S_GetStandard
1488 * @param SPIx SPI Instance
1489 * @retval Returned value can be one of the following values:
1490 * @arg @ref LL_I2S_STANDARD_PHILIPS
1491 * @arg @ref LL_I2S_STANDARD_MSB
1492 * @arg @ref LL_I2S_STANDARD_LSB
1493 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1494 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1495 */
LL_I2S_GetStandard(SPI_TypeDef * SPIx)1496 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
1497 {
1498 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
1499 }
1500
1501 /**
1502 * @brief Set I2S transfer mode
1503 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
1504 * @param SPIx SPI Instance
1505 * @param Mode This parameter can be one of the following values:
1506 * @arg @ref LL_I2S_MODE_SLAVE_TX
1507 * @arg @ref LL_I2S_MODE_SLAVE_RX
1508 * @arg @ref LL_I2S_MODE_MASTER_TX
1509 * @arg @ref LL_I2S_MODE_MASTER_RX
1510 * @retval None
1511 */
LL_I2S_SetTransferMode(SPI_TypeDef * SPIx,uint32_t Mode)1512 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
1513 {
1514 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
1515 }
1516
1517 /**
1518 * @brief Get I2S transfer mode
1519 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
1520 * @param SPIx SPI Instance
1521 * @retval Returned value can be one of the following values:
1522 * @arg @ref LL_I2S_MODE_SLAVE_TX
1523 * @arg @ref LL_I2S_MODE_SLAVE_RX
1524 * @arg @ref LL_I2S_MODE_MASTER_TX
1525 * @arg @ref LL_I2S_MODE_MASTER_RX
1526 */
LL_I2S_GetTransferMode(SPI_TypeDef * SPIx)1527 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
1528 {
1529 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
1530 }
1531
1532 /**
1533 * @brief Set I2S linear prescaler
1534 * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
1535 * @param SPIx SPI Instance
1536 * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1537 * @retval None
1538 */
LL_I2S_SetPrescalerLinear(SPI_TypeDef * SPIx,uint8_t PrescalerLinear)1539 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
1540 {
1541 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
1542 }
1543
1544 /**
1545 * @brief Get I2S linear prescaler
1546 * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
1547 * @param SPIx SPI Instance
1548 * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1549 */
LL_I2S_GetPrescalerLinear(SPI_TypeDef * SPIx)1550 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
1551 {
1552 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
1553 }
1554
1555 /**
1556 * @brief Set I2S parity prescaler
1557 * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
1558 * @param SPIx SPI Instance
1559 * @param PrescalerParity This parameter can be one of the following values:
1560 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1561 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1562 * @retval None
1563 */
LL_I2S_SetPrescalerParity(SPI_TypeDef * SPIx,uint32_t PrescalerParity)1564 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
1565 {
1566 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
1567 }
1568
1569 /**
1570 * @brief Get I2S parity prescaler
1571 * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
1572 * @param SPIx SPI Instance
1573 * @retval Returned value can be one of the following values:
1574 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1575 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1576 */
LL_I2S_GetPrescalerParity(SPI_TypeDef * SPIx)1577 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
1578 {
1579 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
1580 }
1581
1582 /**
1583 * @brief Enable the master clock output (Pin MCK)
1584 * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
1585 * @param SPIx SPI Instance
1586 * @retval None
1587 */
LL_I2S_EnableMasterClock(SPI_TypeDef * SPIx)1588 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
1589 {
1590 SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1591 }
1592
1593 /**
1594 * @brief Disable the master clock output (Pin MCK)
1595 * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
1596 * @param SPIx SPI Instance
1597 * @retval None
1598 */
LL_I2S_DisableMasterClock(SPI_TypeDef * SPIx)1599 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
1600 {
1601 CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1602 }
1603
1604 /**
1605 * @brief Check if the master clock output (Pin MCK) is enabled
1606 * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
1607 * @param SPIx SPI Instance
1608 * @retval State of bit (1 or 0).
1609 */
LL_I2S_IsEnabledMasterClock(SPI_TypeDef * SPIx)1610 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
1611 {
1612 return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
1613 }
1614
1615 #if defined(SPI_I2SCFGR_ASTRTEN)
1616 /**
1617 * @brief Enable asynchronous start
1618 * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
1619 * @param SPIx SPI Instance
1620 * @retval None
1621 */
LL_I2S_EnableAsyncStart(SPI_TypeDef * SPIx)1622 __STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
1623 {
1624 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
1625 }
1626
1627 /**
1628 * @brief Disable asynchronous start
1629 * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
1630 * @param SPIx SPI Instance
1631 * @retval None
1632 */
LL_I2S_DisableAsyncStart(SPI_TypeDef * SPIx)1633 __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
1634 {
1635 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
1636 }
1637
1638 /**
1639 * @brief Check if asynchronous start is enabled
1640 * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
1641 * @param SPIx SPI Instance
1642 * @retval State of bit (1 or 0).
1643 */
LL_I2S_IsEnabledAsyncStart(SPI_TypeDef * SPIx)1644 __STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
1645 {
1646 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL);
1647 }
1648 #endif /* SPI_I2SCFGR_ASTRTEN */
1649
1650 /**
1651 * @}
1652 */
1653
1654 /** @defgroup I2S_LL_EF_FLAG FLAG Management
1655 * @{
1656 */
1657
1658 /**
1659 * @brief Check if Rx buffer is not empty
1660 * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
1661 * @param SPIx SPI Instance
1662 * @retval State of bit (1 or 0).
1663 */
LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef * SPIx)1664 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
1665 {
1666 return LL_SPI_IsActiveFlag_RXNE(SPIx);
1667 }
1668
1669 /**
1670 * @brief Check if Tx buffer is empty
1671 * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
1672 * @param SPIx SPI Instance
1673 * @retval State of bit (1 or 0).
1674 */
LL_I2S_IsActiveFlag_TXE(SPI_TypeDef * SPIx)1675 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
1676 {
1677 return LL_SPI_IsActiveFlag_TXE(SPIx);
1678 }
1679
1680 /**
1681 * @brief Get busy flag
1682 * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
1683 * @param SPIx SPI Instance
1684 * @retval State of bit (1 or 0).
1685 */
LL_I2S_IsActiveFlag_BSY(SPI_TypeDef * SPIx)1686 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
1687 {
1688 return LL_SPI_IsActiveFlag_BSY(SPIx);
1689 }
1690
1691 /**
1692 * @brief Get overrun error flag
1693 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
1694 * @param SPIx SPI Instance
1695 * @retval State of bit (1 or 0).
1696 */
LL_I2S_IsActiveFlag_OVR(SPI_TypeDef * SPIx)1697 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
1698 {
1699 return LL_SPI_IsActiveFlag_OVR(SPIx);
1700 }
1701
1702 /**
1703 * @brief Get underrun error flag
1704 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
1705 * @param SPIx SPI Instance
1706 * @retval State of bit (1 or 0).
1707 */
LL_I2S_IsActiveFlag_UDR(SPI_TypeDef * SPIx)1708 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
1709 {
1710 return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
1711 }
1712
1713 /**
1714 * @brief Get frame format error flag
1715 * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
1716 * @param SPIx SPI Instance
1717 * @retval State of bit (1 or 0).
1718 */
LL_I2S_IsActiveFlag_FRE(SPI_TypeDef * SPIx)1719 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
1720 {
1721 return LL_SPI_IsActiveFlag_FRE(SPIx);
1722 }
1723
1724 /**
1725 * @brief Get channel side flag.
1726 * @note 0: Channel Left has to be transmitted or has been received\n
1727 * 1: Channel Right has to be transmitted or has been received\n
1728 * It has no significance in PCM mode.
1729 * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
1730 * @param SPIx SPI Instance
1731 * @retval State of bit (1 or 0).
1732 */
LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef * SPIx)1733 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
1734 {
1735 return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
1736 }
1737
1738 /**
1739 * @brief Clear overrun error flag
1740 * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
1741 * @param SPIx SPI Instance
1742 * @retval None
1743 */
LL_I2S_ClearFlag_OVR(SPI_TypeDef * SPIx)1744 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
1745 {
1746 LL_SPI_ClearFlag_OVR(SPIx);
1747 }
1748
1749 /**
1750 * @brief Clear underrun error flag
1751 * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
1752 * @param SPIx SPI Instance
1753 * @retval None
1754 */
LL_I2S_ClearFlag_UDR(SPI_TypeDef * SPIx)1755 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
1756 {
1757 __IO uint32_t tmpreg;
1758 tmpreg = SPIx->SR;
1759 (void)tmpreg;
1760 }
1761
1762 /**
1763 * @brief Clear frame format error flag
1764 * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
1765 * @param SPIx SPI Instance
1766 * @retval None
1767 */
LL_I2S_ClearFlag_FRE(SPI_TypeDef * SPIx)1768 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
1769 {
1770 LL_SPI_ClearFlag_FRE(SPIx);
1771 }
1772
1773 /**
1774 * @}
1775 */
1776
1777 /** @defgroup I2S_LL_EF_IT Interrupt Management
1778 * @{
1779 */
1780
1781 /**
1782 * @brief Enable error IT
1783 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
1784 * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
1785 * @param SPIx SPI Instance
1786 * @retval None
1787 */
LL_I2S_EnableIT_ERR(SPI_TypeDef * SPIx)1788 __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
1789 {
1790 LL_SPI_EnableIT_ERR(SPIx);
1791 }
1792
1793 /**
1794 * @brief Enable Rx buffer not empty IT
1795 * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
1796 * @param SPIx SPI Instance
1797 * @retval None
1798 */
LL_I2S_EnableIT_RXNE(SPI_TypeDef * SPIx)1799 __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
1800 {
1801 LL_SPI_EnableIT_RXNE(SPIx);
1802 }
1803
1804 /**
1805 * @brief Enable Tx buffer empty IT
1806 * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
1807 * @param SPIx SPI Instance
1808 * @retval None
1809 */
LL_I2S_EnableIT_TXE(SPI_TypeDef * SPIx)1810 __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
1811 {
1812 LL_SPI_EnableIT_TXE(SPIx);
1813 }
1814
1815 /**
1816 * @brief Disable error IT
1817 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
1818 * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
1819 * @param SPIx SPI Instance
1820 * @retval None
1821 */
LL_I2S_DisableIT_ERR(SPI_TypeDef * SPIx)1822 __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
1823 {
1824 LL_SPI_DisableIT_ERR(SPIx);
1825 }
1826
1827 /**
1828 * @brief Disable Rx buffer not empty IT
1829 * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
1830 * @param SPIx SPI Instance
1831 * @retval None
1832 */
LL_I2S_DisableIT_RXNE(SPI_TypeDef * SPIx)1833 __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
1834 {
1835 LL_SPI_DisableIT_RXNE(SPIx);
1836 }
1837
1838 /**
1839 * @brief Disable Tx buffer empty IT
1840 * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
1841 * @param SPIx SPI Instance
1842 * @retval None
1843 */
LL_I2S_DisableIT_TXE(SPI_TypeDef * SPIx)1844 __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
1845 {
1846 LL_SPI_DisableIT_TXE(SPIx);
1847 }
1848
1849 /**
1850 * @brief Check if ERR IT is enabled
1851 * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
1852 * @param SPIx SPI Instance
1853 * @retval State of bit (1 or 0).
1854 */
LL_I2S_IsEnabledIT_ERR(SPI_TypeDef * SPIx)1855 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
1856 {
1857 return LL_SPI_IsEnabledIT_ERR(SPIx);
1858 }
1859
1860 /**
1861 * @brief Check if RXNE IT is enabled
1862 * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
1863 * @param SPIx SPI Instance
1864 * @retval State of bit (1 or 0).
1865 */
LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef * SPIx)1866 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
1867 {
1868 return LL_SPI_IsEnabledIT_RXNE(SPIx);
1869 }
1870
1871 /**
1872 * @brief Check if TXE IT is enabled
1873 * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
1874 * @param SPIx SPI Instance
1875 * @retval State of bit (1 or 0).
1876 */
LL_I2S_IsEnabledIT_TXE(SPI_TypeDef * SPIx)1877 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
1878 {
1879 return LL_SPI_IsEnabledIT_TXE(SPIx);
1880 }
1881
1882 /**
1883 * @}
1884 */
1885
1886 /** @defgroup I2S_LL_EF_DMA DMA Management
1887 * @{
1888 */
1889
1890 /**
1891 * @brief Enable DMA Rx
1892 * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
1893 * @param SPIx SPI Instance
1894 * @retval None
1895 */
LL_I2S_EnableDMAReq_RX(SPI_TypeDef * SPIx)1896 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
1897 {
1898 LL_SPI_EnableDMAReq_RX(SPIx);
1899 }
1900
1901 /**
1902 * @brief Disable DMA Rx
1903 * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
1904 * @param SPIx SPI Instance
1905 * @retval None
1906 */
LL_I2S_DisableDMAReq_RX(SPI_TypeDef * SPIx)1907 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
1908 {
1909 LL_SPI_DisableDMAReq_RX(SPIx);
1910 }
1911
1912 /**
1913 * @brief Check if DMA Rx is enabled
1914 * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
1915 * @param SPIx SPI Instance
1916 * @retval State of bit (1 or 0).
1917 */
LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef * SPIx)1918 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
1919 {
1920 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
1921 }
1922
1923 /**
1924 * @brief Enable DMA Tx
1925 * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
1926 * @param SPIx SPI Instance
1927 * @retval None
1928 */
LL_I2S_EnableDMAReq_TX(SPI_TypeDef * SPIx)1929 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
1930 {
1931 LL_SPI_EnableDMAReq_TX(SPIx);
1932 }
1933
1934 /**
1935 * @brief Disable DMA Tx
1936 * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
1937 * @param SPIx SPI Instance
1938 * @retval None
1939 */
LL_I2S_DisableDMAReq_TX(SPI_TypeDef * SPIx)1940 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1941 {
1942 LL_SPI_DisableDMAReq_TX(SPIx);
1943 }
1944
1945 /**
1946 * @brief Check if DMA Tx is enabled
1947 * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
1948 * @param SPIx SPI Instance
1949 * @retval State of bit (1 or 0).
1950 */
LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef * SPIx)1951 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
1952 {
1953 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
1954 }
1955
1956 /**
1957 * @}
1958 */
1959
1960 /** @defgroup I2S_LL_EF_DATA DATA Management
1961 * @{
1962 */
1963
1964 /**
1965 * @brief Read 16-Bits in data register
1966 * @rmtoll DR DR LL_I2S_ReceiveData16
1967 * @param SPIx SPI Instance
1968 * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
1969 */
LL_I2S_ReceiveData16(SPI_TypeDef * SPIx)1970 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
1971 {
1972 return LL_SPI_ReceiveData16(SPIx);
1973 }
1974
1975 /**
1976 * @brief Write 16-Bits in data register
1977 * @rmtoll DR DR LL_I2S_TransmitData16
1978 * @param SPIx SPI Instance
1979 * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
1980 * @retval None
1981 */
LL_I2S_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)1982 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1983 {
1984 LL_SPI_TransmitData16(SPIx, TxData);
1985 }
1986
1987 /**
1988 * @}
1989 */
1990
1991 #if defined(USE_FULL_LL_DRIVER)
1992 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
1993 * @{
1994 */
1995
1996 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
1997 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
1998 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
1999 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
2000
2001 /**
2002 * @}
2003 */
2004 #endif /* USE_FULL_LL_DRIVER */
2005
2006 /**
2007 * @}
2008 */
2009
2010 /**
2011 * @}
2012 */
2013 #endif /* SPI_I2S_SUPPORT */
2014
2015 #endif /* defined (SPI1) || defined (SPI2) */
2016
2017 /**
2018 * @}
2019 */
2020
2021 #ifdef __cplusplus
2022 }
2023 #endif
2024
2025 #endif /* STM32L0xx_LL_SPI_H */
2026
2027
