1 /**
2 ******************************************************************************
3 * @file stm32l0xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32L0xx_LL_ADC_H
21 #define __STM32L0xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l0xx.h"
29
30 /** @addtogroup STM32L0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular trigger: */
49 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
50 /* - regular trigger source */
51 /* - regular trigger edge */
52 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
53
54 /* Mask containing trigger source masks for each of possible */
55 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
56 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
57 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0U)) | \
58 ((ADC_CFGR1_EXTSEL) << (4U * 1U)) | \
59 ((ADC_CFGR1_EXTSEL) << (4U * 2U)) | \
60 ((ADC_CFGR1_EXTSEL) << (4U * 3U)) )
61
62 /* Mask containing trigger edge masks for each of possible */
63 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
64 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
65 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0U)) | \
66 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \
67 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \
68 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) )
69
70 /* Definition of ADC group regular trigger bits information. */
71 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (6U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTSEL) */
72 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTEN) */
73
74
75
76 /* Internal mask for ADC channel: */
77 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
78 /* - channel identifier defined by number */
79 /* - channel identifier defined by bitfield */
80 /* - channel differentiation between external channels (connected to */
81 /* GPIO pins) and internal channels (connected to internal paths) */
82 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWDCH)
83 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
84 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
85 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
86 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
87 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
88
89 /* Channel differentiation between external and internal channels */
90 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000U) /* Marker of internal channel */
91 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
92
93 /* Definition of channels ID number information to be inserted into */
94 /* channels literals definition. */
95 #define ADC_CHANNEL_0_NUMBER (0x00000000U)
96 #define ADC_CHANNEL_1_NUMBER ( ADC_CFGR1_AWDCH_0)
97 #define ADC_CHANNEL_2_NUMBER ( ADC_CFGR1_AWDCH_1 )
98 #define ADC_CHANNEL_3_NUMBER ( ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
99 #define ADC_CHANNEL_4_NUMBER ( ADC_CFGR1_AWDCH_2 )
100 #define ADC_CHANNEL_5_NUMBER ( ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_0)
101 #define ADC_CHANNEL_6_NUMBER ( ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1 )
102 #define ADC_CHANNEL_7_NUMBER ( ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
103 #define ADC_CHANNEL_8_NUMBER ( ADC_CFGR1_AWDCH_3 )
104 #define ADC_CHANNEL_9_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_0)
105 #define ADC_CHANNEL_10_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_1 )
106 #define ADC_CHANNEL_11_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
107 #define ADC_CHANNEL_12_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2 )
108 #define ADC_CHANNEL_13_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_0)
109 #define ADC_CHANNEL_14_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1 )
110 #define ADC_CHANNEL_15_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
111 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWDCH_4 )
112 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWDCH_4 | ADC_CFGR1_AWDCH_0)
113 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWDCH_4 | ADC_CFGR1_AWDCH_1 )
114
115 /* Definition of channels ID bitfield information to be inserted into */
116 /* channels literals definition. */
117 #define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
118 #define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
119 #define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
120 #define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
121 #define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
122 #define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
123 #define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
124 #define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
125 #define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
126 #define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
127 #define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
128 #define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
129 #define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
130 #define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
131 #define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
132 #define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
133 #if defined(ADC_CCR_VLCDEN)
134 #define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
135 #endif
136 #define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
137 #define ADC_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18)
138
139 /* Internal mask for ADC analog watchdog: */
140 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
141 /* (concatenation of multiple bits used in different analog watchdogs, */
142 /* (feature of several watchdogs not available on all STM32 families)). */
143 /* - analog watchdog 1: monitored channel defined by number, */
144 /* selection of ADC group (ADC group regular). */
145
146 /* Internal register offset for ADC analog watchdog channel configuration */
147 #define ADC_AWD_CR1_REGOFFSET (0x00000000U)
148
149 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
150
151 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)
152 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
153
154 /* Internal register offset for ADC analog watchdog threshold configuration */
155 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
156 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET)
157
158
159 /* ADC registers bits positions */
160 #define ADC_CFGR1_RES_BITOFFSET_POS (3U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_RES) */
161 #define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_AWDSGL) */
162 #define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
163 #define ADC_CHSELR_CHSEL0_BITOFFSET_POS (0U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL0) */
164 #define ADC_CHSELR_CHSEL1_BITOFFSET_POS (1U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL1) */
165 #define ADC_CHSELR_CHSEL2_BITOFFSET_POS (2U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL2) */
166 #define ADC_CHSELR_CHSEL3_BITOFFSET_POS (3U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL3) */
167 #define ADC_CHSELR_CHSEL4_BITOFFSET_POS (4U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL4) */
168 #define ADC_CHSELR_CHSEL5_BITOFFSET_POS (5U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL5) */
169 #define ADC_CHSELR_CHSEL6_BITOFFSET_POS (6U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL6) */
170 #define ADC_CHSELR_CHSEL7_BITOFFSET_POS (7U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL7) */
171 #define ADC_CHSELR_CHSEL8_BITOFFSET_POS (8U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL8) */
172 #define ADC_CHSELR_CHSEL9_BITOFFSET_POS (9U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL9) */
173 #define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL10) */
174 #define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL11) */
175 #define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL12) */
176 #define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL13) */
177 #define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL14) */
178 #define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL15) */
179 #if defined(ADC_CCR_VLCDEN)
180 #define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL16) */
181 #endif
182 #define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL17) */
183 #define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL18) */
184
185
186 /* ADC registers bits groups */
187 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
188
189
190 /* ADC internal channels related definitions */
191 /* Internal voltage reference VrefInt */
192 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF80078U)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
193 #define VREFINT_CAL_VREF (3000U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
194 /* Temperature sensor */
195 /* Note: On device STM32L011, calibration parameter TS_CAL1 is not available. */
196 #if !defined(STM32L011xx)
197 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF8007AU)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L0, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
198 #endif
199 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF8007EU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L0, temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
200 #if !defined(STM32L011xx)
201 #define TEMPSENSOR_CAL1_TEMP (30U) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
202 #endif
203 #define TEMPSENSOR_CAL2_TEMP (130U) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
204 #define TEMPSENSOR_CAL_VREFANALOG (3000U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
205
206
207 /**
208 * @}
209 */
210
211
212 #if defined(USE_FULL_LL_DRIVER)
213 /* Private macros ------------------------------------------------------------*/
214 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
215 * @{
216 */
217
218
219 /**
220 * @}
221 */
222
223 #endif
224
225 /* Exported types ------------------------------------------------------------*/
226 #if defined(USE_FULL_LL_DRIVER)
227 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
228 * @{
229 */
230
231 /**
232 * @brief Structure definition of some features of ADC common parameters
233 * and multimode
234 * (all ADC instances belonging to the same ADC common instance).
235 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
236 * is conditioned to ADC instances state (all ADC instances
237 * sharing the same ADC common instance):
238 * All ADC instances sharing the same ADC common instance must be
239 * disabled.
240 */
241 typedef struct
242 {
243 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
244 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
245
246 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
247
248 } LL_ADC_CommonInitTypeDef;
249
250 /**
251 * @brief Structure definition of some features of ADC instance.
252 * @note These parameters have an impact on ADC scope: ADC instance.
253 * Refer to corresponding unitary functions into
254 * @ref ADC_LL_EF_Configuration_ADC_Instance .
255 * @note The setting of these parameters by function @ref LL_ADC_Init()
256 * is conditioned to ADC state:
257 * ADC instance must be disabled.
258 * This condition is applied to all ADC features, for efficiency
259 * and compatibility over all STM32 families. However, the different
260 * features can be set under different ADC state conditions
261 * (setting possible with ADC enabled without conversion on going,
262 * ADC enabled with conversion on going, ...)
263 * Each feature can be updated afterwards with a unitary function
264 * and potentially with ADC in a different state than disabled,
265 * refer to description of each function for setting
266 * conditioned to ADC state.
267 */
268 typedef struct
269 {
270 uint32_t Clock; /*!< Set ADC instance clock source and prescaler.
271 This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
272 @note On this STM32 series, this parameter has some clock ratio constraints:
273 ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle
274 (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle).
275
276
277 This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock().
278 For more details, refer to description of this function. */
279
280 uint32_t Resolution; /*!< Set ADC resolution.
281 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
282
283 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
284
285 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
286 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
287
288 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
289
290 uint32_t LowPowerMode; /*!< Set ADC low power mode.
291 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
292
293 This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
294
295 } LL_ADC_InitTypeDef;
296
297 /**
298 * @brief Structure definition of some features of ADC group regular.
299 * @note These parameters have an impact on ADC scope: ADC group regular.
300 * Refer to corresponding unitary functions into
301 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
302 * (functions with prefix "REG").
303 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
304 * is conditioned to ADC state:
305 * ADC instance must be disabled.
306 * This condition is applied to all ADC features, for efficiency
307 * and compatibility over all STM32 families. However, the different
308 * features can be set under different ADC state conditions
309 * (setting possible with ADC enabled without conversion on going,
310 * ADC enabled with conversion on going, ...)
311 * Each feature can be updated afterwards with a unitary function
312 * and potentially with ADC in a different state than disabled,
313 * refer to description of each function for setting
314 * conditioned to ADC state.
315 */
316 typedef struct
317 {
318 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
319 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
320 @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
321 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
322 In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
323
324 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
325
326 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
327 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
328 @note This parameter has an effect only if group regular sequencer is enabled
329 (several ADC channels enabled in group regular sequencer).
330
331 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
332
333 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
334 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
335 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
336
337 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
338
339 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
340 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
341
342 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
343
344 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
345 data preserved or overwritten.
346 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
347
348 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
349
350 } LL_ADC_REG_InitTypeDef;
351
352 /**
353 * @}
354 */
355 #endif /* USE_FULL_LL_DRIVER */
356
357 /* Exported constants --------------------------------------------------------*/
358 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
359 * @{
360 */
361
362 /** @defgroup ADC_LL_EC_FLAG ADC flags
363 * @brief Flags defines which can be used with LL_ADC_ReadReg function
364 * @{
365 */
366 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
367 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
368 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
369 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
370 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
371 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD /*!< ADC flag ADC analog watchdog 1 */
372 #define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */
373 /**
374 * @}
375 */
376
377 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
378 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
379 * @{
380 */
381 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
382 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
383 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
384 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
385 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
386 #define LL_ADC_IT_AWD1 ADC_IER_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
387 #define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of calibration */
388 /**
389 * @}
390 */
391
392 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
393 * @{
394 */
395 /* List of ADC registers intended to be used (most commonly) with */
396 /* DMA transfer. */
397 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
398 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
399 /**
400 * @}
401 */
402
403 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
404 * @{
405 */
406 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock without prescaler */
407 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
408 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
409 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
410 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
411 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
412 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
413 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
414 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
415 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
416 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
417 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
418 /**
419 * @}
420 */
421
422 /** @defgroup ADC_LL_EC_COMMON_CLOCK_FREQ_MODE ADC common - Clock frequency mode
423 * @{
424 */
425 #define LL_ADC_CLOCK_FREQ_MODE_HIGH (0x00000000U)/*!< ADC clock mode to high frequency. On STM32L0, ADC clock frequency above 2.8MHz. */
426 #define LL_ADC_CLOCK_FREQ_MODE_LOW (ADC_CCR_LFMEN) /*!< ADC clock mode to low frequency. On STM32L0, ADC clock frequency below 2.8MHz. */
427 /**
428 * @}
429 */
430
431 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
432 * @{
433 */
434 /* Note: Other measurement paths to internal channels may be available */
435 /* (connections to other peripherals). */
436 /* If they are not listed below, they do not require any specific */
437 /* path enable. In this case, Access to measurement path is done */
438 /* only by selecting the corresponding ADC internal channel. */
439 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000U)/*!< ADC measurement paths all disabled */
440 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
441 #if defined(ADC_CCR_TSEN)
442 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
443 #endif
444 #if defined(ADC_CCR_VLCDEN)
445 #define LL_ADC_PATH_INTERNAL_VLCD (ADC_CCR_VLCDEN) /*!< ADC measurement path to internal channel Vlcd */
446 #endif
447 /**
448 * @}
449 */
450
451 /** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source
452 * @{
453 */
454 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 4 */
455 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by 2 */
456 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock not divided */
457 #define LL_ADC_CLOCK_ASYNC (0x00000000U) /*!< ADC asynchronous clock. Asynchronous clock prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */
458 /**
459 * @}
460 */
461
462 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
463 * @{
464 */
465 #define LL_ADC_RESOLUTION_12B (0x00000000U) /*!< ADC resolution 12 bits */
466 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */
467 #define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 8 bits */
468 #define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bits */
469 /**
470 * @}
471 */
472
473 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
474 * @{
475 */
476 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
477 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
478 /**
479 * @}
480 */
481
482 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
483 * @{
484 */
485 #define LL_ADC_LP_MODE_NONE (0x00000000U) /*!< No ADC low power mode activated */
486 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
487 #define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). */
488 #define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */
489 /**
490 * @}
491 */
492
493 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
494 * @{
495 */
496 #define LL_ADC_GROUP_REGULAR (0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
497 /**
498 * @}
499 */
500
501 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
502 * @{
503 */
504 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
505 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
506 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
507 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
508 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
509 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
510 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
511 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
512 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
513 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
514 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
515 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
516 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
517 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
518 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
519 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
520 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
521 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
522 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
523 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
524 #if defined(ADC_CCR_VLCDEN)
525 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
526 #define LL_ADC_CHANNEL_VLCD (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vlcd: Vlcd voltage through a divider ladder of factor 1/4, 1/3 or 1/2 (set by LCD voltage generator biasing), to have Vlcd always below Vdda. */
527 #endif
528 /**
529 * @}
530 */
531
532 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
533 * @{
534 */
535 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000U) /*!< ADC group regular conversion trigger internal: SW start. */
536 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
537 #define LL_ADC_REG_TRIG_EXT_TIM21_CH2 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM21 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
538 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
539 #define LL_ADC_REG_TRIG_EXT_TIM2_CH4 (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
540 #define LL_ADC_REG_TRIG_EXT_TIM22_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM22 TRGO. Trigger edge set to rising edge (default setting). */
541 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
542 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
543
544 /* ADC group regular external trigger TIM2_CC3 available only on */
545 /* STM32L0 devices categories: Cat.1, Cat.2, Cat.5 */
546 #if defined (STM32L011xx) || defined (STM32L021xx) || \
547 defined (STM32L031xx) || defined (STM32L041xx) || \
548 defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || \
549 defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) || \
550 defined (STM32L010x6) || defined (STM32L010x8) || defined (STM32L010xB)
551 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
552 #endif
553
554 /* ADC group regular external trigger TIM21_TRGO available only on */
555 /* STM32L0 devices categories: Cat.2, Cat.3, Cat.5 */
556 #if defined (STM32L031xx) || defined (STM32L041xx) || \
557 defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || \
558 defined (STM32L062xx) || defined (STM32L063xx) || \
559 defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || \
560 defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) || \
561 defined (STM32L010x6) || defined (STM32L010x8) || defined (STM32L010xB)
562 #define LL_ADC_REG_TRIG_EXT_TIM21_TRGO (LL_ADC_REG_TRIG_EXT_TIM22_TRGO)
563 #endif
564
565 /**
566 * @}
567 */
568
569 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
570 * @{
571 */
572 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
573 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
574 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
575 /**
576 * @}
577 */
578
579 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
580 * @{
581 */
582 #define LL_ADC_REG_CONV_SINGLE (0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */
583 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
584 /**
585 * @}
586 */
587
588 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
589 * @{
590 */
591 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DMA */
592 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
593 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
594 /**
595 * @}
596 */
597
598 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
599 * @{
600 */
601 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000U) /*!< ADC group regular behavior in case of overrun: data preserved */
602 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
603 /**
604 * @}
605 */
606
607 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
608 * @{
609 */
610 #define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000U) /*!< ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */
611 #define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */
612 /**
613 * @}
614 */
615
616 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
617 * @{
618 */
619 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */
620 #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
621 /**
622 * @}
623 */
624
625 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
626 * @{
627 */
628 #define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */
629 #define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP_0) /*!< Sampling time 3.5 ADC clock cycles */
630 #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP_1) /*!< Sampling time 7.5 ADC clock cycles */
631 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0) /*!< Sampling time 12.5 ADC clock cycles */
632 #define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP_2) /*!< Sampling time 19.5 ADC clock cycles */
633 #define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0) /*!< Sampling time 39.5 ADC clock cycles */
634 #define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1) /*!< Sampling time 79.5 ADC clock cycles */
635 #define LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0) /*!< Sampling time 160.5 ADC clock cycles */
636 /**
637 * @}
638 */
639
640 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
641 * @{
642 */
643 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
644 /**
645 * @}
646 */
647
648 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
649 * @{
650 */
651 #define LL_ADC_AWD_DISABLE (0x00000000U) /*!< ADC analog watchdog monitoring disabled */
652 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CFGR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
653 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
654 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
655 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
656 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
657 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
658 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
659 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
660 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
661 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
662 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
663 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
664 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
665 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
666 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
667 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
668 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
669 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
670 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
671 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
672 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
673 #if defined(ADC_CCR_VLCDEN)
674 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
675 #define LL_ADC_AWD_CH_VLCD_REG ((LL_ADC_CHANNEL_VLCD & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
676 #endif
677 /**
678 * @}
679 */
680
681 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
682 * @{
683 */
684 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR_HT ) /*!< ADC analog watchdog threshold high */
685 #define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR_LT) /*!< ADC analog watchdog threshold low */
686 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR_HT | ADC_TR_LT) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
687 /**
688 * @}
689 */
690
691 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
692 * @{
693 */
694 #define LL_ADC_OVS_DISABLE (0x00000000U) /*!< ADC oversampling disabled. */
695 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of ADC group regular. Literal suffix "continued" is kept for compatibility with other STM32 devices featuring ADC group injected, in this case other oversampling scope parameters are available. */
696 /**
697 * @}
698 */
699
700 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
701 * @{
702 */
703 #define LL_ADC_OVS_REG_CONT (0x00000000U) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
704 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
705 /**
706 * @}
707 */
708
709 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
710 * @{
711 */
712 #define LL_ADC_OVS_RATIO_2 (0x00000000U) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
713 #define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
714 #define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
715 #define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
716 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
717 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
718 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
719 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
720 /**
721 * @}
722 */
723
724 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
725 * @{
726 */
727 #define LL_ADC_OVS_SHIFT_NONE (0x00000000U) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
728 #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
729 #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
730 #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
731 #define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
732 #define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
733 #define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
734 #define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
735 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
736 /**
737 * @}
738 */
739
740
741 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
742 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
743 * not timeout values.
744 * For details on delays values, refer to descriptions in source code
745 * above each literal definition.
746 * @{
747 */
748
749 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
750 /* not timeout values. */
751 /* Timeout values for ADC operations are dependent to device clock */
752 /* configuration (system clock versus ADC clock), */
753 /* and therefore must be defined in user application. */
754 /* Indications for estimation of ADC timeout delays, for this */
755 /* STM32 series: */
756 /* - ADC calibration time: maximum delay is 83/fADC. */
757 /* (refer to device datasheet, parameter "tCAL") */
758 /* - ADC enable time: maximum delay is 1 conversion cycle. */
759 /* (refer to device datasheet, parameter "tSTAB") */
760 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
761 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
762 /* cycles */
763 /* - ADC conversion time: duration depending on ADC clock and ADC */
764 /* configuration. */
765 /* (refer to device reference manual, section "Timing") */
766
767 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
768 /* Delay set to maximum value (refer to device datasheet, */
769 /* parameter "tUP_LDO"). */
770 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US (10U) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
771
772 /* Delay for internal voltage reference stabilization time. */
773 /* Delay set to maximum value (refer to device datasheet, */
774 /* parameter "TADC_BUF"). */
775 /* Unit: us */
776 #define LL_ADC_DELAY_VREFINT_STAB_US (10U) /*!< Delay for internal voltage reference stabilization time */
777
778 /* Delay for temperature sensor stabilization time. */
779 /* Literal set to maximum value (refer to device datasheet, */
780 /* parameter "tSTART"). */
781 /* Unit: us */
782 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (10U) /*!< Delay for temperature sensor stabilization time */
783
784 /* Delay required between ADC end of calibration and ADC enable. */
785 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
786 /* are required between ADC end of calibration and ADC enable. */
787 /* Wait time can be computed in user application by waiting for the */
788 /* equivalent number of CPU cycles, by taking into account */
789 /* ratio of CPU clock versus ADC clock prescalers. */
790 /* Unit: ADC clock cycles. */
791 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES (2U) /*!< Delay required between ADC end of calibration and ADC enable */
792
793 /**
794 * @}
795 */
796
797 /**
798 * @}
799 */
800
801
802 /* Exported macro ------------------------------------------------------------*/
803 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
804 * @{
805 */
806
807 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
808 * @{
809 */
810
811 /**
812 * @brief Write a value in ADC register
813 * @param __INSTANCE__ ADC Instance
814 * @param __REG__ Register to be written
815 * @param __VALUE__ Value to be written in the register
816 * @retval None
817 */
818 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
819
820 /**
821 * @brief Read a value in ADC register
822 * @param __INSTANCE__ ADC Instance
823 * @param __REG__ Register to be read
824 * @retval Register value
825 */
826 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
827 /**
828 * @}
829 */
830
831 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
832 * @{
833 */
834
835 /**
836 * @brief Helper macro to get ADC channel number in decimal format
837 * from literals LL_ADC_CHANNEL_x.
838 * @note Example:
839 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
840 * will return decimal number "4".
841 * @note The input can be a value from functions where a channel
842 * number is returned, either defined with number
843 * or with bitfield (only one bit must be set).
844 * @param __CHANNEL__ This parameter can be one of the following values:
845 * @arg @ref LL_ADC_CHANNEL_0
846 * @arg @ref LL_ADC_CHANNEL_1
847 * @arg @ref LL_ADC_CHANNEL_2
848 * @arg @ref LL_ADC_CHANNEL_3
849 * @arg @ref LL_ADC_CHANNEL_4
850 * @arg @ref LL_ADC_CHANNEL_5
851 * @arg @ref LL_ADC_CHANNEL_6
852 * @arg @ref LL_ADC_CHANNEL_7
853 * @arg @ref LL_ADC_CHANNEL_8
854 * @arg @ref LL_ADC_CHANNEL_9
855 * @arg @ref LL_ADC_CHANNEL_10
856 * @arg @ref LL_ADC_CHANNEL_11
857 * @arg @ref LL_ADC_CHANNEL_12
858 * @arg @ref LL_ADC_CHANNEL_13
859 * @arg @ref LL_ADC_CHANNEL_14
860 * @arg @ref LL_ADC_CHANNEL_15
861 * @arg @ref LL_ADC_CHANNEL_16 (1)
862 * @arg @ref LL_ADC_CHANNEL_17
863 * @arg @ref LL_ADC_CHANNEL_18
864 * @arg @ref LL_ADC_CHANNEL_VREFINT
865 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
866 * @arg @ref LL_ADC_CHANNEL_VLCD (1)
867 *
868 * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
869 * @retval Value between Min_Data=0 and Max_Data=18
870 */
871 #if defined(ADC_CCR_VLCDEN)
872 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
873 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) \
874 ? ( \
875 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
876 ) \
877 : \
878 ( \
879 (((__CHANNEL__) & ADC_CHSELR_CHSEL0) == ADC_CHSELR_CHSEL0) ? (0U) : \
880 ( \
881 (((__CHANNEL__) & ADC_CHSELR_CHSEL1) == ADC_CHSELR_CHSEL1) ? (1U) : \
882 ( \
883 (((__CHANNEL__) & ADC_CHSELR_CHSEL2) == ADC_CHSELR_CHSEL2) ? (2U) : \
884 ( \
885 (((__CHANNEL__) & ADC_CHSELR_CHSEL3) == ADC_CHSELR_CHSEL3) ? (3U) : \
886 ( \
887 (((__CHANNEL__) & ADC_CHSELR_CHSEL4) == ADC_CHSELR_CHSEL4) ? (4U) : \
888 ( \
889 (((__CHANNEL__) & ADC_CHSELR_CHSEL5) == ADC_CHSELR_CHSEL5) ? (5U) : \
890 ( \
891 (((__CHANNEL__) & ADC_CHSELR_CHSEL6) == ADC_CHSELR_CHSEL6) ? (6U) : \
892 ( \
893 (((__CHANNEL__) & ADC_CHSELR_CHSEL7) == ADC_CHSELR_CHSEL7) ? (7U) : \
894 ( \
895 (((__CHANNEL__) & ADC_CHSELR_CHSEL8) == ADC_CHSELR_CHSEL8) ? (8U) : \
896 ( \
897 (((__CHANNEL__) & ADC_CHSELR_CHSEL9) == ADC_CHSELR_CHSEL9) ? (9U) : \
898 ( \
899 (((__CHANNEL__) & ADC_CHSELR_CHSEL10) == ADC_CHSELR_CHSEL10) ? (10U) : \
900 ( \
901 (((__CHANNEL__) & ADC_CHSELR_CHSEL11) == ADC_CHSELR_CHSEL11) ? (11U) : \
902 ( \
903 (((__CHANNEL__) & ADC_CHSELR_CHSEL12) == ADC_CHSELR_CHSEL12) ? (12U) : \
904 ( \
905 (((__CHANNEL__) & ADC_CHSELR_CHSEL13) == ADC_CHSELR_CHSEL13) ? (13U) : \
906 ( \
907 (((__CHANNEL__) & ADC_CHSELR_CHSEL14) == ADC_CHSELR_CHSEL14) ? (14U) : \
908 ( \
909 (((__CHANNEL__) & ADC_CHSELR_CHSEL15) == ADC_CHSELR_CHSEL15) ? (15U) : \
910 ( \
911 (((__CHANNEL__) & ADC_CHSELR_CHSEL16) == ADC_CHSELR_CHSEL16) ? (16U) : \
912 ( \
913 (((__CHANNEL__) & ADC_CHSELR_CHSEL17) == ADC_CHSELR_CHSEL17) ? (17U) : \
914 ( \
915 (((__CHANNEL__) & ADC_CHSELR_CHSEL18) == ADC_CHSELR_CHSEL18) ? (18U) : \
916 (0U) \
917 ) \
918 ) \
919 ) \
920 ) \
921 ) \
922 ) \
923 ) \
924 ) \
925 ) \
926 ) \
927 ) \
928 ) \
929 ) \
930 ) \
931 ) \
932 ) \
933 ) \
934 ) \
935 ) \
936 )
937 #else
938 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
939 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) \
940 ? ( \
941 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
942 ) \
943 : \
944 ( \
945 (((__CHANNEL__) & ADC_CHSELR_CHSEL0) == ADC_CHSELR_CHSEL0) ? (0U) : \
946 ( \
947 (((__CHANNEL__) & ADC_CHSELR_CHSEL1) == ADC_CHSELR_CHSEL1) ? (1U) : \
948 ( \
949 (((__CHANNEL__) & ADC_CHSELR_CHSEL2) == ADC_CHSELR_CHSEL2) ? (2U) : \
950 ( \
951 (((__CHANNEL__) & ADC_CHSELR_CHSEL3) == ADC_CHSELR_CHSEL3) ? (3U) : \
952 ( \
953 (((__CHANNEL__) & ADC_CHSELR_CHSEL4) == ADC_CHSELR_CHSEL4) ? (4U) : \
954 ( \
955 (((__CHANNEL__) & ADC_CHSELR_CHSEL5) == ADC_CHSELR_CHSEL5) ? (5U) : \
956 ( \
957 (((__CHANNEL__) & ADC_CHSELR_CHSEL6) == ADC_CHSELR_CHSEL6) ? (6U) : \
958 ( \
959 (((__CHANNEL__) & ADC_CHSELR_CHSEL7) == ADC_CHSELR_CHSEL7) ? (7U) : \
960 ( \
961 (((__CHANNEL__) & ADC_CHSELR_CHSEL8) == ADC_CHSELR_CHSEL8) ? (8U) : \
962 ( \
963 (((__CHANNEL__) & ADC_CHSELR_CHSEL9) == ADC_CHSELR_CHSEL9) ? (9U) : \
964 ( \
965 (((__CHANNEL__) & ADC_CHSELR_CHSEL10) == ADC_CHSELR_CHSEL10) ? (10U) : \
966 ( \
967 (((__CHANNEL__) & ADC_CHSELR_CHSEL11) == ADC_CHSELR_CHSEL11) ? (11U) : \
968 ( \
969 (((__CHANNEL__) & ADC_CHSELR_CHSEL12) == ADC_CHSELR_CHSEL12) ? (12U) : \
970 ( \
971 (((__CHANNEL__) & ADC_CHSELR_CHSEL13) == ADC_CHSELR_CHSEL13) ? (13U) : \
972 ( \
973 (((__CHANNEL__) & ADC_CHSELR_CHSEL14) == ADC_CHSELR_CHSEL14) ? (14U) : \
974 ( \
975 (((__CHANNEL__) & ADC_CHSELR_CHSEL15) == ADC_CHSELR_CHSEL15) ? (15U) : \
976 ( \
977 (((__CHANNEL__) & ADC_CHSELR_CHSEL17) == ADC_CHSELR_CHSEL17) ? (17U) : \
978 ( \
979 (((__CHANNEL__) & ADC_CHSELR_CHSEL18) == ADC_CHSELR_CHSEL18) ? (18U) : \
980 (0U) \
981 ) \
982 ) \
983 ) \
984 ) \
985 ) \
986 ) \
987 ) \
988 ) \
989 ) \
990 ) \
991 ) \
992 ) \
993 ) \
994 ) \
995 ) \
996 ) \
997 ) \
998 ) \
999 )
1000 #endif
1001
1002 /**
1003 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1004 * from number in decimal format.
1005 * @note Example:
1006 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1007 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1008 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1009 * @retval Returned value can be one of the following values:
1010 * @arg @ref LL_ADC_CHANNEL_0
1011 * @arg @ref LL_ADC_CHANNEL_1
1012 * @arg @ref LL_ADC_CHANNEL_2
1013 * @arg @ref LL_ADC_CHANNEL_3
1014 * @arg @ref LL_ADC_CHANNEL_4
1015 * @arg @ref LL_ADC_CHANNEL_5
1016 * @arg @ref LL_ADC_CHANNEL_6
1017 * @arg @ref LL_ADC_CHANNEL_7
1018 * @arg @ref LL_ADC_CHANNEL_8
1019 * @arg @ref LL_ADC_CHANNEL_9
1020 * @arg @ref LL_ADC_CHANNEL_10
1021 * @arg @ref LL_ADC_CHANNEL_11
1022 * @arg @ref LL_ADC_CHANNEL_12
1023 * @arg @ref LL_ADC_CHANNEL_13
1024 * @arg @ref LL_ADC_CHANNEL_14
1025 * @arg @ref LL_ADC_CHANNEL_15
1026 * @arg @ref LL_ADC_CHANNEL_16 (1)
1027 * @arg @ref LL_ADC_CHANNEL_17
1028 * @arg @ref LL_ADC_CHANNEL_18
1029 * @arg @ref LL_ADC_CHANNEL_VREFINT (2)
1030 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
1031 * @arg @ref LL_ADC_CHANNEL_VLCD (1)(2)
1032 *
1033 * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.\n
1034 * (2) For ADC channel read back from ADC register,
1035 * comparison with internal channel parameter to be done
1036 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1037 */
1038 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1039 ( \
1040 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1041 (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)) \
1042 )
1043
1044 /**
1045 * @brief Helper macro to determine whether the selected channel
1046 * corresponds to literal definitions of driver.
1047 * @note The different literal definitions of ADC channels are:
1048 * - ADC internal channel:
1049 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1050 * - ADC external channel (channel connected to a GPIO pin):
1051 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1052 * @note The channel parameter must be a value defined from literal
1053 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1054 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1055 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1056 * must not be a value from functions where a channel number is
1057 * returned from ADC registers,
1058 * because internal and external channels share the same channel
1059 * number in ADC registers. The differentiation is made only with
1060 * parameters definitions of driver.
1061 * @param __CHANNEL__ This parameter can be one of the following values:
1062 * @arg @ref LL_ADC_CHANNEL_0
1063 * @arg @ref LL_ADC_CHANNEL_1
1064 * @arg @ref LL_ADC_CHANNEL_2
1065 * @arg @ref LL_ADC_CHANNEL_3
1066 * @arg @ref LL_ADC_CHANNEL_4
1067 * @arg @ref LL_ADC_CHANNEL_5
1068 * @arg @ref LL_ADC_CHANNEL_6
1069 * @arg @ref LL_ADC_CHANNEL_7
1070 * @arg @ref LL_ADC_CHANNEL_8
1071 * @arg @ref LL_ADC_CHANNEL_9
1072 * @arg @ref LL_ADC_CHANNEL_10
1073 * @arg @ref LL_ADC_CHANNEL_11
1074 * @arg @ref LL_ADC_CHANNEL_12
1075 * @arg @ref LL_ADC_CHANNEL_13
1076 * @arg @ref LL_ADC_CHANNEL_14
1077 * @arg @ref LL_ADC_CHANNEL_15
1078 * @arg @ref LL_ADC_CHANNEL_16 (1)
1079 * @arg @ref LL_ADC_CHANNEL_17
1080 * @arg @ref LL_ADC_CHANNEL_18
1081 * @arg @ref LL_ADC_CHANNEL_VREFINT
1082 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1083 * @arg @ref LL_ADC_CHANNEL_VLCD (1)
1084 *
1085 * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
1086 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1087 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1088 */
1089 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1090 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
1091
1092 /**
1093 * @brief Helper macro to convert a channel defined from parameter
1094 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1095 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1096 * to its equivalent parameter definition of a ADC external channel
1097 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1098 * @note The channel parameter can be, additionally to a value
1099 * defined from parameter definition of a ADC internal channel
1100 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1101 * a value defined from parameter definition of
1102 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1103 * or a value from functions where a channel number is returned
1104 * from ADC registers.
1105 * @param __CHANNEL__ This parameter can be one of the following values:
1106 * @arg @ref LL_ADC_CHANNEL_0
1107 * @arg @ref LL_ADC_CHANNEL_1
1108 * @arg @ref LL_ADC_CHANNEL_2
1109 * @arg @ref LL_ADC_CHANNEL_3
1110 * @arg @ref LL_ADC_CHANNEL_4
1111 * @arg @ref LL_ADC_CHANNEL_5
1112 * @arg @ref LL_ADC_CHANNEL_6
1113 * @arg @ref LL_ADC_CHANNEL_7
1114 * @arg @ref LL_ADC_CHANNEL_8
1115 * @arg @ref LL_ADC_CHANNEL_9
1116 * @arg @ref LL_ADC_CHANNEL_10
1117 * @arg @ref LL_ADC_CHANNEL_11
1118 * @arg @ref LL_ADC_CHANNEL_12
1119 * @arg @ref LL_ADC_CHANNEL_13
1120 * @arg @ref LL_ADC_CHANNEL_14
1121 * @arg @ref LL_ADC_CHANNEL_15
1122 * @arg @ref LL_ADC_CHANNEL_16 (1)
1123 * @arg @ref LL_ADC_CHANNEL_17
1124 * @arg @ref LL_ADC_CHANNEL_18
1125 * @arg @ref LL_ADC_CHANNEL_VREFINT
1126 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1127 * @arg @ref LL_ADC_CHANNEL_VLCD (1)
1128 *
1129 * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
1130 * @retval Returned value can be one of the following values:
1131 * @arg @ref LL_ADC_CHANNEL_0
1132 * @arg @ref LL_ADC_CHANNEL_1
1133 * @arg @ref LL_ADC_CHANNEL_2
1134 * @arg @ref LL_ADC_CHANNEL_3
1135 * @arg @ref LL_ADC_CHANNEL_4
1136 * @arg @ref LL_ADC_CHANNEL_5
1137 * @arg @ref LL_ADC_CHANNEL_6
1138 * @arg @ref LL_ADC_CHANNEL_7
1139 * @arg @ref LL_ADC_CHANNEL_8
1140 * @arg @ref LL_ADC_CHANNEL_9
1141 * @arg @ref LL_ADC_CHANNEL_10
1142 * @arg @ref LL_ADC_CHANNEL_11
1143 * @arg @ref LL_ADC_CHANNEL_12
1144 * @arg @ref LL_ADC_CHANNEL_13
1145 * @arg @ref LL_ADC_CHANNEL_14
1146 * @arg @ref LL_ADC_CHANNEL_15
1147 * @arg @ref LL_ADC_CHANNEL_16
1148 * @arg @ref LL_ADC_CHANNEL_17
1149 * @arg @ref LL_ADC_CHANNEL_18
1150 */
1151 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1152 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1153
1154 /**
1155 * @brief Helper macro to determine whether the internal channel
1156 * selected is available on the ADC instance selected.
1157 * @note The channel parameter must be a value defined from parameter
1158 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1159 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1160 * must not be a value defined from parameter definition of
1161 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1162 * or a value from functions where a channel number is
1163 * returned from ADC registers,
1164 * because internal and external channels share the same channel
1165 * number in ADC registers. The differentiation is made only with
1166 * parameters definitions of driver.
1167 * @param __ADC_INSTANCE__ ADC instance
1168 * @param __CHANNEL__ This parameter can be one of the following values:
1169 * @arg @ref LL_ADC_CHANNEL_VREFINT
1170 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1171 * @arg @ref LL_ADC_CHANNEL_VLCD (1)
1172 *
1173 * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
1174
1175 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1176 * Value "1" if the internal channel selected is available on the ADC instance selected.
1177 */
1178 #if defined(ADC_CCR_VLCDEN)
1179 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1180 ( \
1181 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1182 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1183 ((__CHANNEL__) == LL_ADC_CHANNEL_VLCD) \
1184 )
1185 #else
1186 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1187 ( \
1188 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1189 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \
1190 )
1191 #endif
1192
1193 /**
1194 * @brief Helper macro to define ADC analog watchdog parameter:
1195 * define a single channel to monitor with analog watchdog
1196 * from sequencer channel and groups definition.
1197 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1198 * Example:
1199 * LL_ADC_SetAnalogWDMonitChannels(
1200 * ADC1, LL_ADC_AWD1,
1201 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1202 * @param __CHANNEL__ This parameter can be one of the following values:
1203 * @arg @ref LL_ADC_CHANNEL_0
1204 * @arg @ref LL_ADC_CHANNEL_1
1205 * @arg @ref LL_ADC_CHANNEL_2
1206 * @arg @ref LL_ADC_CHANNEL_3
1207 * @arg @ref LL_ADC_CHANNEL_4
1208 * @arg @ref LL_ADC_CHANNEL_5
1209 * @arg @ref LL_ADC_CHANNEL_6
1210 * @arg @ref LL_ADC_CHANNEL_7
1211 * @arg @ref LL_ADC_CHANNEL_8
1212 * @arg @ref LL_ADC_CHANNEL_9
1213 * @arg @ref LL_ADC_CHANNEL_10
1214 * @arg @ref LL_ADC_CHANNEL_11
1215 * @arg @ref LL_ADC_CHANNEL_12
1216 * @arg @ref LL_ADC_CHANNEL_13
1217 * @arg @ref LL_ADC_CHANNEL_14
1218 * @arg @ref LL_ADC_CHANNEL_15
1219 * @arg @ref LL_ADC_CHANNEL_16 (1)
1220 * @arg @ref LL_ADC_CHANNEL_17
1221 * @arg @ref LL_ADC_CHANNEL_18
1222 * @arg @ref LL_ADC_CHANNEL_VREFINT (2)
1223 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
1224 * @arg @ref LL_ADC_CHANNEL_VLCD (1)(2)
1225 *
1226 * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.\n
1227 * (2) For ADC channel read back from ADC register,
1228 * comparison with internal channel parameter to be done
1229 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1230 * @param __GROUP__ This parameter can be one of the following values:
1231 * @arg @ref LL_ADC_GROUP_REGULAR
1232 * @retval Returned value can be one of the following values:
1233 * @arg @ref LL_ADC_AWD_DISABLE
1234 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
1235 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
1236 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
1237 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
1238 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
1239 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
1240 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
1241 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
1242 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
1243 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
1244 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
1245 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
1246 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
1247 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
1248 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
1249 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
1250 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
1251 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (1)
1252 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
1253 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
1254 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
1255 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
1256 * @arg @ref LL_ADC_AWD_CH_VLCD_REG (1)
1257 *
1258 * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
1259 */
1260 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1261 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)
1262
1263 /**
1264 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1265 * or low in function of ADC resolution, when ADC resolution is
1266 * different of 12 bits.
1267 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
1268 * or @ref LL_ADC_SetAnalogWDThresholds().
1269 * Example, with a ADC resolution of 8 bits, to set the value of
1270 * analog watchdog threshold high (on 8 bits):
1271 * LL_ADC_SetAnalogWDThresholds
1272 * (< ADCx param >,
1273 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1274 * );
1275 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1276 * @arg @ref LL_ADC_RESOLUTION_12B
1277 * @arg @ref LL_ADC_RESOLUTION_10B
1278 * @arg @ref LL_ADC_RESOLUTION_8B
1279 * @arg @ref LL_ADC_RESOLUTION_6B
1280 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1281 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1282 */
1283 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1284 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
1285
1286 /**
1287 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1288 * or low in function of ADC resolution, when ADC resolution is
1289 * different of 12 bits.
1290 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1291 * Example, with a ADC resolution of 8 bits, to get the value of
1292 * analog watchdog threshold high (on 8 bits):
1293 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1294 * (LL_ADC_RESOLUTION_8B,
1295 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1296 * );
1297 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1298 * @arg @ref LL_ADC_RESOLUTION_12B
1299 * @arg @ref LL_ADC_RESOLUTION_10B
1300 * @arg @ref LL_ADC_RESOLUTION_8B
1301 * @arg @ref LL_ADC_RESOLUTION_6B
1302 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1303 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1304 */
1305 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1306 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
1307
1308 /**
1309 * @brief Helper macro to get the ADC analog watchdog threshold high
1310 * or low from raw value containing both thresholds concatenated.
1311 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1312 * Example, to get analog watchdog threshold high from the register raw value:
1313 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
1314 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
1315 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
1316 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
1317 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1318 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1319 */
1320 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
1321 (((__AWD_THRESHOLD_TYPE__) == LL_ADC_AWD_THRESHOLD_LOW) \
1322 ? ( \
1323 (__AWD_THRESHOLDS__) & LL_ADC_AWD_THRESHOLD_LOW \
1324 ) \
1325 : \
1326 ( \
1327 ((__AWD_THRESHOLDS__) >> ADC_TR_HT_BITOFFSET_POS) & LL_ADC_AWD_THRESHOLD_LOW \
1328 ) \
1329 )
1330
1331 /**
1332 * @brief Helper macro to select the ADC common instance
1333 * to which is belonging the selected ADC instance.
1334 * @note ADC common register instance can be used for:
1335 * - Set parameters common to several ADC instances
1336 * - Multimode (for devices with several ADC instances)
1337 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1338 * @param __ADCx__ ADC instance
1339 * @retval ADC common register instance
1340 */
1341 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1342 (ADC1_COMMON)
1343
1344 /**
1345 * @brief Helper macro to check if all ADC instances sharing the same
1346 * ADC common instance are disabled.
1347 * @note This check is required by functions with setting conditioned to
1348 * ADC state:
1349 * All ADC instances of the ADC common group must be disabled.
1350 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1351 * @note On devices with only 1 ADC common instance, parameter of this macro
1352 * is useless and can be ignored (parameter kept for compatibility
1353 * with devices featuring several ADC common instances).
1354 * @param __ADCXY_COMMON__ ADC common instance
1355 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1356 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1357 * are disabled.
1358 * Value "1" if at least one ADC instance sharing the same ADC common instance
1359 * is enabled.
1360 */
1361 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1362 LL_ADC_IsEnabled(ADC1)
1363
1364 /**
1365 * @brief Helper macro to define the ADC conversion data full-scale digital
1366 * value corresponding to the selected ADC resolution.
1367 * @note ADC conversion data full-scale corresponds to voltage range
1368 * determined by analog voltage references Vref+ and Vref-
1369 * (refer to reference manual).
1370 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1371 * @arg @ref LL_ADC_RESOLUTION_12B
1372 * @arg @ref LL_ADC_RESOLUTION_10B
1373 * @arg @ref LL_ADC_RESOLUTION_8B
1374 * @arg @ref LL_ADC_RESOLUTION_6B
1375 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1376 */
1377 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1378 ((0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)))
1379
1380 /**
1381 * @brief Helper macro to convert the ADC conversion data from
1382 * a resolution to another resolution.
1383 * @param __DATA__ ADC conversion data to be converted
1384 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
1385 * This parameter can be one of the following values:
1386 * @arg @ref LL_ADC_RESOLUTION_12B
1387 * @arg @ref LL_ADC_RESOLUTION_10B
1388 * @arg @ref LL_ADC_RESOLUTION_8B
1389 * @arg @ref LL_ADC_RESOLUTION_6B
1390 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1391 * This parameter can be one of the following values:
1392 * @arg @ref LL_ADC_RESOLUTION_12B
1393 * @arg @ref LL_ADC_RESOLUTION_10B
1394 * @arg @ref LL_ADC_RESOLUTION_8B
1395 * @arg @ref LL_ADC_RESOLUTION_6B
1396 * @retval ADC conversion data to the requested resolution
1397 */
1398 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
1399 (((__DATA__) \
1400 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U))) \
1401 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)) \
1402 )
1403
1404 /**
1405 * @brief Helper macro to calculate the voltage (unit: mVolt)
1406 * corresponding to a ADC conversion data (unit: digital value).
1407 * @note Analog reference voltage (Vref+) must be either known from
1408 * user board environment or can be calculated using ADC measurement
1409 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1410 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1411 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1412 * (unit: digital value).
1413 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1414 * @arg @ref LL_ADC_RESOLUTION_12B
1415 * @arg @ref LL_ADC_RESOLUTION_10B
1416 * @arg @ref LL_ADC_RESOLUTION_8B
1417 * @arg @ref LL_ADC_RESOLUTION_6B
1418 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1419 */
1420 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1421 __ADC_DATA__,\
1422 __ADC_RESOLUTION__) \
1423 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
1424 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1425 )
1426
1427 /**
1428 * @brief Helper macro to calculate analog reference voltage (Vref+)
1429 * (unit: mVolt) from ADC conversion data of internal voltage
1430 * reference VrefInt.
1431 * @note Computation is using VrefInt calibration value
1432 * stored in system memory for each device during production.
1433 * @note This voltage depends on user board environment: voltage level
1434 * connected to pin Vref+.
1435 * On devices with small package, the pin Vref+ is not present
1436 * and internally bonded to pin Vdda.
1437 * @note On this STM32 series, calibration data of internal voltage reference
1438 * VrefInt corresponds to a resolution of 12 bits,
1439 * this is the recommended ADC resolution to convert voltage of
1440 * internal voltage reference VrefInt.
1441 * Otherwise, this macro performs the processing to scale
1442 * ADC conversion data to 12 bits.
1443 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
1444 * of internal voltage reference VrefInt (unit: digital value).
1445 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1446 * @arg @ref LL_ADC_RESOLUTION_12B
1447 * @arg @ref LL_ADC_RESOLUTION_10B
1448 * @arg @ref LL_ADC_RESOLUTION_8B
1449 * @arg @ref LL_ADC_RESOLUTION_6B
1450 * @retval Analog reference voltage (unit: mV)
1451 */
1452 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
1453 __ADC_RESOLUTION__) \
1454 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
1455 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
1456 (__ADC_RESOLUTION__), \
1457 LL_ADC_RESOLUTION_12B) \
1458 )
1459
1460 /* Note: On device STM32L011, calibration parameter TS_CAL1 is not available. */
1461 /* Therefore, helper macro __LL_ADC_CALC_TEMPERATURE() is not available.*/
1462 /* Use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). */
1463 /* Note: On device STM32L010xx, temperature sensor is not available. */
1464 /* Therefore, helper macro related to temperature sensor are */
1465 /* not available. */
1466 #if !defined(STM32L011xx) && !defined(STM32L010xB) && !defined(STM32L010x8) && !defined(STM32L010x6) && !defined(STM32L010x4)
1467 /**
1468 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1469 * from ADC conversion data of internal temperature sensor.
1470 * @note Computation is using temperature sensor calibration values
1471 * stored in system memory for each device during production.
1472 * @note Calculation formula:
1473 * Temperature = ((TS_ADC_DATA - TS_CAL1)
1474 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
1475 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
1476 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1477 * Avg_Slope = (TS_CAL2 - TS_CAL1)
1478 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
1479 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
1480 * TEMP_DEGC_CAL1 (calibrated in factory)
1481 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
1482 * TEMP_DEGC_CAL2 (calibrated in factory)
1483 * Caution: Calculation relevancy under reserve that calibration
1484 * parameters are correct (address and data).
1485 * To calculate temperature using temperature sensor
1486 * datasheet typical values (generic values less, therefore
1487 * less accurate than calibrated values),
1488 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
1489 * @note As calculation input, the analog reference voltage (Vref+) must be
1490 * defined as it impacts the ADC LSB equivalent voltage.
1491 * @note Analog reference voltage (Vref+) must be either known from
1492 * user board environment or can be calculated using ADC measurement
1493 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1494 * @note On this STM32 series, calibration data of temperature sensor
1495 * corresponds to a resolution of 12 bits,
1496 * this is the recommended ADC resolution to convert voltage of
1497 * temperature sensor.
1498 * Otherwise, this macro performs the processing to scale
1499 * ADC conversion data to 12 bits.
1500 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1501 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
1502 * temperature sensor (unit: digital value).
1503 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
1504 * sensor voltage has been measured.
1505 * This parameter can be one of the following values:
1506 * @arg @ref LL_ADC_RESOLUTION_12B
1507 * @arg @ref LL_ADC_RESOLUTION_10B
1508 * @arg @ref LL_ADC_RESOLUTION_8B
1509 * @arg @ref LL_ADC_RESOLUTION_6B
1510 * @retval Temperature (unit: degree Celsius)
1511 */
1512 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
1513 __TEMPSENSOR_ADC_DATA__,\
1514 __ADC_RESOLUTION__) \
1515 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
1516 (__ADC_RESOLUTION__), \
1517 LL_ADC_RESOLUTION_12B) \
1518 * (__VREFANALOG_VOLTAGE__)) \
1519 / TEMPSENSOR_CAL_VREFANALOG) \
1520 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
1521 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
1522 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
1523 ) + TEMPSENSOR_CAL1_TEMP \
1524 )
1525 #endif
1526
1527 /* Note: On device STM32L010xx, temperature sensor is not available. */
1528 /* Therefore, helper macro related to temperature sensor are */
1529 /* not available. */
1530 #if !defined(STM32L010xB) && !defined(STM32L010x8) && !defined(STM32L010x6) && !defined(STM32L010x4)
1531 /**
1532 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1533 * from ADC conversion data of internal temperature sensor.
1534 * @note Computation is using temperature sensor typical values
1535 * (refer to device datasheet).
1536 * @note Calculation formula:
1537 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1538 * / Avg_Slope + CALx_TEMP
1539 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1540 * (unit: digital value)
1541 * Avg_Slope = temperature sensor slope
1542 * (unit: uV/Degree Celsius)
1543 * TS_TYP_CALx_VOLT = temperature sensor digital value at
1544 * temperature CALx_TEMP (unit: mV)
1545 * Caution: Calculation relevancy under reserve the temperature sensor
1546 * of the current device has characteristics in line with
1547 * datasheet typical values.
1548 * If temperature sensor calibration values are available on
1549 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
1550 * temperature calculation will be more accurate using
1551 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
1552 * @note As calculation input, the analog reference voltage (Vref+) must be
1553 * defined as it impacts the ADC LSB equivalent voltage.
1554 * @note Analog reference voltage (Vref+) must be either known from
1555 * user board environment or can be calculated using ADC measurement
1556 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1557 * @note ADC measurement data must correspond to a resolution of 12bits
1558 * (full scale digital value 4095). If not the case, the data must be
1559 * preliminarily rescaled to an equivalent resolution of 12 bits.
1560 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
1561 * On STM32L0, refer to device datasheet parameter "Avg_Slope".
1562 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
1563 * On STM32L0, refer to device datasheet parameter "V130" (corresponding to TS_CAL2).
1564 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
1565 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
1566 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
1567 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1568 * This parameter can be one of the following values:
1569 * @arg @ref LL_ADC_RESOLUTION_12B
1570 * @arg @ref LL_ADC_RESOLUTION_10B
1571 * @arg @ref LL_ADC_RESOLUTION_8B
1572 * @arg @ref LL_ADC_RESOLUTION_6B
1573 * @retval Temperature (unit: degree Celsius)
1574 */
1575 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1576 __TEMPSENSOR_TYP_CALX_V__,\
1577 __TEMPSENSOR_CALX_TEMP__,\
1578 __VREFANALOG_VOLTAGE__,\
1579 __TEMPSENSOR_ADC_DATA__,\
1580 __ADC_RESOLUTION__) \
1581 ((( ( \
1582 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
1583 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
1584 * 1000) \
1585 - \
1586 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
1587 * 1000) \
1588 ) \
1589 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
1590 ) + (__TEMPSENSOR_CALX_TEMP__) \
1591 )
1592 #endif
1593 /**
1594 * @}
1595 */
1596
1597 /**
1598 * @}
1599 */
1600
1601
1602 /* Exported functions --------------------------------------------------------*/
1603 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
1604 * @{
1605 */
1606
1607 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
1608 * @{
1609 */
1610 /* Note: LL ADC functions to set DMA transfer are located into sections of */
1611 /* configuration of ADC instance, groups and multimode (if available): */
1612 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
1613
1614 /**
1615 * @brief Function to help to configure DMA transfer from ADC: retrieve the
1616 * ADC register address from ADC instance and a list of ADC registers
1617 * intended to be used (most commonly) with DMA transfer.
1618 * @note These ADC registers are data registers:
1619 * when ADC conversion data is available in ADC data registers,
1620 * ADC generates a DMA transfer request.
1621 * @note This macro is intended to be used with LL DMA driver, refer to
1622 * function "LL_DMA_ConfigAddresses()".
1623 * Example:
1624 * LL_DMA_ConfigAddresses(DMA1,
1625 * LL_DMA_CHANNEL_1,
1626 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
1627 * (uint32_t)&< array or variable >,
1628 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
1629 * @note For devices with several ADC: in multimode, some devices
1630 * use a different data register outside of ADC instance scope
1631 * (common data register). This macro manages this register difference,
1632 * only ADC instance has to be set as parameter.
1633 * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
1634 * @param ADCx ADC instance
1635 * @param Register This parameter can be one of the following values:
1636 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
1637 * @retval ADC register address
1638 */
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)1639 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
1640 {
1641 /* Prevent unused argument compilation warning */
1642 (void)Register;
1643
1644 /* Retrieve address of register DR */
1645 return (uint32_t) & (ADCx->DR);
1646 }
1647
1648 /**
1649 * @}
1650 */
1651
1652 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
1653 * @{
1654 */
1655
1656 /**
1657 * @brief Set parameter common to several ADC: Clock source and prescaler.
1658 * @note On this STM32 series, setting of this feature is conditioned to
1659 * ADC state:
1660 * All ADC instances of the ADC common group must be disabled.
1661 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1662 * ADC instance or by using helper macro helper macro
1663 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1664 * @rmtoll CCR PRESC LL_ADC_SetCommonClock
1665 * @param ADCxy_COMMON ADC common instance
1666 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1667 * @param CommonClock This parameter can be one of the following values:
1668 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1)
1669 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1)
1670 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1)
1671 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1)
1672 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1)
1673 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1)
1674 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1)
1675 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1)
1676 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1)
1677 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1)
1678 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
1679 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
1680 *
1681 * (1) ADC common clock asynchronous prescaler is applied to
1682 * each ADC instance if the corresponding ADC instance clock
1683 * is set to clock source asynchronous.
1684 * (refer to function @ref LL_ADC_SetClock() ).
1685 * @retval None
1686 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)1687 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
1688 {
1689 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);
1690 }
1691
1692 /**
1693 * @brief Get parameter common to several ADC: Clock source and prescaler.
1694 * @rmtoll CCR PRESC LL_ADC_GetCommonClock
1695 * @param ADCxy_COMMON ADC common instance
1696 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1697 * @retval Returned value can be one of the following values:
1698 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1)
1699 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1)
1700 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1)
1701 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1)
1702 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1)
1703 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1)
1704 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1)
1705 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1)
1706 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1)
1707 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1)
1708 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
1709 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
1710 *
1711 * (1) ADC common clock asynchronous prescaler is applied to
1712 * each ADC instance if the corresponding ADC instance clock
1713 * is set to clock source asynchronous.
1714 * (refer to function @ref LL_ADC_SetClock() ).
1715 */
LL_ADC_GetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON)1716 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
1717 {
1718 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));
1719 }
1720
1721 /**
1722 * @brief Set parameter common to several ADC: Clock low frequency mode.
1723 * Refer to reference manual for alignments formats
1724 * dependencies to ADC resolutions.
1725 * @note On this STM32 series, setting of this feature is conditioned to
1726 * ADC state:
1727 * ADC must be disabled or enabled without conversion on going
1728 * on group regular.
1729 * @rmtoll CCR LFMEN LL_ADC_SetCommonFrequencyMode
1730 * @param ADCxy_COMMON ADC common instance
1731 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1732 * @param CommonFrequencyMode This parameter can be one of the following values:
1733 * @arg @ref LL_ADC_CLOCK_FREQ_MODE_HIGH
1734 * @arg @ref LL_ADC_CLOCK_FREQ_MODE_LOW
1735 * @retval None
1736 */
LL_ADC_SetCommonFrequencyMode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonFrequencyMode)1737 __STATIC_INLINE void LL_ADC_SetCommonFrequencyMode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonFrequencyMode)
1738 {
1739 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_LFMEN, CommonFrequencyMode);
1740 }
1741
1742 /**
1743 * @brief Get parameter common to several ADC: Clock low frequency mode.
1744 * Refer to reference manual for alignments formats
1745 * dependencies to ADC resolutions.
1746 * @rmtoll CCR LFMEN LL_ADC_GetCommonFrequencyMode
1747 * @param ADCxy_COMMON ADC common instance
1748 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1749 * @retval Returned value can be one of the following values:
1750 * @arg @ref LL_ADC_CLOCK_FREQ_MODE_HIGH
1751 * @arg @ref LL_ADC_CLOCK_FREQ_MODE_LOW
1752 */
LL_ADC_GetCommonFrequencyMode(ADC_Common_TypeDef * ADCxy_COMMON)1753 __STATIC_INLINE uint32_t LL_ADC_GetCommonFrequencyMode(ADC_Common_TypeDef *ADCxy_COMMON)
1754 {
1755 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_LFMEN));
1756 }
1757
1758 /**
1759 * @brief Set parameter common to several ADC: measurement path to internal
1760 * channels (VrefInt, temperature sensor, ...).
1761 * @note One or several values can be selected.
1762 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1763 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1764 * @note Stabilization time of measurement path to internal channel:
1765 * After enabling internal paths, before starting ADC conversion,
1766 * a delay is required for internal voltage reference and
1767 * temperature sensor stabilization time.
1768 * Refer to device datasheet.
1769 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
1770 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
1771 * @note ADC internal channel sampling time constraint:
1772 * For ADC conversion of internal channels,
1773 * a sampling time minimum value is required.
1774 * Refer to device datasheet.
1775 * @note On this STM32 series, setting of this feature is conditioned to
1776 * ADC state:
1777 * All ADC instances of the ADC common group must be disabled.
1778 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1779 * ADC instance or by using helper macro helper macro
1780 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1781 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
1782 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
1783 * CCR VLCDEN LL_ADC_SetCommonPathInternalCh
1784 * @param ADCxy_COMMON ADC common instance
1785 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1786 * @param PathInternal This parameter can be a combination of the following values:
1787 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1788 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1789 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR (2)
1790 * @arg @ref LL_ADC_PATH_INTERNAL_VLCD (1)
1791 *
1792 * (1) value not defined in all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
1793 * (2) value not defined in all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx, STM32L04xxx, STM32L03xxx, STM32L02xxx.
1794 * @retval None
1795 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)1796 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1797 {
1798 #if defined (ADC_CCR_VLCDEN) && defined (ADC_CCR_TSEN)
1799 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VLCDEN, PathInternal);
1800 #elif defined (ADC_CCR_TSEN)
1801 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
1802 #else
1803 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN, PathInternal);
1804 #endif
1805 }
1806
1807 /**
1808 * @brief Get parameter common to several ADC: measurement path to internal
1809 * channels (VrefInt, temperature sensor, ...).
1810 * @note One or several values can be selected.
1811 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1812 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1813 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
1814 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
1815 * CCR VLCDEN LL_ADC_GetCommonPathInternalCh
1816 * @param ADCxy_COMMON ADC common instance
1817 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1818 * @retval Returned value can be a combination of the following values:
1819 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1820 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1821 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR (2)
1822 * @arg @ref LL_ADC_PATH_INTERNAL_VLCD (1)
1823 *
1824 * (1) value not defined in all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
1825 * (2) value not defined in all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx, STM32L04xxx, STM32L03xxx, STM32L02xxx.
1826 */
LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON)1827 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
1828 {
1829 #if defined (ADC_CCR_VLCDEN) && defined (ADC_CCR_TSEN)
1830 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VLCDEN));
1831 #elif defined (ADC_CCR_TSEN)
1832 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN));
1833 #else
1834 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN));
1835 #endif
1836 }
1837
1838 /**
1839 * @}
1840 */
1841
1842 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
1843 * @{
1844 */
1845
1846 /**
1847 * @brief Set ADC instance clock source and prescaler.
1848 * @note On this STM32 series, setting of this feature is conditioned to
1849 * ADC state:
1850 * ADC must be disabled.
1851 * @rmtoll CFGR2 CKMODE LL_ADC_SetClock
1852 * @param ADCx ADC instance
1853 * @param ClockSource This parameter can be one of the following values:
1854 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1855 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1856 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
1857 * @arg @ref LL_ADC_CLOCK_ASYNC (1)
1858 *
1859 * (1) Asynchronous clock prescaler can be configured using
1860 * function @ref LL_ADC_SetCommonClock().\n
1861 * (2) Caution: This parameter has some clock ratio constraints:
1862 * This configuration must be enabled only if PCLK has a 50%
1863 * duty clock cycle (APB prescaler configured inside the RCC
1864 * must be bypassed and the system clock must by 50% duty
1865 * cycle).
1866 * Refer to reference manual.
1867 * @retval None
1868 */
LL_ADC_SetClock(ADC_TypeDef * ADCx,uint32_t ClockSource)1869 __STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource)
1870 {
1871 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource);
1872 }
1873
1874 /**
1875 * @brief Get ADC instance clock source and prescaler.
1876 * @rmtoll CFGR2 CKMODE LL_ADC_GetClock
1877 * @param ADCx ADC instance
1878 * @retval Returned value can be one of the following values:
1879 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1880 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1881 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
1882 * @arg @ref LL_ADC_CLOCK_ASYNC (1)
1883 *
1884 * (1) Asynchronous clock prescaler can be retrieved using
1885 * function @ref LL_ADC_GetCommonClock().\n
1886 * (2) Caution: This parameter has some clock ratio constraints:
1887 * This configuration must be enabled only if PCLK has a 50%
1888 * duty clock cycle (APB prescaler configured inside the RCC
1889 * must be bypassed and the system clock must by 50% duty
1890 * cycle).
1891 * Refer to reference manual.
1892 */
LL_ADC_GetClock(ADC_TypeDef * ADCx)1893 __STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx)
1894 {
1895 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE));
1896 }
1897
1898 /**
1899 * @brief Set ADC calibration factor in the mode single-ended
1900 * or differential (for devices with differential mode available).
1901 * @note This function is intended to set calibration parameters
1902 * without having to perform a new calibration using
1903 * @ref LL_ADC_StartCalibration().
1904 * @note On this STM32 series, setting of this feature is conditioned to
1905 * ADC state:
1906 * ADC must be enabled, without calibration on going, without conversion
1907 * on going on group regular.
1908 * @rmtoll CALFACT CALFACT LL_ADC_SetCalibrationFactor
1909 * @param ADCx ADC instance
1910 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
1911 * @retval None
1912 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t CalibrationFactor)1913 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor)
1914 {
1915 MODIFY_REG(ADCx->CALFACT,
1916 ADC_CALFACT_CALFACT,
1917 CalibrationFactor);
1918 }
1919
1920 /**
1921 * @brief Get ADC calibration factor in the mode single-ended
1922 * or differential (for devices with differential mode available).
1923 * @note Calibration factors are set by hardware after performing
1924 * a calibration run using function @ref LL_ADC_StartCalibration().
1925 * @rmtoll CALFACT CALFACT LL_ADC_GetCalibrationFactor
1926 * @param ADCx ADC instance
1927 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
1928 */
LL_ADC_GetCalibrationFactor(ADC_TypeDef * ADCx)1929 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx)
1930 {
1931 return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT));
1932 }
1933
1934 /**
1935 * @brief Set ADC resolution.
1936 * Refer to reference manual for alignments formats
1937 * dependencies to ADC resolutions.
1938 * @note On this STM32 series, setting of this feature is conditioned to
1939 * ADC state:
1940 * ADC must be disabled or enabled without conversion on going
1941 * on group regular.
1942 * @rmtoll CFGR1 RES LL_ADC_SetResolution
1943 * @param ADCx ADC instance
1944 * @param Resolution This parameter can be one of the following values:
1945 * @arg @ref LL_ADC_RESOLUTION_12B
1946 * @arg @ref LL_ADC_RESOLUTION_10B
1947 * @arg @ref LL_ADC_RESOLUTION_8B
1948 * @arg @ref LL_ADC_RESOLUTION_6B
1949 * @retval None
1950 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)1951 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
1952 {
1953 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
1954 }
1955
1956 /**
1957 * @brief Get ADC resolution.
1958 * Refer to reference manual for alignments formats
1959 * dependencies to ADC resolutions.
1960 * @rmtoll CFGR1 RES LL_ADC_GetResolution
1961 * @param ADCx ADC instance
1962 * @retval Returned value can be one of the following values:
1963 * @arg @ref LL_ADC_RESOLUTION_12B
1964 * @arg @ref LL_ADC_RESOLUTION_10B
1965 * @arg @ref LL_ADC_RESOLUTION_8B
1966 * @arg @ref LL_ADC_RESOLUTION_6B
1967 */
LL_ADC_GetResolution(ADC_TypeDef * ADCx)1968 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
1969 {
1970 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
1971 }
1972
1973 /**
1974 * @brief Set ADC conversion data alignment.
1975 * @note Refer to reference manual for alignments formats
1976 * dependencies to ADC resolutions.
1977 * @note On this STM32 series, setting of this feature is conditioned to
1978 * ADC state:
1979 * ADC must be disabled or enabled without conversion on going
1980 * on group regular.
1981 * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment
1982 * @param ADCx ADC instance
1983 * @param DataAlignment This parameter can be one of the following values:
1984 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
1985 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
1986 * @retval None
1987 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)1988 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
1989 {
1990 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
1991 }
1992
1993 /**
1994 * @brief Get ADC conversion data alignment.
1995 * @note Refer to reference manual for alignments formats
1996 * dependencies to ADC resolutions.
1997 * @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment
1998 * @param ADCx ADC instance
1999 * @retval Returned value can be one of the following values:
2000 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2001 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2002 */
LL_ADC_GetDataAlignment(ADC_TypeDef * ADCx)2003 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
2004 {
2005 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
2006 }
2007
2008 /**
2009 * @brief Set ADC low power mode.
2010 * @note Description of ADC low power modes:
2011 * - ADC low power mode "auto wait": Dynamic low power mode,
2012 * ADC conversions occurrences are limited to the minimum necessary
2013 * in order to reduce power consumption.
2014 * New ADC conversion starts only when the previous
2015 * unitary conversion data (for ADC group regular)
2016 * has been retrieved by user software.
2017 * In the meantime, ADC remains idle: does not performs any
2018 * other conversion.
2019 * This mode allows to automatically adapt the ADC conversions
2020 * triggers to the speed of the software that reads the data.
2021 * Moreover, this avoids risk of overrun for low frequency
2022 * applications.
2023 * How to use this low power mode:
2024 * - Do not use with interruption or DMA since these modes
2025 * have to clear immediately the EOC flag to free the
2026 * IRQ vector sequencer.
2027 * - Do use with polling: 1. Start conversion,
2028 * 2. Later on, when conversion data is needed: poll for end of
2029 * conversion to ensure that conversion is completed and
2030 * retrieve ADC conversion data. This will trig another
2031 * ADC conversion start.
2032 * - ADC low power mode "auto power-off" (feature available on
2033 * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
2034 * the ADC automatically powers-off after a conversion and
2035 * automatically wakes up when a new conversion is triggered
2036 * (with startup time between trigger and start of sampling).
2037 * This feature can be combined with low power mode "auto wait".
2038 * @note With ADC low power mode "auto wait", the ADC conversion data read
2039 * is corresponding to previous ADC conversion start, independently
2040 * of delay during which ADC was idle.
2041 * Therefore, the ADC conversion data may be outdated: does not
2042 * correspond to the current voltage level on the selected
2043 * ADC channel.
2044 * @note On this STM32 series, setting of this feature is conditioned to
2045 * ADC state:
2046 * ADC must be disabled or enabled without conversion on going
2047 * on group regular.
2048 * @rmtoll CFGR1 WAIT LL_ADC_SetLowPowerMode\n
2049 * CFGR1 AUTOFF LL_ADC_SetLowPowerMode
2050 * @param ADCx ADC instance
2051 * @param LowPowerMode This parameter can be one of the following values:
2052 * @arg @ref LL_ADC_LP_MODE_NONE
2053 * @arg @ref LL_ADC_LP_AUTOWAIT
2054 * @arg @ref LL_ADC_LP_AUTOPOWEROFF
2055 * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
2056 * @retval None
2057 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)2058 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
2059 {
2060 MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode);
2061 }
2062
2063 /**
2064 * @brief Get ADC low power mode:
2065 * @note Description of ADC low power modes:
2066 * - ADC low power mode "auto wait": Dynamic low power mode,
2067 * ADC conversions occurrences are limited to the minimum necessary
2068 * in order to reduce power consumption.
2069 * New ADC conversion starts only when the previous
2070 * unitary conversion data (for ADC group regular)
2071 * has been retrieved by user software.
2072 * In the meantime, ADC remains idle: does not performs any
2073 * other conversion.
2074 * This mode allows to automatically adapt the ADC conversions
2075 * triggers to the speed of the software that reads the data.
2076 * Moreover, this avoids risk of overrun for low frequency
2077 * applications.
2078 * How to use this low power mode:
2079 * - Do not use with interruption or DMA since these modes
2080 * have to clear immediately the EOC flag to free the
2081 * IRQ vector sequencer.
2082 * - Do use with polling: 1. Start conversion,
2083 * 2. Later on, when conversion data is needed: poll for end of
2084 * conversion to ensure that conversion is completed and
2085 * retrieve ADC conversion data. This will trig another
2086 * ADC conversion start.
2087 * - ADC low power mode "auto power-off" (feature available on
2088 * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
2089 * the ADC automatically powers-off after a conversion and
2090 * automatically wakes up when a new conversion is triggered
2091 * (with startup time between trigger and start of sampling).
2092 * This feature can be combined with low power mode "auto wait".
2093 * @note With ADC low power mode "auto wait", the ADC conversion data read
2094 * is corresponding to previous ADC conversion start, independently
2095 * of delay during which ADC was idle.
2096 * Therefore, the ADC conversion data may be outdated: does not
2097 * correspond to the current voltage level on the selected
2098 * ADC channel.
2099 * @rmtoll CFGR1 WAIT LL_ADC_GetLowPowerMode\n
2100 * CFGR1 AUTOFF LL_ADC_GetLowPowerMode
2101 * @param ADCx ADC instance
2102 * @retval Returned value can be one of the following values:
2103 * @arg @ref LL_ADC_LP_MODE_NONE
2104 * @arg @ref LL_ADC_LP_AUTOWAIT
2105 * @arg @ref LL_ADC_LP_AUTOPOWEROFF
2106 * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
2107 */
LL_ADC_GetLowPowerMode(ADC_TypeDef * ADCx)2108 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
2109 {
2110 return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)));
2111 }
2112
2113 /**
2114 * @brief Set sampling time common to a group of channels.
2115 * @note Unit: ADC clock cycles.
2116 * @note On this STM32 series, sampling time scope is on ADC instance:
2117 * Sampling time common to all channels.
2118 * (on some other STM32 families, sampling time is channel wise)
2119 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
2120 * converted:
2121 * sampling time constraints must be respected (sampling time can be
2122 * adjusted in function of ADC clock frequency and sampling time
2123 * setting).
2124 * Refer to device datasheet for timings values (parameters TS_vrefint,
2125 * TS_temp, ...).
2126 * @note Conversion time is the addition of sampling time and processing time.
2127 * On this STM32 series, ADC processing time is:
2128 * - 12.5 ADC clock cycles at ADC resolution 12 bits
2129 * - 10.5 ADC clock cycles at ADC resolution 10 bits
2130 * - 8.5 ADC clock cycles at ADC resolution 8 bits
2131 * - 6.5 ADC clock cycles at ADC resolution 6 bits
2132 * @note In case of ADC conversion of internal channel (VrefInt,
2133 * temperature sensor, ...), a sampling time minimum value
2134 * is required.
2135 * Refer to device datasheet.
2136 * @note On this STM32 series, setting of this feature is conditioned to
2137 * ADC state:
2138 * ADC must be disabled or enabled without conversion on going
2139 * on group regular.
2140 * @rmtoll SMPR SMP LL_ADC_SetSamplingTimeCommonChannels
2141 * @param ADCx ADC instance
2142 * @param SamplingTime This parameter can be one of the following values:
2143 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
2144 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
2145 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
2146 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
2147 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
2148 * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
2149 * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
2150 * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
2151 * @retval None
2152 */
LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef * ADCx,uint32_t SamplingTime)2153 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTime)
2154 {
2155 MODIFY_REG(ADCx->SMPR, ADC_SMPR_SMP, SamplingTime);
2156 }
2157
2158 /**
2159 * @brief Get sampling time common to a group of channels.
2160 * @note Unit: ADC clock cycles.
2161 * @note On this STM32 series, sampling time scope is on ADC instance:
2162 * Sampling time common to all channels.
2163 * (on some other STM32 families, sampling time is channel wise)
2164 * @note Conversion time is the addition of sampling time and processing time.
2165 * Refer to reference manual for ADC processing time of
2166 * this STM32 series.
2167 * @rmtoll SMPR SMP LL_ADC_GetSamplingTimeCommonChannels
2168 * @param ADCx ADC instance
2169 * @retval Returned value can be one of the following values:
2170 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
2171 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
2172 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
2173 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
2174 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
2175 * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
2176 * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
2177 * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
2178 */
LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef * ADCx)2179 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx)
2180 {
2181 return (uint32_t)(READ_BIT(ADCx->SMPR, ADC_SMPR_SMP));
2182 }
2183
2184 /**
2185 * @}
2186 */
2187
2188 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
2189 * @{
2190 */
2191
2192 /**
2193 * @brief Set ADC group regular conversion trigger source:
2194 * internal (SW start) or from external peripheral (timer event,
2195 * external interrupt line).
2196 * @note On this STM32 series, setting trigger source to external trigger
2197 * also set trigger polarity to rising edge
2198 * (default setting for compatibility with some ADC on other
2199 * STM32 families having this setting set by HW default value).
2200 * In case of need to modify trigger edge, use
2201 * function @ref LL_ADC_REG_SetTriggerEdge().
2202 * @note Availability of parameters of trigger sources from timer
2203 * depends on timers availability on the selected device.
2204 * @note On this STM32 series, setting of this feature is conditioned to
2205 * ADC state:
2206 * ADC must be disabled or enabled without conversion on going
2207 * on group regular.
2208 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n
2209 * CFGR1 EXTEN LL_ADC_REG_SetTriggerSource
2210 * @param ADCx ADC instance
2211 * @param TriggerSource This parameter can be one of the following values:
2212 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2213 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
2214 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM21_CH2
2215 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2216 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
2217 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM22_TRGO
2218 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (*)
2219 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2220 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2221 *
2222 * (*) value not defined in all devices
2223 * @retval None
2224 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)2225 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2226 {
2227 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
2228 }
2229
2230 /**
2231 * @brief Get ADC group regular conversion trigger source:
2232 * internal (SW start) or from external peripheral (timer event,
2233 * external interrupt line).
2234 * @note To determine whether group regular trigger source is
2235 * internal (SW start) or external, without detail
2236 * of which peripheral is selected as external trigger,
2237 * (equivalent to
2238 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
2239 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
2240 * @note Availability of parameters of trigger sources from timer
2241 * depends on timers availability on the selected device.
2242 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n
2243 * CFGR1 EXTEN LL_ADC_REG_GetTriggerSource
2244 * @param ADCx ADC instance
2245 * @retval Returned value can be one of the following values:
2246 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2247 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
2248 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM21_CH2
2249 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2250 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
2251 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM22_TRGO
2252 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (*)
2253 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2254 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2255 *
2256 * (*) value not defined in all devices
2257 */
LL_ADC_REG_GetTriggerSource(ADC_TypeDef * ADCx)2258 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
2259 {
2260 uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
2261
2262 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2263 /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */
2264 uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
2265
2266 /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */
2267 /* to match with triggers literals definition. */
2268 return ((TriggerSource
2269 & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL)
2270 | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN)
2271 );
2272 }
2273
2274 /**
2275 * @brief Get ADC group regular conversion trigger source internal (SW start)
2276 or external.
2277 * @note In case of group regular trigger source set to external trigger,
2278 * to determine which peripheral is selected as external trigger,
2279 * use function @ref LL_ADC_REG_GetTriggerSource().
2280 * @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
2281 * @param ADCx ADC instance
2282 * @retval Value "0" if trigger source external trigger
2283 * Value "1" if trigger source SW start.
2284 */
LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)2285 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
2286 {
2287 return (READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN));
2288 }
2289
2290 /**
2291 * @brief Set ADC group regular conversion trigger polarity.
2292 * @note Applicable only for trigger source set to external trigger.
2293 * @note On this STM32 series, setting of this feature is conditioned to
2294 * ADC state:
2295 * ADC must be disabled or enabled without conversion on going
2296 * on group regular.
2297 * @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge
2298 * @param ADCx ADC instance
2299 * @param ExternalTriggerEdge This parameter can be one of the following values:
2300 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2301 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2302 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2303 * @retval None
2304 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)2305 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
2306 {
2307 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
2308 }
2309
2310 /**
2311 * @brief Get ADC group regular conversion trigger polarity.
2312 * @note Applicable only for trigger source set to external trigger.
2313 * @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge
2314 * @param ADCx ADC instance
2315 * @retval Returned value can be one of the following values:
2316 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2317 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2318 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2319 */
LL_ADC_REG_GetTriggerEdge(ADC_TypeDef * ADCx)2320 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
2321 {
2322 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
2323 }
2324
2325
2326 /**
2327 * @brief Set ADC group regular sequencer scan direction.
2328 * @note On some other STM32 families, this setting is not available and
2329 * the default scan direction is forward.
2330 * @note On this STM32 series, setting of this feature is conditioned to
2331 * ADC state:
2332 * ADC must be disabled or enabled without conversion on going
2333 * on group regular.
2334 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection
2335 * @param ADCx ADC instance
2336 * @param ScanDirection This parameter can be one of the following values:
2337 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
2338 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
2339 * @retval None
2340 */
LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef * ADCx,uint32_t ScanDirection)2341 __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
2342 {
2343 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);
2344 }
2345
2346 /**
2347 * @brief Get ADC group regular sequencer scan direction.
2348 * @note On some other STM32 families, this setting is not available and
2349 * the default scan direction is forward.
2350 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection
2351 * @param ADCx ADC instance
2352 * @retval Returned value can be one of the following values:
2353 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
2354 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
2355 */
LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef * ADCx)2356 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx)
2357 {
2358 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));
2359 }
2360
2361 /**
2362 * @brief Set ADC group regular sequencer discontinuous mode:
2363 * sequence subdivided and scan conversions interrupted every selected
2364 * number of ranks.
2365 * @note It is not possible to enable both ADC group regular
2366 * continuous mode and sequencer discontinuous mode.
2367 * @note On this STM32 series, setting of this feature is conditioned to
2368 * ADC state:
2369 * ADC must be disabled or enabled without conversion on going
2370 * on group regular.
2371 * @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
2372 * @param ADCx ADC instance
2373 * @param SeqDiscont This parameter can be one of the following values:
2374 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2375 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2376 * @retval None
2377 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)2378 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2379 {
2380 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
2381 }
2382
2383 /**
2384 * @brief Get ADC group regular sequencer discontinuous mode:
2385 * sequence subdivided and scan conversions interrupted every selected
2386 * number of ranks.
2387 * @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
2388 * @param ADCx ADC instance
2389 * @retval Returned value can be one of the following values:
2390 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2391 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2392 */
LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef * ADCx)2393 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
2394 {
2395 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
2396 }
2397
2398 /**
2399 * @brief Set ADC group regular sequence: channel on rank corresponding to
2400 * channel number.
2401 * @note This function performs:
2402 * - Channels ordering into each rank of scan sequence:
2403 * rank of each channel is fixed by channel HW number
2404 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2405 * - Set channels selected by overwriting the current sequencer
2406 * configuration.
2407 * @note On this STM32 series, ADC group regular sequencer is
2408 * not fully configurable: sequencer length and each rank
2409 * affectation to a channel are fixed by channel HW number.
2410 * @note Depending on devices and packages, some channels may not be available.
2411 * Refer to device datasheet for channels availability.
2412 * @note On this STM32 series, to measure internal channels (VrefInt,
2413 * TempSensor, ...), measurement paths to internal channels must be
2414 * enabled separately.
2415 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2416 * @note On this STM32 series, setting of this feature is conditioned to
2417 * ADC state:
2418 * ADC must be disabled or enabled without conversion on going
2419 * on group regular.
2420 * @note One or several values can be selected.
2421 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
2422 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n
2423 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n
2424 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n
2425 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n
2426 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n
2427 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n
2428 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n
2429 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n
2430 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n
2431 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n
2432 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n
2433 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n
2434 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n
2435 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n
2436 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n
2437 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n
2438 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n
2439 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n
2440 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels
2441 * @param ADCx ADC instance
2442 * @param Channel This parameter can be a combination of the following values:
2443 * @arg @ref LL_ADC_CHANNEL_0
2444 * @arg @ref LL_ADC_CHANNEL_1
2445 * @arg @ref LL_ADC_CHANNEL_2
2446 * @arg @ref LL_ADC_CHANNEL_3
2447 * @arg @ref LL_ADC_CHANNEL_4
2448 * @arg @ref LL_ADC_CHANNEL_5
2449 * @arg @ref LL_ADC_CHANNEL_6
2450 * @arg @ref LL_ADC_CHANNEL_7
2451 * @arg @ref LL_ADC_CHANNEL_8
2452 * @arg @ref LL_ADC_CHANNEL_9
2453 * @arg @ref LL_ADC_CHANNEL_10
2454 * @arg @ref LL_ADC_CHANNEL_11
2455 * @arg @ref LL_ADC_CHANNEL_12
2456 * @arg @ref LL_ADC_CHANNEL_13
2457 * @arg @ref LL_ADC_CHANNEL_14
2458 * @arg @ref LL_ADC_CHANNEL_15
2459 * @arg @ref LL_ADC_CHANNEL_16 (1)
2460 * @arg @ref LL_ADC_CHANNEL_17
2461 * @arg @ref LL_ADC_CHANNEL_18
2462 * @arg @ref LL_ADC_CHANNEL_VREFINT
2463 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
2464 * @arg @ref LL_ADC_CHANNEL_VLCD (1)
2465 *
2466 * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
2467 * @retval None
2468 */
LL_ADC_REG_SetSequencerChannels(ADC_TypeDef * ADCx,uint32_t Channel)2469 __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
2470 {
2471 /* Parameter "Channel" is used with masks because containing */
2472 /* other bits reserved for other purpose. */
2473 WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
2474 }
2475
2476 /**
2477 * @brief Add channel to ADC group regular sequence: channel on rank corresponding to
2478 * channel number.
2479 * @note This function performs:
2480 * - Channels ordering into each rank of scan sequence:
2481 * rank of each channel is fixed by channel HW number
2482 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2483 * - Set channels selected by adding them to the current sequencer
2484 * configuration.
2485 * @note On this STM32 series, ADC group regular sequencer is
2486 * not fully configurable: sequencer length and each rank
2487 * affectation to a channel are fixed by channel HW number.
2488 * @note Depending on devices and packages, some channels may not be available.
2489 * Refer to device datasheet for channels availability.
2490 * @note On this STM32 series, to measure internal channels (VrefInt,
2491 * TempSensor, ...), measurement paths to internal channels must be
2492 * enabled separately.
2493 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2494 * @note On this STM32 series, setting of this feature is conditioned to
2495 * ADC state:
2496 * ADC must be disabled or enabled without conversion on going
2497 * on group regular.
2498 * @note One or several values can be selected.
2499 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
2500 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n
2501 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n
2502 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n
2503 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n
2504 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n
2505 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n
2506 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n
2507 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n
2508 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n
2509 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n
2510 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n
2511 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n
2512 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n
2513 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n
2514 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n
2515 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n
2516 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n
2517 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n
2518 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd
2519 * @param ADCx ADC instance
2520 * @param Channel This parameter can be a combination of the following values:
2521 * @arg @ref LL_ADC_CHANNEL_0
2522 * @arg @ref LL_ADC_CHANNEL_1
2523 * @arg @ref LL_ADC_CHANNEL_2
2524 * @arg @ref LL_ADC_CHANNEL_3
2525 * @arg @ref LL_ADC_CHANNEL_4
2526 * @arg @ref LL_ADC_CHANNEL_5
2527 * @arg @ref LL_ADC_CHANNEL_6
2528 * @arg @ref LL_ADC_CHANNEL_7
2529 * @arg @ref LL_ADC_CHANNEL_8
2530 * @arg @ref LL_ADC_CHANNEL_9
2531 * @arg @ref LL_ADC_CHANNEL_10
2532 * @arg @ref LL_ADC_CHANNEL_11
2533 * @arg @ref LL_ADC_CHANNEL_12
2534 * @arg @ref LL_ADC_CHANNEL_13
2535 * @arg @ref LL_ADC_CHANNEL_14
2536 * @arg @ref LL_ADC_CHANNEL_15
2537 * @arg @ref LL_ADC_CHANNEL_16 (1)
2538 * @arg @ref LL_ADC_CHANNEL_17
2539 * @arg @ref LL_ADC_CHANNEL_18
2540 * @arg @ref LL_ADC_CHANNEL_VREFINT
2541 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
2542 * @arg @ref LL_ADC_CHANNEL_VLCD (1)
2543 *
2544 * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
2545 * @retval None
2546 */
LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef * ADCx,uint32_t Channel)2547 __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
2548 {
2549 /* Parameter "Channel" is used with masks because containing */
2550 /* other bits reserved for other purpose. */
2551 SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
2552 }
2553
2554 /**
2555 * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to
2556 * channel number.
2557 * @note This function performs:
2558 * - Channels ordering into each rank of scan sequence:
2559 * rank of each channel is fixed by channel HW number
2560 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2561 * - Set channels selected by removing them to the current sequencer
2562 * configuration.
2563 * @note On this STM32 series, ADC group regular sequencer is
2564 * not fully configurable: sequencer length and each rank
2565 * affectation to a channel are fixed by channel HW number.
2566 * @note Depending on devices and packages, some channels may not be available.
2567 * Refer to device datasheet for channels availability.
2568 * @note On this STM32 series, to measure internal channels (VrefInt,
2569 * TempSensor, ...), measurement paths to internal channels must be
2570 * enabled separately.
2571 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2572 * @note On this STM32 series, setting of this feature is conditioned to
2573 * ADC state:
2574 * ADC must be disabled or enabled without conversion on going
2575 * on group regular.
2576 * @note One or several values can be selected.
2577 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
2578 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n
2579 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n
2580 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n
2581 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n
2582 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n
2583 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n
2584 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n
2585 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n
2586 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n
2587 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n
2588 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n
2589 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n
2590 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n
2591 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n
2592 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n
2593 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n
2594 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n
2595 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n
2596 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem
2597 * @param ADCx ADC instance
2598 * @param Channel This parameter can be a combination of the following values:
2599 * @arg @ref LL_ADC_CHANNEL_0
2600 * @arg @ref LL_ADC_CHANNEL_1
2601 * @arg @ref LL_ADC_CHANNEL_2
2602 * @arg @ref LL_ADC_CHANNEL_3
2603 * @arg @ref LL_ADC_CHANNEL_4
2604 * @arg @ref LL_ADC_CHANNEL_5
2605 * @arg @ref LL_ADC_CHANNEL_6
2606 * @arg @ref LL_ADC_CHANNEL_7
2607 * @arg @ref LL_ADC_CHANNEL_8
2608 * @arg @ref LL_ADC_CHANNEL_9
2609 * @arg @ref LL_ADC_CHANNEL_10
2610 * @arg @ref LL_ADC_CHANNEL_11
2611 * @arg @ref LL_ADC_CHANNEL_12
2612 * @arg @ref LL_ADC_CHANNEL_13
2613 * @arg @ref LL_ADC_CHANNEL_14
2614 * @arg @ref LL_ADC_CHANNEL_15
2615 * @arg @ref LL_ADC_CHANNEL_16 (1)
2616 * @arg @ref LL_ADC_CHANNEL_17
2617 * @arg @ref LL_ADC_CHANNEL_18
2618 * @arg @ref LL_ADC_CHANNEL_VREFINT
2619 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
2620 * @arg @ref LL_ADC_CHANNEL_VLCD (1)
2621 *
2622 * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
2623 * @retval None
2624 */
LL_ADC_REG_SetSequencerChRem(ADC_TypeDef * ADCx,uint32_t Channel)2625 __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
2626 {
2627 /* Parameter "Channel" is used with masks because containing */
2628 /* other bits reserved for other purpose. */
2629 CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
2630 }
2631
2632 /**
2633 * @brief Get ADC group regular sequence: channel on rank corresponding to
2634 * channel number.
2635 * @note This function performs:
2636 * - Channels order reading into each rank of scan sequence:
2637 * rank of each channel is fixed by channel HW number
2638 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2639 * @note On this STM32 series, ADC group regular sequencer is
2640 * not fully configurable: sequencer length and each rank
2641 * affectation to a channel are fixed by channel HW number.
2642 * @note Depending on devices and packages, some channels may not be available.
2643 * Refer to device datasheet for channels availability.
2644 * @note On this STM32 series, to measure internal channels (VrefInt,
2645 * TempSensor, ...), measurement paths to internal channels must be
2646 * enabled separately.
2647 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2648 * @note On this STM32 series, setting of this feature is conditioned to
2649 * ADC state:
2650 * ADC must be disabled or enabled without conversion on going
2651 * on group regular.
2652 * @note One or several values can be retrieved.
2653 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
2654 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n
2655 * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n
2656 * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n
2657 * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n
2658 * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n
2659 * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n
2660 * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n
2661 * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n
2662 * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n
2663 * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n
2664 * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n
2665 * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n
2666 * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n
2667 * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n
2668 * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n
2669 * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n
2670 * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n
2671 * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n
2672 * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels
2673 * @param ADCx ADC instance
2674 * @retval Returned value can be a combination of the following values:
2675 * @arg @ref LL_ADC_CHANNEL_0
2676 * @arg @ref LL_ADC_CHANNEL_1
2677 * @arg @ref LL_ADC_CHANNEL_2
2678 * @arg @ref LL_ADC_CHANNEL_3
2679 * @arg @ref LL_ADC_CHANNEL_4
2680 * @arg @ref LL_ADC_CHANNEL_5
2681 * @arg @ref LL_ADC_CHANNEL_6
2682 * @arg @ref LL_ADC_CHANNEL_7
2683 * @arg @ref LL_ADC_CHANNEL_8
2684 * @arg @ref LL_ADC_CHANNEL_9
2685 * @arg @ref LL_ADC_CHANNEL_10
2686 * @arg @ref LL_ADC_CHANNEL_11
2687 * @arg @ref LL_ADC_CHANNEL_12
2688 * @arg @ref LL_ADC_CHANNEL_13
2689 * @arg @ref LL_ADC_CHANNEL_14
2690 * @arg @ref LL_ADC_CHANNEL_15
2691 * @arg @ref LL_ADC_CHANNEL_16 (1)
2692 * @arg @ref LL_ADC_CHANNEL_17
2693 * @arg @ref LL_ADC_CHANNEL_18
2694 * @arg @ref LL_ADC_CHANNEL_VREFINT
2695 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
2696 * @arg @ref LL_ADC_CHANNEL_VLCD (1)
2697 *
2698 * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
2699 */
LL_ADC_REG_GetSequencerChannels(ADC_TypeDef * ADCx)2700 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx)
2701 {
2702 uint32_t ChannelsBitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
2703
2704 return ((((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
2705 | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
2706 | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
2707 | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
2708 | (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
2709 | (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
2710 | (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
2711 | (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
2712 | (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
2713 | (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
2714 | (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
2715 | (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
2716 | (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
2717 | (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
2718 | (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
2719 | (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
2720 #if defined(ADC_CCR_VLCDEN)
2721 | (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
2722 #endif
2723 | (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
2724 | (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
2725 );
2726 }
2727 /**
2728 * @brief Set ADC continuous conversion mode on ADC group regular.
2729 * @note Description of ADC continuous conversion mode:
2730 * - single mode: one conversion per trigger
2731 * - continuous mode: after the first trigger, following
2732 * conversions launched successively automatically.
2733 * @note It is not possible to enable both ADC group regular
2734 * continuous mode and sequencer discontinuous mode.
2735 * @note On this STM32 series, setting of this feature is conditioned to
2736 * ADC state:
2737 * ADC must be disabled or enabled without conversion on going
2738 * on group regular.
2739 * @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode
2740 * @param ADCx ADC instance
2741 * @param Continuous This parameter can be one of the following values:
2742 * @arg @ref LL_ADC_REG_CONV_SINGLE
2743 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2744 * @retval None
2745 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)2746 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
2747 {
2748 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
2749 }
2750
2751 /**
2752 * @brief Get ADC continuous conversion mode on ADC group regular.
2753 * @note Description of ADC continuous conversion mode:
2754 * - single mode: one conversion per trigger
2755 * - continuous mode: after the first trigger, following
2756 * conversions launched successively automatically.
2757 * @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode
2758 * @param ADCx ADC instance
2759 * @retval Returned value can be one of the following values:
2760 * @arg @ref LL_ADC_REG_CONV_SINGLE
2761 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2762 */
LL_ADC_REG_GetContinuousMode(ADC_TypeDef * ADCx)2763 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
2764 {
2765 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
2766 }
2767
2768 /**
2769 * @brief Set ADC group regular conversion data transfer: no transfer or
2770 * transfer by DMA, and DMA requests mode.
2771 * @note If transfer by DMA selected, specifies the DMA requests
2772 * mode:
2773 * - Limited mode (One shot mode): DMA transfer requests are stopped
2774 * when number of DMA data transfers (number of
2775 * ADC conversions) is reached.
2776 * This ADC mode is intended to be used with DMA mode non-circular.
2777 * - Unlimited mode: DMA transfer requests are unlimited,
2778 * whatever number of DMA data transfers (number of
2779 * ADC conversions).
2780 * This ADC mode is intended to be used with DMA mode circular.
2781 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2782 * mode non-circular:
2783 * when DMA transfers size will be reached, DMA will stop transfers of
2784 * ADC conversions data ADC will raise an overrun error
2785 * (overrun flag and interruption if enabled).
2786 * @note To configure DMA source address (peripheral address),
2787 * use function @ref LL_ADC_DMA_GetRegAddr().
2788 * @note On this STM32 series, setting of this feature is conditioned to
2789 * ADC state:
2790 * ADC must be disabled or enabled without conversion on going
2791 * on group regular.
2792 * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n
2793 * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer
2794 * @param ADCx ADC instance
2795 * @param DMATransfer This parameter can be one of the following values:
2796 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2797 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
2798 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2799 * @retval None
2800 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)2801 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
2802 {
2803 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer);
2804 }
2805
2806 /**
2807 * @brief Get ADC group regular conversion data transfer: no transfer or
2808 * transfer by DMA, and DMA requests mode.
2809 * @note If transfer by DMA selected, specifies the DMA requests
2810 * mode:
2811 * - Limited mode (One shot mode): DMA transfer requests are stopped
2812 * when number of DMA data transfers (number of
2813 * ADC conversions) is reached.
2814 * This ADC mode is intended to be used with DMA mode non-circular.
2815 * - Unlimited mode: DMA transfer requests are unlimited,
2816 * whatever number of DMA data transfers (number of
2817 * ADC conversions).
2818 * This ADC mode is intended to be used with DMA mode circular.
2819 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2820 * mode non-circular:
2821 * when DMA transfers size will be reached, DMA will stop transfers of
2822 * ADC conversions data ADC will raise an overrun error
2823 * (overrun flag and interruption if enabled).
2824 * @note To configure DMA source address (peripheral address),
2825 * use function @ref LL_ADC_DMA_GetRegAddr().
2826 * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n
2827 * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer
2828 * @param ADCx ADC instance
2829 * @retval Returned value can be one of the following values:
2830 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2831 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
2832 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2833 */
LL_ADC_REG_GetDMATransfer(ADC_TypeDef * ADCx)2834 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
2835 {
2836 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));
2837 }
2838
2839 /**
2840 * @brief Set ADC group regular behavior in case of overrun:
2841 * data preserved or overwritten.
2842 * @note Compatibility with devices without feature overrun:
2843 * other devices without this feature have a behavior
2844 * equivalent to data overwritten.
2845 * The default setting of overrun is data preserved.
2846 * Therefore, for compatibility with all devices, parameter
2847 * overrun should be set to data overwritten.
2848 * @note On this STM32 series, setting of this feature is conditioned to
2849 * ADC state:
2850 * ADC must be disabled or enabled without conversion on going
2851 * on group regular.
2852 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun
2853 * @param ADCx ADC instance
2854 * @param Overrun This parameter can be one of the following values:
2855 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
2856 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
2857 * @retval None
2858 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)2859 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
2860 {
2861 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
2862 }
2863
2864 /**
2865 * @brief Get ADC group regular behavior in case of overrun:
2866 * data preserved or overwritten.
2867 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun
2868 * @param ADCx ADC instance
2869 * @retval Returned value can be one of the following values:
2870 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
2871 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
2872 */
LL_ADC_REG_GetOverrun(ADC_TypeDef * ADCx)2873 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
2874 {
2875 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
2876 }
2877
2878 /**
2879 * @}
2880 */
2881
2882
2883 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
2884 * @{
2885 */
2886
2887 /**
2888 * @brief Set ADC analog watchdog monitored channels:
2889 * a single channel or all channels,
2890 * on ADC group regular.
2891 * @note Once monitored channels are selected, analog watchdog
2892 * is enabled.
2893 * @note In case of need to define a single channel to monitor
2894 * with analog watchdog from sequencer channel definition,
2895 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
2896 * @note On this STM32 series, there is only 1 kind of analog watchdog
2897 * instance:
2898 * - AWD standard (instance AWD1):
2899 * - channels monitored: can monitor 1 channel or all channels.
2900 * - groups monitored: ADC group regular.
2901 * - resolution: resolution is not limited (corresponds to
2902 * ADC resolution configured).
2903 * @note On this STM32 series, setting of this feature is conditioned to
2904 * ADC state:
2905 * ADC must be disabled or enabled without conversion on going
2906 * on group regular.
2907 * @rmtoll CFGR1 AWDCH LL_ADC_SetAnalogWDMonitChannels\n
2908 * CFGR1 AWDSGL LL_ADC_SetAnalogWDMonitChannels\n
2909 * CFGR1 AWDEN LL_ADC_SetAnalogWDMonitChannels
2910 * @param ADCx ADC instance
2911 * @param AWDChannelGroup This parameter can be one of the following values:
2912 * @arg @ref LL_ADC_AWD_DISABLE
2913 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
2914 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
2915 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
2916 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
2917 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
2918 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
2919 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
2920 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
2921 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
2922 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
2923 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
2924 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
2925 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
2926 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
2927 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
2928 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
2929 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
2930 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (1)
2931 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
2932 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
2933 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
2934 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
2935 * @arg @ref LL_ADC_AWD_CH_VLCD_REG (1)
2936 *
2937 * (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
2938 * @retval None
2939 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDChannelGroup)2940 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
2941 {
2942 MODIFY_REG(ADCx->CFGR1,
2943 (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN),
2944 (AWDChannelGroup & ADC_AWD_CR_ALL_CHANNEL_MASK));
2945 }
2946
2947 /**
2948 * @brief Get ADC analog watchdog monitored channel.
2949 * @note Usage of the returned channel number:
2950 * - To reinject this channel into another function LL_ADC_xxx:
2951 * the returned channel number is only partly formatted on definition
2952 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2953 * with parts of literals LL_ADC_CHANNEL_x or using
2954 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2955 * Then the selected literal LL_ADC_CHANNEL_x can be used
2956 * as parameter for another function.
2957 * - To get the channel number in decimal format:
2958 * process the returned value with the helper macro
2959 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2960 * Applicable only when the analog watchdog is set to monitor
2961 * one channel.
2962 * @note On this STM32 series, there is only 1 kind of analog watchdog
2963 * instance:
2964 * - AWD standard (instance AWD1):
2965 * - channels monitored: can monitor 1 channel or all channels.
2966 * - groups monitored: ADC group regular.
2967 * - resolution: resolution is not limited (corresponds to
2968 * ADC resolution configured).
2969 * @note On this STM32 series, setting of this feature is conditioned to
2970 * ADC state:
2971 * ADC must be disabled or enabled without conversion on going
2972 * on group regular.
2973 * @rmtoll CFGR1 AWDCH LL_ADC_GetAnalogWDMonitChannels\n
2974 * CFGR1 AWDSGL LL_ADC_GetAnalogWDMonitChannels\n
2975 * CFGR1 AWDEN LL_ADC_GetAnalogWDMonitChannels
2976 * @param ADCx ADC instance
2977 * @retval Returned value can be one of the following values:
2978 * @arg @ref LL_ADC_AWD_DISABLE
2979 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
2980 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
2981 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
2982 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
2983 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
2984 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
2985 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
2986 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
2987 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
2988 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
2989 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
2990 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
2991 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
2992 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
2993 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
2994 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
2995 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
2996 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
2997 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
2998 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
2999 */
LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef * ADCx)3000 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
3001 {
3002 uint32_t AWDChannelGroup = READ_BIT(ADCx->CFGR1, (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN));
3003
3004 /* Note: Set variable according to channel definition including channel ID */
3005 /* with bitfield. */
3006 uint32_t AWDChannelSingle = ((AWDChannelGroup & ADC_CFGR1_AWDSGL) >> ADC_CFGR1_AWDSGL_BITOFFSET_POS);
3007 uint32_t AWDChannelBitField = (ADC_CHANNEL_0_BITFIELD << ((AWDChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS));
3008
3009 return (AWDChannelGroup | (AWDChannelBitField * AWDChannelSingle));
3010 }
3011
3012 /**
3013 * @brief Set ADC analog watchdog thresholds value of both thresholds
3014 * high and low.
3015 * @note If value of only one threshold high or low must be set,
3016 * use function @ref LL_ADC_SetAnalogWDThresholds().
3017 * @note In case of ADC resolution different of 12 bits,
3018 * analog watchdog thresholds data require a specific shift.
3019 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
3020 * @note On this STM32 series, there is only 1 kind of analog watchdog
3021 * instance:
3022 * - AWD standard (instance AWD1):
3023 * - channels monitored: can monitor 1 channel or all channels.
3024 * - groups monitored: ADC group regular.
3025 * - resolution: resolution is not limited (corresponds to
3026 * ADC resolution configured).
3027 * @note On this STM32 series, setting of this feature is conditioned to
3028 * ADC state:
3029 * ADC must be disabled or enabled without conversion on going
3030 * on group regular.
3031 * @rmtoll TR HT LL_ADC_ConfigAnalogWDThresholds\n
3032 * TR LT LL_ADC_ConfigAnalogWDThresholds
3033 * @param ADCx ADC instance
3034 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
3035 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
3036 * @retval None
3037 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)3038 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
3039 {
3040 MODIFY_REG(ADCx->TR,
3041 ADC_TR_HT | ADC_TR_LT,
3042 (AWDThresholdHighValue << ADC_TR_HT_BITOFFSET_POS) | AWDThresholdLowValue);
3043 }
3044
3045 /**
3046 * @brief Set ADC analog watchdog threshold value of threshold
3047 * high or low.
3048 * @note If values of both thresholds high or low must be set,
3049 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
3050 * @note In case of ADC resolution different of 12 bits,
3051 * analog watchdog thresholds data require a specific shift.
3052 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
3053 * @note On this STM32 series, there is only 1 kind of analog watchdog
3054 * instance:
3055 * - AWD standard (instance AWD1):
3056 * - channels monitored: can monitor 1 channel or all channels.
3057 * - groups monitored: ADC group regular.
3058 * - resolution: resolution is not limited (corresponds to
3059 * ADC resolution configured).
3060 * @note On this STM32 series, setting of this feature is conditioned to
3061 * ADC state:
3062 * ADC must be disabled or enabled without conversion on going
3063 * on group regular.
3064 * @rmtoll TR HT LL_ADC_SetAnalogWDThresholds\n
3065 * TR LT LL_ADC_SetAnalogWDThresholds
3066 * @param ADCx ADC instance
3067 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3068 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3069 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3070 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
3071 * @retval None
3072 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)3073 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
3074 {
3075 /* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010" */
3076 /* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold */
3077 /* high is selected, then data is shifted to LSB. Else(threshold low), */
3078 /* data is not shifted. */
3079 MODIFY_REG(ADCx->TR,
3080 AWDThresholdsHighLow,
3081 AWDThresholdValue << ((AWDThresholdsHighLow >> ADC_TR_HT_BITOFFSET_POS) & ((uint32_t)0x00000010U)));
3082 }
3083
3084 /**
3085 * @brief Get ADC analog watchdog threshold value of threshold high,
3086 * threshold low or raw data with ADC thresholds high and low
3087 * concatenated.
3088 * @note If raw data with ADC thresholds high and low is retrieved,
3089 * the data of each threshold high or low can be isolated
3090 * using helper macro:
3091 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
3092 * @note In case of ADC resolution different of 12 bits,
3093 * analog watchdog thresholds data require a specific shift.
3094 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
3095 * @rmtoll TR HT LL_ADC_GetAnalogWDThresholds\n
3096 * TR LT LL_ADC_GetAnalogWDThresholds
3097 * @param ADCx ADC instance
3098 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3099 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3100 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3101 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
3102 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3103 */
LL_ADC_GetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDThresholdsHighLow)3104 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
3105 {
3106 /* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010" */
3107 /* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold */
3108 /* high is selected, then data is shifted to LSB. Else(threshold low or */
3109 /* both thresholds), data is not shifted. */
3110 return (uint32_t)(READ_BIT(ADCx->TR,
3111 (AWDThresholdsHighLow | ADC_TR_LT))
3112 >> ((~AWDThresholdsHighLow) & (0x00000010U))
3113 );
3114 }
3115
3116 /**
3117 * @}
3118 */
3119
3120 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
3121 * @{
3122 */
3123
3124 /**
3125 * @brief Set ADC oversampling scope.
3126 * @note On this STM32 series, setting of this feature is conditioned to
3127 * ADC state:
3128 * ADC must be disabled or enabled without conversion on going
3129 * on group regular.
3130 * @rmtoll CFGR2 OVSE LL_ADC_SetOverSamplingScope
3131 * @param ADCx ADC instance
3132 * @param OvsScope This parameter can be one of the following values:
3133 * @arg @ref LL_ADC_OVS_DISABLE
3134 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
3135 * @retval None
3136 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)3137 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
3138 {
3139 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope);
3140 }
3141
3142 /**
3143 * @brief Get ADC oversampling scope.
3144 * @rmtoll CFGR2 OVSE LL_ADC_GetOverSamplingScope
3145 * @param ADCx ADC instance
3146 * @retval Returned value can be one of the following values:
3147 * @arg @ref LL_ADC_OVS_DISABLE
3148 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
3149 */
LL_ADC_GetOverSamplingScope(ADC_TypeDef * ADCx)3150 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
3151 {
3152 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE));
3153 }
3154
3155 /**
3156 * @brief Set ADC oversampling discontinuous mode (triggered mode)
3157 * on the selected ADC group.
3158 * @note Number of oversampled conversions are done either in:
3159 * - continuous mode (all conversions of oversampling ratio
3160 * are done from 1 trigger)
3161 * - discontinuous mode (each conversion of oversampling ratio
3162 * needs a trigger)
3163 * @note On this STM32 series, setting of this feature is conditioned to
3164 * ADC state:
3165 * ADC must be disabled or enabled without conversion on going
3166 * on group regular.
3167 * @rmtoll CFGR2 TOVS LL_ADC_SetOverSamplingDiscont
3168 * @param ADCx ADC instance
3169 * @param OverSamplingDiscont This parameter can be one of the following values:
3170 * @arg @ref LL_ADC_OVS_REG_CONT
3171 * @arg @ref LL_ADC_OVS_REG_DISCONT
3172 * @retval None
3173 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)3174 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
3175 {
3176 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont);
3177 }
3178
3179 /**
3180 * @brief Get ADC oversampling discontinuous mode (triggered mode)
3181 * on the selected ADC group.
3182 * @note Number of oversampled conversions are done either in:
3183 * - continuous mode (all conversions of oversampling ratio
3184 * are done from 1 trigger)
3185 * - discontinuous mode (each conversion of oversampling ratio
3186 * needs a trigger)
3187 * @rmtoll CFGR2 TOVS LL_ADC_GetOverSamplingDiscont
3188 * @param ADCx ADC instance
3189 * @retval Returned value can be one of the following values:
3190 * @arg @ref LL_ADC_OVS_REG_CONT
3191 * @arg @ref LL_ADC_OVS_REG_DISCONT
3192 */
LL_ADC_GetOverSamplingDiscont(ADC_TypeDef * ADCx)3193 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
3194 {
3195 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS));
3196 }
3197
3198 /**
3199 * @brief Set ADC oversampling
3200 * @note This function set the 2 items of oversampling configuration:
3201 * - ratio
3202 * - shift
3203 * @note On this STM32 series, setting of this feature is conditioned to
3204 * ADC state:
3205 * ADC must be disabled or enabled without conversion on going
3206 * on group regular.
3207 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
3208 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
3209 * @param ADCx ADC instance
3210 * @param Ratio This parameter can be one of the following values:
3211 * @arg @ref LL_ADC_OVS_RATIO_2
3212 * @arg @ref LL_ADC_OVS_RATIO_4
3213 * @arg @ref LL_ADC_OVS_RATIO_8
3214 * @arg @ref LL_ADC_OVS_RATIO_16
3215 * @arg @ref LL_ADC_OVS_RATIO_32
3216 * @arg @ref LL_ADC_OVS_RATIO_64
3217 * @arg @ref LL_ADC_OVS_RATIO_128
3218 * @arg @ref LL_ADC_OVS_RATIO_256
3219 * @param Shift This parameter can be one of the following values:
3220 * @arg @ref LL_ADC_OVS_SHIFT_NONE
3221 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
3222 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
3223 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
3224 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
3225 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
3226 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
3227 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
3228 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
3229 * @retval None
3230 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)3231 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
3232 {
3233 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
3234 }
3235
3236 /**
3237 * @brief Get ADC oversampling ratio
3238 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
3239 * @param ADCx ADC instance
3240 * @retval Ratio This parameter can be one of the following values:
3241 * @arg @ref LL_ADC_OVS_RATIO_2
3242 * @arg @ref LL_ADC_OVS_RATIO_4
3243 * @arg @ref LL_ADC_OVS_RATIO_8
3244 * @arg @ref LL_ADC_OVS_RATIO_16
3245 * @arg @ref LL_ADC_OVS_RATIO_32
3246 * @arg @ref LL_ADC_OVS_RATIO_64
3247 * @arg @ref LL_ADC_OVS_RATIO_128
3248 * @arg @ref LL_ADC_OVS_RATIO_256
3249 */
LL_ADC_GetOverSamplingRatio(ADC_TypeDef * ADCx)3250 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
3251 {
3252 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
3253 }
3254
3255 /**
3256 * @brief Get ADC oversampling shift
3257 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
3258 * @param ADCx ADC instance
3259 * @retval Shift This parameter can be one of the following values:
3260 * @arg @ref LL_ADC_OVS_SHIFT_NONE
3261 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
3262 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
3263 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
3264 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
3265 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
3266 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
3267 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
3268 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
3269 */
LL_ADC_GetOverSamplingShift(ADC_TypeDef * ADCx)3270 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
3271 {
3272 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
3273 }
3274
3275 /**
3276 * @}
3277 */
3278
3279 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
3280 * @{
3281 */
3282
3283 /**
3284 * @brief Enable ADC instance internal voltage regulator.
3285 * @note On this STM32 series, there are three possibilities to enable
3286 * the voltage regulator:
3287 * - by enabling it manually
3288 * using function @ref LL_ADC_EnableInternalRegulator().
3289 * - by launching a calibration
3290 * using function @ref LL_ADC_StartCalibration().
3291 * - by enabling the ADC
3292 * using function @ref LL_ADC_Enable().
3293 * @note On this STM32 series, after ADC internal voltage regulator enable,
3294 * a delay for ADC internal voltage regulator stabilization
3295 * is required before performing a ADC calibration or ADC enable.
3296 * Refer to device datasheet, parameter "tUP_LDO".
3297 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
3298 * @note On this STM32 series, setting of this feature is conditioned to
3299 * ADC state:
3300 * ADC must be ADC disabled.
3301 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
3302 * @param ADCx ADC instance
3303 * @retval None
3304 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)3305 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
3306 {
3307 /* Note: Write register with some additional bits forced to state reset */
3308 /* instead of modifying only the selected bit for this function, */
3309 /* to not interfere with bits with HW property "rs". */
3310 MODIFY_REG(ADCx->CR,
3311 ADC_CR_BITS_PROPERTY_RS,
3312 ADC_CR_ADVREGEN);
3313 }
3314
3315 /**
3316 * @brief Disable ADC internal voltage regulator.
3317 * @note On this STM32 series, setting of this feature is conditioned to
3318 * ADC state:
3319 * ADC must be ADC disabled.
3320 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
3321 * @param ADCx ADC instance
3322 * @retval None
3323 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)3324 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
3325 {
3326 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
3327 }
3328
3329 /**
3330 * @brief Get the selected ADC instance internal voltage regulator state.
3331 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
3332 * @param ADCx ADC instance
3333 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
3334 */
LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef * ADCx)3335 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
3336 {
3337 return (READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN));
3338 }
3339
3340 /**
3341 * @brief Enable the selected ADC instance.
3342 * @note On this STM32 series, after ADC enable, a delay for
3343 * ADC internal analog stabilization is required before performing a
3344 * ADC conversion start.
3345 * Refer to device datasheet, parameter tSTAB.
3346 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
3347 * is enabled and when conversion clock is active.
3348 * (not only core clock: this ADC has a dual clock domain)
3349 * @note On this STM32 series, setting of this feature is conditioned to
3350 * ADC state:
3351 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
3352 * @rmtoll CR ADEN LL_ADC_Enable
3353 * @param ADCx ADC instance
3354 * @retval None
3355 */
LL_ADC_Enable(ADC_TypeDef * ADCx)3356 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
3357 {
3358 /* Note: Write register with some additional bits forced to state reset */
3359 /* instead of modifying only the selected bit for this function, */
3360 /* to not interfere with bits with HW property "rs". */
3361 MODIFY_REG(ADCx->CR,
3362 ADC_CR_BITS_PROPERTY_RS,
3363 ADC_CR_ADEN);
3364 }
3365
3366 /**
3367 * @brief Disable the selected ADC instance.
3368 * @note On this STM32 series, setting of this feature is conditioned to
3369 * ADC state:
3370 * ADC must be not disabled. Must be enabled without conversion on going
3371 * on group regular.
3372 * @rmtoll CR ADDIS LL_ADC_Disable
3373 * @param ADCx ADC instance
3374 * @retval None
3375 */
LL_ADC_Disable(ADC_TypeDef * ADCx)3376 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
3377 {
3378 /* Note: Write register with some additional bits forced to state reset */
3379 /* instead of modifying only the selected bit for this function, */
3380 /* to not interfere with bits with HW property "rs". */
3381 MODIFY_REG(ADCx->CR,
3382 ADC_CR_BITS_PROPERTY_RS,
3383 ADC_CR_ADDIS);
3384 }
3385
3386 /**
3387 * @brief Get the selected ADC instance enable state.
3388 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
3389 * is enabled and when conversion clock is active.
3390 * (not only core clock: this ADC has a dual clock domain)
3391 * @rmtoll CR ADEN LL_ADC_IsEnabled
3392 * @param ADCx ADC instance
3393 * @retval 0: ADC is disabled, 1: ADC is enabled.
3394 */
LL_ADC_IsEnabled(ADC_TypeDef * ADCx)3395 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
3396 {
3397 return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN));
3398 }
3399
3400 /**
3401 * @brief Get the selected ADC instance disable state.
3402 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
3403 * @param ADCx ADC instance
3404 * @retval 0: no ADC disable command on going.
3405 */
LL_ADC_IsDisableOngoing(ADC_TypeDef * ADCx)3406 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
3407 {
3408 return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS));
3409 }
3410
3411 /**
3412 * @brief Start ADC calibration in the mode single-ended
3413 * or differential (for devices with differential mode available).
3414 * @note On this STM32 series, a minimum number of ADC clock cycles
3415 * are required between ADC end of calibration and ADC enable.
3416 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
3417 * @note In case of usage of ADC with DMA transfer:
3418 * On this STM32 series, ADC DMA transfer request should be disabled
3419 * during calibration:
3420 * Calibration factor is available in data register
3421 * and also transferred by DMA.
3422 * To not insert ADC calibration factor among ADC conversion data
3423 * in array variable, DMA transfer must be disabled during
3424 * calibration.
3425 * (DMA transfer setting backup and disable before calibration,
3426 * DMA transfer setting restore after calibration.
3427 * Refer to functions @ref LL_ADC_REG_GetDMATransfer(),
3428 * @ref LL_ADC_REG_SetDMATransfer() ).
3429 * @note On this STM32 series, setting of this feature is conditioned to
3430 * ADC state:
3431 * ADC must be ADC disabled.
3432 * @rmtoll CR ADCAL LL_ADC_StartCalibration
3433 * @param ADCx ADC instance
3434 * @retval None
3435 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx)3436 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
3437 {
3438 /* Note: Write register with some additional bits forced to state reset */
3439 /* instead of modifying only the selected bit for this function, */
3440 /* to not interfere with bits with HW property "rs". */
3441 MODIFY_REG(ADCx->CR,
3442 ADC_CR_BITS_PROPERTY_RS,
3443 ADC_CR_ADCAL);
3444 }
3445
3446 /**
3447 * @brief Get ADC calibration state.
3448 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
3449 * @param ADCx ADC instance
3450 * @retval 0: calibration complete, 1: calibration in progress.
3451 */
LL_ADC_IsCalibrationOnGoing(ADC_TypeDef * ADCx)3452 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
3453 {
3454 return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL));
3455 }
3456
3457 /**
3458 * @}
3459 */
3460
3461 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
3462 * @{
3463 */
3464
3465 /**
3466 * @brief Start ADC group regular conversion.
3467 * @note On this STM32 series, this function is relevant for both
3468 * internal trigger (SW start) and external trigger:
3469 * - If ADC trigger has been set to software start, ADC conversion
3470 * starts immediately.
3471 * - If ADC trigger has been set to external trigger, ADC conversion
3472 * will start at next trigger event (on the selected trigger edge)
3473 * following the ADC start conversion command.
3474 * @note On this STM32 series, setting of this feature is conditioned to
3475 * ADC state:
3476 * ADC must be enabled without conversion on going on group regular,
3477 * without conversion stop command on going on group regular,
3478 * without ADC disable command on going.
3479 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
3480 * @param ADCx ADC instance
3481 * @retval None
3482 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)3483 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
3484 {
3485 /* Note: Write register with some additional bits forced to state reset */
3486 /* instead of modifying only the selected bit for this function, */
3487 /* to not interfere with bits with HW property "rs". */
3488 MODIFY_REG(ADCx->CR,
3489 ADC_CR_BITS_PROPERTY_RS,
3490 ADC_CR_ADSTART);
3491 }
3492
3493 /**
3494 * @brief Stop ADC group regular conversion.
3495 * @note On this STM32 series, setting of this feature is conditioned to
3496 * ADC state:
3497 * ADC must be enabled with conversion on going on group regular,
3498 * without ADC disable command on going.
3499 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
3500 * @param ADCx ADC instance
3501 * @retval None
3502 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)3503 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
3504 {
3505 /* Note: Write register with some additional bits forced to state reset */
3506 /* instead of modifying only the selected bit for this function, */
3507 /* to not interfere with bits with HW property "rs". */
3508 MODIFY_REG(ADCx->CR,
3509 ADC_CR_BITS_PROPERTY_RS,
3510 ADC_CR_ADSTP);
3511 }
3512
3513 /**
3514 * @brief Get ADC group regular conversion state.
3515 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
3516 * @param ADCx ADC instance
3517 * @retval 0: no conversion is on going on ADC group regular.
3518 */
LL_ADC_REG_IsConversionOngoing(ADC_TypeDef * ADCx)3519 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
3520 {
3521 return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART));
3522 }
3523
3524 /**
3525 * @brief Get ADC group regular command of conversion stop state
3526 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
3527 * @param ADCx ADC instance
3528 * @retval 0: no command of conversion stop is on going on ADC group regular.
3529 */
LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef * ADCx)3530 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
3531 {
3532 return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP));
3533 }
3534
3535 /**
3536 * @brief Get ADC group regular conversion data, range fit for
3537 * all ADC configurations: all ADC resolutions and
3538 * all oversampling increased data width (for devices
3539 * with feature oversampling).
3540 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData32
3541 * @param ADCx ADC instance
3542 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
3543 */
LL_ADC_REG_ReadConversionData32(ADC_TypeDef * ADCx)3544 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
3545 {
3546 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3547 }
3548
3549 /**
3550 * @brief Get ADC group regular conversion data, range fit for
3551 * ADC resolution 12 bits.
3552 * @note For devices with feature oversampling: Oversampling
3553 * can increase data width, function for extended range
3554 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3555 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData12
3556 * @param ADCx ADC instance
3557 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3558 */
LL_ADC_REG_ReadConversionData12(ADC_TypeDef * ADCx)3559 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
3560 {
3561 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3562 }
3563
3564 /**
3565 * @brief Get ADC group regular conversion data, range fit for
3566 * ADC resolution 10 bits.
3567 * @note For devices with feature oversampling: Oversampling
3568 * can increase data width, function for extended range
3569 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3570 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData10
3571 * @param ADCx ADC instance
3572 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
3573 */
LL_ADC_REG_ReadConversionData10(ADC_TypeDef * ADCx)3574 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
3575 {
3576 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3577 }
3578
3579 /**
3580 * @brief Get ADC group regular conversion data, range fit for
3581 * ADC resolution 8 bits.
3582 * @note For devices with feature oversampling: Oversampling
3583 * can increase data width, function for extended range
3584 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3585 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData8
3586 * @param ADCx ADC instance
3587 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
3588 */
LL_ADC_REG_ReadConversionData8(ADC_TypeDef * ADCx)3589 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
3590 {
3591 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3592 }
3593
3594 /**
3595 * @brief Get ADC group regular conversion data, range fit for
3596 * ADC resolution 6 bits.
3597 * @note For devices with feature oversampling: Oversampling
3598 * can increase data width, function for extended range
3599 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3600 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData6
3601 * @param ADCx ADC instance
3602 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
3603 */
LL_ADC_REG_ReadConversionData6(ADC_TypeDef * ADCx)3604 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
3605 {
3606 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3607 }
3608
3609 /**
3610 * @}
3611 */
3612
3613 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
3614 * @{
3615 */
3616
3617 /**
3618 * @brief Get flag ADC ready.
3619 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
3620 * is enabled and when conversion clock is active.
3621 * (not only core clock: this ADC has a dual clock domain)
3622 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
3623 * @param ADCx ADC instance
3624 * @retval State of bit (1 or 0).
3625 */
LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef * ADCx)3626 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
3627 {
3628 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));
3629 }
3630
3631 /**
3632 * @brief Get flag ADC group regular end of unitary conversion.
3633 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
3634 * @param ADCx ADC instance
3635 * @retval State of bit (1 or 0).
3636 */
LL_ADC_IsActiveFlag_EOC(ADC_TypeDef * ADCx)3637 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
3638 {
3639 return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC));
3640 }
3641
3642 /**
3643 * @brief Get flag ADC group regular end of sequence conversions.
3644 * @rmtoll ISR EOSEQ LL_ADC_IsActiveFlag_EOS
3645 * @param ADCx ADC instance
3646 * @retval State of bit (1 or 0).
3647 */
LL_ADC_IsActiveFlag_EOS(ADC_TypeDef * ADCx)3648 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
3649 {
3650 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
3651 }
3652
3653 /**
3654 * @brief Get flag ADC group regular overrun.
3655 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
3656 * @param ADCx ADC instance
3657 * @retval State of bit (1 or 0).
3658 */
LL_ADC_IsActiveFlag_OVR(ADC_TypeDef * ADCx)3659 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
3660 {
3661 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
3662 }
3663
3664 /**
3665 * @brief Get flag ADC group regular end of sampling phase.
3666 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
3667 * @param ADCx ADC instance
3668 * @retval State of bit (1 or 0).
3669 */
LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef * ADCx)3670 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
3671 {
3672 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP));
3673 }
3674
3675 /**
3676 * @brief Get flag ADC analog watchdog 1 flag
3677 * @rmtoll ISR AWD LL_ADC_IsActiveFlag_AWD1
3678 * @param ADCx ADC instance
3679 * @retval State of bit (1 or 0).
3680 */
LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef * ADCx)3681 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
3682 {
3683 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
3684 }
3685
3686 /**
3687 * @brief Get flag ADC end of calibration.
3688 * @rmtoll ISR EOCAL LL_ADC_IsActiveFlag_EOCAL
3689 * @param ADCx ADC instance
3690 * @retval State of bit (1 or 0).
3691 */
LL_ADC_IsActiveFlag_EOCAL(ADC_TypeDef * ADCx)3692 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(ADC_TypeDef *ADCx)
3693 {
3694 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL));
3695 }
3696
3697 /**
3698 * @brief Clear flag ADC ready.
3699 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
3700 * is enabled and when conversion clock is active.
3701 * (not only core clock: this ADC has a dual clock domain)
3702 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
3703 * @param ADCx ADC instance
3704 * @retval None
3705 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)3706 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
3707 {
3708 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
3709 }
3710
3711 /**
3712 * @brief Clear flag ADC group regular end of unitary conversion.
3713 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
3714 * @param ADCx ADC instance
3715 * @retval None
3716 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)3717 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
3718 {
3719 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
3720 }
3721
3722 /**
3723 * @brief Clear flag ADC group regular end of sequence conversions.
3724 * @rmtoll ISR EOSEQ LL_ADC_ClearFlag_EOS
3725 * @param ADCx ADC instance
3726 * @retval None
3727 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)3728 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
3729 {
3730 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
3731 }
3732
3733 /**
3734 * @brief Clear flag ADC group regular overrun.
3735 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
3736 * @param ADCx ADC instance
3737 * @retval None
3738 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)3739 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
3740 {
3741 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
3742 }
3743
3744 /**
3745 * @brief Clear flag ADC group regular end of sampling phase.
3746 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
3747 * @param ADCx ADC instance
3748 * @retval None
3749 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)3750 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
3751 {
3752 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
3753 }
3754
3755 /**
3756 * @brief Clear flag ADC analog watchdog 1.
3757 * @rmtoll ISR AWD LL_ADC_ClearFlag_AWD1
3758 * @param ADCx ADC instance
3759 * @retval None
3760 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)3761 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
3762 {
3763 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
3764 }
3765
3766 /**
3767 * @brief Clear flag ADC end of calibration.
3768 * @rmtoll ISR EOCAL LL_ADC_ClearFlag_EOCAL
3769 * @param ADCx ADC instance
3770 * @retval None
3771 */
LL_ADC_ClearFlag_EOCAL(ADC_TypeDef * ADCx)3772 __STATIC_INLINE void LL_ADC_ClearFlag_EOCAL(ADC_TypeDef *ADCx)
3773 {
3774 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL);
3775 }
3776
3777 /**
3778 * @}
3779 */
3780
3781 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
3782 * @{
3783 */
3784
3785 /**
3786 * @brief Enable ADC ready.
3787 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
3788 * @param ADCx ADC instance
3789 * @retval None
3790 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)3791 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
3792 {
3793 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
3794 }
3795
3796 /**
3797 * @brief Enable interruption ADC group regular end of unitary conversion.
3798 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
3799 * @param ADCx ADC instance
3800 * @retval None
3801 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)3802 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
3803 {
3804 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
3805 }
3806
3807 /**
3808 * @brief Enable interruption ADC group regular end of sequence conversions.
3809 * @rmtoll IER EOSEQIE LL_ADC_EnableIT_EOS
3810 * @param ADCx ADC instance
3811 * @retval None
3812 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)3813 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
3814 {
3815 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
3816 }
3817
3818 /**
3819 * @brief Enable ADC group regular interruption overrun.
3820 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
3821 * @param ADCx ADC instance
3822 * @retval None
3823 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)3824 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
3825 {
3826 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
3827 }
3828
3829 /**
3830 * @brief Enable interruption ADC group regular end of sampling.
3831 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
3832 * @param ADCx ADC instance
3833 * @retval None
3834 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)3835 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
3836 {
3837 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
3838 }
3839
3840 /**
3841 * @brief Enable interruption ADC analog watchdog 1.
3842 * @rmtoll IER AWDIE LL_ADC_EnableIT_AWD1
3843 * @param ADCx ADC instance
3844 * @retval None
3845 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)3846 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
3847 {
3848 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
3849 }
3850
3851 /**
3852 * @brief Enable interruption ADC end of calibration.
3853 * @rmtoll IER EOCALIE LL_ADC_EnableIT_EOCAL
3854 * @param ADCx ADC instance
3855 * @retval None
3856 */
LL_ADC_EnableIT_EOCAL(ADC_TypeDef * ADCx)3857 __STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx)
3858 {
3859 SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
3860 }
3861
3862 /**
3863 * @brief Disable interruption ADC ready.
3864 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
3865 * @param ADCx ADC instance
3866 * @retval None
3867 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)3868 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
3869 {
3870 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
3871 }
3872
3873 /**
3874 * @brief Disable interruption ADC group regular end of unitary conversion.
3875 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
3876 * @param ADCx ADC instance
3877 * @retval None
3878 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)3879 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
3880 {
3881 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
3882 }
3883
3884 /**
3885 * @brief Disable interruption ADC group regular end of sequence conversions.
3886 * @rmtoll IER EOSEQIE LL_ADC_DisableIT_EOS
3887 * @param ADCx ADC instance
3888 * @retval None
3889 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)3890 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
3891 {
3892 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
3893 }
3894
3895 /**
3896 * @brief Disable interruption ADC group regular overrun.
3897 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
3898 * @param ADCx ADC instance
3899 * @retval None
3900 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)3901 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
3902 {
3903 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
3904 }
3905
3906 /**
3907 * @brief Disable interruption ADC group regular end of sampling.
3908 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
3909 * @param ADCx ADC instance
3910 * @retval None
3911 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)3912 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
3913 {
3914 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
3915 }
3916
3917 /**
3918 * @brief Disable interruption ADC analog watchdog 1.
3919 * @rmtoll IER AWDIE LL_ADC_DisableIT_AWD1
3920 * @param ADCx ADC instance
3921 * @retval None
3922 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)3923 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
3924 {
3925 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
3926 }
3927
3928 /**
3929 * @brief Disable interruption ADC end of calibration.
3930 * @rmtoll IER EOCALIE LL_ADC_DisableIT_EOCAL
3931 * @param ADCx ADC instance
3932 * @retval None
3933 */
LL_ADC_DisableIT_EOCAL(ADC_TypeDef * ADCx)3934 __STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx)
3935 {
3936 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
3937 }
3938
3939 /**
3940 * @brief Get state of interruption ADC ready
3941 * (0: interrupt disabled, 1: interrupt enabled).
3942 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
3943 * @param ADCx ADC instance
3944 * @retval State of bit (1 or 0).
3945 */
LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef * ADCx)3946 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
3947 {
3948 return (READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY));
3949 }
3950
3951 /**
3952 * @brief Get state of interruption ADC group regular end of unitary conversion
3953 * (0: interrupt disabled, 1: interrupt enabled).
3954 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
3955 * @param ADCx ADC instance
3956 * @retval State of bit (1 or 0).
3957 */
LL_ADC_IsEnabledIT_EOC(ADC_TypeDef * ADCx)3958 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
3959 {
3960 return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC));
3961 }
3962
3963 /**
3964 * @brief Get state of interruption ADC group regular end of sequence conversions
3965 * (0: interrupt disabled, 1: interrupt enabled).
3966 * @rmtoll IER EOSEQIE LL_ADC_IsEnabledIT_EOS
3967 * @param ADCx ADC instance
3968 * @retval State of bit (1 or 0).
3969 */
LL_ADC_IsEnabledIT_EOS(ADC_TypeDef * ADCx)3970 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
3971 {
3972 return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
3973 }
3974
3975 /**
3976 * @brief Get state of interruption ADC group regular overrun
3977 * (0: interrupt disabled, 1: interrupt enabled).
3978 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
3979 * @param ADCx ADC instance
3980 * @retval State of bit (1 or 0).
3981 */
LL_ADC_IsEnabledIT_OVR(ADC_TypeDef * ADCx)3982 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
3983 {
3984 return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
3985 }
3986
3987 /**
3988 * @brief Get state of interruption ADC group regular end of sampling
3989 * (0: interrupt disabled, 1: interrupt enabled).
3990 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
3991 * @param ADCx ADC instance
3992 * @retval State of bit (1 or 0).
3993 */
LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef * ADCx)3994 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
3995 {
3996 return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP));
3997 }
3998
3999 /**
4000 * @brief Get state of interruption ADC analog watchdog 1
4001 * (0: interrupt disabled, 1: interrupt enabled).
4002 * @rmtoll IER AWDIE LL_ADC_IsEnabledIT_AWD1
4003 * @param ADCx ADC instance
4004 * @retval State of bit (1 or 0).
4005 */
LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef * ADCx)4006 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
4007 {
4008 return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
4009 }
4010
4011 /**
4012 * @brief Get state of interruption ADC end of calibration
4013 * (0: interrupt disabled, 1: interrupt enabled).
4014 * @rmtoll IER EOCALIE LL_ADC_IsEnabledIT_EOCAL
4015 * @param ADCx ADC instance
4016 * @retval State of bit (1 or 0).
4017 */
LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef * ADCx)4018 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx)
4019 {
4020 return (READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL));
4021 }
4022
4023 /**
4024 * @}
4025 */
4026
4027 #if defined(USE_FULL_LL_DRIVER)
4028 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
4029 * @{
4030 */
4031
4032 /* Initialization of some features of ADC common parameters and multimode */
4033 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
4034 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
4035 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
4036
4037 /* De-initialization of ADC instance */
4038 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
4039
4040 /* Initialization of some features of ADC instance */
4041 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
4042 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
4043
4044 /* Initialization of some features of ADC instance and ADC group regular */
4045 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
4046 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
4047
4048 /**
4049 * @}
4050 */
4051 #endif /* USE_FULL_LL_DRIVER */
4052
4053 /**
4054 * @}
4055 */
4056
4057 /**
4058 * @}
4059 */
4060
4061 #endif /* ADC1 */
4062
4063 /**
4064 * @}
4065 */
4066
4067 #ifdef __cplusplus
4068 }
4069 #endif
4070
4071 #endif /* __STM32L0xx_LL_ADC_H */
4072
4073
