1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal_tim.h 4 * @author MCD Application Team 5 * @brief Header file of TIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L0xx_HAL_TIM_H 21 #define STM32L0xx_HAL_TIM_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l0xx_hal_def.h" 29 30 /** @addtogroup STM32L0xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup TIM 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup TIM_Exported_Types TIM Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief TIM Time base Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 49 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 50 51 uint32_t CounterMode; /*!< Specifies the counter mode. 52 This parameter can be a value of @ref TIM_Counter_Mode */ 53 54 uint32_t Period; /*!< Specifies the period value to be loaded into the active 55 Auto-Reload Register at the next update event. 56 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 57 58 uint32_t ClockDivision; /*!< Specifies the clock division. 59 This parameter can be a value of @ref TIM_ClockDivision */ 60 61 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. 62 This parameter can be a value of @ref TIM_AutoReloadPreload */ 63 } TIM_Base_InitTypeDef; 64 65 /** 66 * @brief TIM Output Compare Configuration Structure definition 67 */ 68 typedef struct 69 { 70 uint32_t OCMode; /*!< Specifies the TIM mode. 71 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 72 73 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 74 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 75 76 uint32_t OCPolarity; /*!< Specifies the output polarity. 77 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 78 79 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 80 This parameter can be a value of @ref TIM_Output_Fast_State 81 @note This parameter is valid only in PWM1 and PWM2 mode. */ 82 } TIM_OC_InitTypeDef; 83 84 /** 85 * @brief TIM One Pulse Mode Configuration Structure definition 86 */ 87 typedef struct 88 { 89 uint32_t OCMode; /*!< Specifies the TIM mode. 90 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 91 92 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 93 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 94 95 uint32_t OCPolarity; /*!< Specifies the output polarity. 96 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 97 98 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 99 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 100 101 uint32_t ICSelection; /*!< Specifies the input. 102 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 103 104 uint32_t ICFilter; /*!< Specifies the input capture filter. 105 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 106 } TIM_OnePulse_InitTypeDef; 107 108 /** 109 * @brief TIM Input Capture Configuration Structure definition 110 */ 111 typedef struct 112 { 113 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 114 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 115 116 uint32_t ICSelection; /*!< Specifies the input. 117 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 118 119 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 120 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 121 122 uint32_t ICFilter; /*!< Specifies the input capture filter. 123 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 124 } TIM_IC_InitTypeDef; 125 126 /** 127 * @brief TIM Encoder Configuration Structure definition 128 */ 129 typedef struct 130 { 131 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 132 This parameter can be a value of @ref TIM_Encoder_Mode */ 133 134 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 135 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 136 137 uint32_t IC1Selection; /*!< Specifies the input. 138 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 139 140 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 141 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 142 143 uint32_t IC1Filter; /*!< Specifies the input capture filter. 144 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 145 146 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 147 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 148 149 uint32_t IC2Selection; /*!< Specifies the input. 150 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 151 152 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 153 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 154 155 uint32_t IC2Filter; /*!< Specifies the input capture filter. 156 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 157 } TIM_Encoder_InitTypeDef; 158 159 /** 160 * @brief Clock Configuration Handle Structure definition 161 */ 162 typedef struct 163 { 164 uint32_t ClockSource; /*!< TIM clock sources 165 This parameter can be a value of @ref TIM_Clock_Source */ 166 uint32_t ClockPolarity; /*!< TIM clock polarity 167 This parameter can be a value of @ref TIM_Clock_Polarity */ 168 uint32_t ClockPrescaler; /*!< TIM clock prescaler 169 This parameter can be a value of @ref TIM_Clock_Prescaler */ 170 uint32_t ClockFilter; /*!< TIM clock filter 171 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 172 } TIM_ClockConfigTypeDef; 173 174 /** 175 * @brief TIM Clear Input Configuration Handle Structure definition 176 */ 177 typedef struct 178 { 179 uint32_t ClearInputState; /*!< TIM clear Input state 180 This parameter can be ENABLE or DISABLE */ 181 uint32_t ClearInputSource; /*!< TIM clear Input sources 182 This parameter can be a value of @ref TIM_ClearInput_Source */ 183 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity 184 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 185 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler 186 This parameter must be 0: When OCRef clear feature is used with ETR source, 187 ETR prescaler must be off */ 188 uint32_t ClearInputFilter; /*!< TIM Clear Input filter 189 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 190 } TIM_ClearInputConfigTypeDef; 191 192 /** 193 * @brief TIM Master configuration Structure definition 194 */ 195 typedef struct 196 { 197 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection 198 This parameter can be a value of @ref TIM_Master_Mode_Selection */ 199 uint32_t MasterSlaveMode; /*!< Master/slave mode selection 200 This parameter can be a value of @ref TIM_Master_Slave_Mode 201 @note When the Master/slave mode is enabled, the effect of 202 an event on the trigger input (TRGI) is delayed to allow a 203 perfect synchronization between the current timer and its 204 slaves (through TRGO). It is not mandatory in case of timer 205 synchronization mode. */ 206 } TIM_MasterConfigTypeDef; 207 208 /** 209 * @brief TIM Slave configuration Structure definition 210 */ 211 typedef struct 212 { 213 uint32_t SlaveMode; /*!< Slave mode selection 214 This parameter can be a value of @ref TIM_Slave_Mode */ 215 uint32_t InputTrigger; /*!< Input Trigger source 216 This parameter can be a value of @ref TIM_Trigger_Selection */ 217 uint32_t TriggerPolarity; /*!< Input Trigger polarity 218 This parameter can be a value of @ref TIM_Trigger_Polarity */ 219 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 220 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 221 uint32_t TriggerFilter; /*!< Input trigger filter 222 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 223 224 } TIM_SlaveConfigTypeDef; 225 226 /** 227 * @brief HAL State structures definition 228 */ 229 typedef enum 230 { 231 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 232 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 233 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 234 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 235 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 236 } HAL_TIM_StateTypeDef; 237 238 /** 239 * @brief TIM Channel States definition 240 */ 241 typedef enum 242 { 243 HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ 244 HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ 245 HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ 246 } HAL_TIM_ChannelStateTypeDef; 247 248 /** 249 * @brief DMA Burst States definition 250 */ 251 typedef enum 252 { 253 HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ 254 HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ 255 HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ 256 } HAL_TIM_DMABurstStateTypeDef; 257 258 /** 259 * @brief HAL Active channel structures definition 260 */ 261 typedef enum 262 { 263 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 264 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 265 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 266 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 267 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 268 } HAL_TIM_ActiveChannel; 269 270 /** 271 * @brief TIM Time Base Handle Structure definition 272 */ 273 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 274 typedef struct __TIM_HandleTypeDef 275 #else 276 typedef struct 277 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 278 { 279 TIM_TypeDef *Instance; /*!< Register base address */ 280 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 281 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 282 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 283 This array is accessed by a @ref DMA_Handle_index */ 284 HAL_LockTypeDef Lock; /*!< Locking object */ 285 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 286 __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ 287 __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ 288 289 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 290 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ 291 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ 292 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ 293 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ 294 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ 295 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ 296 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ 297 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ 298 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ 299 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ 300 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ 301 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ 302 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ 303 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ 304 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ 305 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ 306 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ 307 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ 308 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ 309 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ 310 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ 311 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ 312 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 313 } TIM_HandleTypeDef; 314 315 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 316 /** 317 * @brief HAL TIM Callback ID enumeration definition 318 */ 319 typedef enum 320 { 321 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ 322 , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ 323 , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ 324 , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ 325 , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ 326 , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ 327 , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ 328 , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ 329 , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ 330 , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ 331 , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ 332 , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ 333 , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ 334 , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ 335 , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ 336 , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ 337 338 , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ 339 , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ 340 , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ 341 , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ 342 , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ 343 , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ 344 } HAL_TIM_CallbackIDTypeDef; 345 346 /** 347 * @brief HAL TIM Callback pointer definition 348 */ 349 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ 350 351 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 352 353 /** 354 * @} 355 */ 356 /* End of exported types -----------------------------------------------------*/ 357 358 /* Exported constants --------------------------------------------------------*/ 359 /** @defgroup TIM_Exported_Constants TIM Exported Constants 360 * @{ 361 */ 362 363 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source 364 * @{ 365 */ 366 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ 367 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ 368 /** 369 * @} 370 */ 371 372 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address 373 * @{ 374 */ 375 #define TIM_DMABASE_CR1 0x00000000U 376 #define TIM_DMABASE_CR2 0x00000001U 377 #define TIM_DMABASE_SMCR 0x00000002U 378 #define TIM_DMABASE_DIER 0x00000003U 379 #define TIM_DMABASE_SR 0x00000004U 380 #define TIM_DMABASE_EGR 0x00000005U 381 #define TIM_DMABASE_CCMR1 0x00000006U 382 #define TIM_DMABASE_CCMR2 0x00000007U 383 #define TIM_DMABASE_CCER 0x00000008U 384 #define TIM_DMABASE_CNT 0x00000009U 385 #define TIM_DMABASE_PSC 0x0000000AU 386 #define TIM_DMABASE_ARR 0x0000000BU 387 #define TIM_DMABASE_CCR1 0x0000000DU 388 #define TIM_DMABASE_CCR2 0x0000000EU 389 #define TIM_DMABASE_CCR3 0x0000000FU 390 #define TIM_DMABASE_CCR4 0x00000010U 391 #define TIM_DMABASE_DCR 0x00000012U 392 #define TIM_DMABASE_DMAR 0x00000013U 393 #define TIM_DMABASE_OR 0x00000014U 394 /** 395 * @} 396 */ 397 398 /** @defgroup TIM_Event_Source TIM Event Source 399 * @{ 400 */ 401 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ 402 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ 403 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ 404 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ 405 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ 406 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ 407 /** 408 * @} 409 */ 410 411 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity 412 * @{ 413 */ 414 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 415 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ 416 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 417 /** 418 * @} 419 */ 420 421 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 422 * @{ 423 */ 424 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ 425 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 426 /** 427 * @} 428 */ 429 430 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 431 * @{ 432 */ 433 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 434 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ 435 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ 436 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ 437 /** 438 * @} 439 */ 440 441 /** @defgroup TIM_Counter_Mode TIM Counter Mode 442 * @{ 443 */ 444 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ 445 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ 446 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ 447 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ 448 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ 449 /** 450 * @} 451 */ 452 453 /** @defgroup TIM_ClockDivision TIM Clock Division 454 * @{ 455 */ 456 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 457 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ 458 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ 459 /** 460 * @} 461 */ 462 463 /** @defgroup TIM_Output_Compare_State TIM Output Compare State 464 * @{ 465 */ 466 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ 467 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ 468 /** 469 * @} 470 */ 471 472 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload 473 * @{ 474 */ 475 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ 476 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ 477 478 /** 479 * @} 480 */ 481 482 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 483 * @{ 484 */ 485 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ 486 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ 487 /** 488 * @} 489 */ 490 491 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State 492 * @{ 493 */ 494 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ 495 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ 496 /** 497 * @} 498 */ 499 500 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 501 * @{ 502 */ 503 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ 504 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ 505 /** 506 * @} 507 */ 508 509 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 510 * @{ 511 */ 512 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ 513 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ 514 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ 515 /** 516 * @} 517 */ 518 519 /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity 520 * @{ 521 */ 522 #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ 523 #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ 524 /** 525 * @} 526 */ 527 528 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 529 * @{ 530 */ 531 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ 532 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ 533 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 534 /** 535 * @} 536 */ 537 538 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 539 * @{ 540 */ 541 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 542 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ 543 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ 544 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ 545 /** 546 * @} 547 */ 548 549 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 550 * @{ 551 */ 552 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 553 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 554 /** 555 * @} 556 */ 557 558 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 559 * @{ 560 */ 561 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ 562 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ 563 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ 564 /** 565 * @} 566 */ 567 568 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition 569 * @{ 570 */ 571 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ 572 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ 573 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ 574 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ 575 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ 576 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ 577 /** 578 * @} 579 */ 580 581 /** @defgroup TIM_DMA_sources TIM DMA Sources 582 * @{ 583 */ 584 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ 585 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ 586 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ 587 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ 588 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ 589 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ 590 /** 591 * @} 592 */ 593 594 /** @defgroup TIM_CC_DMA_Request CCx DMA request selection 595 * @{ 596 */ 597 #define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ 598 #define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ 599 /** 600 * @} 601 */ 602 603 /** @defgroup TIM_Flag_definition TIM Flag Definition 604 * @{ 605 */ 606 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ 607 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ 608 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ 609 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ 610 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ 611 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ 612 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ 613 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ 614 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ 615 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ 616 /** 617 * @} 618 */ 619 620 /** @defgroup TIM_Channel TIM Channel 621 * @{ 622 */ 623 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ 624 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ 625 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ 626 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ 627 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ 628 /** 629 * @} 630 */ 631 632 /** @defgroup TIM_Clock_Source TIM Clock Source 633 * @{ 634 */ 635 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ 636 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ 637 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ 638 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ 639 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ 640 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ 641 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ 642 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ 643 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ 644 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ 645 /** 646 * @} 647 */ 648 649 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 650 * @{ 651 */ 652 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 653 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 654 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 655 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 656 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 657 /** 658 * @} 659 */ 660 661 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 662 * @{ 663 */ 664 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 665 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 666 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 667 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 668 /** 669 * @} 670 */ 671 672 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 673 * @{ 674 */ 675 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 676 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 677 /** 678 * @} 679 */ 680 681 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 682 * @{ 683 */ 684 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 685 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 686 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 687 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 688 /** 689 * @} 690 */ 691 692 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 693 * @{ 694 */ 695 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ 696 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ 697 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ 698 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ 699 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ 700 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ 701 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ 702 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ 703 /** 704 * @} 705 */ 706 707 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode 708 * @{ 709 */ 710 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ 711 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ 712 /** 713 * @} 714 */ 715 716 /** @defgroup TIM_Slave_Mode TIM Slave mode 717 * @{ 718 */ 719 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ 720 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ 721 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ 722 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ 723 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ 724 /** 725 * @} 726 */ 727 728 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes 729 * @{ 730 */ 731 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ 732 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ 733 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ 734 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ 735 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ 736 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ 737 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ 738 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ 739 /** 740 * @} 741 */ 742 743 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 744 * @{ 745 */ 746 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ 747 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ 748 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ 749 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ 750 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ 751 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ 752 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ 753 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ 754 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ 755 /** 756 * @} 757 */ 758 759 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 760 * @{ 761 */ 762 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 763 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 764 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 765 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 766 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 767 /** 768 * @} 769 */ 770 771 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 772 * @{ 773 */ 774 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 775 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 776 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 777 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 778 /** 779 * @} 780 */ 781 782 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection 783 * @{ 784 */ 785 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ 786 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ 787 /** 788 * @} 789 */ 790 791 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 792 * @{ 793 */ 794 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ 795 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 796 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 797 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 798 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 799 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 800 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 801 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 802 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 803 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 804 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 805 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 806 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 807 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 808 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 809 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 810 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 811 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 812 /** 813 * @} 814 */ 815 816 /** @defgroup DMA_Handle_index TIM DMA Handle Index 817 * @{ 818 */ 819 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 820 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 821 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 822 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 823 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 824 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ 825 /** 826 * @} 827 */ 828 829 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State 830 * @{ 831 */ 832 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ 833 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ 834 /** 835 * @} 836 */ 837 838 /** 839 * @} 840 */ 841 /* End of exported constants -------------------------------------------------*/ 842 843 /* Exported macros -----------------------------------------------------------*/ 844 /** @defgroup TIM_Exported_Macros TIM Exported Macros 845 * @{ 846 */ 847 848 /** @brief Reset TIM handle state. 849 * @param __HANDLE__ TIM handle. 850 * @retval None 851 */ 852 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 853 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 854 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 855 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 856 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 857 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 858 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 859 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 860 (__HANDLE__)->Base_MspInitCallback = NULL; \ 861 (__HANDLE__)->Base_MspDeInitCallback = NULL; \ 862 (__HANDLE__)->IC_MspInitCallback = NULL; \ 863 (__HANDLE__)->IC_MspDeInitCallback = NULL; \ 864 (__HANDLE__)->OC_MspInitCallback = NULL; \ 865 (__HANDLE__)->OC_MspDeInitCallback = NULL; \ 866 (__HANDLE__)->PWM_MspInitCallback = NULL; \ 867 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ 868 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ 869 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ 870 (__HANDLE__)->Encoder_MspInitCallback = NULL; \ 871 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ 872 } while(0) 873 #else 874 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 875 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 876 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 877 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 878 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 879 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 880 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 881 } while(0) 882 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 883 884 /** 885 * @brief Enable the TIM peripheral. 886 * @param __HANDLE__ TIM handle 887 * @retval None 888 */ 889 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 890 891 /** 892 * @brief Disable the TIM peripheral. 893 * @param __HANDLE__ TIM handle 894 * @retval None 895 */ 896 #define __HAL_TIM_DISABLE(__HANDLE__) \ 897 do { \ 898 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 899 { \ 900 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 901 } \ 902 } while(0) 903 904 /** @brief Enable the specified TIM interrupt. 905 * @param __HANDLE__ specifies the TIM Handle. 906 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. 907 * This parameter can be one of the following values: 908 * @arg TIM_IT_UPDATE: Update interrupt 909 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 910 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 911 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 912 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 913 * @arg TIM_IT_TRIGGER: Trigger interrupt 914 * @retval None 915 */ 916 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 917 918 /** @brief Disable the specified TIM interrupt. 919 * @param __HANDLE__ specifies the TIM Handle. 920 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. 921 * This parameter can be one of the following values: 922 * @arg TIM_IT_UPDATE: Update interrupt 923 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 924 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 925 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 926 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 927 * @arg TIM_IT_TRIGGER: Trigger interrupt 928 * @retval None 929 */ 930 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 931 932 /** @brief Enable the specified DMA request. 933 * @param __HANDLE__ specifies the TIM Handle. 934 * @param __DMA__ specifies the TIM DMA request to enable. 935 * This parameter can be one of the following values: 936 * @arg TIM_DMA_UPDATE: Update DMA request 937 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 938 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 939 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 940 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 941 * @arg TIM_DMA_TRIGGER: Trigger DMA request 942 * @retval None 943 */ 944 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 945 946 /** @brief Disable the specified DMA request. 947 * @param __HANDLE__ specifies the TIM Handle. 948 * @param __DMA__ specifies the TIM DMA request to disable. 949 * This parameter can be one of the following values: 950 * @arg TIM_DMA_UPDATE: Update DMA request 951 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 952 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 953 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 954 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 955 * @arg TIM_DMA_TRIGGER: Trigger DMA request 956 * @retval None 957 */ 958 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 959 960 /** @brief Check whether the specified TIM interrupt flag is set or not. 961 * @param __HANDLE__ specifies the TIM Handle. 962 * @param __FLAG__ specifies the TIM interrupt flag to check. 963 * This parameter can be one of the following values: 964 * @arg TIM_FLAG_UPDATE: Update interrupt flag 965 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 966 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 967 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 968 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 969 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 970 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 971 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 972 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 973 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 974 * @retval The new state of __FLAG__ (TRUE or FALSE). 975 */ 976 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 977 978 /** @brief Clear the specified TIM interrupt flag. 979 * @param __HANDLE__ specifies the TIM Handle. 980 * @param __FLAG__ specifies the TIM interrupt flag to clear. 981 * This parameter can be one of the following values: 982 * @arg TIM_FLAG_UPDATE: Update interrupt flag 983 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 984 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 985 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 986 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 987 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 988 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 989 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 990 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 991 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 992 * @retval The new state of __FLAG__ (TRUE or FALSE). 993 */ 994 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 995 996 /** 997 * @brief Check whether the specified TIM interrupt source is enabled or not. 998 * @param __HANDLE__ TIM handle 999 * @param __INTERRUPT__ specifies the TIM interrupt source to check. 1000 * This parameter can be one of the following values: 1001 * @arg TIM_IT_UPDATE: Update interrupt 1002 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1003 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1004 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1005 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1006 * @arg TIM_IT_TRIGGER: Trigger interrupt 1007 * @retval The state of TIM_IT (SET or RESET). 1008 */ 1009 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ 1010 == (__INTERRUPT__)) ? SET : RESET) 1011 1012 /** @brief Clear the TIM interrupt pending bits. 1013 * @param __HANDLE__ TIM handle 1014 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1015 * This parameter can be one of the following values: 1016 * @arg TIM_IT_UPDATE: Update interrupt 1017 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1018 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1019 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1020 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1021 * @arg TIM_IT_TRIGGER: Trigger interrupt 1022 * @retval None 1023 */ 1024 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 1025 1026 /** 1027 * @brief Indicates whether or not the TIM Counter is used as downcounter. 1028 * @param __HANDLE__ TIM handle. 1029 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 1030 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode 1031 * or Encoder mode. 1032 */ 1033 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 1034 1035 /** 1036 * @brief Set the TIM Prescaler on runtime. 1037 * @param __HANDLE__ TIM handle. 1038 * @param __PRESC__ specifies the Prescaler new value. 1039 * @retval None 1040 */ 1041 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 1042 1043 /** 1044 * @brief Set the TIM Counter Register value on runtime. 1045 * @param __HANDLE__ TIM handle. 1046 * @param __COUNTER__ specifies the Counter register new value. 1047 * @retval None 1048 */ 1049 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 1050 1051 /** 1052 * @brief Get the TIM Counter Register value on runtime. 1053 * @param __HANDLE__ TIM handle. 1054 * @retval 16-bit value of the timer counter register (TIMx_CNT) 1055 */ 1056 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) 1057 1058 /** 1059 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. 1060 * @param __HANDLE__ TIM handle. 1061 * @param __AUTORELOAD__ specifies the Counter register new value. 1062 * @retval None 1063 */ 1064 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 1065 do{ \ 1066 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 1067 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 1068 } while(0) 1069 1070 /** 1071 * @brief Get the TIM Autoreload Register value on runtime. 1072 * @param __HANDLE__ TIM handle. 1073 * @retval 16-bit value of the timer auto-reload register(TIMx_ARR) 1074 */ 1075 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) 1076 1077 /** 1078 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. 1079 * @param __HANDLE__ TIM handle. 1080 * @param __CKD__ specifies the clock division value. 1081 * This parameter can be one of the following value: 1082 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1083 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1084 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1085 * @retval None 1086 */ 1087 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 1088 do{ \ 1089 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ 1090 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 1091 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 1092 } while(0) 1093 1094 /** 1095 * @brief Get the TIM Clock Division value on runtime. 1096 * @param __HANDLE__ TIM handle. 1097 * @retval The clock division can be one of the following values: 1098 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1099 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1100 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1101 */ 1102 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 1103 1104 /** 1105 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() 1106 * function. 1107 * @param __HANDLE__ TIM handle. 1108 * @param __CHANNEL__ TIM Channels to be configured. 1109 * This parameter can be one of the following values: 1110 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1111 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1112 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1113 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1114 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. 1115 * This parameter can be one of the following values: 1116 * @arg TIM_ICPSC_DIV1: no prescaler 1117 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1118 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1119 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1120 * @retval None 1121 */ 1122 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1123 do{ \ 1124 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 1125 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 1126 } while(0) 1127 1128 /** 1129 * @brief Get the TIM Input Capture prescaler on runtime. 1130 * @param __HANDLE__ TIM handle. 1131 * @param __CHANNEL__ TIM Channels to be configured. 1132 * This parameter can be one of the following values: 1133 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 1134 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 1135 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 1136 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 1137 * @retval The input capture prescaler can be one of the following values: 1138 * @arg TIM_ICPSC_DIV1: no prescaler 1139 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1140 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1141 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1142 */ 1143 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 1144 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 1145 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ 1146 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 1147 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 1148 1149 /** 1150 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. 1151 * @param __HANDLE__ TIM handle. 1152 * @param __CHANNEL__ TIM Channels to be configured. 1153 * This parameter can be one of the following values: 1154 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1155 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1156 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1157 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1158 * @param __COMPARE__ specifies the Capture Compare register new value. 1159 * @retval None 1160 */ 1161 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 1162 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 1163 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 1164 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 1165 ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) 1166 1167 /** 1168 * @brief Get the TIM Capture Compare Register value on runtime. 1169 * @param __HANDLE__ TIM handle. 1170 * @param __CHANNEL__ TIM Channel associated with the capture compare register 1171 * This parameter can be one of the following values: 1172 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 1173 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 1174 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 1175 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 1176 * @retval 16-bit value of the capture/compare register (TIMx_CCRy) 1177 */ 1178 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 1179 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 1180 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 1181 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 1182 ((__HANDLE__)->Instance->CCR4)) 1183 1184 /** 1185 * @brief Set the TIM Output compare preload. 1186 * @param __HANDLE__ TIM handle. 1187 * @param __CHANNEL__ TIM Channels to be configured. 1188 * This parameter can be one of the following values: 1189 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1190 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1191 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1192 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1193 * @retval None 1194 */ 1195 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1196 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 1197 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 1198 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 1199 ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) 1200 1201 /** 1202 * @brief Reset the TIM Output compare preload. 1203 * @param __HANDLE__ TIM handle. 1204 * @param __CHANNEL__ TIM Channels to be configured. 1205 * This parameter can be one of the following values: 1206 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1207 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1208 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1209 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1210 * @retval None 1211 */ 1212 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1213 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ 1214 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ 1215 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ 1216 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) 1217 1218 /** 1219 * @brief Enable fast mode for a given channel. 1220 * @param __HANDLE__ TIM handle. 1221 * @param __CHANNEL__ TIM Channels to be configured. 1222 * This parameter can be one of the following values: 1223 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1224 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1225 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1226 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1227 * @note When fast mode is enabled an active edge on the trigger input acts 1228 * like a compare match on CCx output. Delay to sample the trigger 1229 * input and to activate CCx output is reduced to 3 clock cycles. 1230 * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. 1231 * @retval None 1232 */ 1233 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1234 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ 1235 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ 1236 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ 1237 ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) 1238 1239 /** 1240 * @brief Disable fast mode for a given channel. 1241 * @param __HANDLE__ TIM handle. 1242 * @param __CHANNEL__ TIM Channels to be configured. 1243 * This parameter can be one of the following values: 1244 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1245 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1246 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1247 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1248 * @note When fast mode is disabled CCx output behaves normally depending 1249 * on counter and CCRx values even when the trigger is ON. The minimum 1250 * delay to activate CCx output when an active edge occurs on the 1251 * trigger input is 5 clock cycles. 1252 * @retval None 1253 */ 1254 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1255 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ 1256 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ 1257 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ 1258 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) 1259 1260 /** 1261 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. 1262 * @param __HANDLE__ TIM handle. 1263 * @note When the URS bit of the TIMx_CR1 register is set, only counter 1264 * overflow/underflow generates an update interrupt or DMA request (if 1265 * enabled) 1266 * @retval None 1267 */ 1268 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) 1269 1270 /** 1271 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. 1272 * @param __HANDLE__ TIM handle. 1273 * @note When the URS bit of the TIMx_CR1 register is reset, any of the 1274 * following events generate an update interrupt or DMA request (if 1275 * enabled): 1276 * _ Counter overflow underflow 1277 * _ Setting the UG bit 1278 * _ Update generation through the slave mode controller 1279 * @retval None 1280 */ 1281 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) 1282 1283 /** 1284 * @brief Set the TIM Capture x input polarity on runtime. 1285 * @param __HANDLE__ TIM handle. 1286 * @param __CHANNEL__ TIM Channels to be configured. 1287 * This parameter can be one of the following values: 1288 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1289 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1290 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1291 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1292 * @param __POLARITY__ Polarity for TIx source 1293 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 1294 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 1295 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 1296 * @retval None 1297 */ 1298 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1299 do{ \ 1300 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 1301 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 1302 }while(0) 1303 1304 /** @brief Select the Capture/compare DMA request source. 1305 * @param __HANDLE__ specifies the TIM Handle. 1306 * @param __CCDMA__ specifies Capture/compare DMA request source 1307 * This parameter can be one of the following values: 1308 * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event 1309 * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event 1310 * @retval None 1311 */ 1312 #define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ 1313 MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) 1314 1315 /** 1316 * @} 1317 */ 1318 /* End of exported macros ----------------------------------------------------*/ 1319 1320 /* Private constants ---------------------------------------------------------*/ 1321 /** @defgroup TIM_Private_Constants TIM Private Constants 1322 * @{ 1323 */ 1324 /* The counter of a timer instance is disabled only if all the CCx and CCxN 1325 channels have been disabled */ 1326 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 1327 /** 1328 * @} 1329 */ 1330 /* End of private constants --------------------------------------------------*/ 1331 1332 /* Private macros ------------------------------------------------------------*/ 1333 /** @defgroup TIM_Private_Macros TIM Private Macros 1334 * @{ 1335 */ 1336 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ 1337 ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) 1338 1339 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 1340 ((__BASE__) == TIM_DMABASE_CR2) || \ 1341 ((__BASE__) == TIM_DMABASE_SMCR) || \ 1342 ((__BASE__) == TIM_DMABASE_DIER) || \ 1343 ((__BASE__) == TIM_DMABASE_SR) || \ 1344 ((__BASE__) == TIM_DMABASE_EGR) || \ 1345 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 1346 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 1347 ((__BASE__) == TIM_DMABASE_CCER) || \ 1348 ((__BASE__) == TIM_DMABASE_CNT) || \ 1349 ((__BASE__) == TIM_DMABASE_PSC) || \ 1350 ((__BASE__) == TIM_DMABASE_ARR) || \ 1351 ((__BASE__) == TIM_DMABASE_CCR1) || \ 1352 ((__BASE__) == TIM_DMABASE_CCR2) || \ 1353 ((__BASE__) == TIM_DMABASE_CCR3) || \ 1354 ((__BASE__) == TIM_DMABASE_CCR4) || \ 1355 ((__BASE__) == TIM_DMABASE_OR)) 1356 1357 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1358 1359 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ 1360 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ 1361 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 1362 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 1363 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 1364 1365 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ 1366 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ 1367 ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 1368 1369 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ 1370 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) 1371 1372 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ 1373 ((__STATE__) == TIM_OCFAST_ENABLE)) 1374 1375 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ 1376 ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 1377 1378 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ 1379 ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) 1380 1381 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ 1382 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ 1383 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 1384 1385 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ 1386 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ 1387 ((__SELECTION__) == TIM_ICSELECTION_TRC)) 1388 1389 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ 1390 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ 1391 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ 1392 ((__PRESCALER__) == TIM_ICPSC_DIV8)) 1393 1394 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ 1395 ((__MODE__) == TIM_OPMODE_REPETITIVE)) 1396 1397 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ 1398 ((__MODE__) == TIM_ENCODERMODE_TI2) || \ 1399 ((__MODE__) == TIM_ENCODERMODE_TI12)) 1400 1401 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1402 1403 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1404 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1405 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1406 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 1407 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 1408 1409 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1410 ((__CHANNEL__) == TIM_CHANNEL_2)) 1411 1412 #define IS_TIM_PERIOD(__PERIOD__) (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0xFFFFU)) 1413 1414 #define IS_TIM_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFFU) 1415 1416 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 1417 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ 1418 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 1419 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 1420 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 1421 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 1422 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 1423 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 1424 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 1425 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)) 1426 1427 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ 1428 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 1429 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ 1430 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ 1431 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 1432 1433 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ 1434 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ 1435 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ 1436 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 1437 1438 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1439 1440 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 1441 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 1442 1443 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 1444 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 1445 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 1446 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 1447 1448 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1449 1450 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ 1451 ((__SOURCE__) == TIM_TRGO_ENABLE) || \ 1452 ((__SOURCE__) == TIM_TRGO_UPDATE) || \ 1453 ((__SOURCE__) == TIM_TRGO_OC1) || \ 1454 ((__SOURCE__) == TIM_TRGO_OC1REF) || \ 1455 ((__SOURCE__) == TIM_TRGO_OC2REF) || \ 1456 ((__SOURCE__) == TIM_TRGO_OC3REF) || \ 1457 ((__SOURCE__) == TIM_TRGO_OC4REF)) 1458 1459 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ 1460 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) 1461 1462 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 1463 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 1464 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 1465 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 1466 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) 1467 1468 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 1469 ((__MODE__) == TIM_OCMODE_PWM2)) 1470 1471 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 1472 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 1473 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 1474 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 1475 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 1476 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) 1477 1478 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 1479 ((__SELECTION__) == TIM_TS_ITR1) || \ 1480 ((__SELECTION__) == TIM_TS_ITR2) || \ 1481 ((__SELECTION__) == TIM_TS_ITR3) || \ 1482 ((__SELECTION__) == TIM_TS_TI1F_ED) || \ 1483 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 1484 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 1485 ((__SELECTION__) == TIM_TS_ETRF)) 1486 1487 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 1488 ((__SELECTION__) == TIM_TS_ITR1) || \ 1489 ((__SELECTION__) == TIM_TS_ITR2) || \ 1490 ((__SELECTION__) == TIM_TS_ITR3) || \ 1491 ((__SELECTION__) == TIM_TS_NONE)) 1492 1493 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 1494 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 1495 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ 1496 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ 1497 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 1498 1499 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ 1500 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ 1501 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ 1502 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 1503 1504 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1505 1506 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ 1507 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 1508 1509 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 1510 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 1511 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 1512 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 1513 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 1514 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 1515 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 1516 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 1517 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 1518 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 1519 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 1520 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 1521 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 1522 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 1523 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 1524 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 1525 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 1526 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) 1527 1528 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) 1529 1530 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1531 1532 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) 1533 1534 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1535 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 1536 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 1537 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 1538 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 1539 1540 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 1541 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ 1542 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ 1543 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ 1544 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) 1545 1546 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1547 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 1548 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 1549 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 1550 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) 1551 1552 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 1553 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 1554 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 1555 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 1556 ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) 1557 1558 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ 1559 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ 1560 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ 1561 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ 1562 (__HANDLE__)->ChannelState[3]) 1563 1564 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 1565 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ 1566 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ 1567 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ 1568 ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) 1569 1570 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 1571 (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ 1572 (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ 1573 (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ 1574 (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ 1575 } while(0) 1576 1577 /** 1578 * @} 1579 */ 1580 /* End of private macros -----------------------------------------------------*/ 1581 1582 /* Include TIM HAL Extended module */ 1583 #include "stm32l0xx_hal_tim_ex.h" 1584 1585 /* Exported functions --------------------------------------------------------*/ 1586 /** @addtogroup TIM_Exported_Functions TIM Exported Functions 1587 * @{ 1588 */ 1589 1590 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions 1591 * @brief Time Base functions 1592 * @{ 1593 */ 1594 /* Time Base functions ********************************************************/ 1595 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 1596 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 1597 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 1598 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 1599 /* Blocking mode: Polling */ 1600 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 1601 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 1602 /* Non-Blocking mode: Interrupt */ 1603 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 1604 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 1605 /* Non-Blocking mode: DMA */ 1606 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); 1607 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 1608 /** 1609 * @} 1610 */ 1611 1612 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions 1613 * @brief TIM Output Compare functions 1614 * @{ 1615 */ 1616 /* Timer Output Compare functions *********************************************/ 1617 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 1618 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 1619 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 1620 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 1621 /* Blocking mode: Polling */ 1622 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1623 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1624 /* Non-Blocking mode: Interrupt */ 1625 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1626 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1627 /* Non-Blocking mode: DMA */ 1628 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, 1629 uint16_t Length); 1630 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 1631 /** 1632 * @} 1633 */ 1634 1635 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions 1636 * @brief TIM PWM functions 1637 * @{ 1638 */ 1639 /* Timer PWM functions ********************************************************/ 1640 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 1641 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 1642 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 1643 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 1644 /* Blocking mode: Polling */ 1645 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1646 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1647 /* Non-Blocking mode: Interrupt */ 1648 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1649 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1650 /* Non-Blocking mode: DMA */ 1651 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, 1652 uint16_t Length); 1653 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 1654 /** 1655 * @} 1656 */ 1657 1658 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions 1659 * @brief TIM Input Capture functions 1660 * @{ 1661 */ 1662 /* Timer Input Capture functions **********************************************/ 1663 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 1664 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 1665 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 1666 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 1667 /* Blocking mode: Polling */ 1668 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1669 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1670 /* Non-Blocking mode: Interrupt */ 1671 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1672 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1673 /* Non-Blocking mode: DMA */ 1674 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 1675 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 1676 /** 1677 * @} 1678 */ 1679 1680 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions 1681 * @brief TIM One Pulse functions 1682 * @{ 1683 */ 1684 /* Timer One Pulse functions **************************************************/ 1685 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 1686 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 1687 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 1688 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 1689 /* Blocking mode: Polling */ 1690 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1691 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1692 /* Non-Blocking mode: Interrupt */ 1693 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1694 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1695 /** 1696 * @} 1697 */ 1698 1699 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions 1700 * @brief TIM Encoder functions 1701 * @{ 1702 */ 1703 /* Timer Encoder functions ****************************************************/ 1704 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); 1705 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 1706 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 1707 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 1708 /* Blocking mode: Polling */ 1709 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1710 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1711 /* Non-Blocking mode: Interrupt */ 1712 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1713 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1714 /* Non-Blocking mode: DMA */ 1715 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, 1716 uint32_t *pData2, uint16_t Length); 1717 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 1718 /** 1719 * @} 1720 */ 1721 1722 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management 1723 * @brief IRQ handler management 1724 * @{ 1725 */ 1726 /* Interrupt Handler functions ***********************************************/ 1727 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 1728 /** 1729 * @} 1730 */ 1731 1732 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions 1733 * @brief Peripheral Control functions 1734 * @{ 1735 */ 1736 /* Control functions *********************************************************/ 1737 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, 1738 uint32_t Channel); 1739 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, 1740 uint32_t Channel); 1741 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, 1742 uint32_t Channel); 1743 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, 1744 uint32_t OutputChannel, uint32_t InputChannel); 1745 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, 1746 const TIM_ClearInputConfigTypeDef *sClearInputConfig, 1747 uint32_t Channel); 1748 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); 1749 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 1750 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); 1751 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); 1752 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 1753 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); 1754 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 1755 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, 1756 uint32_t BurstLength, uint32_t DataLength); 1757 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 1758 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 1759 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 1760 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 1761 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, 1762 uint32_t BurstLength, uint32_t DataLength); 1763 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 1764 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 1765 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); 1766 /** 1767 * @} 1768 */ 1769 1770 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 1771 * @brief TIM Callbacks functions 1772 * @{ 1773 */ 1774 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 1775 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 1776 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); 1777 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 1778 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 1779 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); 1780 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 1781 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); 1782 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 1783 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); 1784 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 1785 1786 /* Callbacks Register/UnRegister functions ***********************************/ 1787 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 1788 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, 1789 pTIM_CallbackTypeDef pCallback); 1790 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); 1791 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 1792 1793 /** 1794 * @} 1795 */ 1796 1797 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions 1798 * @brief Peripheral State functions 1799 * @{ 1800 */ 1801 /* Peripheral State functions ************************************************/ 1802 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); 1803 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); 1804 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); 1805 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); 1806 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); 1807 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); 1808 1809 /* Peripheral Channel state functions ************************************************/ 1810 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); 1811 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); 1812 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); 1813 /** 1814 * @} 1815 */ 1816 1817 /** 1818 * @} 1819 */ 1820 /* End of exported functions -------------------------------------------------*/ 1821 1822 /* Private functions----------------------------------------------------------*/ 1823 /** @defgroup TIM_Private_Functions TIM Private Functions 1824 * @{ 1825 */ 1826 void TIM_DMAError(DMA_HandleTypeDef *hdma); 1827 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 1828 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); 1829 1830 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 1831 void TIM_ResetCallback(TIM_HandleTypeDef *htim); 1832 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 1833 1834 /** 1835 * @} 1836 */ 1837 /* End of private functions --------------------------------------------------*/ 1838 1839 /** 1840 * @} 1841 */ 1842 1843 /** 1844 * @} 1845 */ 1846 1847 #ifdef __cplusplus 1848 } 1849 #endif 1850 1851 #endif /* STM32L0xx_HAL_TIM_H */ 1852
