1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal_pwr.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32L0xx_HAL_PWR_H 21 #define __STM32L0xx_HAL_PWR_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l0xx_hal_def.h" 29 30 /** @addtogroup STM32L0xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @defgroup PWR PWR 35 * @{ 36 */ 37 38 /** @defgroup PWR_Exported_Types PWR Exported Types 39 * @{ 40 */ 41 42 #if defined(PWR_PVD_SUPPORT) 43 /** 44 * @brief PWR PVD configuration structure definition 45 */ 46 typedef struct 47 { 48 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. 49 This parameter can be a value of @ref PWR_PVD_detection_level */ 50 51 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. 52 This parameter can be a value of @ref PWR_PVD_Mode */ 53 }PWR_PVDTypeDef; 54 #endif 55 56 /** 57 * @} 58 */ 59 60 /** @addtogroup PWR_Private 61 * @{ 62 */ 63 64 #if defined(PWR_PVD_SUPPORT) 65 #define PWR_EXTI_LINE_PVD EXTI_FTSR_TR16 /*!< External interrupt line 16 Connected to the PVD EXTI Line */ 66 #endif 67 68 /** 69 * @} 70 */ 71 72 /** @defgroup PWR_Exported_Constants PWR Exported Constants 73 * @{ 74 */ 75 76 /** @defgroup PWR_register_alias_address PWR Register alias address 77 * @{ 78 */ 79 #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1 80 #if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx) 81 #else 82 #define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2 83 #endif 84 #if defined (STM32L010x4) || defined (STM32L010x6) || defined (STM32L011xx) || defined (STM32L021xx) || \ 85 defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L071xx) || defined (STM32L072xx) || \ 86 defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) 87 #define PWR_WAKEUP_PIN3 PWR_CSR_EWUP3 88 #endif 89 /** 90 * @} 91 */ 92 93 #if defined(PWR_PVD_SUPPORT) 94 /** @defgroup PWR_PVD_detection_level PVD detection level 95 * @{ 96 */ 97 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 98 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 99 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 100 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 101 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 102 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 103 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 104 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage 105 (Compare internally to VREFINT) */ 106 /** 107 * @} 108 */ 109 110 /** @defgroup PWR_PVD_Mode PWR PVD Mode 111 * @{ 112 */ 113 #define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< basic mode is used */ 114 #define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ 115 #define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ 116 #define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 117 #define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ 118 #define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ 119 #define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ 120 /** 121 * @} 122 */ 123 #endif /* PWR_PVD_SUPPORT */ 124 125 /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode 126 * @{ 127 */ 128 #define PWR_MAINREGULATOR_ON (0x00000000U) 129 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR 130 131 /** 132 * @} 133 */ 134 135 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry 136 * @{ 137 */ 138 #define PWR_SLEEPENTRY_WFI (0x01U) 139 #define PWR_SLEEPENTRY_WFE (0x02U) 140 /** 141 * @} 142 */ 143 144 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry 145 * @{ 146 */ 147 #define PWR_STOPENTRY_WFI (0x01U) 148 #define PWR_STOPENTRY_WFE (0x02U) 149 /** 150 * @} 151 */ 152 153 /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale 154 * @{ 155 */ 156 157 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0 158 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 159 #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS 160 161 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ 162 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ 163 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) 164 /** 165 * @} 166 */ 167 168 /** @defgroup PWR_Flag PWR Flag 169 * @{ 170 */ 171 #define PWR_FLAG_WU PWR_CSR_WUF 172 #define PWR_FLAG_SB PWR_CSR_SBF 173 #if defined(PWR_PVD_SUPPORT) 174 #define PWR_FLAG_PVDO PWR_CSR_PVDO 175 #endif 176 #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF 177 #define PWR_FLAG_VOS PWR_CSR_VOSF 178 #define PWR_FLAG_REGLP PWR_CSR_REGLPF 179 180 181 /** 182 * @} 183 */ 184 185 /** 186 * @} 187 */ 188 189 /** @defgroup PWR_Exported_Macro PWR Exported Macros 190 * @{ 191 */ 192 /** @brief macros configure the main internal regulator output voltage. 193 * When exiting Low Power Run Mode or during dynamic voltage scaling configuration, 194 * the reference manual recommends to poll PWR_FLAG_REGLP bit to wait for the regulator 195 * to reach main mode (resp. to get stabilized) for a transition from 0 to 1. 196 * Only then the clock can be increased. 197 * 198 * @param __REGULATOR__ specifies the regulator output voltage to achieve 199 * a tradeoff between performance and power consumption when the device does 200 * not operate at the maximum frequency (refer to the datasheets for more details). 201 * This parameter can be one of the following values: 202 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode, 203 * System frequency up to 32 MHz. 204 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode, 205 * System frequency up to 16 MHz. 206 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode, 207 * System frequency up to 4.2 MHz 208 * @retval None 209 */ 210 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__))) 211 212 /** @brief Check PWR flag is set or not. 213 * @param __FLAG__ specifies the flag to check. 214 * This parameter can be one of the following values: 215 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 216 * was received from the WKUP pin or from the RTC alarm (Alarm B), 217 * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. 218 * An additional wakeup event is detected if the WKUP pin is enabled 219 * (by setting the EWUP bit) when the WKUP pin level is already high. 220 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was 221 * resumed from StandBy mode. 222 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 223 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode. 224 * For this reason, this bit is equal to 0 after Standby or reset 225 * until the PVDE bit is set. Not available on L0 Value line. 226 * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag. 227 * This bit indicates the state of the internal voltage reference, VREFINT. 228 * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for 229 * the internal regulator to be ready after the voltage range is changed. 230 * The VOSF bit indicates that the regulator has reached the voltage level 231 * defined with bits VOS of PWR_CR register. 232 * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run 233 * mode, this bit stays at 1 until the regulator is ready in main mode. 234 * A polling on this bit is recommended to wait for the regulator main mode. 235 * This bit is reset by hardware when the regulator is ready. 236 * @retval The new state of __FLAG__ (TRUE or FALSE). 237 */ 238 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) 239 240 /** @brief Clear the PWR pending flags. 241 * @param __FLAG__ specifies the flag to clear. 242 * This parameter can be one of the following values: 243 * @arg PWR_FLAG_WU: Wake Up flag 244 * @arg PWR_FLAG_SB: StandBy flag 245 */ 246 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, (__FLAG__) << 2U) 247 248 #if defined(PWR_PVD_SUPPORT) 249 /** 250 * @brief Enable interrupt on PVD Exti Line 16. 251 * @retval None. 252 */ 253 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) 254 255 /** 256 * @brief Disable interrupt on PVD Exti Line 16. 257 * @retval None. 258 */ 259 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) 260 261 /** 262 * @brief Enable event on PVD Exti Line 16. 263 * @retval None. 264 */ 265 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) 266 267 /** 268 * @brief Disable event on PVD Exti Line 16. 269 * @retval None. 270 */ 271 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) 272 273 /** 274 * @brief PVD EXTI line configuration: set falling edge trigger. 275 * @retval None. 276 */ 277 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) 278 279 /** 280 * @brief Disable the PVD Extended Interrupt Falling Trigger. 281 * @retval None. 282 */ 283 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) 284 285 /** 286 * @brief PVD EXTI line configuration: set rising edge trigger. 287 * @retval None. 288 */ 289 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) 290 291 /** 292 * @brief Disable the PVD Extended Interrupt Rising Trigger. 293 * This parameter can be: 294 * @retval None. 295 */ 296 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) 297 298 /** 299 * @brief PVD EXTI line configuration: set rising & falling edge trigger. 300 * @retval None. 301 */ 302 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } while(0); 303 304 /** 305 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. 306 * This parameter can be: 307 * @retval None. 308 */ 309 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0); 310 311 /** 312 * @brief Check whether the specified PVD EXTI interrupt flag is set or not. 313 * @retval EXTI PVD Line Status. 314 */ 315 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) 316 317 /** 318 * @brief Clear the PVD EXTI flag. 319 * @retval None. 320 */ 321 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) 322 323 /** 324 * @brief Generate a Software interrupt on selected EXTI line. 325 * @retval None. 326 */ 327 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) 328 329 #endif /* PWR_PVD_SUPPORT */ 330 331 /** 332 * @} 333 */ 334 335 /** @addtogroup PWR_Private 336 * @{ 337 */ 338 #if defined(PWR_PVD_SUPPORT) 339 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ 340 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ 341 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ 342 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) 343 344 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ 345 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ 346 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ 347 ((MODE) == PWR_PVD_MODE_NORMAL)) 348 #endif /* PWR_PVD_SUPPORT */ 349 350 #if defined (STM32L010x6) || defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) 351 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ 352 ((PIN) == PWR_WAKEUP_PIN2) || \ 353 ((PIN) == PWR_WAKEUP_PIN3)) 354 #elif defined (STM32L010xB) || defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L062xx) || defined (STM32L063xx) 355 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ 356 ((PIN) == PWR_WAKEUP_PIN2)) 357 #elif defined (STM32L010x8) || defined (STM32L031xx) || defined (STM32L041xx) 358 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ 359 ((PIN) == PWR_WAKEUP_PIN2)) 360 #elif defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx) 361 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ 362 ((PIN) == PWR_WAKEUP_PIN3)) 363 #endif 364 365 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ 366 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) 367 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) 368 369 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) 370 371 /** 372 * @} 373 */ 374 375 /* Include PWR HAL Extension module */ 376 #include "stm32l0xx_hal_pwr_ex.h" 377 378 /** @defgroup PWR_Exported_Functions PWR Exported Functions 379 * @{ 380 */ 381 382 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 383 * @{ 384 */ 385 void HAL_PWR_DeInit(void); 386 void HAL_PWR_EnableBkUpAccess(void); 387 void HAL_PWR_DisableBkUpAccess(void); 388 /** 389 * @} 390 */ 391 392 /** @defgroup PWR_Exported_Functions_Group2 Low Power modes configuration functions 393 * @{ 394 */ 395 396 #if defined(PWR_PVD_SUPPORT) 397 /* PVD control functions ************************************************/ 398 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); 399 void HAL_PWR_EnablePVD(void); 400 void HAL_PWR_DisablePVD(void); 401 void HAL_PWR_PVD_IRQHandler(void); 402 void HAL_PWR_PVDCallback(void); 403 #endif 404 405 /* WakeUp pins configuration functions ****************************************/ 406 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); 407 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); 408 409 /* Low Power modes configuration functions ************************************/ 410 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); 411 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); 412 void HAL_PWR_EnterSTANDBYMode(void); 413 414 void HAL_PWR_EnableSleepOnExit(void); 415 void HAL_PWR_DisableSleepOnExit(void); 416 void HAL_PWR_EnableSEVOnPend(void); 417 void HAL_PWR_DisableSEVOnPend(void); 418 419 /** 420 * @} 421 */ 422 423 /** 424 * @} 425 */ 426 427 /* Define the private group ***********************************/ 428 /**************************************************************/ 429 /** @defgroup PWR_Private PWR Private 430 * @{ 431 */ 432 /** 433 * @} 434 */ 435 /**************************************************************/ 436 437 /** 438 * @} 439 */ 440 441 /** 442 * @} 443 */ 444 445 #ifdef __cplusplus 446 } 447 #endif 448 449 450 #endif /* __STM32L0xx_HAL_PWR_H */ 451
