1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L0xx_HAL_DMA_H 21 #define STM32L0xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l0xx_hal_def.h" 29 30 /** @addtogroup STM32L0xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup DMA_Exported_Types DMA Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief DMA Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Request; /*!< Specifies the request selected for the specified channel. 49 This parameter can be a value of @ref DMA_request */ 50 51 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 52 from memory to memory or from peripheral to memory. 53 This parameter can be a value of @ref DMA_Data_transfer_direction */ 54 55 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 56 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 57 58 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 59 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 60 61 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 62 This parameter can be a value of @ref DMA_Peripheral_data_size */ 63 64 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 65 This parameter can be a value of @ref DMA_Memory_data_size */ 66 67 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 68 This parameter can be a value of @ref DMA_mode 69 @note The circular buffer mode cannot be used if the memory-to-memory 70 data transfer is configured on the selected Channel */ 71 72 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 73 This parameter can be a value of @ref DMA_Priority_level */ 74 } DMA_InitTypeDef; 75 76 /** 77 * @brief HAL DMA State structures definition 78 */ 79 typedef enum 80 { 81 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 82 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 83 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 84 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 85 }HAL_DMA_StateTypeDef; 86 87 /** 88 * @brief HAL DMA Error Code structure definition 89 */ 90 typedef enum 91 { 92 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 93 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 94 }HAL_DMA_LevelCompleteTypeDef; 95 96 97 /** 98 * @brief HAL DMA Callback ID structure definition 99 */ 100 typedef enum 101 { 102 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 103 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 104 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 105 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 106 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 107 }HAL_DMA_CallbackIDTypeDef; 108 109 /** 110 * @brief DMA handle Structure definition 111 */ 112 typedef struct __DMA_HandleTypeDef 113 { 114 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 115 116 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 117 118 HAL_LockTypeDef Lock; /*!< DMA locking object */ 119 120 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 121 122 void *Parent; /*!< Parent object state */ 123 124 void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 125 126 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 127 128 void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 129 130 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ 131 132 __IO uint32_t ErrorCode; /*!< DMA Error code */ 133 134 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 135 136 uint32_t ChannelIndex; /*!< DMA Channel Index */ 137 138 }DMA_HandleTypeDef; 139 140 /** 141 * @} 142 */ 143 144 /* Exported constants --------------------------------------------------------*/ 145 146 /** @defgroup DMA_Exported_Constants DMA Exported Constants 147 * @{ 148 */ 149 150 /** @defgroup DMA_Error_Code DMA Error Code 151 * @{ 152 */ 153 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 154 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 155 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ 156 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 157 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 158 159 /** 160 * @} 161 */ 162 163 /** @defgroup DMA_request DMA request 164 * @{ 165 */ 166 167 #if defined (STM32L010x4) || defined (STM32L010x6) || defined (STM32L010x8) || defined (STM32L010xC) 168 169 #define DMA_REQUEST_0 0U 170 #define DMA_REQUEST_1 1U 171 #define DMA_REQUEST_4 4U 172 #define DMA_REQUEST_5 5U 173 #define DMA_REQUEST_6 6U 174 #define DMA_REQUEST_8 8U 175 176 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ 177 ((REQUEST) == DMA_REQUEST_1) || \ 178 ((REQUEST) == DMA_REQUEST_4) || \ 179 ((REQUEST) == DMA_REQUEST_5) || \ 180 ((REQUEST) == DMA_REQUEST_6) || \ 181 ((REQUEST) == DMA_REQUEST_8)) 182 183 /* STM32L010x4 || STM32L010x6 || STM32L010x8 || STM32L010xC */ 184 185 #elif defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) 186 187 #define DMA_REQUEST_0 0U 188 #define DMA_REQUEST_1 1U 189 #define DMA_REQUEST_2 2U 190 #define DMA_REQUEST_3 3U 191 #define DMA_REQUEST_4 4U 192 #define DMA_REQUEST_5 5U 193 #define DMA_REQUEST_6 6U 194 #define DMA_REQUEST_7 7U 195 #define DMA_REQUEST_8 8U 196 #define DMA_REQUEST_9 9U 197 #define DMA_REQUEST_10 10U 198 #define DMA_REQUEST_11 11U /* AES product only */ 199 #define DMA_REQUEST_12 12U 200 #define DMA_REQUEST_13 13U 201 #define DMA_REQUEST_14 14U 202 #define DMA_REQUEST_15 15U 203 204 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ 205 ((REQUEST) == DMA_REQUEST_1) || \ 206 ((REQUEST) == DMA_REQUEST_2) || \ 207 ((REQUEST) == DMA_REQUEST_3) || \ 208 ((REQUEST) == DMA_REQUEST_4) || \ 209 ((REQUEST) == DMA_REQUEST_5) || \ 210 ((REQUEST) == DMA_REQUEST_6) || \ 211 ((REQUEST) == DMA_REQUEST_7) || \ 212 ((REQUEST) == DMA_REQUEST_8) || \ 213 ((REQUEST) == DMA_REQUEST_9) || \ 214 ((REQUEST) == DMA_REQUEST_10) || \ 215 ((REQUEST) == DMA_REQUEST_11) || \ 216 ((REQUEST) == DMA_REQUEST_12) || \ 217 ((REQUEST) == DMA_REQUEST_13) || \ 218 ((REQUEST) == DMA_REQUEST_14) || \ 219 ((REQUEST) == DMA_REQUEST_15)) 220 221 /* (STM32L021xx) || (STM32L041xx) || (STM32L062xx) || (STM32L063xx) || (STM32L081xx) || (STM32L082xx) || (STM32L083xx) */ 222 223 #else 224 225 #define DMA_REQUEST_0 0U 226 #define DMA_REQUEST_1 1U 227 #define DMA_REQUEST_2 2U 228 #define DMA_REQUEST_3 3U 229 #define DMA_REQUEST_4 4U 230 #define DMA_REQUEST_5 5U 231 #define DMA_REQUEST_6 6U 232 #define DMA_REQUEST_7 7U 233 #define DMA_REQUEST_8 8U 234 #define DMA_REQUEST_9 9U 235 #define DMA_REQUEST_10 10U 236 #define DMA_REQUEST_12 12U 237 #define DMA_REQUEST_13 13U 238 #define DMA_REQUEST_14 14U 239 #define DMA_REQUEST_15 15U 240 241 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ 242 ((REQUEST) == DMA_REQUEST_1) || \ 243 ((REQUEST) == DMA_REQUEST_2) || \ 244 ((REQUEST) == DMA_REQUEST_3) || \ 245 ((REQUEST) == DMA_REQUEST_4) || \ 246 ((REQUEST) == DMA_REQUEST_5) || \ 247 ((REQUEST) == DMA_REQUEST_6) || \ 248 ((REQUEST) == DMA_REQUEST_7) || \ 249 ((REQUEST) == DMA_REQUEST_8) || \ 250 ((REQUEST) == DMA_REQUEST_9) || \ 251 ((REQUEST) == DMA_REQUEST_10) || \ 252 ((REQUEST) == DMA_REQUEST_12) || \ 253 ((REQUEST) == DMA_REQUEST_13) || \ 254 ((REQUEST) == DMA_REQUEST_14) || \ 255 ((REQUEST) == DMA_REQUEST_15)) 256 257 #endif /* (STM32L031xx) || (STM32L051xx) || (STM32L052xx) || (STM32L053xx) || (STM32L071xx) || (STM32L072xx) || (STM32L073xx) */ 258 259 260 261 /** 262 * @} 263 */ 264 265 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 266 * @{ 267 */ 268 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 269 #define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ 270 #define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ 271 /** 272 * @} 273 */ 274 275 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 276 * @{ 277 */ 278 #define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ 279 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ 280 /** 281 * @} 282 */ 283 284 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 285 * @{ 286 */ 287 #define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ 288 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ 289 /** 290 * @} 291 */ 292 293 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 294 * @{ 295 */ 296 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 297 #define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 298 #define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 299 /** 300 * @} 301 */ 302 303 /** @defgroup DMA_Memory_data_size DMA Memory data size 304 * @{ 305 */ 306 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 307 #define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 308 #define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ 309 /** 310 * @} 311 */ 312 313 /** @defgroup DMA_mode DMA mode 314 * @{ 315 */ 316 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 317 #define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */ 318 /** 319 * @} 320 */ 321 322 /** @defgroup DMA_Priority_level DMA Priority level 323 * @{ 324 */ 325 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 326 #define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ 327 #define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ 328 #define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */ 329 /** 330 * @} 331 */ 332 333 334 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 335 * @{ 336 */ 337 #define DMA_IT_TC DMA_CCR_TCIE 338 #define DMA_IT_HT DMA_CCR_HTIE 339 #define DMA_IT_TE DMA_CCR_TEIE 340 /** 341 * @} 342 */ 343 344 /** @defgroup DMA_flag_definitions DMA flag definitions 345 * @{ 346 */ 347 #define DMA_FLAG_GL1 DMA_ISR_GIF1 348 #define DMA_FLAG_TC1 DMA_ISR_TCIF1 349 #define DMA_FLAG_HT1 DMA_ISR_HTIF1 350 #define DMA_FLAG_TE1 DMA_ISR_TEIF1 351 #define DMA_FLAG_GL2 DMA_ISR_GIF2 352 #define DMA_FLAG_TC2 DMA_ISR_TCIF2 353 #define DMA_FLAG_HT2 DMA_ISR_HTIF2 354 #define DMA_FLAG_TE2 DMA_ISR_TEIF2 355 #define DMA_FLAG_GL3 DMA_ISR_GIF3 356 #define DMA_FLAG_TC3 DMA_ISR_TCIF3 357 #define DMA_FLAG_HT3 DMA_ISR_HTIF3 358 #define DMA_FLAG_TE3 DMA_ISR_TEIF3 359 #define DMA_FLAG_GL4 DMA_ISR_GIF4 360 #define DMA_FLAG_TC4 DMA_ISR_TCIF4 361 #define DMA_FLAG_HT4 DMA_ISR_HTIF4 362 #define DMA_FLAG_TE4 DMA_ISR_TEIF4 363 #define DMA_FLAG_GL5 DMA_ISR_GIF5 364 #define DMA_FLAG_TC5 DMA_ISR_TCIF5 365 #define DMA_FLAG_HT5 DMA_ISR_HTIF5 366 #define DMA_FLAG_TE5 DMA_ISR_TEIF5 367 #define DMA_FLAG_GL6 DMA_ISR_GIF6 368 #define DMA_FLAG_TC6 DMA_ISR_TCIF6 369 #define DMA_FLAG_HT6 DMA_ISR_HTIF6 370 #define DMA_FLAG_TE6 DMA_ISR_TEIF6 371 #define DMA_FLAG_GL7 DMA_ISR_GIF7 372 #define DMA_FLAG_TC7 DMA_ISR_TCIF7 373 #define DMA_FLAG_HT7 DMA_ISR_HTIF7 374 #define DMA_FLAG_TE7 DMA_ISR_TEIF7 375 /** 376 * @} 377 */ 378 379 /** 380 * @} 381 */ 382 383 /* Exported macros -----------------------------------------------------------*/ 384 /** @defgroup DMA_Exported_Macros DMA Exported Macros 385 * @{ 386 */ 387 388 /** @brief Reset DMA handle state 389 * @param __HANDLE__ DMA handle 390 * @retval None 391 */ 392 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 393 394 /** 395 * @brief Enable the specified DMA Channel. 396 * @param __HANDLE__ DMA handle 397 * @retval None 398 */ 399 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 400 401 /** 402 * @brief Disable the specified DMA Channel. 403 * @param __HANDLE__ DMA handle 404 * @retval None 405 */ 406 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 407 408 409 /* Interrupt & Flag management */ 410 411 /** 412 * @brief Return the current DMA Channel transfer complete flag. 413 * @param __HANDLE__: DMA handle 414 * @retval The specified transfer complete flag index. 415 */ 416 417 #if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx) 418 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 419 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 420 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 421 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 422 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 423 DMA_FLAG_TC5) 424 #else 425 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 426 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 427 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 428 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 429 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 430 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 431 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 432 DMA_FLAG_TC7) 433 #endif 434 /** 435 * @brief Return the current DMA Channel half transfer complete flag. 436 * @param __HANDLE__ DMA handle 437 * @retval The specified half transfer complete flag index. 438 */ 439 #if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx) 440 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 441 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 442 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 443 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 444 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 445 DMA_FLAG_HT5) 446 #else 447 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 448 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 449 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 450 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 451 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 454 DMA_FLAG_HT7) 455 #endif 456 /** 457 * @brief Returns the current DMA Channel transfer error flag. 458 * @param __HANDLE__ DMA handle 459 * @retval The specified transfer error flag index. 460 */ 461 #if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx) 462 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 463 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 467 DMA_FLAG_TE5) 468 #else 469 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 470 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 476 DMA_FLAG_TE7) 477 #endif 478 /** 479 * @brief Returns the current DMA Channel Global interrupt flag. 480 * @param __HANDLE__ DMA handle 481 * @retval The specified transfer error flag index. 482 */ 483 #if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx) 484 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 485 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 486 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 489 DMA_ISR_GIF5) 490 #else 491 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 492 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ 498 DMA_ISR_GIF7) 499 #endif 500 /** 501 * @brief Get the DMA Channel pending flags. 502 * @param __HANDLE__ DMA handle 503 * @param __FLAG__ Get the specified flag. 504 * This parameter can be any combination of the following values: 505 * @arg DMA_FLAG_TCIFx: Transfer complete flag 506 * @arg DMA_FLAG_HTIFx: Half transfer complete flag 507 * @arg DMA_FLAG_TEIFx: Transfer error flag 508 * @arg DMA_ISR_GIFx: Global interrupt flag 509 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. 510 * @retval The state of FLAG (SET or RESET). 511 */ 512 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) 513 514 /** 515 * @brief Clears the DMA Channel pending flags. 516 * @param __HANDLE__ DMA handle 517 * @param __FLAG__ specifies the flag to clear. 518 * This parameter can be any combination of the following values: 519 * @arg DMA_FLAG_TCx: Transfer complete flag 520 * @arg DMA_FLAG_HTx: Half transfer complete flag 521 * @arg DMA_FLAG_TEx: Transfer error flag 522 * @arg DMA_FLAG_GLx: Global interrupt flag 523 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. 524 * @retval None 525 */ 526 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) 527 528 /** 529 * @brief Enable the specified DMA Channel interrupts. 530 * @param __HANDLE__ DMA handle 531 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 532 * This parameter can be any combination of the following values: 533 * @arg DMA_IT_TC: Transfer complete interrupt mask 534 * @arg DMA_IT_HT: Half transfer complete interrupt mask 535 * @arg DMA_IT_TE: Transfer error interrupt mask 536 * @retval None 537 */ 538 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 539 540 /** 541 * @brief Disable the specified DMA Channel interrupts. 542 * @param __HANDLE__ DMA handle 543 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 544 * This parameter can be any combination of the following values: 545 * @arg DMA_IT_TC: Transfer complete interrupt mask 546 * @arg DMA_IT_HT: Half transfer complete interrupt mask 547 * @arg DMA_IT_TE: Transfer error interrupt mask 548 * @retval None 549 */ 550 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 551 552 /** 553 * @brief Check whether the specified DMA Channel interrupt is enabled or not. 554 * @param __HANDLE__ DMA handle 555 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 556 * This parameter can be one of the following values: 557 * @arg DMA_IT_TC: Transfer complete interrupt mask 558 * @arg DMA_IT_HT: Half transfer complete interrupt mask 559 * @arg DMA_IT_TE: Transfer error interrupt mask 560 * @retval The state of DMA_IT (SET or RESET). 561 */ 562 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 563 564 /** 565 * @brief Return the number of remaining data units in the current DMA Channel transfer. 566 * @param __HANDLE__ DMA handle 567 * @retval The number of remaining data units in the current DMA Channel transfer. 568 */ 569 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 570 571 /** 572 * @} 573 */ 574 575 /* Exported functions --------------------------------------------------------*/ 576 577 /** @addtogroup DMA_Exported_Functions 578 * @{ 579 */ 580 581 /** @addtogroup DMA_Exported_Functions_Group1 582 * @{ 583 */ 584 /* Initialization and de-initialization functions *****************************/ 585 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 586 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); 587 /** 588 * @} 589 */ 590 591 /** @addtogroup DMA_Exported_Functions_Group2 592 * @{ 593 */ 594 /* IO operation functions *****************************************************/ 595 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 596 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 597 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 598 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 599 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 600 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 601 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); 602 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 603 604 /** 605 * @} 606 */ 607 608 /** @addtogroup DMA_Exported_Functions_Group3 609 * @{ 610 */ 611 /* Peripheral State and Error functions ***************************************/ 612 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 613 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 614 /** 615 * @} 616 */ 617 618 /** 619 * @} 620 */ 621 /* Define the private group ***********************************/ 622 /**************************************************************/ 623 /** @defgroup DMA_Private DMA Private 624 * @{ 625 */ 626 627 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 628 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 629 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 630 631 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) 632 633 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 634 ((STATE) == DMA_PINC_DISABLE)) 635 636 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 637 ((STATE) == DMA_MINC_DISABLE)) 638 639 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 640 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 641 ((SIZE) == DMA_PDATAALIGN_WORD)) 642 643 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 644 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 645 ((SIZE) == DMA_MDATAALIGN_WORD )) 646 647 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 648 ((MODE) == DMA_CIRCULAR)) 649 650 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 651 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 652 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 653 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 654 655 /** 656 * @} 657 */ 658 /**************************************************************/ 659 660 /** 661 * @} 662 */ 663 664 /** 665 * @} 666 */ 667 668 #ifdef __cplusplus 669 } 670 #endif 671 672 #endif /* STM32L0xx_HAL_DMA_H */ 673 674
