1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32L0xx_HAL_CORTEX_H 21 #define __STM32L0xx_HAL_CORTEX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l0xx_hal_def.h" 29 30 /** @addtogroup STM32L0xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @defgroup CORTEX CORTEX 35 * @{ 36 */ 37 /* Exported types ------------------------------------------------------------*/ 38 39 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 40 * @{ 41 */ 42 43 #if (__MPU_PRESENT == 1) 44 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 45 * @{ 46 */ 47 typedef struct 48 { 49 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 50 51 uint8_t Enable; /*!< Specifies the status of the region. 52 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 53 uint8_t Number; /*!< Specifies the number of the region to protect. 54 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 55 56 uint8_t Size; /*!< Specifies the size of the region to protect. 57 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 58 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. 59 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 60 uint8_t TypeExtField; /*!< This parameter is NOT used but is kept to keep API unified through all families*/ 61 62 uint8_t AccessPermission; /*!< Specifies the region access permission type. 63 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 64 uint8_t DisableExec; /*!< Specifies the instruction access status. 65 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 66 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 67 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 68 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. 69 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ 70 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. 71 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ 72 }MPU_Region_InitTypeDef; 73 /** 74 * @} 75 */ 76 #endif /* __MPU_PRESENT */ 77 78 /** 79 * @} 80 */ 81 82 83 /* Exported constants --------------------------------------------------------*/ 84 85 /** @defgroup CORTEX_Exported_Constants CORTEx Exported Constants 86 * @{ 87 */ 88 89 90 #define IS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__) ((__PRIORITY__) < 0x10U) 91 92 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x0) 93 94 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick Clock Source 95 * @{ 96 */ 97 #define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U) 98 #define SYSTICK_CLKSOURCE_HCLK (0x00000004U) 99 #define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \ 100 ((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 101 /** 102 * @} 103 */ 104 105 #if (__MPU_PRESENT == 1) 106 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 107 * @{ 108 */ 109 #define MPU_HFNMI_PRIVDEF_NONE (0x00000000U) 110 #define MPU_HARDFAULT_NMI (0x00000002U) 111 #define MPU_PRIVILEGED_DEFAULT (0x00000004U) 112 #define MPU_HFNMI_PRIVDEF (0x00000006U) 113 /** 114 * @} 115 */ 116 117 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 118 * @{ 119 */ 120 #define MPU_REGION_ENABLE ((uint8_t)0x01) 121 #define MPU_REGION_DISABLE ((uint8_t)0x00) 122 /** 123 * @} 124 */ 125 126 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 127 * @{ 128 */ 129 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) 130 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) 131 /** 132 * @} 133 */ 134 135 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 136 * @{ 137 */ 138 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) 139 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) 140 /** 141 * @} 142 */ 143 144 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 145 * @{ 146 */ 147 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) 148 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) 149 /** 150 * @} 151 */ 152 153 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 154 * @{ 155 */ 156 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) 157 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) 158 /** 159 * @} 160 */ 161 162 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 163 * @{ 164 */ 165 #define MPU_REGION_SIZE_32B ((uint8_t)0x04) 166 #define MPU_REGION_SIZE_64B ((uint8_t)0x05) 167 #define MPU_REGION_SIZE_128B ((uint8_t)0x06) 168 #define MPU_REGION_SIZE_256B ((uint8_t)0x07) 169 #define MPU_REGION_SIZE_512B ((uint8_t)0x08) 170 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) 171 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) 172 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) 173 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) 174 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) 175 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) 176 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) 177 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) 178 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) 179 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) 180 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) 181 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) 182 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) 183 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) 184 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) 185 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) 186 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) 187 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) 188 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) 189 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) 190 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) 191 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) 192 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) 193 /** 194 * @} 195 */ 196 197 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 198 * @{ 199 */ 200 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) 201 #define MPU_REGION_PRIV_RW ((uint8_t)0x01) 202 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) 203 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) 204 #define MPU_REGION_PRIV_RO ((uint8_t)0x05) 205 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) 206 /** 207 * @} 208 */ 209 210 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 211 * @{ 212 */ 213 #define MPU_REGION_NUMBER0 ((uint8_t)0x00) 214 #define MPU_REGION_NUMBER1 ((uint8_t)0x01) 215 #define MPU_REGION_NUMBER2 ((uint8_t)0x02) 216 #define MPU_REGION_NUMBER3 ((uint8_t)0x03) 217 #define MPU_REGION_NUMBER4 ((uint8_t)0x04) 218 #define MPU_REGION_NUMBER5 ((uint8_t)0x05) 219 #define MPU_REGION_NUMBER6 ((uint8_t)0x06) 220 #define MPU_REGION_NUMBER7 ((uint8_t)0x07) 221 /** 222 * @} 223 */ 224 #endif /* __MPU_PRESENT */ 225 226 227 /** 228 * @} 229 */ 230 231 /* Exported functions --------------------------------------------------------*/ 232 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 233 * @{ 234 */ 235 236 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 237 * @brief Initialization and Configuration functions 238 * @{ 239 */ 240 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 241 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 242 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 243 void HAL_NVIC_SystemReset(void); 244 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 245 /** 246 * @} 247 */ 248 249 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 250 * @brief Cortex control functions 251 * @{ 252 */ 253 254 uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); 255 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 256 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 257 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 258 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 259 void HAL_SYSTICK_IRQHandler(void); 260 void HAL_SYSTICK_Callback(void); 261 #if (__MPU_PRESENT == 1U) 262 void HAL_MPU_Enable(uint32_t MPU_Control); 263 void HAL_MPU_Disable(void); 264 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); 265 #endif /* __MPU_PRESENT */ 266 /** 267 * @} 268 */ 269 270 /** 271 * @} 272 */ 273 274 /* Private types -------------------------------------------------------------*/ 275 /* Private variables ---------------------------------------------------------*/ 276 /* Private constants ---------------------------------------------------------*/ 277 /* Private macros ------------------------------------------------------------*/ 278 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 279 * @{ 280 */ 281 282 #if (__MPU_PRESENT == 1) 283 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 284 ((STATE) == MPU_REGION_DISABLE)) 285 286 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 287 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 288 289 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ 290 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 291 292 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ 293 ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) 294 295 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ 296 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) 297 298 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ 299 ((TYPE) == MPU_REGION_PRIV_RW) || \ 300 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ 301 ((TYPE) == MPU_REGION_FULL_ACCESS) || \ 302 ((TYPE) == MPU_REGION_PRIV_RO) || \ 303 ((TYPE) == MPU_REGION_PRIV_RO_URO)) 304 305 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 306 ((NUMBER) == MPU_REGION_NUMBER1) || \ 307 ((NUMBER) == MPU_REGION_NUMBER2) || \ 308 ((NUMBER) == MPU_REGION_NUMBER3) || \ 309 ((NUMBER) == MPU_REGION_NUMBER4) || \ 310 ((NUMBER) == MPU_REGION_NUMBER5) || \ 311 ((NUMBER) == MPU_REGION_NUMBER6) || \ 312 ((NUMBER) == MPU_REGION_NUMBER7)) 313 314 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \ 315 ((SIZE) == MPU_REGION_SIZE_512B) || \ 316 ((SIZE) == MPU_REGION_SIZE_1KB) || \ 317 ((SIZE) == MPU_REGION_SIZE_2KB) || \ 318 ((SIZE) == MPU_REGION_SIZE_4KB) || \ 319 ((SIZE) == MPU_REGION_SIZE_8KB) || \ 320 ((SIZE) == MPU_REGION_SIZE_16KB) || \ 321 ((SIZE) == MPU_REGION_SIZE_32KB) || \ 322 ((SIZE) == MPU_REGION_SIZE_64KB) || \ 323 ((SIZE) == MPU_REGION_SIZE_128KB) || \ 324 ((SIZE) == MPU_REGION_SIZE_256KB) || \ 325 ((SIZE) == MPU_REGION_SIZE_512KB) || \ 326 ((SIZE) == MPU_REGION_SIZE_1MB) || \ 327 ((SIZE) == MPU_REGION_SIZE_2MB) || \ 328 ((SIZE) == MPU_REGION_SIZE_4MB) || \ 329 ((SIZE) == MPU_REGION_SIZE_8MB) || \ 330 ((SIZE) == MPU_REGION_SIZE_16MB) || \ 331 ((SIZE) == MPU_REGION_SIZE_32MB) || \ 332 ((SIZE) == MPU_REGION_SIZE_64MB) || \ 333 ((SIZE) == MPU_REGION_SIZE_128MB) || \ 334 ((SIZE) == MPU_REGION_SIZE_256MB) || \ 335 ((SIZE) == MPU_REGION_SIZE_512MB) || \ 336 ((SIZE) == MPU_REGION_SIZE_1GB) || \ 337 ((SIZE) == MPU_REGION_SIZE_2GB) || \ 338 ((SIZE) == MPU_REGION_SIZE_4GB)) 339 340 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) 341 #endif /* __MPU_PRESENT */ 342 343 344 /** 345 * @} 346 */ 347 348 /** 349 * @} 350 */ 351 352 /** 353 * @} 354 */ 355 356 #ifdef __cplusplus 357 } 358 #endif 359 360 #endif /* __STM32L0xx_HAL_CORTEX_H */ 361 362 363 364 365
