1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32L0xx_HAL_ADC_H 21 #define __STM32L0xx_HAL_ADC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l0xx_hal_def.h" 29 30 /** @addtogroup STM32L0xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup ADC 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup ADC_Exported_Types ADC Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief ADC group regular oversampling structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Ratio; /*!< Configures the oversampling ratio. 49 This parameter can be a value of @ref ADC_Oversampling_Ratio */ 50 51 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 52 This parameter can be a value of @ref ADC_Right_Bit_Shift */ 53 54 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 55 This parameter can be a value of @ref ADC_Triggered_Oversampling_Mode */ 56 } ADC_OversamplingTypeDef; 57 58 /** 59 * @brief Structure definition of ADC instance and ADC group regular. 60 * @note Parameters of this structure are shared within 2 scopes: 61 * - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, 62 * ScanConvMode, EOCSelection, LowPowerAutoWait. 63 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, 64 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. 65 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 66 * ADC state can be either: 67 * - For all parameters: ADC disabled 68 * - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on group regular. 69 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 70 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter 71 * (which fulfills the ADC state condition) on the fly). 72 */ 73 typedef struct 74 { 75 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator) and clock prescaler. 76 This parameter can be a value of @ref ADC_ClockPrescaler. 77 Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only 78 if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC 79 must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. 80 Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level. 81 Note: This parameter can be modified only if the ADC is disabled. */ 82 83 uint32_t Resolution; /*!< Configure the ADC resolution. 84 This parameter can be a value of @ref ADC_Resolution */ 85 86 uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). 87 Refer to reference manual for alignments formats versus resolutions. 88 This parameter can be a value of @ref ADC_Data_align */ 89 90 uint32_t ScanConvMode; /*!< Configure the sequencer of regular group. 91 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 92 Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices): 93 If only 1 channel is set: Conversion is performed in single mode. 94 If several channels are set: Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 95 Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0). 96 This parameter can be a value of @ref ADC_Scan_mode */ 97 98 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. 99 This parameter can be a value of @ref ADC_EOCSelection. */ 100 101 uint32_t LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous 102 conversion (for ADC group regular) has been retrieved by user software, 103 using function HAL_ADC_GetValue(). 104 This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun 105 for low frequency applications. 106 This parameter can be set to ENABLE or DISABLE. 107 Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag 108 to free the IRQ vector sequencer. 109 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: 110 use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. */ 111 112 uint32_t LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). 113 This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). 114 This parameter can be set to ENABLE or DISABLE. 115 Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */ 116 117 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, 118 after the first ADC conversion start trigger occurred (software start or external trigger). 119 This parameter can be set to ENABLE or DISABLE. */ 120 121 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence 122 (main sequence subdivided in successive parts). 123 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 124 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 125 This parameter can be set to ENABLE or DISABLE. 126 Note: On this STM32 series, ADC group regular number of discontinuous ranks increment is fixed to one-by-one. */ 127 128 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. 129 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 130 This parameter can be a value of @ref ADC_regular_external_trigger_source. 131 Caution: external trigger source is common to all ADC instances. */ 132 133 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. 134 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 135 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 136 137 FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) 138 or in continuous mode (DMA transfer unlimited, whatever number of conversions). 139 This parameter can be set to ENABLE or DISABLE. 140 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */ 141 142 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 143 This parameter can be a value of @ref ADC_Overrun. 144 Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear 145 end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function 146 HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). 147 Note: Error reporting with respect to the conversion mode: 148 - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data 149 overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. 150 - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ 151 152 uint32_t LowPowerFrequencyMode; /*!< When selecting an analog ADC clock frequency lower than 2.8MHz, 153 it is mandatory to first enable the Low Frequency Mode. 154 This parameter can be set to ENABLE or DISABLE. 155 Note: This parameter can be modified only if there is no conversion is ongoing. */ 156 157 158 uint32_t SamplingTime; /*!< The sample time common to all channels. 159 Unit: ADC clock cycles 160 This parameter can be a value of @ref ADC_sampling_times 161 Note: This parameter can be modified only if there is no conversion ongoing. */ 162 163 uint32_t OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 164 This parameter can be set to ENABLE or DISABLE. 165 Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */ 166 167 168 ADC_OversamplingTypeDef Oversample; /*!< Specify the Oversampling parameters 169 Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ 170 } ADC_InitTypeDef; 171 172 /** 173 * @brief Structure definition of ADC channel for regular group 174 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 175 * ADC state can be either: 176 * - For all parameters: ADC disabled or enabled without conversion on going on regular group. 177 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 178 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 179 */ 180 typedef struct 181 { 182 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 183 This parameter can be a value of @ref ADC_channels 184 Note: Depending on devices, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 185 186 uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer. 187 On STM32L0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number 188 (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 189 Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer. 190 This parameter can be a value of @ref ADC_rank */ 191 } ADC_ChannelConfTypeDef; 192 193 /** 194 * @brief Structure definition of ADC analog watchdog 195 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 196 * ADC state can be either: 197 * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC group regular 198 * - For parameters 'HighThreshold' and 'LowThreshold': ADC enabled with conversion on going on regular group (AWD thresholds can be modify on the fly while ADC conversion is on going) 199 */ 200 typedef struct 201 { 202 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all channels. 203 This parameter can be a value of @ref ADC_analog_watchdog_mode */ 204 205 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 206 This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) 207 This parameter can be a value of @ref ADC_channels */ 208 209 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 210 This parameter can be set to ENABLE or DISABLE */ 211 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. 212 Depending of ADC resolution selected (12, 10, 8 or 6 bits), 213 this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ 214 215 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. 216 Depending of ADC resolution selected (12, 10, 8 or 6 bits), 217 this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ 218 } ADC_AnalogWDGConfTypeDef; 219 220 /** 221 * @brief HAL ADC state machine: ADC states definition (bitfields) 222 * @note ADC state machine is managed by bitfields, state must be compared 223 * with bit by bit. 224 * For example: 225 * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " 226 * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " 227 */ 228 /* States of ADC global scope */ 229 #define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */ 230 #define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */ 231 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy due to an internal process (initialization, calibration) */ 232 #define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */ 233 234 /* States of ADC errors */ 235 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */ 236 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */ 237 #define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */ 238 239 /* States of ADC group regular */ 240 #define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, 241 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 242 #define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */ 243 #define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */ 244 #define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< Not available on this STM32 series: End Of Sampling flag raised */ 245 246 /* States of ADC group injected */ 247 #define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< Not available on this STM32 series: A conversion on group injected is ongoing or can occur (either by auto-injection mode, 248 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 249 #define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Not available on this STM32 series: Conversion data available on group injected */ 250 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Not available on this STM32 series: Injected queue overflow occurrence */ 251 252 /* States of ADC analog watchdogs */ 253 #define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 254 #define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Not available on this STM32 series: Out-of-window occurrence of ADC analog watchdog 2 */ 255 #define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Not available on this STM32 series: Out-of-window occurrence of ADC analog watchdog 3 */ 256 257 /* States of ADC multi-mode */ 258 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< Not available on this STM32 series: ADC in multimode slave state, controlled by another ADC master (when feature available) */ 259 260 261 262 /** 263 * @brief ADC handle Structure definition 264 */ 265 typedef struct __ADC_HandleTypeDef 266 { 267 ADC_TypeDef *Instance; /*!< Register base address */ 268 269 ADC_InitTypeDef Init; /*!< ADC required parameters */ 270 271 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 272 273 HAL_LockTypeDef Lock; /*!< ADC locking object */ 274 275 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 276 277 __IO uint32_t ErrorCode; /*!< ADC Error code */ 278 279 280 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 281 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 282 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ 283 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 284 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 285 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 286 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 287 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 288 } ADC_HandleTypeDef; 289 290 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 291 /** 292 * @brief HAL ADC Callback ID enumeration definition 293 */ 294 typedef enum 295 { 296 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 297 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 298 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 299 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 300 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 301 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 302 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 303 } HAL_ADC_CallbackIDTypeDef; 304 305 /** 306 * @brief HAL ADC Callback pointer definition 307 */ 308 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 309 310 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 311 312 /** 313 * @} 314 */ 315 316 317 /* Exported constants --------------------------------------------------------*/ 318 319 /** @defgroup ADC_Exported_Constants ADC Exported Constants 320 * @{ 321 */ 322 323 /** @defgroup ADC_Error_Code ADC Error Code 324 * @{ 325 */ 326 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 327 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, 328 enable/disable, erroneous state, ...) */ 329 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 330 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 331 332 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 333 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 334 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 335 /** 336 * @} 337 */ 338 339 /** @defgroup ADC_TimeOut_Values ADC TimeOut Values 340 * @{ 341 */ 342 343 /* Fixed timeout values for ADC calibration, enable settling time, disable */ 344 /* settling time. */ 345 /* Values defined to be higher than worst cases: low clocks freq, */ 346 /* maximum prescalers. */ 347 /* Unit: ms */ 348 #define ADC_ENABLE_TIMEOUT 10U 349 #define ADC_DISABLE_TIMEOUT 10U 350 #define ADC_STOP_CONVERSION_TIMEOUT 10U 351 352 /* Delay of 10us fixed to worst case: maximum CPU frequency 180MHz to have */ 353 /* the minimum number of CPU cycles to fulfill this delay */ 354 #define ADC_DELAY_10US_MIN_CPU_CYCLES 1800U 355 /** 356 * @} 357 */ 358 359 /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler 360 * @{ 361 */ 362 #define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC Asynchronous clock mode divided by 1 */ 363 #define ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ 364 #define ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */ 365 #define ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ 366 #define ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC Asynchronous clock mode divided by 2 */ 367 #define ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ 368 #define ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */ 369 #define ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ 370 #define ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC Asynchronous clock mode divided by 2 */ 371 #define ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ 372 #define ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */ 373 #define ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ 374 375 #define ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE) /*!< Synchronous clock mode divided by 1 376 This configuration must be enabled only if PCLK has a 50% 377 duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock 378 must by 50% duty cycle)*/ 379 #define ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< Synchronous clock mode divided by 2 */ 380 #define ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< Synchronous clock mode divided by 4 */ 381 382 /** 383 * @} 384 */ 385 386 /** @defgroup ADC_Resolution ADC Resolution 387 * @{ 388 */ 389 #define ADC_RESOLUTION_12B (0x00000000U) /*!< ADC 12-bit resolution */ 390 #define ADC_RESOLUTION_10B (ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */ 391 #define ADC_RESOLUTION_8B (ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */ 392 #define ADC_RESOLUTION_6B (ADC_CFGR1_RES) /*!< ADC 6-bit resolution */ 393 /** 394 * @} 395 */ 396 397 /** @defgroup ADC_Data_align ADC conversion data alignment 398 * @{ 399 */ 400 #define ADC_DATAALIGN_RIGHT (0x00000000U) 401 #define ADC_DATAALIGN_LEFT (ADC_CFGR1_ALIGN) 402 /** 403 * @} 404 */ 405 406 /** @defgroup ADC_regular_external_trigger_edge ADC External Trigger Source Edge for Regular Group 407 * @{ 408 */ 409 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U) 410 #define ADC_EXTERNALTRIGCONVEDGE_RISING (ADC_CFGR1_EXTEN_0) 411 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (ADC_CFGR1_EXTEN_1) 412 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (ADC_CFGR1_EXTEN) 413 /** 414 * @} 415 */ 416 417 /** @defgroup ADC_EOCSelection ADC EOC Selection 418 * @{ 419 */ 420 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) 421 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) 422 /** 423 * @} 424 */ 425 426 /** @defgroup ADC_Overrun ADC Overrun 427 * @{ 428 */ 429 #define ADC_OVR_DATA_PRESERVED (0x00000000U) 430 #define ADC_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) 431 /** 432 * @} 433 */ 434 435 436 /** @defgroup ADC_rank ADC rank 437 * @{ 438 */ 439 #define ADC_RANK_CHANNEL_NUMBER (0x00001000U) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ 440 #define ADC_RANK_NONE (0x00001001U) /*!< Disable the selected rank (selected channel) from sequencer */ 441 /** 442 * @} 443 */ 444 445 446 /** @defgroup ADC_channels ADC_Channels 447 * @{ 448 */ 449 #define ADC_CHANNEL_0 (ADC_CHSELR_CHSEL0) 450 #define ADC_CHANNEL_1 ((uint32_t)(ADC_CHSELR_CHSEL1) | ADC_CFGR1_AWDCH_0) 451 #define ADC_CHANNEL_2 ((uint32_t)(ADC_CHSELR_CHSEL2) | ADC_CFGR1_AWDCH_1) 452 #define ADC_CHANNEL_3 ((uint32_t)(ADC_CHSELR_CHSEL3)| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0) 453 #define ADC_CHANNEL_4 ((uint32_t)(ADC_CHSELR_CHSEL4)| ADC_CFGR1_AWDCH_2) 454 #define ADC_CHANNEL_5 ((uint32_t)(ADC_CHSELR_CHSEL5)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0) 455 #define ADC_CHANNEL_6 ((uint32_t)(ADC_CHSELR_CHSEL6)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1) 456 #define ADC_CHANNEL_7 ((uint32_t)(ADC_CHSELR_CHSEL7)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0) 457 #define ADC_CHANNEL_8 ((uint32_t)(ADC_CHSELR_CHSEL8)| ADC_CFGR1_AWDCH_3) 458 #define ADC_CHANNEL_9 ((uint32_t)(ADC_CHSELR_CHSEL9)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_0) 459 #define ADC_CHANNEL_10 ((uint32_t)(ADC_CHSELR_CHSEL10)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1) 460 #define ADC_CHANNEL_11 ((uint32_t)(ADC_CHSELR_CHSEL11)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0) 461 #define ADC_CHANNEL_12 ((uint32_t)(ADC_CHSELR_CHSEL12)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2) 462 #define ADC_CHANNEL_13 ((uint32_t)(ADC_CHSELR_CHSEL13)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0) 463 #define ADC_CHANNEL_14 ((uint32_t)(ADC_CHSELR_CHSEL14)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1) 464 #define ADC_CHANNEL_15 ((uint32_t)(ADC_CHSELR_CHSEL15)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0) 465 #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx) 466 #define ADC_CHANNEL_16 ((uint32_t)(ADC_CHSELR_CHSEL16)| ADC_CFGR1_AWDCH_4) 467 #endif 468 #define ADC_CHANNEL_17 ((uint32_t)(ADC_CHSELR_CHSEL17)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_0) 469 #define ADC_CHANNEL_18 ((uint32_t)(ADC_CHSELR_CHSEL18)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_1) 470 471 /* Internal channels */ 472 #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx) 473 #define ADC_CHANNEL_VLCD ADC_CHANNEL_16 474 #endif 475 #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 476 #if defined(ADC_CCR_TSEN) 477 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18 478 #endif 479 /** 480 * @} 481 */ 482 483 /** @defgroup ADC_Channel_AWD_Masks ADC Channel Masks 484 * @{ 485 */ 486 #define ADC_CHANNEL_MASK (0x0007FFFFU) 487 #define ADC_CHANNEL_AWD_MASK (0x7C000000U) 488 /** 489 * @} 490 */ 491 492 /** @defgroup ADC_sampling_times ADC Sampling Cycles 493 * @{ 494 */ 495 #define ADC_SAMPLETIME_1CYCLE_5 (0x00000000U) /*!< ADC sampling time 1.5 cycle */ 496 #define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR_SMPR_0) /*!< ADC sampling time 3.5 CYCLES */ 497 #define ADC_SAMPLETIME_7CYCLES_5 (ADC_SMPR_SMPR_1) /*!< ADC sampling time 7.5 CYCLES */ 498 #define ADC_SAMPLETIME_12CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_1 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 12.5 CYCLES */ 499 #define ADC_SAMPLETIME_19CYCLES_5 (ADC_SMPR_SMPR_2) /*!< ADC sampling time 19.5 CYCLES */ 500 #define ADC_SAMPLETIME_39CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 39.5 CYCLES */ 501 #define ADC_SAMPLETIME_79CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_1)) /*!< ADC sampling time 79.5 CYCLES */ 502 #define ADC_SAMPLETIME_160CYCLES_5 (ADC_SMPR_SMPR) /*!< ADC sampling time 160.5 CYCLES */ 503 /** 504 * @} 505 */ 506 507 /** @defgroup ADC_Scan_mode ADC Scan mode 508 * @{ 509 */ 510 /* Note: Scan mode values must be compatible with other STM32 devices having */ 511 /* a configurable sequencer. */ 512 /* Scan direction setting values are defined by taking in account */ 513 /* already defined values for other STM32 devices: */ 514 /* ADC_SCAN_DISABLE (0x00000000U) */ 515 /* ADC_SCAN_ENABLE (0x00000001U) */ 516 /* Scan direction forward is considered as default setting equivalent */ 517 /* to scan enable. */ 518 /* Scan direction backward is considered as additional setting. */ 519 /* In case of migration from another STM32 device, the user will be */ 520 /* warned of change of setting choices with assert check. */ 521 #define ADC_SCAN_DIRECTION_FORWARD (0x00000001U) /*!< Scan direction forward: from channel 0 to channel 18 */ 522 #define ADC_SCAN_DIRECTION_BACKWARD (0x00000002U) /*!< Scan direction backward: from channel 18 to channel 0 */ 523 524 #define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */ 525 /** 526 * @} 527 */ 528 529 /** @defgroup ADC_Oversampling_Ratio ADC Oversampling Ratio 530 * @{ 531 */ 532 533 #define ADC_OVERSAMPLING_RATIO_2 (0x00000000U) /*!< ADC Oversampling ratio 2x */ 534 #define ADC_OVERSAMPLING_RATIO_4 (0x00000004U) /*!< ADC Oversampling ratio 4x */ 535 #define ADC_OVERSAMPLING_RATIO_8 (0x00000008U) /*!< ADC Oversampling ratio 8x */ 536 #define ADC_OVERSAMPLING_RATIO_16 (0x0000000CU) /*!< ADC Oversampling ratio 16x */ 537 #define ADC_OVERSAMPLING_RATIO_32 (0x00000010U) /*!< ADC Oversampling ratio 32x */ 538 #define ADC_OVERSAMPLING_RATIO_64 (0x00000014U) /*!< ADC Oversampling ratio 64x */ 539 #define ADC_OVERSAMPLING_RATIO_128 (0x00000018U) /*!< ADC Oversampling ratio 128x */ 540 #define ADC_OVERSAMPLING_RATIO_256 (0x0000001CU) /*!< ADC Oversampling ratio 256x */ 541 /** 542 * @} 543 */ 544 545 /** @defgroup ADC_Right_Bit_Shift ADC Right Bit Shift 546 * @{ 547 */ 548 #define ADC_RIGHTBITSHIFT_NONE (0x00000000U) /*!< ADC No bit shift for oversampling */ 549 #define ADC_RIGHTBITSHIFT_1 (0x00000020U) /*!< ADC 1 bit shift for oversampling */ 550 #define ADC_RIGHTBITSHIFT_2 (0x00000040U) /*!< ADC 2 bits shift for oversampling */ 551 #define ADC_RIGHTBITSHIFT_3 (0x00000060U) /*!< ADC 3 bits shift for oversampling */ 552 #define ADC_RIGHTBITSHIFT_4 (0x00000080U) /*!< ADC 4 bits shift for oversampling */ 553 #define ADC_RIGHTBITSHIFT_5 (0x000000A0U) /*!< ADC 5 bits shift for oversampling */ 554 #define ADC_RIGHTBITSHIFT_6 (0x000000C0U) /*!< ADC 6 bits shift for oversampling */ 555 #define ADC_RIGHTBITSHIFT_7 (0x000000E0U) /*!< ADC 7 bits shift for oversampling */ 556 #define ADC_RIGHTBITSHIFT_8 (0x00000100U) /*!< ADC 8 bits shift for oversampling */ 557 /** 558 * @} 559 */ 560 561 /** @defgroup ADC_Triggered_Oversampling_Mode ADC Triggered Oversampling Mode 562 * @{ 563 */ 564 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (0x00000000U) /*!< ADC No bit shift for oversampling */ 565 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (0x00000200U) /*!< ADC No bit shift for oversampling */ 566 /** 567 * @} 568 */ 569 570 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode 571 * @{ 572 */ 573 #define ADC_ANALOGWATCHDOG_NONE (0x00000000U) 574 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN)) 575 #define ADC_ANALOGWATCHDOG_ALL_REG ( ADC_CFGR1_AWDEN) 576 /** 577 * @} 578 */ 579 580 /** @defgroup ADC_conversion_type ADC Conversion Group 581 * @{ 582 */ 583 #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS)) 584 /** 585 * @} 586 */ 587 588 /** @defgroup ADC_Event_type ADC Event 589 * @{ 590 */ 591 #define ADC_AWD_EVENT (ADC_FLAG_AWD) 592 #define ADC_OVR_EVENT (ADC_FLAG_OVR) 593 /** 594 * @} 595 */ 596 597 /** @defgroup ADC_interrupts_definition ADC Interrupts Definition 598 * @{ 599 */ 600 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready (ADRDY) interrupt source */ 601 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of Sampling interrupt source */ 602 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of Regular Conversion interrupt source */ 603 #define ADC_IT_EOS ADC_IER_EOSEQIE /*!< ADC End of Regular sequence of Conversions interrupt source */ 604 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 605 #define ADC_IT_AWD ADC_IER_AWDIE /*!< ADC Analog watchdog 1 interrupt source */ 606 #define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC End of Calibration interrupt source */ 607 /** 608 * @} 609 */ 610 611 /** @defgroup ADC_flags_definition ADC flags definition 612 * @{ 613 */ 614 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 615 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 616 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 617 #define ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC End of Regular sequence of Conversions flag */ 618 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 619 #define ADC_FLAG_AWD ADC_ISR_AWD /*!< ADC Analog watchdog flag */ 620 #define ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC Enf Of Calibration flag */ 621 622 623 #define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \ 624 ADC_FLAG_OVR | ADC_FLAG_AWD | ADC_FLAG_EOCAL) 625 /** 626 * @} 627 */ 628 629 /** 630 * @} 631 */ 632 633 634 /* Exported macro ------------------------------------------------------------*/ 635 636 /** @defgroup ADC_Exported_Macros ADC Exported Macros 637 * @{ 638 */ 639 /** @brief Reset ADC handle state 640 * @param __HANDLE__ ADC handle 641 * @retval None 642 */ 643 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 644 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 645 do{ \ 646 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 647 (__HANDLE__)->MspInitCallback = NULL; \ 648 (__HANDLE__)->MspDeInitCallback = NULL; \ 649 } while(0) 650 #else 651 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 652 #endif 653 654 /** 655 * @brief Enable the ADC peripheral 656 * @param __HANDLE__ ADC handle 657 * @retval None 658 */ 659 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN) 660 661 /** 662 * @brief Verification of hardware constraints before ADC can be enabled 663 * @param __HANDLE__ ADC handle 664 * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) 665 */ 666 #define ADC_ENABLING_CONDITIONS(__HANDLE__) \ 667 (( ( ((__HANDLE__)->Instance->CR) & \ 668 (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | \ 669 ADC_CR_ADDIS | ADC_CR_ADEN ) \ 670 ) == RESET \ 671 ) ? SET : RESET) 672 673 /** 674 * @brief Disable the ADC peripheral 675 * @param __HANDLE__ ADC handle 676 * @retval None 677 */ 678 #define __HAL_ADC_DISABLE(__HANDLE__) \ 679 do{ \ 680 (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \ 681 __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ 682 } while(0) 683 684 /** 685 * @brief Verification of hardware constraints before ADC can be disabled 686 * @param __HANDLE__ ADC handle 687 * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) 688 */ 689 #define ADC_DISABLING_CONDITIONS(__HANDLE__) \ 690 (( ( ((__HANDLE__)->Instance->CR) & \ 691 (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ 692 ) ? SET : RESET) 693 694 /** 695 * @brief Verification of ADC state: enabled or disabled 696 * @param __HANDLE__ ADC handle 697 * @retval SET (ADC enabled) or RESET (ADC disabled) 698 */ 699 #define ADC_IS_ENABLE(__HANDLE__) \ 700 (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ 701 ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ 702 ) ? SET : RESET) 703 704 /** 705 * @brief Returns resolution bits in CFGR register: RES[1:0]. Return value among parameter to @ref ADC_Resolution. 706 * @param __HANDLE__ ADC handle 707 * @retval None 708 */ 709 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES) 710 /** 711 * @brief Test if conversion trigger of regular group is software start 712 * or external trigger. 713 * @param __HANDLE__ ADC handle 714 * @retval SET (software start) or RESET (external trigger) 715 */ 716 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ 717 (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET) 718 719 720 721 /** 722 * @brief Check if no conversion on going on regular group 723 * @param __HANDLE__ ADC handle 724 * @retval SET (conversion is on going) or RESET (no conversion is on going) 725 */ 726 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ 727 (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \ 728 ) ? RESET : SET) 729 730 /** 731 * @brief Enable ADC continuous conversion mode. 732 * @param _CONTINUOUS_MODE_ Continuous mode. 733 * @retval None 734 */ 735 #define ADC_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U) 736 737 /** 738 * @brief Enable ADC scan mode to convert multiple ranks with sequencer. 739 * @param _SCAN_MODE_ Scan conversion mode. 740 * @retval None 741 */ 742 #define ADC_SCANDIR(_SCAN_MODE_) \ 743 ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \ 744 )? (ADC_CFGR1_SCANDIR) : (0x00000000U) \ 745 ) 746 747 /** 748 * @brief Configures the number of discontinuous conversions for the regular group channels. 749 * @param _NBR_DISCONTINUOUS_CONV_ Number of discontinuous conversions. 750 * @retval None 751 */ 752 #define __HAL_ADC_CFGR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U) 753 754 /** 755 * @brief Enable the ADC DMA continuous request. 756 * @param _DMAContReq_MODE_ DMA continuous request mode. 757 * @retval None 758 */ 759 #define ADC_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1U) 760 761 /** 762 * @brief Enable the ADC Auto Delay. 763 * @param _AutoDelay_ Auto delay bit enable or disable. 764 * @retval None 765 */ 766 #define __HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14U) 767 768 /** 769 * @brief Enable the ADC LowPowerAutoPowerOff. 770 * @param _AUTOFF_ AutoOff bit enable or disable. 771 * @retval None 772 */ 773 #define __HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15U) 774 775 /** 776 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. 777 * @param _Threshold_ Threshold value 778 * @retval None 779 */ 780 #define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U) 781 782 /** 783 * @brief Enable the ADC Low Frequency mode. 784 * @param _LOW_FREQUENCY_MODE_ Low Frequency mode. 785 * @retval None 786 */ 787 #define __HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25U) 788 789 /** 790 * @brief Shift the offset in function of the selected ADC resolution. 791 * Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 792 * If resolution 12 bits, no shift. 793 * If resolution 10 bits, shift of 2 ranks on the right. 794 * If resolution 8 bits, shift of 4 ranks on the right. 795 * If resolution 6 bits, shift of 6 ranks on the right. 796 * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) 797 * @param __HANDLE__ ADC handle. 798 * @param _Offset_ Value to be shifted 799 * @retval None 800 */ 801 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \ 802 ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3U)*2U)) 803 804 /** 805 * @brief Shift the AWD1 threshold in function of the selected ADC resolution. 806 * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0 807 * If resolution 12 bits, no shift. 808 * If resolution 10 bits, shift of 2 ranks on the right. 809 * If resolution 8 bits, shift of 4 ranks on the right. 810 * If resolution 6 bits, shift of 6 ranks on the right. 811 * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) 812 * @param __HANDLE__ ADC handle. 813 * @param _Threshold_ Value to be shifted 814 * @retval None 815 */ 816 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ 817 ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U)) 818 819 /** 820 * @brief Shift the value on the left, less significant are set to 0. 821 * @param _Value_ Value to be shifted 822 * @param _Shift_ Number of shift to be done 823 * @retval None 824 */ 825 #define __HAL_ADC_Value_Shift_left(_Value_, _Shift_) ((_Value_) << (_Shift_)) 826 827 828 /** 829 * @brief Enable the ADC end of conversion interrupt. 830 * @param __HANDLE__ ADC handle. 831 * @param __INTERRUPT__ ADC Interrupt. 832 * @retval None 833 */ 834 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 835 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 836 837 /** 838 * @brief Disable the ADC end of conversion interrupt. 839 * @param __HANDLE__ ADC handle. 840 * @param __INTERRUPT__ ADC interrupt. 841 * @retval None 842 */ 843 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 844 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 845 846 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 847 * @param __HANDLE__ ADC handle 848 * @param __INTERRUPT__ ADC interrupt source to check 849 * @arg ... 850 * @arg ... 851 * @retval State of interruption (TRUE or FALSE) 852 */ 853 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 854 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 855 856 /** 857 * @brief Clear the ADC's pending flags 858 * @param __HANDLE__ ADC handle. 859 * @param __FLAG__ ADC flag. 860 * @retval None 861 */ 862 /* Note: bit cleared bit by writing 1 */ 863 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 864 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 865 866 /** 867 * @brief Get the selected ADC's flag status. 868 * @param __HANDLE__ ADC handle. 869 * @param __FLAG__ ADC flag. 870 * @retval None 871 */ 872 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 873 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 874 875 876 /** 877 * @brief Simultaneously clears and sets specific bits of the handle State 878 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 879 * the first parameter is the ADC handle State, the second parameter is the 880 * bit field to clear, the third and last parameter is the bit field to set. 881 * @retval None 882 */ 883 #define ADC_STATE_CLR_SET MODIFY_REG 884 885 /** 886 * @brief Clear ADC error code (set it to error code: "no error") 887 * @param __HANDLE__ ADC handle 888 * @retval None 889 */ 890 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ 891 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 892 893 894 /** 895 * @brief Configuration of ADC clock & prescaler: clock source PCLK or Asynchronous with selectable prescaler 896 * @param __HANDLE__ ADC handle 897 * @retval None 898 */ 899 900 #define __HAL_ADC_CLOCK_PRESCALER(__HANDLE__) \ 901 do{ \ 902 if ((((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ 903 (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 904 (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV4)) \ 905 { \ 906 (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \ 907 (__HANDLE__)->Instance->CFGR2 |= (__HANDLE__)->Init.ClockPrescaler; \ 908 } \ 909 else \ 910 { \ 911 /* CKMOD bits must be reset */ \ 912 (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \ 913 ADC->CCR &= ~(ADC_CCR_PRESC); \ 914 ADC->CCR |= (__HANDLE__)->Init.ClockPrescaler; \ 915 } \ 916 } while(0) 917 918 919 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) ||\ 920 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\ 921 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\ 922 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\ 923 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) ||\ 924 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\ 925 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\ 926 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) ||\ 927 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) ||\ 928 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\ 929 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\ 930 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\ 931 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\ 932 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\ 933 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\ 934 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256)) 935 936 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ 937 ((RESOLUTION) == ADC_RESOLUTION_10B) || \ 938 ((RESOLUTION) == ADC_RESOLUTION_8B) || \ 939 ((RESOLUTION) == ADC_RESOLUTION_6B)) 940 941 #define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \ 942 ((RESOLUTION) == ADC_RESOLUTION_6B)) 943 944 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ 945 ((ALIGN) == ADC_DATAALIGN_LEFT)) 946 947 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 948 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 949 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 950 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) 951 952 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ 953 ((EOC_SELECTION) == ADC_EOC_SEQ_CONV)) 954 955 #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ 956 ((OVR) == ADC_OVR_DATA_OVERWRITTEN)) 957 958 #define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \ 959 ((WATCHDOG) == ADC_RANK_NONE)) 960 961 #if defined (ADC_CHANNEL_VLCD) 962 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ 963 ((CHANNEL) == ADC_CHANNEL_1) || \ 964 ((CHANNEL) == ADC_CHANNEL_2) || \ 965 ((CHANNEL) == ADC_CHANNEL_3) || \ 966 ((CHANNEL) == ADC_CHANNEL_4) || \ 967 ((CHANNEL) == ADC_CHANNEL_5) || \ 968 ((CHANNEL) == ADC_CHANNEL_6) || \ 969 ((CHANNEL) == ADC_CHANNEL_7) || \ 970 ((CHANNEL) == ADC_CHANNEL_8) || \ 971 ((CHANNEL) == ADC_CHANNEL_9) || \ 972 ((CHANNEL) == ADC_CHANNEL_10) || \ 973 ((CHANNEL) == ADC_CHANNEL_11) || \ 974 ((CHANNEL) == ADC_CHANNEL_12) || \ 975 ((CHANNEL) == ADC_CHANNEL_13) || \ 976 ((CHANNEL) == ADC_CHANNEL_14) || \ 977 ((CHANNEL) == ADC_CHANNEL_15) || \ 978 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ 979 ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ 980 ((CHANNEL) == ADC_CHANNEL_VLCD)) 981 #elif defined (ADC_CHANNEL_TEMPSENSOR) 982 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ 983 ((CHANNEL) == ADC_CHANNEL_1) || \ 984 ((CHANNEL) == ADC_CHANNEL_2) || \ 985 ((CHANNEL) == ADC_CHANNEL_3) || \ 986 ((CHANNEL) == ADC_CHANNEL_4) || \ 987 ((CHANNEL) == ADC_CHANNEL_5) || \ 988 ((CHANNEL) == ADC_CHANNEL_6) || \ 989 ((CHANNEL) == ADC_CHANNEL_7) || \ 990 ((CHANNEL) == ADC_CHANNEL_8) || \ 991 ((CHANNEL) == ADC_CHANNEL_9) || \ 992 ((CHANNEL) == ADC_CHANNEL_10) || \ 993 ((CHANNEL) == ADC_CHANNEL_11) || \ 994 ((CHANNEL) == ADC_CHANNEL_12) || \ 995 ((CHANNEL) == ADC_CHANNEL_13) || \ 996 ((CHANNEL) == ADC_CHANNEL_14) || \ 997 ((CHANNEL) == ADC_CHANNEL_15) || \ 998 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ 999 ((CHANNEL) == ADC_CHANNEL_VREFINT)) 1000 #else 1001 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ 1002 ((CHANNEL) == ADC_CHANNEL_1) || \ 1003 ((CHANNEL) == ADC_CHANNEL_2) || \ 1004 ((CHANNEL) == ADC_CHANNEL_3) || \ 1005 ((CHANNEL) == ADC_CHANNEL_4) || \ 1006 ((CHANNEL) == ADC_CHANNEL_5) || \ 1007 ((CHANNEL) == ADC_CHANNEL_6) || \ 1008 ((CHANNEL) == ADC_CHANNEL_7) || \ 1009 ((CHANNEL) == ADC_CHANNEL_8) || \ 1010 ((CHANNEL) == ADC_CHANNEL_9) || \ 1011 ((CHANNEL) == ADC_CHANNEL_10) || \ 1012 ((CHANNEL) == ADC_CHANNEL_11) || \ 1013 ((CHANNEL) == ADC_CHANNEL_12) || \ 1014 ((CHANNEL) == ADC_CHANNEL_13) || \ 1015 ((CHANNEL) == ADC_CHANNEL_14) || \ 1016 ((CHANNEL) == ADC_CHANNEL_15) || \ 1017 ((CHANNEL) == ADC_CHANNEL_VREFINT)) 1018 #endif 1019 1020 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5 ) || \ 1021 ((TIME) == ADC_SAMPLETIME_3CYCLES_5 ) || \ 1022 ((TIME) == ADC_SAMPLETIME_7CYCLES_5 ) || \ 1023 ((TIME) == ADC_SAMPLETIME_12CYCLES_5 ) || \ 1024 ((TIME) == ADC_SAMPLETIME_19CYCLES_5 ) || \ 1025 ((TIME) == ADC_SAMPLETIME_39CYCLES_5 ) || \ 1026 ((TIME) == ADC_SAMPLETIME_79CYCLES_5 ) || \ 1027 ((TIME) == ADC_SAMPLETIME_160CYCLES_5)) 1028 1029 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \ 1030 ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD)) 1031 1032 #define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) == ADC_OVERSAMPLING_RATIO_2 ) || \ 1033 ((RATIO) == ADC_OVERSAMPLING_RATIO_4 ) || \ 1034 ((RATIO) == ADC_OVERSAMPLING_RATIO_8 ) || \ 1035 ((RATIO) == ADC_OVERSAMPLING_RATIO_16 ) || \ 1036 ((RATIO) == ADC_OVERSAMPLING_RATIO_32 ) || \ 1037 ((RATIO) == ADC_OVERSAMPLING_RATIO_64 ) || \ 1038 ((RATIO) == ADC_OVERSAMPLING_RATIO_128 ) || \ 1039 ((RATIO) == ADC_OVERSAMPLING_RATIO_256 )) 1040 1041 #define IS_ADC_RIGHT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) || \ 1042 ((SHIFT) == ADC_RIGHTBITSHIFT_1 ) || \ 1043 ((SHIFT) == ADC_RIGHTBITSHIFT_2 ) || \ 1044 ((SHIFT) == ADC_RIGHTBITSHIFT_3 ) || \ 1045 ((SHIFT) == ADC_RIGHTBITSHIFT_4 ) || \ 1046 ((SHIFT) == ADC_RIGHTBITSHIFT_5 ) || \ 1047 ((SHIFT) == ADC_RIGHTBITSHIFT_6 ) || \ 1048 ((SHIFT) == ADC_RIGHTBITSHIFT_7 ) || \ 1049 ((SHIFT) == ADC_RIGHTBITSHIFT_8 )) 1050 1051 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ 1052 ((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 1053 1054 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE ) || \ 1055 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 1056 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG )) 1057 1058 #define IS_ADC_CONVERSION_GROUP(CONVERSION) ((CONVERSION) == ADC_REGULAR_GROUP) 1059 1060 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ 1061 ((EVENT) == ADC_OVR_EVENT)) 1062 1063 1064 /** @defgroup ADC_range_verification ADC Range Verification 1065 * in function of ADC resolution selected (12, 10, 8 or 6 bits) 1066 * @{ 1067 */ 1068 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ 1069 ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= (0x0FFFU))) || \ 1070 (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= (0x03FFU))) || \ 1071 (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= (0x00FFU))) || \ 1072 (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= (0x003FU)))) 1073 /** 1074 * @} 1075 */ 1076 1077 /** @defgroup ADC_regular_nb_conv_verification ADC Regular Nb Conversion Verification 1078 * @{ 1079 */ 1080 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U))) 1081 /** 1082 * @} 1083 */ 1084 1085 /** 1086 * @} 1087 */ 1088 1089 /* Include ADC HAL Extended module */ 1090 #include "stm32l0xx_hal_adc_ex.h" 1091 1092 /* Exported functions --------------------------------------------------------*/ 1093 /** @addtogroup ADC_Exported_Functions 1094 * @{ 1095 */ 1096 1097 /** @addtogroup ADC_Exported_Functions_Group1 1098 * @brief Initialization and Configuration functions 1099 * @{ 1100 */ 1101 /* Initialization and de-initialization functions ****************************/ 1102 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); 1103 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 1104 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); 1105 void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); 1106 1107 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1108 /* Callbacks Register/UnRegister functions ***********************************/ 1109 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); 1110 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 1111 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1112 1113 /** 1114 * @} 1115 */ 1116 1117 /** @addtogroup ADC_Exported_Functions_Group2 1118 * @brief IO operation functions 1119 * @{ 1120 */ 1121 /* IO operation functions *****************************************************/ 1122 1123 /* Blocking mode: Polling */ 1124 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); 1125 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); 1126 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1127 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); 1128 1129 /* Non-blocking mode: Interruption */ 1130 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); 1131 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); 1132 1133 /* Non-blocking mode: DMA */ 1134 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1135 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); 1136 1137 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1138 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); 1139 1140 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 1141 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); 1142 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); 1143 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); 1144 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); 1145 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 1146 /** 1147 * @} 1148 */ 1149 1150 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 1151 * @brief Peripheral Control functions 1152 * @{ 1153 */ 1154 /* Peripheral Control functions ***********************************************/ 1155 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); 1156 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); 1157 /** 1158 * @} 1159 */ 1160 1161 /* Peripheral State functions *************************************************/ 1162 /** @addtogroup ADC_Exported_Functions_Group4 1163 * @{ 1164 */ 1165 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); 1166 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 1167 /** 1168 * @} 1169 */ 1170 1171 1172 /** 1173 * @} 1174 */ 1175 1176 /** 1177 * @} 1178 */ 1179 1180 /** 1181 * @} 1182 */ 1183 1184 #ifdef __cplusplus 1185 } 1186 #endif 1187 1188 1189 #endif /*__STM32L0xx_HAL_ADC_H */ 1190 1191
