1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2016 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32L0xx_HAL_H 22 #define __STM32L0xx_HAL_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l0xx_hal_conf.h" 30 31 /** @addtogroup STM32L0xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @defgroup HAL HAL 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /* Exported constants --------------------------------------------------------*/ 41 42 /** @defgroup HAL_Exported_Constants HAL Exported Constants 43 * @{ 44 */ 45 46 /** @defgroup HAL_TICK_FREQ Tick Frequency 47 * @{ 48 */ 49 typedef enum 50 { 51 HAL_TICK_FREQ_10HZ = 100U, 52 HAL_TICK_FREQ_100HZ = 10U, 53 HAL_TICK_FREQ_1KHZ = 1U, 54 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 55 } HAL_TickFreqTypeDef; 56 /** 57 * @} 58 */ 59 60 /** @defgroup SYSCFG_BootMode Boot Mode 61 * @{ 62 */ 63 #define SYSCFG_BOOT_MAINFLASH (0x00000000U) 64 #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_CFGR1_BOOT_MODE_0 65 #define SYSCFG_BOOT_SRAM SYSCFG_CFGR1_BOOT_MODE 66 67 /** 68 * @} 69 */ 70 71 /** @defgroup DBGMCU_Low_Power_Config DBGMCU Low Power Configuration 72 * @{ 73 */ 74 #define DBGMCU_SLEEP DBGMCU_CR_DBG_SLEEP 75 #define DBGMCU_STOP DBGMCU_CR_DBG_STOP 76 #define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY 77 #define IS_DBGMCU_PERIPH(__PERIPH__) ((((__PERIPH__) & (~(DBGMCU_CR_DBG))) == 0x00U) && ((__PERIPH__) != 0x00U)) 78 79 80 /** 81 * @} 82 */ 83 84 #if defined (LCD_BASE) /* STM32L0x3xx only */ 85 /** @defgroup SYSCFG_LCD_EXT_CAPA SYSCFG LCD External Capacitors 86 * @{ 87 */ 88 #define SYSCFG_LCD_EXT_CAPA SYSCFG_CFGR2_CAPA /*!< Connection of internal Vlcd rail to external capacitors */ 89 #define SYSCFG_VLCD_PB2_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_0 /*!< Connection on PB2 */ 90 #define SYSCFG_VLCD_PB12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_1 /*!< Connection on PB12 */ 91 #define SYSCFG_VLCD_PB0_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_2 /*!< Connection on PB0 */ 92 #if defined (SYSCFG_CFGR2_CAPA_3) 93 #define SYSCFG_VLCD_PE11_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_3 /*!< Connection on PE11 */ 94 #endif 95 #if defined (SYSCFG_CFGR2_CAPA_4) 96 #define SYSCFG_VLCD_PE12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_4 /*!< Connection on PE12 */ 97 #endif 98 99 /** 100 * @} 101 */ 102 #endif 103 104 /** @defgroup SYSCFG_VREFINT_OUT_SELECT SYSCFG VREFINT Out Selection 105 * @{ 106 */ 107 #define SYSCFG_VREFINT_OUT_NONE (0x00000000U) /* no pad connected */ 108 #define SYSCFG_VREFINT_OUT_PB0 SYSCFG_CFGR3_VREF_OUT_0 /* Selects PBO as output for the Vrefint */ 109 #define SYSCFG_VREFINT_OUT_PB1 SYSCFG_CFGR3_VREF_OUT_1 /* Selects PB1 as output for the Vrefint */ 110 #define SYSCFG_VREFINT_OUT_PB0_PB1 SYSCFG_CFGR3_VREF_OUT /* Selects PBO and PB1 as output for the Vrefint */ 111 112 #define IS_SYSCFG_VREFINT_OUT_SELECT(OUTPUT) (((OUTPUT) == SYSCFG_VREFINT_OUT_NONE) || \ 113 ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0) || \ 114 ((OUTPUT) == SYSCFG_VREFINT_OUT_PB1) || \ 115 ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0_PB1)) 116 /** 117 * @} 118 */ 119 120 /** @defgroup SYSCFG_flags_definition SYSCFG Flags Definition 121 * @{ 122 */ 123 #define SYSCFG_FLAG_VREFINT_READY SYSCFG_CFGR3_VREFINT_RDYF 124 125 #define IS_SYSCFG_FLAG(FLAG) ((FLAG) == SYSCFG_FLAG_VREFINT_READY)) 126 127 /** 128 * @} 129 */ 130 131 /** @defgroup SYSCFG_FastModePlus_GPIO Fast Mode Plus on GPIO 132 * @{ 133 */ 134 /** @brief Fast mode Plus driving capability on a specific GPIO 135 */ 136 #if defined (SYSCFG_CFGR2_I2C_PB6_FMP) 137 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR2_I2C_PB6_FMP /* Enable Fast Mode Plus on PB6 */ 138 #endif 139 #if defined (SYSCFG_CFGR2_I2C_PB7_FMP) 140 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR2_I2C_PB7_FMP /* Enable Fast Mode Plus on PB7 */ 141 #endif 142 #if defined (SYSCFG_CFGR2_I2C_PB8_FMP) 143 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR2_I2C_PB8_FMP /* Enable Fast Mode Plus on PB8 */ 144 #endif 145 #if defined (SYSCFG_CFGR2_I2C_PB9_FMP) 146 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR2_I2C_PB9_FMP /* Enable Fast Mode Plus on PB9 */ 147 #endif 148 149 #define IS_SYSCFG_FASTMODEPLUS(PIN) ((((PIN) & (SYSCFG_FASTMODEPLUS_PB6)) == SYSCFG_FASTMODEPLUS_PB6) || \ 150 (((PIN) & (SYSCFG_FASTMODEPLUS_PB7)) == SYSCFG_FASTMODEPLUS_PB7) || \ 151 (((PIN) & (SYSCFG_FASTMODEPLUS_PB8)) == SYSCFG_FASTMODEPLUS_PB8) || \ 152 (((PIN) & (SYSCFG_FASTMODEPLUS_PB9)) == SYSCFG_FASTMODEPLUS_PB9) ) 153 /** 154 * @} 155 */ 156 /** 157 * @} 158 */ 159 160 /* Exported macros -----------------------------------------------------------*/ 161 /** @defgroup HAL_Exported_Macros HAL Exported Macros 162 * @{ 163 */ 164 165 /** @brief Freeze/Unfreeze Peripherals in Debug mode 166 */ 167 #if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP) 168 /** 169 * @brief TIM2 Peripherals Debug mode 170 */ 171 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP) 172 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP) 173 #endif 174 175 #if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP) 176 /** 177 * @brief TIM3 Peripherals Debug mode 178 */ 179 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP) 180 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP) 181 #endif 182 183 #if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP) 184 /** 185 * @brief TIM6 Peripherals Debug mode 186 */ 187 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) 188 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) 189 #endif 190 191 #if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP) 192 /** 193 * @brief TIM7 Peripherals Debug mode 194 */ 195 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) 196 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) 197 #endif 198 199 #if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP) 200 /** 201 * @brief RTC Peripherals Debug mode 202 */ 203 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) 204 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) 205 #endif 206 207 #if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP) 208 /** 209 * @brief WWDG Peripherals Debug mode 210 */ 211 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) 212 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) 213 #endif 214 215 #if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP) 216 /** 217 * @brief IWDG Peripherals Debug mode 218 */ 219 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) 220 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) 221 #endif 222 223 #if defined (DBGMCU_APB1_FZ_DBG_I2C1_STOP) 224 /** 225 * @brief I2C1 Peripherals Debug mode 226 */ 227 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP) 228 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP) 229 #endif 230 231 #if defined (DBGMCU_APB1_FZ_DBG_I2C2_STOP) 232 /** 233 * @brief I2C2 Peripherals Debug mode 234 */ 235 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP) 236 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP) 237 #endif 238 239 #if defined (DBGMCU_APB1_FZ_DBG_I2C3_STOP) 240 /** 241 * @brief I2C3 Peripherals Debug mode 242 */ 243 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP) 244 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP) 245 #endif 246 247 #if defined (DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) 248 /** 249 * @brief LPTIMER Peripherals Debug mode 250 */ 251 #define __HAL_DBGMCU_FREEZE_LPTIMER() SET_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) 252 #define __HAL_DBGMCU_UNFREEZE_LPTIMER() CLEAR_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) 253 #endif 254 255 #if defined (DBGMCU_APB2_FZ_DBG_TIM22_STOP) 256 /** 257 * @brief TIM22 Peripherals Debug mode 258 */ 259 #define __HAL_DBGMCU_FREEZE_TIM22() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP) 260 #define __HAL_DBGMCU_UNFREEZE_TIM22() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP) 261 #endif 262 263 #if defined (DBGMCU_APB2_FZ_DBG_TIM21_STOP) 264 /** 265 * @brief TIM21 Peripherals Debug mode 266 */ 267 #define __HAL_DBGMCU_FREEZE_TIM21() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP) 268 #define __HAL_DBGMCU_UNFREEZE_TIM21() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP) 269 #endif 270 271 /** @brief Main Flash memory mapped at 0x00000000 272 */ 273 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) 274 275 /** @brief System Flash memory mapped at 0x00000000 276 */ 277 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0) 278 279 280 /** @brief Embedded SRAM mapped at 0x00000000 281 */ 282 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1) 283 284 /** @brief Configuration of the DBG Low Power mode. 285 * @param __DBGLPMODE__ bit field to indicate in which Low Power mode DBG is still active. 286 * This parameter can be a value of 287 * - DBGMCU_SLEEP 288 * - DBGMCU_STOP 289 * - DBGMCU_STANDBY 290 */ 291 #define __HAL_SYSCFG_DBG_LP_CONFIG(__DBGLPMODE__) do {assert_param(IS_DBGMCU_PERIPH(__DBGLPMODE__)); \ 292 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG, (__DBGLPMODE__)); \ 293 } while (0) 294 295 #if defined (LCD_BASE) /* STM32L0x3xx only */ 296 297 /** @brief Macro to configure the VLCD Decoupling capacitance connection. 298 * 299 * @param __SYSCFG_VLCD_CAPA__ specifies the decoupling of LCD capacitance for rails connection on GPIO. 300 * This parameter can be a combination of following values (when available): 301 * @arg SYSCFG_VLCD_PB2_EXT_CAPA_ON: Connection on PB2 302 * @arg SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12 303 * @arg SYSCFG_VLCD_PB0_EXT_CAPA_ON: Connection on PB0 304 * @arg SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11 305 * @arg SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12 306 * @retval None 307 */ 308 #define __HAL_SYSCFG_VLCD_CAPA_CONFIG(__SYSCFG_VLCD_CAPA__) \ 309 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA, (uint32_t)(__SYSCFG_VLCD_CAPA__)) 310 311 /** 312 * @brief Returns the decoupling of LCD capacitance configured by user. 313 * @retval The LCD capacitance connection as configured by user. The returned can be a combination of : 314 * SYSCFG_VLCD_PB2_EXT_CAPA_ON: Connection on PB2 315 * SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12 316 * SYSCFG_VLCD_PB0_EXT_CAPA_ON: Connection on PB0 317 * SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11 318 * SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12 319 */ 320 #define __HAL_SYSCFG_GET_VLCD_CAPA_CONFIG() READ_BIT(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA) 321 322 #endif 323 324 /** 325 * @brief Returns the boot mode as configured by user. 326 * @retval The boot mode as configured by user. The returned can be a value of : 327 * - SYSCFG_BOOT_MAINFLASH 328 * - SYSCFG_BOOT_SYSTEMFLASH 329 * - SYSCFG_BOOT_SRAM 330 */ 331 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOT_MODE) 332 333 334 /** @brief Check whether the specified SYSCFG flag is set or not. 335 * @param __FLAG__ specifies the flag to check. 336 * The only parameter supported is SYSCFG_FLAG_VREFINT_READY 337 * @retval The new state of __FLAG__ (TRUE or FALSE). 338 */ 339 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) (((SYSCFG->CFGR3) & (__FLAG__)) == (__FLAG__)) 340 341 /** @brief Fast mode Plus driving capability enable macro 342 * @param __FASTMODEPLUS__ This parameter can be a value of : 343 * @arg SYSCFG_FASTMODEPLUS_PB6 344 * @arg SYSCFG_FASTMODEPLUS_PB7 345 * @arg SYSCFG_FASTMODEPLUS_PB8 346 * @arg SYSCFG_FASTMODEPLUS_PB9 347 */ 348 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ 349 SET_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); \ 350 }while(0) 351 /** @brief Fast mode Plus driving capability disable macro 352 * @param __FASTMODEPLUS__ This parameter can be a value of : 353 * @arg SYSCFG_FASTMODEPLUS_PB6 354 * @arg SYSCFG_FASTMODEPLUS_PB7 355 * @arg SYSCFG_FASTMODEPLUS_PB8 356 * @arg SYSCFG_FASTMODEPLUS_PB9 357 */ 358 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ 359 CLEAR_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); \ 360 }while(0) 361 362 363 /** 364 * @} 365 */ 366 367 /** @defgroup HAL_Private_Macros HAL Private Macros 368 * @{ 369 */ 370 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 371 ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 372 ((FREQ) == HAL_TICK_FREQ_1KHZ)) 373 /** 374 * @} 375 */ 376 377 /* Exported variables --------------------------------------------------------*/ 378 /** @defgroup HAL_Exported_Variables HAL Exported Variables 379 * @{ 380 */ 381 extern __IO uint32_t uwTick; 382 extern uint32_t uwTickPrio; 383 extern HAL_TickFreqTypeDef uwTickFreq; 384 385 /** 386 * @} 387 */ 388 389 /* Exported functions --------------------------------------------------------*/ 390 /** @defgroup HAL_Exported_Functions HAL Exported Functions 391 * @{ 392 */ 393 /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization functions 394 * @brief Initialization and de-initialization functions 395 * @{ 396 */ 397 HAL_StatusTypeDef HAL_Init(void); 398 HAL_StatusTypeDef HAL_DeInit(void); 399 void HAL_MspInit(void); 400 void HAL_MspDeInit(void); 401 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 402 403 /** 404 * @} 405 */ 406 407 /** @defgroup HAL_Exported_Functions_Group2 Peripheral Control functions 408 * @brief Peripheral Control functions 409 * @{ 410 */ 411 void HAL_IncTick(void); 412 void HAL_Delay(uint32_t Delay); 413 uint32_t HAL_GetTick(void); 414 uint32_t HAL_GetTickPrio(void); 415 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 416 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 417 void HAL_SuspendTick(void); 418 void HAL_ResumeTick(void); 419 uint32_t HAL_GetHalVersion(void); 420 uint32_t HAL_GetREVID(void); 421 uint32_t HAL_GetDEVID(void); 422 uint32_t HAL_GetUIDw0(void); 423 uint32_t HAL_GetUIDw1(void); 424 uint32_t HAL_GetUIDw2(void); 425 /** 426 * @} 427 */ 428 429 /** @defgroup HAL_Exported_Functions_Group3 DBGMCU Peripheral Control functions 430 * @brief DBGMCU Peripheral Control functions 431 * @{ 432 */ 433 void HAL_DBGMCU_EnableDBGSleepMode(void); 434 void HAL_DBGMCU_DisableDBGSleepMode(void); 435 void HAL_DBGMCU_EnableDBGStopMode(void); 436 void HAL_DBGMCU_DisableDBGStopMode(void); 437 void HAL_DBGMCU_EnableDBGStandbyMode(void); 438 void HAL_DBGMCU_DisableDBGStandbyMode(void); 439 void HAL_DBGMCU_DBG_EnableLowPowerConfig(uint32_t Periph); 440 void HAL_DBGMCU_DBG_DisableLowPowerConfig(uint32_t Periph); 441 /** 442 * @} 443 */ 444 445 /** @defgroup HAL_Exported_Functions_Group4 SYSCFG Peripheral Control functions 446 * @brief SYSCFG Peripheral Control functions 447 * @{ 448 */ 449 uint32_t HAL_SYSCFG_GetBootMode(void); 450 void HAL_SYSCFG_Enable_Lock_VREFINT(void); 451 void HAL_SYSCFG_Disable_Lock_VREFINT(void); 452 void HAL_SYSCFG_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT); 453 /** 454 * @} 455 */ 456 /** 457 * @} 458 */ 459 460 /* Define the private group ***********************************/ 461 /**************************************************************/ 462 /** @defgroup HAL_Private HAL Private 463 * @{ 464 */ 465 /** 466 * @} 467 */ 468 /**************************************************************/ 469 470 471 /** 472 * @} 473 */ 474 475 /** 476 * @} 477 */ 478 479 #ifdef __cplusplus 480 } 481 #endif 482 483 #endif /* __STM32L0xx_HAL_H */ 484 485 486
