1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_utils.c
4 * @author MCD Application Team
5 * @brief UTILS LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 /* Includes ------------------------------------------------------------------*/
19 #include "stm32h7xx_ll_utils.h"
20 #include "stm32h7xx_ll_rcc.h"
21 #include "stm32h7xx_ll_pwr.h"
22
23 #ifdef USE_FULL_ASSERT
24 #include "stm32_assert.h"
25 #else
26 #define assert_param(expr) ((void)0U)
27 #endif /* USE_FULL_ASSERT */
28
29 /** @addtogroup STM32H7xx_LL_Driver
30 * @{
31 */
32
33 /** @addtogroup UTILS_LL
34 * @{
35 */
36
37 /* Private types -------------------------------------------------------------*/
38 /* Private variables ---------------------------------------------------------*/
39 /* Private constants ---------------------------------------------------------*/
40 /** @addtogroup UTILS_LL_Private_Constants
41 * @{
42 */
43 #if (STM32H7_DEV_ID == 0x450UL)
44 #define UTILS_MAX_FREQUENCY_SCALE1 480000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
45 #define UTILS_MAX_FREQUENCY_SCALE2 300000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
46 #define UTILS_MAX_FREQUENCY_SCALE3 200000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
47 #elif (STM32H7_DEV_ID == 0x480UL)
48 #define UTILS_MAX_FREQUENCY_SCALE0 280000000U /*!< Maximum frequency for system clock at power scale0, in Hz */
49 #define UTILS_MAX_FREQUENCY_SCALE1 225000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
50 #define UTILS_MAX_FREQUENCY_SCALE2 160000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
51 #define UTILS_MAX_FREQUENCY_SCALE3 88000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
52 #elif (STM32H7_DEV_ID == 0x483UL)
53 #define UTILS_MAX_FREQUENCY_SCALE0 550000000U /*!< Maximum frequency for system clock at power scale0, in Hz */
54 #define UTILS_MAX_FREQUENCY_SCALE1 200000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
55 #define UTILS_MAX_FREQUENCY_SCALE2 150000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
56 #define UTILS_MAX_FREQUENCY_SCALE3 85000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
57 #endif /*STM32H7_DEV_ID == 0x450UL*/
58
59 /* Defines used for PLL range */
60 #define UTILS_PLLVCO_INPUT_MIN1 1000000U /*!< Frequency min for the low range PLLVCO input, in Hz */
61 #define UTILS_PLLVCO_INPUT_MAX1 2000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */
62 #define UTILS_PLLVCO_INPUT_MIN2 2000000U /*!< Frequency min for the low range PLLVCO input, in Hz */
63 #define UTILS_PLLVCO_INPUT_MAX2 4000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */
64 #define UTILS_PLLVCO_INPUT_MIN3 4000000U /*!< Frequency min for the low range PLLVCO input, in Hz */
65 #define UTILS_PLLVCO_INPUT_MAX3 8000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */
66 #define UTILS_PLLVCO_INPUT_MIN4 8000000U /*!< Frequency min for the low range PLLVCO input, in Hz */
67 #define UTILS_PLLVCO_INPUT_MAX4 16000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */
68
69 #if (POWER_DOMAINS_NUMBER == 3U)
70 #define UTILS_PLLVCO_MEDIUM_OUTPUT_MIN 150000000U /*!< Frequency min for the medium range PLLVCO output, in Hz */
71 #define UTILS_PLLVCO_WIDE_OUTPUT_MIN 192000000U /*!< Frequency min for the wide range PLLVCO output, in Hz */
72 #define UTILS_PLLVCO_MEDIUM_OUTPUT_MAX 420000000U /*!< Frequency max for the medium range PLLVCO output, in Hz */
73 #define UTILS_PLLVCO_WIDE_OUTPUT_MAX 836000000U /*!< Frequency max for the wide range PLLVCO output, in Hz */
74 #else
75 #define UTILS_PLLVCO_MEDIUM_OUTPUT_MIN 150000000U /*!< Frequency min for the medium range PLLVCO output, in Hz */
76 #define UTILS_PLLVCO_WIDE_OUTPUT_MIN 128000000U /*!< Frequency min for the wide range PLLVCO output, in Hz */
77 #define UTILS_PLLVCO_MEDIUM_OUTPUT_MAX 420000000U /*!< Frequency max for the medium range PLLVCO output, in Hz */
78 #define UTILS_PLLVCO_WIDE_OUTPUT_MAX 560000000U /*!< Frequency max for the wide range PLLVCO output, in Hz */
79 #endif /*POWER_DOMAINS_NUMBER == 3U*/
80
81 /* Defines used for HSE range */
82 #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
83 #define UTILS_HSE_FREQUENCY_MAX 48000000U /*!< Frequency max for HSE frequency, in Hz */
84
85 /* Defines used for FLASH latency according to HCLK Frequency */
86 #if (STM32H7_DEV_ID == 0x480UL)
87 #define UTILS_SCALE0_LATENCY0_FREQ 44000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 0 */
88 #define UTILS_SCALE0_LATENCY1_FREQ 88000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 0 */
89 #define UTILS_SCALE0_LATENCY2_FREQ 132000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 0 */
90 #define UTILS_SCALE0_LATENCY3_FREQ 176000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 0 */
91 #define UTILS_SCALE0_LATENCY4_FREQ 220000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 0 */
92 #define UTILS_SCALE0_LATENCY5_FREQ 264000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 0 */
93 #define UTILS_SCALE0_LATENCY6_FREQ 280000000U /*!< HCLK frequency to set FLASH latency 6 in power scale 0 */
94
95 #define UTILS_SCALE1_LATENCY0_FREQ 42000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 1 */
96 #define UTILS_SCALE1_LATENCY1_FREQ 84000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
97 #define UTILS_SCALE1_LATENCY2_FREQ 126000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
98 #define UTILS_SCALE1_LATENCY3_FREQ 168000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
99 #define UTILS_SCALE1_LATENCY4_FREQ 210000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
100 #define UTILS_SCALE1_LATENCY5_FREQ 225000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
101
102 #define UTILS_SCALE2_LATENCY0_FREQ 34000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 2 */
103 #define UTILS_SCALE2_LATENCY1_FREQ 68000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
104 #define UTILS_SCALE2_LATENCY2_FREQ 102000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
105 #define UTILS_SCALE2_LATENCY3_FREQ 136000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
106 #define UTILS_SCALE2_LATENCY4_FREQ 160000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
107
108 #define UTILS_SCALE3_LATENCY0_FREQ 22000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 3 */
109 #define UTILS_SCALE3_LATENCY1_FREQ 44000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
110 #define UTILS_SCALE3_LATENCY2_FREQ 66000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
111 #define UTILS_SCALE3_LATENCY3_FREQ 88000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
112
113 #elif (STM32H7_DEV_ID == 0x450UL)
114
115 #define UTILS_SCALE1_LATENCY0_FREQ 70000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 1 */
116 #define UTILS_SCALE1_LATENCY1_FREQ 140000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
117 #define UTILS_SCALE1_LATENCY2_FREQ 240000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
118
119 #define UTILS_SCALE2_LATENCY0_FREQ 55000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 2 */
120 #define UTILS_SCALE2_LATENCY1_FREQ 110000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
121 #define UTILS_SCALE2_LATENCY2_FREQ 165000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
122 #define UTILS_SCALE2_LATENCY3_FREQ 220000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
123
124 #define UTILS_SCALE3_LATENCY0_FREQ 45000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 3 */
125 #define UTILS_SCALE3_LATENCY1_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
126 #define UTILS_SCALE3_LATENCY2_FREQ 135000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
127 #define UTILS_SCALE3_LATENCY3_FREQ 180000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
128 #define UTILS_SCALE3_LATENCY4_FREQ 225000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */
129
130 #elif (STM32H7_DEV_ID == 0x483UL)
131
132 #define UTILS_SCALE0_LATENCY0_FREQ 70000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 0 */
133 #define UTILS_SCALE0_LATENCY1_FREQ 140000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 0 */
134 #define UTILS_SCALE0_LATENCY2_FREQ 210000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 0 */
135 #define UTILS_SCALE0_LATENCY3_FREQ 275000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 0 */
136
137 #define UTILS_SCALE1_LATENCY0_FREQ 67000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 1 */
138 #define UTILS_SCALE1_LATENCY1_FREQ 133000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
139 #define UTILS_SCALE1_LATENCY2_FREQ 200000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
140
141 #define UTILS_SCALE2_LATENCY0_FREQ 50000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 2 */
142 #define UTILS_SCALE2_LATENCY1_FREQ 100000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
143 #define UTILS_SCALE2_LATENCY2_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
144
145 #define UTILS_SCALE3_LATENCY0_FREQ 35000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 3 */
146 #define UTILS_SCALE3_LATENCY1_FREQ 70000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
147 #define UTILS_SCALE3_LATENCY2_FREQ 85000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
148
149 #endif /*STM32H7_DEV_ID == 0x480UL*/
150 /**
151 * @}
152 */
153
154 /* Private macros ------------------------------------------------------------*/
155 /** @addtogroup UTILS_LL_Private_Macros
156 * @{
157 */
158 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
159 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
160 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
161 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
162 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
163 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
164 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
165 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
166 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
167
168 #define IS_LL_UTILS_AHB_DIV(__VALUE__) (((__VALUE__) == LL_RCC_AHB_DIV_1) \
169 || ((__VALUE__) == LL_RCC_AHB_DIV_2) \
170 || ((__VALUE__) == LL_RCC_AHB_DIV_4) \
171 || ((__VALUE__) == LL_RCC_AHB_DIV_8) \
172 || ((__VALUE__) == LL_RCC_AHB_DIV_16) \
173 || ((__VALUE__) == LL_RCC_AHB_DIV_64) \
174 || ((__VALUE__) == LL_RCC_AHB_DIV_128) \
175 || ((__VALUE__) == LL_RCC_AHB_DIV_256) \
176 || ((__VALUE__) == LL_RCC_AHB_DIV_512))
177
178 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
179 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
180 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
181 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
182 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
183
184 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
185 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
186 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
187 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
188 || ((__VALUE__) == LL_RCC_APB2_DIV_16))
189
190 #define IS_LL_UTILS_APB3_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB3_DIV_1) \
191 || ((__VALUE__) == LL_RCC_APB3_DIV_2) \
192 || ((__VALUE__) == LL_RCC_APB3_DIV_4) \
193 || ((__VALUE__) == LL_RCC_APB3_DIV_8) \
194 || ((__VALUE__) == LL_RCC_APB3_DIV_16))
195
196 #define IS_LL_UTILS_APB4_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB4_DIV_1) \
197 || ((__VALUE__) == LL_RCC_APB4_DIV_2) \
198 || ((__VALUE__) == LL_RCC_APB4_DIV_4) \
199 || ((__VALUE__) == LL_RCC_APB4_DIV_8) \
200 || ((__VALUE__) == LL_RCC_APB4_DIV_16))
201
202 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U))
203
204 #if (POWER_DOMAINS_NUMBER == 3U)
205 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((4U <= (__VALUE__)) && ((__VALUE__) <= 512U))
206 #else
207 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 420U))
208 #endif /*POWER_DOMAINS_NUMBER == 3U*/
209
210 #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U))
211
212 #define IS_LL_UTILS_FRACN_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU)
213
214 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__, __RANGE__) ( \
215 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_1_2) && (UTILS_PLLVCO_INPUT_MIN1 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX1)) || \
216 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_2_4) && (UTILS_PLLVCO_INPUT_MIN2 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX2)) || \
217 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_4_8) && (UTILS_PLLVCO_INPUT_MIN3 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX3)) || \
218 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_8_16) && (UTILS_PLLVCO_INPUT_MIN4 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX4)))
219
220 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__, __RANGE__) ( \
221 (((__RANGE__) == LL_RCC_PLLVCORANGE_MEDIUM) && (UTILS_PLLVCO_MEDIUM_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_MEDIUM_OUTPUT_MAX)) || \
222 (((__RANGE__) == LL_RCC_PLLVCORANGE_WIDE) && (UTILS_PLLVCO_WIDE_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_WIDE_OUTPUT_MAX)))
223
224 #define IS_LL_UTILS_CHECK_VCO_RANGES(__RANGEIN__, __RANGEOUT__) ( \
225 (((__RANGEIN__) == LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_MEDIUM)) || \
226 (((__RANGEIN__) != LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_WIDE)))
227
228 #if (STM32H7_DEV_ID == 0x450UL)
229 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
230 (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
231 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
232 #else
233 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE0) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE0) : \
234 (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
235 (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
236 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
237 #endif /* STM32H7_DEV_ID == 0x450UL */
238
239 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
240 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
241
242 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
243 /**
244 * @}
245 */
246 /* Private function prototypes -----------------------------------------------*/
247 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
248 * @{
249 */
250 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
251 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
252 static ErrorStatus UTILS_IsPLLsReady(void);
253 /**
254 * @}
255 */
256
257 /* Exported functions --------------------------------------------------------*/
258 /** @addtogroup UTILS_LL_Exported_Functions
259 * @{
260 */
261
262 /** @addtogroup UTILS_LL_EF_DELAY
263 * @{
264 */
265 #if defined (DUAL_CORE)
266 /**
267 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
268 * @note When a RTOS is used, it is recommended to avoid changing the Systick
269 * configuration by calling this function, for a delay use rather osDelay RTOS service.
270 * @param CPU_Frequency Core frequency in Hz
271 * @note CPU_Frequency can be calculated thanks to RCC helper macro or function
272 * @ref LL_RCC_GetSystemClocksFreq
273 * LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency
274 * and __LL_RCC_CALC_HCLK_FREQ is used to calculate the CM4 clock frequency.
275 * @retval None
276 */
277 #else
278 /**
279 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
280 * @note When a RTOS is used, it is recommended to avoid changing the Systick
281 * configuration by calling this function, for a delay use rather osDelay RTOS service.
282 * @param CPU_Frequency Core frequency in Hz
283 * @note CPU_Frequency can be calculated thanks to RCC helper macro or function
284 * @ref LL_RCC_GetSystemClocksFreq
285 * @retval None
286 */
287 #endif /* DUAL_CORE */
LL_Init1msTick(uint32_t CPU_Frequency)288 void LL_Init1msTick(uint32_t CPU_Frequency)
289 {
290 /* Use frequency provided in argument */
291 LL_InitTick(CPU_Frequency, 1000U);
292 }
293
294
295 /**
296 * @brief This function provides accurate delay (in milliseconds) based
297 * on SysTick counter flag
298 * @note When a RTOS is used, it is recommended to avoid using blocking delay
299 * and use rather osDelay service.
300 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
301 * will configure Systick to 1ms
302 * @param Delay specifies the delay time length, in milliseconds.
303 * @retval None
304 */
LL_mDelay(uint32_t Delay)305 void LL_mDelay(uint32_t Delay)
306 {
307 uint32_t count = Delay;
308 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
309 /* Add this code to indicate that local variable is not used */
310 ((void)tmp);
311
312 /* Add a period to guaranty minimum wait */
313 if(count < LL_MAX_DELAY)
314 {
315 count++;
316 }
317
318 while (count != 0U)
319 {
320 if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
321 {
322 count--;
323 }
324 }
325 }
326
327 /**
328 * @}
329 */
330
331 #if (STM32H7_DEV_ID == 0x450UL)
332 /** @addtogroup UTILS_EF_SYSTEM
333 * @brief System Configuration functions
334 *
335 @verbatim
336 ===============================================================================
337 ##### System Configuration functions #####
338 ===============================================================================
339 [..]
340 System, AHB and APB buses clocks configuration
341
342 (+) The maximum frequency of the SYSCLK is 480 MHz(*) and HCLK is 240 MHz.
343 (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 120 MHz.
344 @endverbatim
345 @internal
346 Depending on the device voltage range, the maximum frequency should be
347 adapted accordingly:
348 (++) +----------------------------------------------------------------------------+
349 (++) | Wait states | HCLK clock frequency (MHz) |
350 (++) | |-----------------------------------------------------------|
351 (++) | (Latency) | voltage range 1 | voltage range 2 | voltage range 3 |
352 (++) | | 1.15V - 1.26V | 1.05V - 1.15V | 0.95V - 1.05V |
353 (++) |----------------|-------------------|-------------------|-------------------|
354 (++) |0WS(1CPU cycle) | 0 < HCLK <= 70 | 0 < HCLK <= 55 | 0 < HCLK <= 45 |
355 (++) |----------------|-------------------|-------------------|-------------------|
356 (++) |1WS(2CPU cycle) | 70 < HCLK <= 140 | 55 < HCLK <= 110 | 45 < HCLK <= 90 |
357 (++) |----------------|-------------------|-------------------|-------------------|
358 (++) |2WS(3CPU cycle) | 140 < HCLK <= 240 | 110 < HCLK <= 165 | 90 < HCLK <= 135 |
359 (++) |----------------|-------------------|-------------------|-------------------|
360 (++) |3WS(4CPU cycle) | -- | 165 < HCLK <= 220 | 135 < HCLK <= 180 |
361 (++) |----------------|-------------------|-------------------|-------------------|
362 (++) |4WS(5CPU cycle) | -- | -- | 180 < HCLK <= 225 |
363 (++) +----------------------------------------------------------------------------+
364
365 (*) : For stm32h74xxx and stm32h75xxx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise.
366 @endinternal
367 * @{
368 */
369
370 #elif (STM32H7_DEV_ID == 0x480UL)
371 /** @addtogroup UTILS_EF_SYSTEM
372 * @brief System Configuration functions
373 *
374 @verbatim
375 ===============================================================================
376 ##### System Configuration functions #####
377 ===============================================================================
378 [..]
379 System, AHB and APB buses clocks configuration
380
381 (+) The maximum frequency of the SYSCLK is 280 MHz and HCLK is 280 MHz.
382 (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 140 MHz.
383 @endverbatim
384 @internal
385 Depending on the device voltage range, the maximum frequency should be
386 adapted accordingly:
387 (++) +------------------------------------------------------------------------------------------------+
388 (++) | Wait states | HCLK clock frequency (MHz) |
389 (++) | |-------------------------------------------------------------------------------|
390 (++) | (Latency) | voltage range 0 | voltage range 1 | voltage range 2 | voltage range 3 |
391 (++) | | 1.26V - 1.35V | 1.15V - 1.26V | 1.05V - 1.15V | 0.95V - 1.05V |
392 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
393 (++) |0WS(1CPU cycle) | 0 < HCLK <= 44 | 0 < HCLK <= 42 | 0 < HCLK <= 34 | 0 < HCLK <= 22 |
394 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
395 (++) |1WS(2CPU cycle) | 44 < HCLK <= 88 | 42 < HCLK <= 84 | 34 < HCLK <= 68 | 22 < HCLK <= 44 |
396 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
397 (++) |2WS(3CPU cycle) | 88 < HCLK <= 132 | 84 < HCLK <= 126 | 68 < HCLK <= 102 | 44 < HCLK <= 66 |
398 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
399 (++) |3WS(4CPU cycle) | 132 < HCLK <= 176 | 126 < HCLK <= 168 | 102 < HCLK <= 136 | 66 < HCLK <= 88 |
400 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
401 (++) |4WS(5CPU cycle) | 176 < HCLK <= 220 | 168 < HCLK <= 210 | 136 < HCLK <= 160 | -- |
402 (++) +------------------------------------------------------------------------------------------------+
403 (++) |5WS(6CPU cycle) | 220 < HCLK <= 264 | 210 < HCLK <= 225 | -- | -- |
404 (++) +------------------------------------------------------------------------------------------------+
405 (++) |6WS(7CPU cycle) | 264 < HCLK <= 280 | -- | -- | -- |
406 (++) +------------------------------------------------------------------------------------------------+
407 (++) |7WS(8CPU cycle) | -- | -- | -- | -- |
408 (++) +------------------------------------------------------------------------------------------------+
409
410 @endinternal
411 * @{
412 */
413
414 #elif (STM32H7_DEV_ID == 0x483UL)
415 /** @addtogroup UTILS_EF_SYSTEM
416 * @brief System Configuration functions
417 *
418 @verbatim
419 ===============================================================================
420 ##### System Configuration functions #####
421 ===============================================================================
422 [..]
423 System, AHB and APB buses clocks configuration
424
425 (+) The maximum frequency of the SYSCLK is 550 MHz(*) and HCLK is 275 MHz.
426 (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 137.5 MHz.
427 @endverbatim
428 @internal
429 Depending on the device voltage range, the maximum frequency should be
430 adapted accordingly:
431 (++) +------------------------------------------------------------------------------------------------+
432 (++) | Wait states | HCLK clock frequency (MHz) |
433 (++) | |-------------------------------------------------------------------------------|
434 (++) | (Latency) | voltage range 0 | voltage range 1 | voltage range 2 | voltage range 3 |
435 (++) | | 1.26V - 1.40V | 1.15V - 1.26V | 1.05V - 1.15V | 0.95V - 1.05V |
436 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
437 (++) |0WS(1CPU cycle) | 0 < HCLK <= 70 | 0 < HCLK <= 67 | 0 < HCLK <= 50 | 0 < HCLK <= 35 |
438 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
439 (++) |1WS(2CPU cycle) | 70 < HCLK <= 140 | 67 < HCLK <= 133 | 50 < HCLK <= 100 | 35 < HCLK <= 70 |
440 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
441 (++) |2WS(3CPU cycle) | 140 < HCLK <= 210 | 133 < HCLK <= 200 | 100 < HCLK <= 150 | 70 < HCLK <= 85 |
442 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
443 (++) |3WS(4CPU cycle) | 210 < HCLK <= 275 | -- | -- | -- |
444 (++) +----------------|-------------------|-------------------|-------------------|-------------------|
445
446 (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise.
447 @endinternal
448 * @{
449 */
450 #endif /* STM32H7_DEV_ID == 0x450UL */
451
452 #if defined (DUAL_CORE)
453 /**
454 * @brief This function sets directly SystemCoreClock CMSIS variable.
455 * @note Variable can be calculated also through SystemCoreClockUpdate function.
456 * @param CPU_Frequency Core frequency in Hz
457 * @note CPU_Frequency can be calculated thanks to RCC helper macro or function
458 * @ref LL_RCC_GetSystemClocksFreq
459 * LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency
460 * and __LL_RCC_CALC_HCLK_FREQ is used to calculate the CM4 clock frequency.
461 * @retval None
462 */
463 #else
464 /**
465 * @brief This function sets directly SystemCoreClock CMSIS variable.
466 * @note Variable can be calculated also through SystemCoreClockUpdate function.
467 * @param CPU_Frequency Core frequency in Hz
468 * @note CPU_Frequency can be calculated thanks to RCC helper macro or function
469 * @ref LL_RCC_GetSystemClocksFreq
470 * @retval None
471 */
472 #endif /* DUAL_CORE */
LL_SetSystemCoreClock(uint32_t CPU_Frequency)473 void LL_SetSystemCoreClock(uint32_t CPU_Frequency)
474 {
475 /* HCLK clock frequency */
476 SystemCoreClock = CPU_Frequency;
477 }
478
479 /**
480 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
481 * @note The application need to ensure that PLL is disabled.
482 * @note Function is based on the following formula:
483 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
484 * - PLLM: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
485 * - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(***) (PLLVCO_output = PLLVCO_input * PLLN)
486 * - PLLP: ensure that max frequency at 550000000 Hz(*), 480000000 Hz(**) or 280000000 Hz(***) is reach (PLLVCO_output / PLLP)
487 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
488 * the configuration information for the PLL.
489 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
490 * the configuration information for the BUS prescalers.
491 * @retval An ErrorStatus enumeration value:
492 * - SUCCESS: Max frequency configuration done
493 * - ERROR: Max frequency configuration not done
494 *
495 * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise.
496 * (**) : For stm32h74xxx and stm32h75xxx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise.
497 * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
498 *
499 */
LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)500 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
501 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
502 {
503 ErrorStatus status;
504 #ifdef USE_FULL_ASSERT
505 uint32_t vcoinput_freq, vcooutput_freq;
506 #endif
507 uint32_t pllfreq, hsi_clk;
508
509 /* Check the parameters */
510 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
511 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
512 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
513 assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
514
515 hsi_clk = (HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos));
516
517 /* Check VCO Input frequency */
518 #ifdef USE_FULL_ASSERT
519 vcoinput_freq = hsi_clk / UTILS_PLLInitStruct->PLLM;
520 #endif
521 assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input));
522
523 /* Check VCO Output frequency */
524 #ifdef USE_FULL_ASSERT
525 vcooutput_freq = LL_RCC_CalcPLLClockFreq(hsi_clk, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1UL);
526 #endif
527 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
528
529 /* Check VCO Input ranges */
530 assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output));
531
532 /* Check if one of the PLL is enabled */
533 if(UTILS_IsPLLsReady() == SUCCESS)
534 {
535 /* Calculate the new PLL output frequency */
536 pllfreq = UTILS_GetPLLOutputFrequency(hsi_clk, UTILS_PLLInitStruct);
537
538 /* Enable HSI if not enabled */
539 if(LL_RCC_HSI_IsReady() != 1U)
540 {
541 LL_RCC_HSI_Enable();
542 while (LL_RCC_HSI_IsReady() != 1U)
543 {
544 /* Wait for HSI ready */
545 }
546 }
547
548 /* Configure PLL */
549 LL_RCC_PLL1P_Enable();
550 LL_RCC_PLL1FRACN_Enable();
551 LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSI);
552 LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input);
553 LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output);
554 LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM);
555 LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN);
556 LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP);
557 LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN);
558
559 /* Enable PLL and switch system clock to PLL */
560 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
561 }
562 else
563 {
564 /* Current PLL configuration cannot be modified */
565 status = ERROR;
566 }
567
568 return status;
569 }
570
571 /**
572 * @brief This function configures system clock with HSE as clock source of the PLL
573 * @note The application need to ensure that PLL is disabled.
574 * @note Function is based on the following formula:
575 * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
576 * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
577 * - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(***) (PLLVCO_output = PLLVCO_input * PLLN)
578 * - PLLP: ensure that max frequency at 550000000 Hz(*), 480000000 Hz(**) or 280000000 Hz(***) is reached (PLLVCO_output / PLLP)
579 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
580 * @param HSEBypass This parameter can be one of the following values:
581 * @arg @ref LL_UTILS_HSEBYPASS_ON
582 * @arg @ref LL_UTILS_HSEBYPASS_OFF
583 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
584 * the configuration information for the PLL.
585 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
586 * the configuration information for the BUS prescalers.
587 * @retval An ErrorStatus enumeration value:
588 * - SUCCESS: Max frequency configuration done
589 * - ERROR: Max frequency configuration not done
590 *
591 * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise.
592 * (**) : For stm32h74xxx and stm32h75xxx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise.
593 * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
594 *
595 */
LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,uint32_t HSEBypass,LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)596 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
597 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
598 {
599 ErrorStatus status;
600 #ifdef USE_FULL_ASSERT
601 uint32_t vcoinput_freq, vcooutput_freq;
602 #endif
603 uint32_t pllfreq;
604
605 /* Check the parameters */
606 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
607 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
608 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
609 assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
610 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
611 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
612
613 /* Check VCO Input frequency */
614 #ifdef USE_FULL_ASSERT
615 vcoinput_freq = HSEFrequency / UTILS_PLLInitStruct->PLLM;
616 #endif
617 assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input));
618
619 /* Check VCO output frequency */
620 #ifdef USE_FULL_ASSERT
621 vcooutput_freq = LL_RCC_CalcPLLClockFreq(HSEFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1U);
622 #endif
623 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
624
625 /* Check VCO Input/output ranges compatibility */
626 assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output));
627
628 /* Check if one of the PLL is enabled */
629 if(UTILS_IsPLLsReady() == SUCCESS)
630 {
631 /* Calculate the new PLL output frequency */
632 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
633
634 /* Enable HSE if not enabled */
635 if(LL_RCC_HSE_IsReady() != 1U)
636 {
637 /* Check if need to enable HSE bypass feature or not */
638 if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
639 {
640 LL_RCC_HSE_EnableBypass();
641 }
642 else
643 {
644 LL_RCC_HSE_DisableBypass();
645 }
646
647 /* Enable HSE */
648 LL_RCC_HSE_Enable();
649 while (LL_RCC_HSE_IsReady() != 1U)
650 {
651 /* Wait for HSE ready */
652 }
653 }
654
655 /* Configure PLL */
656 LL_RCC_PLL1P_Enable();
657 LL_RCC_PLL1FRACN_Enable();
658 LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
659 LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input);
660 LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output);
661 LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM);
662 LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN);
663 LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP);
664 LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN);
665
666 /* Enable PLL and switch system clock to PLL */
667 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
668 }
669 else
670 {
671 /* Current PLL configuration cannot be modified */
672 status = ERROR;
673 }
674
675 return status;
676 }
677
678 /**
679 * @}
680 */
681
682 /**
683 * @brief Update number of Flash wait states in line with new frequency and current
684 voltage range.
685 * @param HCLK_Frequency HCLK frequency
686 * @retval An ErrorStatus enumeration value:
687 * - SUCCESS: Latency has been modified
688 * - ERROR: Latency cannot be modified
689 */
LL_SetFlashLatency(uint32_t HCLK_Frequency)690 ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
691 {
692 ErrorStatus status = SUCCESS;
693 uint32_t timeout;
694 uint32_t getlatency;
695 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
696
697
698
699 /* Frequency cannot be equal to 0 */
700 if (HCLK_Frequency == 0U)
701 {
702 status = ERROR;
703 }
704 else
705 {
706 #if (STM32H7_DEV_ID == 0x480UL) || (STM32H7_DEV_ID == 0x483UL)
707 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE0)
708 {
709 #if (STM32H7_DEV_ID == 0x480UL)
710 if((HCLK_Frequency > UTILS_SCALE0_LATENCY5_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY6_FREQ))
711 {
712 /* 264 < HCLK <= 280 => 6WS (7 CPU cycles) */
713 latency = LL_FLASH_LATENCY_6;
714 }
715 else if((HCLK_Frequency > UTILS_SCALE0_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY5_FREQ))
716 {
717 /* 220 < HCLK <= 264 => 5WS (6 CPU cycles) */
718 latency = LL_FLASH_LATENCY_5;
719 }
720 else if((HCLK_Frequency > UTILS_SCALE0_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY4_FREQ))
721 {
722 /* 176 < HCLK <= 220 => 4WS (5 CPU cycles) */
723 latency = LL_FLASH_LATENCY_4;
724 }
725 else if((HCLK_Frequency > UTILS_SCALE0_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY3_FREQ))
726 #elif (STM32H7_DEV_ID == 0x483UL)
727 if((HCLK_Frequency > UTILS_SCALE0_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY3_FREQ))
728 #endif /* STM32H7_DEV_ID == 0x480UL */
729 {
730 /* 132 < HCLK <= 176 => 3WS (4 CPU cycles) */
731 latency = LL_FLASH_LATENCY_3;
732 }
733 else if((HCLK_Frequency > UTILS_SCALE0_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY2_FREQ))
734 {
735 /* 88 < HCLK <= 132 => 2WS (3 CPU cycles) */
736 latency = LL_FLASH_LATENCY_2;
737 }
738 else if((HCLK_Frequency > UTILS_SCALE0_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY1_FREQ))
739 {
740 /* 44 < HCLK <= 88 => 1WS (2 CPU cycles) */
741 latency = LL_FLASH_LATENCY_1;
742 }
743 else if(HCLK_Frequency <= UTILS_SCALE0_LATENCY0_FREQ)
744 {
745 /* HCLK <= 44 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */
746 }
747 else
748 {
749 status = ERROR;
750 }
751 }
752 #if (STM32H7_DEV_ID == 0x480UL)
753 else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
754 {
755 if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY5_FREQ))
756 {
757 /* 210 < HCLK <= 225 => 5WS (6 CPU cycles) */
758 latency = LL_FLASH_LATENCY_5;
759 }
760 else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY4_FREQ))
761 {
762 /* 168 < HCLK <= 210 => 4WS (5 CPU cycles) */
763 latency = LL_FLASH_LATENCY_4;
764 }
765 else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY3_FREQ))
766 {
767 /* 126 < HCLK <= 168 => 3WS (4 CPU cycles) */
768 latency = LL_FLASH_LATENCY_3;
769 }
770 else if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ))
771 #else
772 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
773 {
774 if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ))
775 #endif /* STM32H7_DEV_ID == 0x480UL */
776 #else
777 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
778 {
779 if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ))
780 #endif /* STM32H7_DEV_ID == 0x480UL || STM32H7_DEV_ID == 0x483UL */
781 {
782 /* 140 < HCLK <= 210 => 2WS (3 CPU cycles) */
783 latency = LL_FLASH_LATENCY_2;
784 }
785 else if((HCLK_Frequency > UTILS_SCALE1_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ))
786 {
787 /* 70 < HCLK <= 140 => 1WS (2 CPU cycles) */
788 latency = LL_FLASH_LATENCY_1;
789 }
790 else if(HCLK_Frequency <= UTILS_SCALE1_LATENCY0_FREQ)
791 {
792 /* HCLK <= 70 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */
793 }
794 else
795 {
796 status = ERROR;
797 }
798 }
799 else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
800 {
801 #if (STM32H7_DEV_ID == 0x480UL) || (STM32H7_DEV_ID == 0x450UL)
802 #if (STM32H7_DEV_ID == 0x480UL)
803 if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY4_FREQ))
804 {
805 /* 136 < HCLK <= 160 => 4WS (5 CPU cycles) */
806 latency = LL_FLASH_LATENCY_4;
807 }
808 else if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ))
809 #else
810 if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ))
811 #endif /* STM32H7_DEV_ID == 0x480UL */
812 {
813 /* 165 < HCLK <= 220 => 3WS (4 CPU cycles) */
814 latency = LL_FLASH_LATENCY_3;
815 }
816 else if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ))
817 #else
818 if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ))
819 #endif /* STM32H7_DEV_ID == 0x480UL || STM32H7_DEV_ID == 0x450UL */
820 {
821 /* 110 < HCLK <= 165 => 2WS (3 CPU cycles) */
822 latency = LL_FLASH_LATENCY_2;
823 }
824 else if((HCLK_Frequency > UTILS_SCALE2_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY1_FREQ))
825 {
826 /* 55 < HCLK <= 110 => 1WS (2 CPU cycles) */
827 latency = LL_FLASH_LATENCY_1;
828 }
829 else if(HCLK_Frequency <= UTILS_SCALE2_LATENCY0_FREQ)
830 {
831 /* HCLK <= 55 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */
832 }
833 else
834 {
835 status = ERROR;
836 }
837 }
838 else /* Scale 3 */
839 {
840 #if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL)
841 #if (STM32H7_DEV_ID == 0x450UL)
842 if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY4_FREQ))
843 {
844 /* 180 < HCLK <= 225 => 4WS (5 CPU cycles) */
845 latency = LL_FLASH_LATENCY_4;
846 }
847 else if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ))
848 #else
849 if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ))
850 #endif /*STM32H7_DEV_ID == 0x450UL*/
851 {
852 /* 135 < HCLK <= 180 => 3WS (4 CPU cycles) */
853 latency = LL_FLASH_LATENCY_3;
854 }
855 else if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ))
856 #else
857 if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ))
858 #endif /* STM32H7_DEV_ID == 0x450UL || STM32H7_DEV_ID == 0x480UL */
859 {
860 /* 90 < HCLK <= 135 => 2WS (3 CPU cycles) */
861 latency = LL_FLASH_LATENCY_2;
862 }
863 else if((HCLK_Frequency > UTILS_SCALE3_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY1_FREQ))
864 {
865 /* 45 < HCLK <= 90 => 1WS (2 CPU cycles) */
866 latency = LL_FLASH_LATENCY_1;
867 }
868 else if(HCLK_Frequency <= UTILS_SCALE3_LATENCY0_FREQ)
869 {
870 /* HCLK <= 45 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */
871 }
872 else
873 {
874 status = ERROR;
875 }
876 }
877
878 if(status == SUCCESS)
879 {
880 LL_FLASH_SetLatency(latency);
881
882 /* Check that the new number of wait states is taken into account to access the Flash
883 memory by reading the FLASH_ACR register */
884 timeout = 2;
885 do
886 {
887 /* Wait for Flash latency to be updated */
888 getlatency = LL_FLASH_GetLatency();
889 timeout--;
890 } while ((getlatency != latency) && (timeout > 0U));
891
892 if(getlatency != latency)
893 {
894 status = ERROR;
895 }
896 }
897 }
898
899 return status;
900 }
901
902
903 /**
904 * @}
905 */
906
907 /** @addtogroup UTILS_LL_Private_Functions
908 * @{
909 */
910
911
912 /**
913 * @brief Function to check that PLL can be modified
914 * @param PLL_InputFrequency PLL input frequency (in Hz)
915 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
916 * the configuration information for the PLL.
917 * @retval PLL output frequency (in Hz)
918 */
919 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
920 {
921 uint32_t pllfreq;
922
923 /* Check the parameters */
924 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
925 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
926 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
927 assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
928
929 pllfreq = LL_RCC_CalcPLLClockFreq(PLL_InputFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, UTILS_PLLInitStruct->PLLP);
930
931 return pllfreq;
932 }
933
934 /**
935 * @brief Check that all PLLs are ready therefore configuration can be done
936 * @retval An ErrorStatus enumeration value:
937 * - SUCCESS: All PLLs are ready so configuration can be done
938 * - ERROR: One PLL at least is busy
939 */
940 static ErrorStatus UTILS_IsPLLsReady(void)
941 {
942 ErrorStatus status = SUCCESS;
943
944 /* Check if one of the PLL1 is busy */
945 if(LL_RCC_PLL1_IsReady() != 0U)
946 {
947 /* PLL1 configuration cannot be done */
948 status = ERROR;
949 }
950
951 /* Check if one of the PLL2 is busy */
952 if(LL_RCC_PLL2_IsReady() != 0U)
953 {
954 /* PLL2 configuration cannot be done */
955 status = ERROR;
956 }
957
958 /* Check if one of the PLL3 is busy */
959 if(LL_RCC_PLL3_IsReady() != 0U)
960 {
961 /* PLL3 configuration cannot be done */
962 status = ERROR;
963 }
964
965 return status;
966 }
967
968 /**
969 * @brief Function to enable PLL and switch system clock to PLL
970 * @param SYSCLK_Frequency SYSCLK frequency
971 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
972 * the configuration information for the BUS prescalers.
973 * @retval An ErrorStatus enumeration value:
974 * - SUCCESS: No problem to switch system to PLL
975 * - ERROR: Problem to switch system to PLL
976 */
977 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
978 {
979 ErrorStatus status = SUCCESS;
980 uint32_t new_hclk_frequency;
981
982 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->SYSCLKDivider));
983 assert_param(IS_LL_UTILS_AHB_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
984 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
985 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
986 assert_param(IS_LL_UTILS_APB3_DIV(UTILS_ClkInitStruct->APB3CLKDivider));
987 assert_param(IS_LL_UTILS_APB4_DIV(UTILS_ClkInitStruct->APB4CLKDivider));
988
989 /* Calculate the new HCLK frequency */
990 new_hclk_frequency = LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
991
992 /* Increasing the number of wait states because of higher CPU frequency */
993 if (SystemD2Clock < new_hclk_frequency)
994 {
995 /* Set FLASH latency to highest latency */
996 status = LL_SetFlashLatency(new_hclk_frequency);
997 }
998
999 /* Update system clock configuration */
1000 if(status == SUCCESS)
1001 {
1002 /* Enable PLL */
1003 LL_RCC_PLL1_Enable();
1004 while (LL_RCC_PLL1_IsReady() != 1U)
1005 {
1006 /* Wait for PLL ready */
1007 }
1008
1009 /* Set All APBxPrescaler to the Highest Divider */
1010 LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_16);
1011 LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_16);
1012 LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_16);
1013 LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_16);
1014
1015 /* Set SYS prescaler*/
1016 LL_RCC_SetSysPrescaler(UTILS_ClkInitStruct->SYSCLKDivider);
1017
1018 /* Set AHB prescaler*/
1019 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
1020
1021 /* Sysclk activation on the main PLL */
1022 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
1023 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
1024 {
1025 /* Wait for system clock switch to PLL */
1026 }
1027
1028 /* Set APBn prescaler*/
1029 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
1030 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
1031 LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider);
1032 LL_RCC_SetAPB4Prescaler(UTILS_ClkInitStruct->APB4CLKDivider);
1033
1034 /* Decreasing the number of wait states because of lower CPU frequency */
1035 if (SystemD2Clock > new_hclk_frequency)
1036 {
1037 /* Set FLASH latency to lowest latency */
1038 status = LL_SetFlashLatency(new_hclk_frequency);
1039 }
1040
1041 /* Update the SystemD2Clock global variable */
1042 #if defined(RCC_D1CFGR_HPRE)
1043 SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
1044 #else
1045 SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
1046 #endif
1047
1048 /* Update SystemCoreClock variable */
1049 #if defined(DUAL_CORE) && defined(CORE_CM4)
1050 LL_SetSystemCoreClock(SystemD2Clock);
1051 #else
1052 LL_SetSystemCoreClock(SYSCLK_Frequency);
1053 #endif /* DUAL_CORE && CORE_CM4 */
1054
1055 }
1056
1057
1058 return status;
1059 }
1060
1061 /**
1062 * @}
1063 */
1064
1065 /**
1066 * @}
1067 */
1068
1069 /**
1070 * @}
1071 */
1072
1073
