1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17 #if defined(USE_FULL_LL_DRIVER)
18
19 /* Includes ------------------------------------------------------------------*/
20 #include "stm32h7xx_ll_rcc.h"
21 #include "stm32h7xx_ll_bus.h"
22 #ifdef USE_FULL_ASSERT
23 #include "stm32_assert.h"
24 #else
25 #define assert_param(expr) ((void)0U)
26 #endif
27
28 /** @addtogroup STM32H7xx_LL_Driver
29 * @{
30 */
31
32 #if defined(RCC)
33
34 /** @addtogroup RCC_LL
35 * @{
36 */
37
38 /* Private types -------------------------------------------------------------*/
39 /* Private variables ---------------------------------------------------------*/
40 /** @addtogroup RCC_LL_Private_Variables
41 * @{
42 */
43 const uint8_t LL_RCC_PrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
44
45 /**
46 * @}
47 */
48 /* Private constants ---------------------------------------------------------*/
49 /* Private macros ------------------------------------------------------------*/
50 /** @addtogroup RCC_LL_Private_Macros
51 * @{
52 */
53 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART16_CLKSOURCE) \
54 || ((__VALUE__) == LL_RCC_USART234578_CLKSOURCE))
55
56
57 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C123_CLKSOURCE) \
58 || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
59
60 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
61 || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) \
62 || ((__VALUE__) == LL_RCC_LPTIM345_CLKSOURCE))
63
64 #if defined(SAI3)
65 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
66 || ((__VALUE__) == LL_RCC_SAI23_CLKSOURCE) \
67 || ((__VALUE__) == LL_RCC_SAI4A_CLKSOURCE) \
68 || ((__VALUE__) == LL_RCC_SAI4B_CLKSOURCE))
69 #elif defined(SAI4)
70 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
71 || ((__VALUE__) == LL_RCC_SAI4A_CLKSOURCE) \
72 || ((__VALUE__) == LL_RCC_SAI4B_CLKSOURCE))
73 #else
74 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
75 || ((__VALUE__) == LL_RCC_SAI2A_CLKSOURCE) \
76 || ((__VALUE__) == LL_RCC_SAI2B_CLKSOURCE))
77 #endif /* SAI3 */
78
79 #define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI123_CLKSOURCE) \
80 || ((__VALUE__) == LL_RCC_SPI45_CLKSOURCE) \
81 || ((__VALUE__) == LL_RCC_SPI6_CLKSOURCE))
82
83 /**
84 * @}
85 */
86
87 /* Private function prototypes -----------------------------------------------*/
88 /** @defgroup RCC_LL_Private_Functions RCC Private functions
89 * @{
90 */
91 static uint32_t RCC_GetSystemClockFreq(void);
92 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
93 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
94 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
95 static uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency);
96 static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency);
97
98 /**
99 * @}
100 */
101
102
103 /* Exported functions --------------------------------------------------------*/
104 /** @addtogroup RCC_LL_Exported_Functions
105 * @{
106 */
107
108 /** @addtogroup RCC_LL_EF_Init
109 * @{
110 */
111
112 /**
113 * @brief Resets the RCC clock configuration to the default reset state.
114 * @note The default reset state of the clock configuration is given below:
115 * - HSI ON and used as system clock source
116 * - HSE, PLL1, PLL2 and PLL3 OFF
117 * - AHB, APB Bus pre-scaler set to 1.
118 * - CSS, MCO1 and MCO2 OFF
119 * - All interrupts disabled
120 * @note This function doesn't modify the configuration of the
121 * - Peripheral clocks
122 * - LSI, LSE and RTC clocks
123 * @retval None
124 */
LL_RCC_DeInit(void)125 void LL_RCC_DeInit(void)
126 {
127 /* Increasing the CPU frequency */
128 if (FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
129 {
130 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
131 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
132 }
133
134 /* Set HSION bit */
135 SET_BIT(RCC->CR, RCC_CR_HSION);
136
137 /* Wait for HSI READY bit */
138 while (LL_RCC_HSI_IsReady() == 0U)
139 {}
140
141 /* Reset CFGR register */
142 CLEAR_REG(RCC->CFGR);
143
144 /* Reset CSION , CSIKERON, HSEON, HSI48ON, HSECSSON,HSIDIV, PLL1ON, PLL2ON, PLL3ON bits */
145 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON | RCC_CR_HSIDIV | RCC_CR_HSIDIVF | RCC_CR_CSION | RCC_CR_CSIKERON | RCC_CR_HSI48ON \
146 | RCC_CR_CSSHSEON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
147
148 /* Wait for PLL1 READY bit to be reset */
149 while (LL_RCC_PLL1_IsReady() != 0U)
150 {}
151
152 /* Wait for PLL2 READY bit to be reset */
153 while (LL_RCC_PLL2_IsReady() != 0U)
154 {}
155
156 /* Wait for PLL3 READY bit to be reset */
157 while (LL_RCC_PLL3_IsReady() != 0U)
158 {}
159
160 #if defined(RCC_D1CFGR_HPRE)
161 /* Reset D1CFGR register */
162 CLEAR_REG(RCC->D1CFGR);
163
164 /* Reset D2CFGR register */
165 CLEAR_REG(RCC->D2CFGR);
166
167 /* Reset D3CFGR register */
168 CLEAR_REG(RCC->D3CFGR);
169 #else
170 /* Reset CDCFGR1 register */
171 CLEAR_REG(RCC->CDCFGR1);
172
173 /* Reset CDCFGR2 register */
174 CLEAR_REG(RCC->CDCFGR2);
175
176 /* Reset SRDCFGR register */
177 CLEAR_REG(RCC->SRDCFGR);
178
179 #endif /* RCC_D1CFGR_HPRE */
180
181 /* Reset PLLCKSELR register to default value */
182 RCC->PLLCKSELR = RCC_PLLCKSELR_DIVM1_5 | RCC_PLLCKSELR_DIVM2_5 | RCC_PLLCKSELR_DIVM3_5;
183
184 /* Reset PLLCFGR register to default value */
185 LL_RCC_WriteReg(PLLCFGR, 0x01FF0000U);
186
187 /* Reset PLL1DIVR register to default value */
188 LL_RCC_WriteReg(PLL1DIVR, 0x01010280U);
189
190 /* Reset PLL1FRACR register */
191 CLEAR_REG(RCC->PLL1FRACR);
192
193 /* Reset PLL2DIVR register to default value */
194 LL_RCC_WriteReg(PLL2DIVR, 0x01010280U);
195
196 /* Reset PLL2FRACR register */
197 CLEAR_REG(RCC->PLL2FRACR);
198
199 /* Reset PLL3DIVR register to default value */
200 LL_RCC_WriteReg(PLL3DIVR, 0x01010280U);
201
202 /* Reset PLL3FRACR register */
203 CLEAR_REG(RCC->PLL3FRACR);
204
205 /* Reset HSEBYP bit */
206 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
207
208 /* Disable all interrupts */
209 CLEAR_REG(RCC->CIER);
210
211 /* Clear all interrupts */
212 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC
213 | RCC_CICR_CSIRDYC | RCC_CICR_HSI48RDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLL2RDYC
214 | RCC_CICR_PLL3RDYC | RCC_CICR_LSECSSC | RCC_CICR_HSECSSC);
215
216 /* Clear reset source flags */
217 SET_BIT(RCC->RSR, RCC_RSR_RMVF);
218
219 /* Decreasing the number of wait states because of lower CPU frequency */
220 if (FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
221 {
222 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
223 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
224 }
225
226 }
227
228 /**
229 * @}
230 */
231
232 /** @addtogroup RCC_LL_EF_Get_Freq
233 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
234 * and different peripheral clocks available on the device.
235 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
236 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
237 * @note If SYSCLK source is CSI, function returns values based on CSI_VALUE(***)
238 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
239 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
240 * @note (*) HSI_VALUE is a constant defined in header file (default value
241 * 64 MHz) divider by HSIDIV, but the real value may vary depending on
242 * on the variations in voltage and temperature.
243 * @note (**) HSE_VALUE is a constant defined in header file (default value
244 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
245 * frequency of the crystal used. Otherwise, this function may
246 * have wrong result.
247 * @note (***) CSI_VALUE is a constant defined in header file (default value
248 * 4 MHz) but the real value may vary depending on the variations
249 * in voltage and temperature.
250 * @note The result of this function could be incorrect when using fractional
251 * value for HSE crystal.
252 * @note This function can be used by the user application to compute the
253 * baud-rate for the communication peripherals or configure other parameters.
254 * @{
255 */
256
257 /**
258 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
259 * @note Each time SYSCLK, HCLK, PCLK1, PCLK2, PCLK3 and/or PCLK4 clock changes, this function
260 * must be called to update structure fields. Otherwise, any
261 * configuration based on this function will be incorrect.
262 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
263 * @retval None
264 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)265 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
266 {
267 /* Get SYSCLK frequency */
268 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
269
270 /* HCLK clock frequency */
271 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
272
273 /* PCLK1 clock frequency */
274 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
275
276 /* PCLK2 clock frequency */
277 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
278
279 /* PCLK3 clock frequency */
280 RCC_Clocks->PCLK3_Frequency = RCC_GetPCLK3ClockFreq(RCC_Clocks->HCLK_Frequency);
281
282 /* PCLK4 clock frequency */
283 RCC_Clocks->PCLK4_Frequency = RCC_GetPCLK4ClockFreq(RCC_Clocks->HCLK_Frequency);
284 }
285
286 /**
287 * @brief Return PLL1 clocks frequencies
288 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
289 * @retval None
290 */
LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef * PLL_Clocks)291 void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
292 {
293 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
294 uint32_t m, n, fracn = 0U;
295
296 /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
297 SYSCLK = PLL_VCO / PLLP
298 */
299 pllsource = LL_RCC_PLL_GetSource();
300
301 switch (pllsource)
302 {
303 case LL_RCC_PLLSOURCE_HSI:
304 if (LL_RCC_HSI_IsReady() != 0U)
305 {
306 pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
307 }
308 break;
309
310 case LL_RCC_PLLSOURCE_CSI:
311 if (LL_RCC_CSI_IsReady() != 0U)
312 {
313 pllinputfreq = CSI_VALUE;
314 }
315 break;
316
317 case LL_RCC_PLLSOURCE_HSE:
318 if (LL_RCC_HSE_IsReady() != 0U)
319 {
320 pllinputfreq = HSE_VALUE;
321 }
322 break;
323
324 case LL_RCC_PLLSOURCE_NONE:
325 default:
326 /* PLL clock disabled */
327 break;
328 }
329
330 PLL_Clocks->PLL_P_Frequency = 0U;
331 PLL_Clocks->PLL_Q_Frequency = 0U;
332 PLL_Clocks->PLL_R_Frequency = 0U;
333
334 m = LL_RCC_PLL1_GetM();
335 n = LL_RCC_PLL1_GetN();
336 if (LL_RCC_PLL1FRACN_IsEnabled() != 0U)
337 {
338 fracn = LL_RCC_PLL1_GetFRACN();
339 }
340
341 if (m != 0U)
342 {
343 if (LL_RCC_PLL1P_IsEnabled() != 0U)
344 {
345 PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetP());
346 }
347
348 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
349 {
350 PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetQ());
351 }
352
353 if (LL_RCC_PLL1R_IsEnabled() != 0U)
354 {
355 PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetR());
356 }
357 }
358 }
359
360 /**
361 * @brief Return PLL2 clocks frequencies
362 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
363 * @retval None
364 */
LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef * PLL_Clocks)365 void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
366 {
367 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
368 uint32_t m, n, fracn = 0U;
369
370 /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
371 SYSCLK = PLL_VCO / PLLP
372 */
373 pllsource = LL_RCC_PLL_GetSource();
374
375 switch (pllsource)
376 {
377 case LL_RCC_PLLSOURCE_HSI:
378 if (LL_RCC_HSI_IsReady() != 0U)
379 {
380 pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
381 }
382 break;
383
384 case LL_RCC_PLLSOURCE_CSI:
385 if (LL_RCC_CSI_IsReady() != 0U)
386 {
387 pllinputfreq = CSI_VALUE;
388 }
389 break;
390
391 case LL_RCC_PLLSOURCE_HSE:
392 if (LL_RCC_HSE_IsReady() != 0U)
393 {
394 pllinputfreq = HSE_VALUE;
395 }
396 break;
397
398 case LL_RCC_PLLSOURCE_NONE:
399 default:
400 /* PLL clock disabled */
401 break;
402 }
403
404 PLL_Clocks->PLL_P_Frequency = 0U;
405 PLL_Clocks->PLL_Q_Frequency = 0U;
406 PLL_Clocks->PLL_R_Frequency = 0U;
407
408 m = LL_RCC_PLL2_GetM();
409 n = LL_RCC_PLL2_GetN();
410 if (LL_RCC_PLL2FRACN_IsEnabled() != 0U)
411 {
412 fracn = LL_RCC_PLL2_GetFRACN();
413 }
414
415 if (m != 0U)
416 {
417 if (LL_RCC_PLL2P_IsEnabled() != 0U)
418 {
419 PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetP());
420 }
421
422 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
423 {
424 PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetQ());
425 }
426
427 if (LL_RCC_PLL2R_IsEnabled() != 0U)
428 {
429 PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetR());
430 }
431 }
432 }
433
434 /**
435 * @brief Return PLL3 clocks frequencies
436 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
437 * @retval None
438 */
LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef * PLL_Clocks)439 void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
440 {
441 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
442 uint32_t m, n, fracn = 0U;
443
444 /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
445 SYSCLK = PLL_VCO / PLLP
446 */
447 pllsource = LL_RCC_PLL_GetSource();
448
449 switch (pllsource)
450 {
451 case LL_RCC_PLLSOURCE_HSI:
452 if (LL_RCC_HSI_IsReady() != 0U)
453 {
454 pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
455 }
456 break;
457
458 case LL_RCC_PLLSOURCE_CSI:
459 if (LL_RCC_CSI_IsReady() != 0U)
460 {
461 pllinputfreq = CSI_VALUE;
462 }
463 break;
464
465 case LL_RCC_PLLSOURCE_HSE:
466 if (LL_RCC_HSE_IsReady() != 0U)
467 {
468 pllinputfreq = HSE_VALUE;
469 }
470 break;
471
472 case LL_RCC_PLLSOURCE_NONE:
473 default:
474 /* PLL clock disabled */
475 break;
476 }
477
478 PLL_Clocks->PLL_P_Frequency = 0U;
479 PLL_Clocks->PLL_Q_Frequency = 0U;
480 PLL_Clocks->PLL_R_Frequency = 0U;
481
482 m = LL_RCC_PLL3_GetM();
483 n = LL_RCC_PLL3_GetN();
484 if (LL_RCC_PLL3FRACN_IsEnabled() != 0U)
485 {
486 fracn = LL_RCC_PLL3_GetFRACN();
487 }
488
489 if ((m != 0U) && (pllinputfreq != 0U))
490 {
491 if (LL_RCC_PLL3P_IsEnabled() != 0U)
492 {
493 PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetP());
494 }
495
496 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
497 {
498 PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetQ());
499 }
500
501 if (LL_RCC_PLL3R_IsEnabled() != 0U)
502 {
503 PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetR());
504 }
505 }
506 }
507
508 /**
509 * @brief Helper function to calculate the PLL frequency output
510 * @note ex: @ref LL_RCC_CalcPLLClockFreq (HSE_VALUE, @ref LL_RCC_PLL1_GetM (),
511 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetFRACN (), @ref LL_RCC_PLL1_GetP ());
512 * @param PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/CSI)
513 * @param M Between 1 and 63
514 * @param N Between 4 and 512
515 * @param FRACN Between 0 and 0x1FFF
516 * @param PQR VCO output divider (P, Q or R)
517 * Between 1 and 128, except for PLL1P Odd value not allowed
518 * @retval PLL1 clock frequency (in Hz)
519 */
LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq,uint32_t M,uint32_t N,uint32_t FRACN,uint32_t PQR)520 uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR)
521 {
522 float_t freq;
523
524 freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN / (float_t)0x2000));
525
526 freq = freq / (float_t)PQR;
527
528 return (uint32_t)freq;
529 }
530
531 /**
532 * @brief Return USARTx clock frequency
533 * @param USARTxSource This parameter can be one of the following values:
534 * @arg @ref LL_RCC_USART16_CLKSOURCE
535 * @arg @ref LL_RCC_USART234578_CLKSOURCE
536 * @retval USART clock frequency (in Hz)
537 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
538 */
LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)539 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
540 {
541 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
542 LL_PLL_ClocksTypeDef PLL_Clocks;
543
544 /* Check parameter */
545 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
546
547 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
548 {
549 case LL_RCC_USART16_CLKSOURCE_PCLK2:
550 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
551 break;
552
553 case LL_RCC_USART234578_CLKSOURCE_PCLK1:
554 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
555 break;
556
557 case LL_RCC_USART16_CLKSOURCE_PLL2Q:
558 case LL_RCC_USART234578_CLKSOURCE_PLL2Q:
559 if (LL_RCC_PLL2_IsReady() != 0U)
560 {
561 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
562 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
563 }
564 break;
565
566 case LL_RCC_USART16_CLKSOURCE_PLL3Q:
567 case LL_RCC_USART234578_CLKSOURCE_PLL3Q:
568 if (LL_RCC_PLL3_IsReady() != 0U)
569 {
570 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
571 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
572 }
573 break;
574
575 case LL_RCC_USART16_CLKSOURCE_HSI:
576 case LL_RCC_USART234578_CLKSOURCE_HSI:
577 if (LL_RCC_HSI_IsReady() != 0U)
578 {
579 usart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
580 }
581 break;
582
583 case LL_RCC_USART16_CLKSOURCE_CSI:
584 case LL_RCC_USART234578_CLKSOURCE_CSI:
585 if (LL_RCC_CSI_IsReady() != 0U)
586 {
587 usart_frequency = CSI_VALUE;
588 }
589 break;
590
591 case LL_RCC_USART16_CLKSOURCE_LSE:
592 case LL_RCC_USART234578_CLKSOURCE_LSE:
593 if (LL_RCC_LSE_IsReady() != 0U)
594 {
595 usart_frequency = LSE_VALUE;
596 }
597 break;
598
599 default:
600 /* Kernel clock disabled */
601 break;
602 }
603
604 return usart_frequency;
605 }
606
607 /**
608 * @brief Return LPUART clock frequency
609 * @param LPUARTxSource This parameter can be one of the following values:
610 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
611 * @retval LPUART clock frequency (in Hz)
612 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
613 */
LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)614 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
615 {
616 uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
617 LL_PLL_ClocksTypeDef PLL_Clocks;
618
619 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
620 {
621 case LL_RCC_LPUART1_CLKSOURCE_PCLK4:
622 lpuart_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
623 break;
624
625 case LL_RCC_LPUART1_CLKSOURCE_PLL2Q:
626 if (LL_RCC_PLL2_IsReady() != 0U)
627 {
628 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
629 lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
630 }
631 break;
632
633 case LL_RCC_LPUART1_CLKSOURCE_PLL3Q:
634 if (LL_RCC_PLL3_IsReady() != 0U)
635 {
636 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
637 lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
638 }
639 break;
640
641 case LL_RCC_LPUART1_CLKSOURCE_HSI:
642 if (LL_RCC_HSI_IsReady() != 0U)
643 {
644 lpuart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
645 }
646 break;
647
648 case LL_RCC_LPUART1_CLKSOURCE_CSI:
649 if (LL_RCC_CSI_IsReady() != 0U)
650 {
651 lpuart_frequency = CSI_VALUE;
652 }
653 break;
654
655 case LL_RCC_LPUART1_CLKSOURCE_LSE:
656 if (LL_RCC_LSE_IsReady() != 0U)
657 {
658 lpuart_frequency = LSE_VALUE;
659 }
660 break;
661
662 default:
663 /* Kernel clock disabled */
664 break;
665 }
666
667 return lpuart_frequency;
668 }
669
670 /**
671 * @brief Return I2Cx clock frequency
672 * @param I2CxSource This parameter can be one of the following values:
673 * @arg @ref LL_RCC_I2C123_CLKSOURCE
674 * @arg @ref LL_RCC_I2C4_CLKSOURCE
675 * @retval I2C clock frequency (in Hz)
676 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
677 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)678 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
679 {
680 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
681 LL_PLL_ClocksTypeDef PLL_Clocks;
682
683 /* Check parameter */
684 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
685
686 switch (LL_RCC_GetI2CClockSource(I2CxSource))
687 {
688 case LL_RCC_I2C123_CLKSOURCE_PCLK1:
689 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
690 break;
691
692 case LL_RCC_I2C4_CLKSOURCE_PCLK4:
693 i2c_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
694 break;
695
696 case LL_RCC_I2C123_CLKSOURCE_PLL3R:
697 case LL_RCC_I2C4_CLKSOURCE_PLL3R:
698 if (LL_RCC_PLL3_IsReady() != 0U)
699 {
700 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
701 i2c_frequency = PLL_Clocks.PLL_R_Frequency;
702 }
703 break;
704
705 case LL_RCC_I2C123_CLKSOURCE_HSI:
706 case LL_RCC_I2C4_CLKSOURCE_HSI:
707 if (LL_RCC_HSI_IsReady() != 0U)
708 {
709 i2c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
710 }
711 break;
712
713 case LL_RCC_I2C123_CLKSOURCE_CSI:
714 case LL_RCC_I2C4_CLKSOURCE_CSI:
715 if (LL_RCC_CSI_IsReady() != 0U)
716 {
717 i2c_frequency = CSI_VALUE;
718 }
719 break;
720
721 default:
722 /* Nothing to do */
723 break;
724 }
725
726 return i2c_frequency;
727 }
728
729 /**
730 * @brief Return LPTIMx clock frequency
731 * @param LPTIMxSource This parameter can be one of the following values:
732 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
733 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
734 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE
735 * @retval LPTIM clock frequency (in Hz)
736 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
737 */
LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)738 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
739 {
740 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
741 LL_PLL_ClocksTypeDef PLL_Clocks;
742
743 /* Check parameter */
744 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
745
746 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
747 {
748 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:
749 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
750 break;
751
752 case LL_RCC_LPTIM2_CLKSOURCE_PCLK4:
753 case LL_RCC_LPTIM345_CLKSOURCE_PCLK4:
754 lptim_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
755 break;
756
757 case LL_RCC_LPTIM1_CLKSOURCE_PLL2P:
758 case LL_RCC_LPTIM2_CLKSOURCE_PLL2P:
759 case LL_RCC_LPTIM345_CLKSOURCE_PLL2P:
760 if (LL_RCC_PLL2_IsReady() != 0U)
761 {
762 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
763 lptim_frequency = PLL_Clocks.PLL_P_Frequency;
764 }
765 break;
766
767 case LL_RCC_LPTIM1_CLKSOURCE_PLL3R:
768 case LL_RCC_LPTIM2_CLKSOURCE_PLL3R:
769 case LL_RCC_LPTIM345_CLKSOURCE_PLL3R:
770 if (LL_RCC_PLL3_IsReady() != 0U)
771 {
772 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
773 lptim_frequency = PLL_Clocks.PLL_R_Frequency;
774 }
775 break;
776
777 case LL_RCC_LPTIM1_CLKSOURCE_LSE:
778 case LL_RCC_LPTIM2_CLKSOURCE_LSE:
779 case LL_RCC_LPTIM345_CLKSOURCE_LSE:
780 if (LL_RCC_LSE_IsReady() != 0U)
781 {
782 lptim_frequency = LSE_VALUE;
783 }
784 break;
785
786 case LL_RCC_LPTIM1_CLKSOURCE_LSI:
787 case LL_RCC_LPTIM2_CLKSOURCE_LSI:
788 case LL_RCC_LPTIM345_CLKSOURCE_LSI:
789 if (LL_RCC_LSI_IsReady() != 0U)
790 {
791 lptim_frequency = LSI_VALUE;
792 }
793 break;
794
795 case LL_RCC_LPTIM1_CLKSOURCE_CLKP:
796 case LL_RCC_LPTIM2_CLKSOURCE_CLKP:
797 case LL_RCC_LPTIM345_CLKSOURCE_CLKP:
798 lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
799 break;
800
801 default:
802 /* Kernel clock disabled */
803 break;
804 }
805
806 return lptim_frequency;
807 }
808
809 /**
810 * @brief Return SAIx clock frequency
811 * @param SAIxSource This parameter can be one of the following values:
812 * @arg @ref LL_RCC_SAI1_CLKSOURCE
813 * @arg @ref LL_RCC_SAI23_CLKSOURCE (*)
814 * @arg @ref LL_RCC_SAI2A_CLKSOURCE (*)
815 * @arg @ref LL_RCC_SAI2B_CLKSOURCE (*)
816 * @arg @ref LL_RCC_SAI4A_CLKSOURCE (*)
817 * @arg @ref LL_RCC_SAI4B_CLKSOURCE (*)
818 * @retval SAI clock frequency (in Hz)
819 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
820 *
821 * (*) : Available on some STM32H7 lines only.
822 */
LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)823 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
824 {
825 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
826 LL_PLL_ClocksTypeDef PLL_Clocks;
827
828 /* Check parameter */
829 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
830
831 switch (LL_RCC_GetSAIClockSource(SAIxSource))
832 {
833 case LL_RCC_SAI1_CLKSOURCE_PLL1Q:
834 #if defined(SAI3)
835 case LL_RCC_SAI23_CLKSOURCE_PLL1Q:
836 #endif /* SAI3 */
837 #if defined(SAI4)
838 case LL_RCC_SAI4A_CLKSOURCE_PLL1Q:
839 case LL_RCC_SAI4B_CLKSOURCE_PLL1Q:
840 #endif /* SAI4 */
841 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
842 case LL_RCC_SAI2A_CLKSOURCE_PLL1Q:
843 case LL_RCC_SAI2B_CLKSOURCE_PLL1Q:
844 #endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
845 if (LL_RCC_PLL1_IsReady() != 0U)
846 {
847 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
848 sai_frequency = PLL_Clocks.PLL_Q_Frequency;
849 }
850 break;
851
852 case LL_RCC_SAI1_CLKSOURCE_PLL2P:
853 #if defined(SAI3)
854 case LL_RCC_SAI23_CLKSOURCE_PLL2P:
855 #endif /* SAI3 */
856 #if defined(SAI4)
857 case LL_RCC_SAI4A_CLKSOURCE_PLL2P:
858 case LL_RCC_SAI4B_CLKSOURCE_PLL2P:
859 #endif /* SAI4 */
860 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
861 case LL_RCC_SAI2A_CLKSOURCE_PLL2P:
862 case LL_RCC_SAI2B_CLKSOURCE_PLL2P:
863 #endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
864 if (LL_RCC_PLL2_IsReady() != 0U)
865 {
866 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
867 sai_frequency = PLL_Clocks.PLL_P_Frequency;
868 }
869 break;
870
871 case LL_RCC_SAI1_CLKSOURCE_PLL3P:
872 #if defined(SAI3)
873 case LL_RCC_SAI23_CLKSOURCE_PLL3P:
874 #endif /* SAI3 */
875 #if defined(SAI4)
876 case LL_RCC_SAI4A_CLKSOURCE_PLL3P:
877 case LL_RCC_SAI4B_CLKSOURCE_PLL3P:
878 #endif /* SAI4 */
879 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
880 case LL_RCC_SAI2A_CLKSOURCE_PLL3P:
881 case LL_RCC_SAI2B_CLKSOURCE_PLL3P:
882 #endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
883 if (LL_RCC_PLL3_IsReady() != 0U)
884 {
885 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
886 sai_frequency = PLL_Clocks.PLL_P_Frequency;
887 }
888 break;
889
890 case LL_RCC_SAI1_CLKSOURCE_I2S_CKIN:
891 #if defined(SAI3)
892 case LL_RCC_SAI23_CLKSOURCE_I2S_CKIN:
893 #endif /* SAI3 */
894 #if defined(SAI4)
895 case LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN:
896 case LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN:
897 #endif /* SAI4 */
898 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
899 case LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN:
900 case LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN:
901 #endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
902 sai_frequency = EXTERNAL_CLOCK_VALUE;
903 break;
904
905 case LL_RCC_SAI1_CLKSOURCE_CLKP:
906 #if defined(SAI3)
907 case LL_RCC_SAI23_CLKSOURCE_CLKP:
908 #endif /* SAI3 */
909 #if defined(SAI4)
910 case LL_RCC_SAI4A_CLKSOURCE_CLKP:
911 case LL_RCC_SAI4B_CLKSOURCE_CLKP:
912 #endif /* SAI4 */
913 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
914 case LL_RCC_SAI2A_CLKSOURCE_CLKP:
915 case LL_RCC_SAI2B_CLKSOURCE_CLKP:
916 #endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
917 sai_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
918 break;
919
920 default:
921 /* Kernel clock disabled */
922 break;
923 }
924
925 return sai_frequency;
926 }
927
928 /**
929 * @brief Return ADC clock frequency
930 * @param ADCxSource This parameter can be one of the following values:
931 * @arg @ref LL_RCC_ADC_CLKSOURCE
932 * @retval ADC clock frequency (in Hz)
933 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
934 */
LL_RCC_GetADCClockFreq(uint32_t ADCxSource)935 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
936 {
937 uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
938 LL_PLL_ClocksTypeDef PLL_Clocks;
939
940 switch (LL_RCC_GetADCClockSource(ADCxSource))
941 {
942 case LL_RCC_ADC_CLKSOURCE_PLL2P:
943 if (LL_RCC_PLL2_IsReady() != 0U)
944 {
945 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
946 adc_frequency = PLL_Clocks.PLL_P_Frequency;
947 }
948 break;
949
950 case LL_RCC_ADC_CLKSOURCE_PLL3R:
951 if (LL_RCC_PLL3_IsReady() != 0U)
952 {
953 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
954 adc_frequency = PLL_Clocks.PLL_R_Frequency;
955 }
956 break;
957
958 case LL_RCC_ADC_CLKSOURCE_CLKP:
959 adc_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
960 break;
961
962 default:
963 /* Kernel clock disabled */
964 break;
965 }
966
967 return adc_frequency;
968 }
969
970 /**
971 * @brief Return SDMMC clock frequency
972 * @param SDMMCxSource This parameter can be one of the following values:
973 * @arg @ref LL_RCC_SDMMC_CLKSOURCE
974 * @retval SDMMC clock frequency (in Hz)
975 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
976 */
LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)977 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
978 {
979 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
980 LL_PLL_ClocksTypeDef PLL_Clocks;
981
982 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
983 {
984 case LL_RCC_SDMMC_CLKSOURCE_PLL1Q:
985 if (LL_RCC_PLL1_IsReady() != 0U)
986 {
987 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
988 sdmmc_frequency = PLL_Clocks.PLL_Q_Frequency;
989 }
990 break;
991
992 case LL_RCC_SDMMC_CLKSOURCE_PLL2R:
993 if (LL_RCC_PLL2_IsReady() != 0U)
994 {
995 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
996 sdmmc_frequency = PLL_Clocks.PLL_R_Frequency;
997 }
998 break;
999
1000 default:
1001 /* Nothing to do */
1002 break;
1003 }
1004
1005 return sdmmc_frequency;
1006 }
1007
1008 /**
1009 * @brief Return RNG clock frequency
1010 * @param RNGxSource This parameter can be one of the following values:
1011 * @arg @ref LL_RCC_RNG_CLKSOURCE
1012 * @retval RNG clock frequency (in Hz)
1013 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1014 */
LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)1015 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
1016 {
1017 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1018 LL_PLL_ClocksTypeDef PLL_Clocks;
1019
1020 switch (LL_RCC_GetRNGClockSource(RNGxSource))
1021 {
1022 case LL_RCC_RNG_CLKSOURCE_PLL1Q:
1023 if (LL_RCC_PLL1_IsReady() != 0U)
1024 {
1025 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1026 rng_frequency = PLL_Clocks.PLL_Q_Frequency;
1027 }
1028 break;
1029
1030 case LL_RCC_RNG_CLKSOURCE_HSI48:
1031 if (LL_RCC_HSI48_IsReady() != 0U)
1032 {
1033 rng_frequency = 48000000U;
1034 }
1035 break;
1036
1037 case LL_RCC_RNG_CLKSOURCE_LSE:
1038 if (LL_RCC_LSE_IsReady() != 0U)
1039 {
1040 rng_frequency = LSE_VALUE;
1041 }
1042 break;
1043
1044 case LL_RCC_RNG_CLKSOURCE_LSI:
1045 if (LL_RCC_LSI_IsReady() != 0U)
1046 {
1047 rng_frequency = LSI_VALUE;
1048 }
1049 break;
1050
1051 default:
1052 /* Nothing to do */
1053 break;
1054 }
1055
1056 return rng_frequency;
1057 }
1058
1059 /**
1060 * @brief Return CEC clock frequency
1061 * @param CECxSource This parameter can be one of the following values:
1062 * @arg @ref LL_RCC_RNG_CLKSOURCE
1063 * @retval CEC clock frequency (in Hz)
1064 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1065 */
LL_RCC_GetCECClockFreq(uint32_t CECxSource)1066 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
1067 {
1068 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1069
1070 switch (LL_RCC_GetCECClockSource(CECxSource))
1071 {
1072 case LL_RCC_CEC_CLKSOURCE_LSE:
1073 if (LL_RCC_LSE_IsReady() != 0U)
1074 {
1075 cec_frequency = LSE_VALUE;
1076 }
1077 break;
1078
1079 case LL_RCC_CEC_CLKSOURCE_LSI:
1080 if (LL_RCC_LSI_IsReady() != 0U)
1081 {
1082 cec_frequency = LSI_VALUE;
1083 }
1084 break;
1085
1086 case LL_RCC_CEC_CLKSOURCE_CSI_DIV122:
1087 if (LL_RCC_CSI_IsReady() != 0U)
1088 {
1089 cec_frequency = CSI_VALUE / 122U;
1090 }
1091 break;
1092
1093 default:
1094 /* Kernel clock disabled */
1095 break;
1096 }
1097
1098 return cec_frequency;
1099 }
1100
1101 /**
1102 * @brief Return USB clock frequency
1103 * @param USBxSource This parameter can be one of the following values:
1104 * @arg @ref LL_RCC_USB_CLKSOURCE
1105 * @retval USB clock frequency (in Hz)
1106 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or Disabled
1107 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)1108 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
1109 {
1110 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1111 LL_PLL_ClocksTypeDef PLL_Clocks;
1112
1113 switch (LL_RCC_GetUSBClockSource(USBxSource))
1114 {
1115 case LL_RCC_USB_CLKSOURCE_PLL1Q:
1116 if (LL_RCC_PLL1_IsReady() != 0U)
1117 {
1118 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1119 usb_frequency = PLL_Clocks.PLL_Q_Frequency;
1120 }
1121 break;
1122
1123 case LL_RCC_USB_CLKSOURCE_PLL3Q:
1124 if (LL_RCC_PLL3_IsReady() != 0U)
1125 {
1126 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1127 usb_frequency = PLL_Clocks.PLL_Q_Frequency;
1128 }
1129 break;
1130
1131 case LL_RCC_USB_CLKSOURCE_HSI48:
1132 if (LL_RCC_HSI48_IsReady() != 0U)
1133 {
1134 usb_frequency = HSI48_VALUE;
1135 }
1136 break;
1137
1138 case LL_RCC_USB_CLKSOURCE_DISABLE:
1139 default:
1140 /* Nothing to do */
1141 break;
1142 }
1143
1144 return usb_frequency;
1145 }
1146
1147 /**
1148 * @brief Return DFSDM clock frequency
1149 * @param DFSDMxSource This parameter can be one of the following values:
1150 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
1151 * @retval DFSDM clock frequency (in Hz)
1152 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1153 */
LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)1154 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
1155 {
1156 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1157
1158 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
1159 {
1160 case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK:
1161 dfsdm_frequency = RCC_GetSystemClockFreq();
1162 break;
1163
1164 case LL_RCC_DFSDM1_CLKSOURCE_PCLK2:
1165 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
1166 break;
1167
1168 default:
1169 /* Nothing to do */
1170 break;
1171 }
1172
1173 return dfsdm_frequency;
1174 }
1175
1176 #if defined(DFSDM2_BASE)
1177 /**
1178 * @brief Return DFSDM clock frequency
1179 * @param DFSDMxSource This parameter can be one of the following values:
1180 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE
1181 * @retval DFSDM clock frequency (in Hz)
1182 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1183 */
LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource)1184 uint32_t LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource)
1185 {
1186 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1187
1188
1189 switch (LL_RCC_GetDFSDM2ClockSource(DFSDMxSource))
1190 {
1191
1192 case LL_RCC_DFSDM2_CLKSOURCE_SYSCLK:
1193 dfsdm_frequency = RCC_GetSystemClockFreq();
1194 break;
1195
1196 case LL_RCC_DFSDM2_CLKSOURCE_PCLK4:
1197 dfsdm_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
1198 break;
1199
1200 default:
1201 /* Nothing to do */
1202 break;
1203 }
1204
1205 return dfsdm_frequency;
1206 }
1207 #endif /* DFSDM2_BASE */
1208
1209 #if defined(DSI)
1210 /**
1211 * @brief Return DSI clock frequency
1212 * @param DSIxSource This parameter can be one of the following values:
1213 * @arg @ref LL_RCC_DSI_CLKSOURCE
1214 * @retval DSI clock frequency (in Hz)
1215 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1216 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
1217 */
LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)1218 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
1219 {
1220 uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1221 LL_PLL_ClocksTypeDef PLL_Clocks;
1222
1223 switch (LL_RCC_GetDSIClockSource(DSIxSource))
1224 {
1225 case LL_RCC_DSI_CLKSOURCE_PLL2Q:
1226 if (LL_RCC_PLL2_IsReady() != 0U)
1227 {
1228 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1229 dsi_frequency = PLL_Clocks.PLL_Q_Frequency;
1230 }
1231 break;
1232
1233 case LL_RCC_DSI_CLKSOURCE_PHY:
1234 dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1235 break;
1236
1237 default:
1238 /* Nothing to do */
1239 break;
1240 }
1241
1242 return dsi_frequency;
1243 }
1244 #endif /* DSI */
1245
1246 /**
1247 * @brief Return SPDIF clock frequency
1248 * @param SPDIFxSource This parameter can be one of the following values:
1249 * @arg @ref LL_RCC_SPDIF_CLKSOURCE
1250 * @retval SPDIF clock frequency (in Hz)
1251 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1252 */
LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource)1253 uint32_t LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource)
1254 {
1255 uint32_t spdif_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1256 LL_PLL_ClocksTypeDef PLL_Clocks;
1257
1258 switch (LL_RCC_GetSPDIFClockSource(SPDIFxSource))
1259 {
1260 case LL_RCC_SPDIF_CLKSOURCE_PLL1Q:
1261 if (LL_RCC_PLL1_IsReady() != 0U)
1262 {
1263 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1264 spdif_frequency = PLL_Clocks.PLL_Q_Frequency;
1265 }
1266 break;
1267
1268 case LL_RCC_SPDIF_CLKSOURCE_PLL2R:
1269 if (LL_RCC_PLL2_IsReady() != 0U)
1270 {
1271 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1272 spdif_frequency = PLL_Clocks.PLL_R_Frequency;
1273 }
1274 break;
1275
1276 case LL_RCC_SPDIF_CLKSOURCE_PLL3R:
1277 if (LL_RCC_PLL3_IsReady() != 0U)
1278 {
1279 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1280 spdif_frequency = PLL_Clocks.PLL_R_Frequency;
1281 }
1282 break;
1283
1284 case LL_RCC_SPDIF_CLKSOURCE_HSI:
1285 if (LL_RCC_HSI_IsReady() != 0U)
1286 {
1287 spdif_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
1288 }
1289 break;
1290
1291 default:
1292 /* Nothing to do */
1293 break;
1294 }
1295
1296 return spdif_frequency;
1297 }
1298
1299 /**
1300 * @brief Return SPIx clock frequency
1301 * @param SPIxSource This parameter can be one of the following values:
1302 * @arg @ref LL_RCC_SPI123_CLKSOURCE
1303 * @arg @ref LL_RCC_SPI45_CLKSOURCE
1304 * @arg @ref LL_RCC_SPI6_CLKSOURCE
1305 * @retval SPI clock frequency (in Hz)
1306 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1307 */
LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)1308 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)
1309 {
1310 uint32_t spi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1311 LL_PLL_ClocksTypeDef PLL_Clocks;
1312
1313 /* Check parameter */
1314 assert_param(IS_LL_RCC_SPI_CLKSOURCE(SPIxSource));
1315
1316 switch (LL_RCC_GetSPIClockSource(SPIxSource))
1317 {
1318 case LL_RCC_SPI123_CLKSOURCE_PLL1Q:
1319 if (LL_RCC_PLL1_IsReady() != 0U)
1320 {
1321 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1322 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1323 }
1324 break;
1325
1326 case LL_RCC_SPI123_CLKSOURCE_PLL2P:
1327 if (LL_RCC_PLL2_IsReady() != 0U)
1328 {
1329 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1330 spi_frequency = PLL_Clocks.PLL_P_Frequency;
1331 }
1332 break;
1333
1334 case LL_RCC_SPI123_CLKSOURCE_PLL3P:
1335 if (LL_RCC_PLL3_IsReady() != 0U)
1336 {
1337 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1338 spi_frequency = PLL_Clocks.PLL_P_Frequency;
1339 }
1340 break;
1341
1342 case LL_RCC_SPI123_CLKSOURCE_I2S_CKIN:
1343 #if defined(LL_RCC_SPI6_CLKSOURCE_I2S_CKIN)
1344 case LL_RCC_SPI6_CLKSOURCE_I2S_CKIN:
1345 #endif /* LL_RCC_SPI6_CLKSOURCE_I2S_CKIN */
1346 spi_frequency = EXTERNAL_CLOCK_VALUE;
1347 break;
1348
1349 case LL_RCC_SPI123_CLKSOURCE_CLKP:
1350 spi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1351 break;
1352
1353 case LL_RCC_SPI45_CLKSOURCE_PCLK2:
1354 spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
1355 break;
1356
1357 case LL_RCC_SPI6_CLKSOURCE_PCLK4:
1358 spi_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
1359 break;
1360
1361 case LL_RCC_SPI45_CLKSOURCE_PLL2Q:
1362 case LL_RCC_SPI6_CLKSOURCE_PLL2Q:
1363 if (LL_RCC_PLL2_IsReady() != 0U)
1364 {
1365 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1366 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1367 }
1368 break;
1369
1370 case LL_RCC_SPI45_CLKSOURCE_PLL3Q:
1371 case LL_RCC_SPI6_CLKSOURCE_PLL3Q:
1372 if (LL_RCC_PLL3_IsReady() != 0U)
1373 {
1374 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1375 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1376 }
1377 break;
1378
1379 case LL_RCC_SPI45_CLKSOURCE_HSI:
1380 case LL_RCC_SPI6_CLKSOURCE_HSI:
1381 if (LL_RCC_HSI_IsReady() != 0U)
1382 {
1383 spi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
1384 }
1385 break;
1386
1387 case LL_RCC_SPI45_CLKSOURCE_CSI:
1388 case LL_RCC_SPI6_CLKSOURCE_CSI:
1389 if (LL_RCC_CSI_IsReady() != 0U)
1390 {
1391 spi_frequency = CSI_VALUE;
1392 }
1393 break;
1394
1395 case LL_RCC_SPI45_CLKSOURCE_HSE:
1396 case LL_RCC_SPI6_CLKSOURCE_HSE:
1397 if (LL_RCC_HSE_IsReady() != 0U)
1398 {
1399 spi_frequency = HSE_VALUE;
1400 }
1401 break;
1402
1403 default:
1404 /* Kernel clock disabled */
1405 break;
1406 }
1407
1408 return spi_frequency;
1409 }
1410
1411 /**
1412 * @brief Return SWP clock frequency
1413 * @param SWPxSource This parameter can be one of the following values:
1414 * @arg @ref LL_RCC_SWP_CLKSOURCE
1415 * @retval SWP clock frequency (in Hz)
1416 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1417 */
LL_RCC_GetSWPClockFreq(uint32_t SWPxSource)1418 uint32_t LL_RCC_GetSWPClockFreq(uint32_t SWPxSource)
1419 {
1420 uint32_t swp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1421
1422 switch (LL_RCC_GetSWPClockSource(SWPxSource))
1423 {
1424 case LL_RCC_SWP_CLKSOURCE_PCLK1:
1425 swp_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
1426 break;
1427
1428 case LL_RCC_SWP_CLKSOURCE_HSI:
1429 if (LL_RCC_HSI_IsReady() != 0U)
1430 {
1431 swp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
1432 }
1433 break;
1434
1435 default:
1436 /* Nothing to do */
1437 break;
1438 }
1439
1440 return swp_frequency;
1441 }
1442
1443 /**
1444 * @brief Return FDCAN clock frequency
1445 * @param FDCANxSource This parameter can be one of the following values:
1446 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
1447 * @retval FDCAN clock frequency (in Hz)
1448 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1449 */
LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)1450 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
1451 {
1452 uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1453 LL_PLL_ClocksTypeDef PLL_Clocks;
1454
1455 switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
1456 {
1457 case LL_RCC_FDCAN_CLKSOURCE_HSE:
1458 if (LL_RCC_HSE_IsReady() != 0U)
1459 {
1460 fdcan_frequency = HSE_VALUE;
1461 }
1462 break;
1463
1464 case LL_RCC_FDCAN_CLKSOURCE_PLL1Q:
1465 if (LL_RCC_PLL1_IsReady() != 0U)
1466 {
1467 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1468 fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
1469 }
1470 break;
1471
1472 case LL_RCC_FDCAN_CLKSOURCE_PLL2Q:
1473 if (LL_RCC_PLL2_IsReady() != 0U)
1474 {
1475 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1476 fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
1477 }
1478 break;
1479
1480 default:
1481 /* Kernel clock disabled */
1482 break;
1483 }
1484
1485 return fdcan_frequency;
1486 }
1487
1488 /**
1489 * @brief Return FMC clock frequency
1490 * @param FMCxSource This parameter can be one of the following values:
1491 * @arg @ref LL_RCC_FMC_CLKSOURCE
1492 * @retval FMC clock frequency (in Hz)
1493 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1494 */
LL_RCC_GetFMCClockFreq(uint32_t FMCxSource)1495 uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource)
1496 {
1497 uint32_t fmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1498 LL_PLL_ClocksTypeDef PLL_Clocks;
1499
1500 switch (LL_RCC_GetFMCClockSource(FMCxSource))
1501 {
1502 case LL_RCC_FMC_CLKSOURCE_HCLK:
1503 fmc_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()));
1504 break;
1505
1506 case LL_RCC_FMC_CLKSOURCE_PLL1Q:
1507 if (LL_RCC_PLL1_IsReady() != 0U)
1508 {
1509 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1510 fmc_frequency = PLL_Clocks.PLL_Q_Frequency;
1511 }
1512 break;
1513
1514 case LL_RCC_FMC_CLKSOURCE_PLL2R:
1515 if (LL_RCC_PLL2_IsReady() != 0U)
1516 {
1517 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1518 fmc_frequency = PLL_Clocks.PLL_R_Frequency;
1519 }
1520 break;
1521
1522 case LL_RCC_FMC_CLKSOURCE_CLKP:
1523 fmc_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1524 break;
1525
1526 default:
1527 /* Nothing to do */
1528 break;
1529 }
1530
1531 return fmc_frequency;
1532 }
1533
1534 #if defined(QUADSPI)
1535 /**
1536 * @brief Return QSPI clock frequency
1537 * @param QSPIxSource This parameter can be one of the following values:
1538 * @arg @ref LL_RCC_QSPI_CLKSOURCE
1539 * @retval QSPI clock frequency (in Hz)
1540 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1541 */
LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource)1542 uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource)
1543 {
1544 uint32_t qspi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1545 LL_PLL_ClocksTypeDef PLL_Clocks;
1546
1547 switch (LL_RCC_GetQSPIClockSource(QSPIxSource))
1548 {
1549 case LL_RCC_QSPI_CLKSOURCE_HCLK:
1550 qspi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()));
1551 break;
1552
1553 case LL_RCC_QSPI_CLKSOURCE_PLL1Q:
1554 if (LL_RCC_PLL1_IsReady() != 0U)
1555 {
1556 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1557 qspi_frequency = PLL_Clocks.PLL_Q_Frequency;
1558 }
1559 break;
1560
1561 case LL_RCC_QSPI_CLKSOURCE_PLL2R:
1562 if (LL_RCC_PLL2_IsReady() != 0U)
1563 {
1564 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1565 qspi_frequency = PLL_Clocks.PLL_R_Frequency;
1566 }
1567 break;
1568
1569 case LL_RCC_QSPI_CLKSOURCE_CLKP:
1570 qspi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1571 break;
1572
1573 default:
1574 /* Nothing to do */
1575 break;
1576 }
1577
1578 return qspi_frequency;
1579 }
1580 #endif /* QUADSPI */
1581
1582 #if defined(OCTOSPI1) || defined(OCTOSPI2)
1583 /**
1584 * @brief Return OSPI clock frequency
1585 * @param OSPIxSource This parameter can be one of the following values:
1586 * @arg @ref LL_RCC_OSPI_CLKSOURCE
1587 * @retval OSPI clock frequency (in Hz)
1588 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1589 */
1590
LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource)1591 uint32_t LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource)
1592 {
1593 uint32_t ospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1594 LL_PLL_ClocksTypeDef PLL_Clocks;
1595
1596 switch (LL_RCC_GetOSPIClockSource(OSPIxSource))
1597 {
1598 case LL_RCC_OSPI_CLKSOURCE_HCLK:
1599 ospi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()));
1600 break;
1601
1602 case LL_RCC_OSPI_CLKSOURCE_PLL1Q:
1603 if (LL_RCC_PLL1_IsReady() != 0U)
1604 {
1605 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1606 ospi_frequency = PLL_Clocks.PLL_Q_Frequency;
1607 }
1608 break;
1609
1610 case LL_RCC_OSPI_CLKSOURCE_PLL2R:
1611 if (LL_RCC_PLL2_IsReady() != 0U)
1612 {
1613 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1614 ospi_frequency = PLL_Clocks.PLL_R_Frequency;
1615 }
1616 break;
1617
1618 case LL_RCC_OSPI_CLKSOURCE_CLKP:
1619 ospi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1620 break;
1621
1622 default:
1623 /* Nothing to do */
1624 break;
1625 }
1626
1627 return ospi_frequency;
1628 }
1629 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
1630
1631 /**
1632 * @brief Return CLKP clock frequency
1633 * @param CLKPxSource This parameter can be one of the following values:
1634 * @arg @ref LL_RCC_CLKP_CLKSOURCE
1635 * @retval CLKP clock frequency (in Hz)
1636 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1637 */
LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)1638 uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)
1639 {
1640 uint32_t clkp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1641
1642 switch (LL_RCC_GetCLKPClockSource(CLKPxSource))
1643 {
1644 case LL_RCC_CLKP_CLKSOURCE_HSI:
1645 if (LL_RCC_HSI_IsReady() != 0U)
1646 {
1647 clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
1648 }
1649 break;
1650
1651 case LL_RCC_CLKP_CLKSOURCE_CSI:
1652 if (LL_RCC_CSI_IsReady() != 0U)
1653 {
1654 clkp_frequency = CSI_VALUE;
1655 }
1656 break;
1657
1658 case LL_RCC_CLKP_CLKSOURCE_HSE:
1659 if (LL_RCC_HSE_IsReady() != 0U)
1660 {
1661 clkp_frequency = HSE_VALUE;
1662 }
1663 break;
1664
1665 default:
1666 /* CLKP clock disabled */
1667 break;
1668 }
1669
1670 return clkp_frequency;
1671 }
1672
1673 /**
1674 * @}
1675 */
1676
1677 /**
1678 * @}
1679 */
1680
1681 /** @addtogroup RCC_LL_Private_Functions
1682 * @{
1683 */
1684
1685 /**
1686 * @brief Return SYSTEM clock frequency
1687 * @retval SYSTEM clock frequency (in Hz)
1688 */
RCC_GetSystemClockFreq(void)1689 static uint32_t RCC_GetSystemClockFreq(void)
1690 {
1691 uint32_t frequency = 0U;
1692 LL_PLL_ClocksTypeDef PLL_Clocks;
1693
1694 /* Get SYSCLK source -------------------------------------------------------*/
1695 switch (LL_RCC_GetSysClkSource())
1696 {
1697 /* No check on Ready: Won't be selected by hardware if not */
1698 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
1699 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
1700 break;
1701
1702 case LL_RCC_SYS_CLKSOURCE_STATUS_CSI:
1703 frequency = CSI_VALUE;
1704 break;
1705
1706 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:
1707 frequency = HSE_VALUE;
1708 break;
1709
1710 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1:
1711 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1712 frequency = PLL_Clocks.PLL_P_Frequency;
1713 break;
1714
1715 default:
1716 /* Nothing to do */
1717 break;
1718 }
1719
1720 return frequency;
1721 }
1722
1723 /**
1724 * @brief Return HCLK clock frequency
1725 * @param SYSCLK_Frequency SYSCLK clock frequency
1726 * @retval HCLK clock frequency (in Hz)
1727 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)1728 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1729 {
1730 /* HCLK clock frequency */
1731 return LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1732 }
1733
1734 /**
1735 * @brief Return PCLK1 clock frequency
1736 * @param HCLK_Frequency HCLK clock frequency
1737 * @retval PCLK1 clock frequency (in Hz)
1738 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)1739 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1740 {
1741 /* PCLK1 clock frequency */
1742 return LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1743 }
1744
1745 /**
1746 * @brief Return PCLK2 clock frequency
1747 * @param HCLK_Frequency HCLK clock frequency
1748 * @retval PCLK2 clock frequency (in Hz)
1749 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)1750 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1751 {
1752 /* PCLK2 clock frequency */
1753 return LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1754 }
1755
1756 /**
1757 * @brief Return PCLK3 clock frequency
1758 * @param HCLK_Frequency HCLK clock frequency
1759 * @retval PCLK3 clock frequency (in Hz)
1760 */
RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)1761 static uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)
1762 {
1763 /* PCLK3 clock frequency */
1764 return LL_RCC_CALC_PCLK3_FREQ(HCLK_Frequency, LL_RCC_GetAPB3Prescaler());
1765 }
1766
1767 /**
1768 * @brief Return PCLK4 clock frequency
1769 * @param HCLK_Frequency HCLK clock frequency
1770 * @retval PCLK4 clock frequency (in Hz)
1771 */
RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency)1772 static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency)
1773 {
1774 /* PCLK4 clock frequency */
1775 return LL_RCC_CALC_PCLK4_FREQ(HCLK_Frequency, LL_RCC_GetAPB4Prescaler());
1776 }
1777
1778 /**
1779 * @}
1780 */
1781
1782 /**
1783 * @}
1784 */
1785
1786 #endif /* defined(RCC) */
1787
1788 /**
1789 * @}
1790 */
1791
1792 #endif /* USE_FULL_LL_DRIVER */
1793
1794
