1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_mdma.c
4 * @author MCD Application Team
5 * @brief MDMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32h7xx_ll_mdma.h"
22 #include "stm32h7xx_ll_bus.h"
23 #ifdef USE_FULL_ASSERT
24 #include "stm32_assert.h"
25 #else
26 #define assert_param(expr) ((void)0U)
27 #endif
28
29 /** @addtogroup STM32H7xx_LL_Driver
30 * @{
31 */
32
33 #if defined (MDMA)
34
35 /** @defgroup MDMA_LL MDMA
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /* Private constants ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43 /** @addtogroup MDMA_LL_Private_Macros
44 * @{
45 */
46
47 #define IS_LL_MDMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) (((INSTANCE) == MDMA) && \
48 (((CHANNEL) == LL_MDMA_CHANNEL_0) || \
49 ((CHANNEL) == LL_MDMA_CHANNEL_1) || \
50 ((CHANNEL) == LL_MDMA_CHANNEL_2) || \
51 ((CHANNEL) == LL_MDMA_CHANNEL_3) || \
52 ((CHANNEL) == LL_MDMA_CHANNEL_4) || \
53 ((CHANNEL) == LL_MDMA_CHANNEL_5) || \
54 ((CHANNEL) == LL_MDMA_CHANNEL_6) || \
55 ((CHANNEL) == LL_MDMA_CHANNEL_7) || \
56 ((CHANNEL) == LL_MDMA_CHANNEL_8) || \
57 ((CHANNEL) == LL_MDMA_CHANNEL_9) || \
58 ((CHANNEL) == LL_MDMA_CHANNEL_10)|| \
59 ((CHANNEL) == LL_MDMA_CHANNEL_11)|| \
60 ((CHANNEL) == LL_MDMA_CHANNEL_12)|| \
61 ((CHANNEL) == LL_MDMA_CHANNEL_13)|| \
62 ((CHANNEL) == LL_MDMA_CHANNEL_14)|| \
63 ((CHANNEL) == LL_MDMA_CHANNEL_15)|| \
64 ((CHANNEL) == LL_MDMA_CHANNEL_ALL)))
65
66 #define IS_LL_MDMA_BLK_DATALENGTH(__VALUE__) ((__VALUE__) <= 0x00010000U)
67
68 #define IS_LL_MDMA_BLK_REPEATCOUNT(__VALUE__) ((__VALUE__) <= 0x00000FFFU)
69
70 #define IS_LL_MDMA_WORDENDIANESS(__VALUE__) (((__VALUE__) == LL_MDMA_WORD_ENDIANNESS_PRESERVE) || \
71 ((__VALUE__) == LL_MDMA_WORD_ENDIANNESS_EXCHANGE))
72
73 #define IS_LL_MDMA_HALFWORDENDIANESS(__VALUE__) (((__VALUE__) == LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE) || \
74 ((__VALUE__) == LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE))
75
76 #define IS_LL_MDMA_BYTEENDIANESS(__VALUE__) (((__VALUE__) == LL_MDMA_BYTE_ENDIANNESS_PRESERVE) || \
77 ((__VALUE__) == LL_MDMA_BYTE_ENDIANNESS_EXCHANGE))
78
79 #define IS_LL_MDMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_MDMA_PRIORITY_LOW) || \
80 ((__VALUE__) == LL_MDMA_PRIORITY_MEDIUM) || \
81 ((__VALUE__) == LL_MDMA_PRIORITY_HIGH) || \
82 ((__VALUE__) == LL_MDMA_PRIORITY_VERYHIGH))
83
84 #define IS_LL_MDMA_BUFFWRITEMODE(__VALUE__) (((__VALUE__) == LL_MDMA_BUFF_WRITE_DISABLE) || \
85 ((__VALUE__) == LL_MDMA_BUFF_WRITE_ENABLE))
86
87 #define IS_LL_MDMA_REQUESTMODE(__VALUE__) (((__VALUE__) == LL_MDMA_REQUEST_MODE_HW) || \
88 ((__VALUE__) == LL_MDMA_REQUEST_MODE_SW))
89
90 #define IS_LL_MDMA_TRIGGERMODE(__VALUE__) (((__VALUE__) == LL_MDMA_BUFFER_TRANSFER) || \
91 ((__VALUE__) == LL_MDMA_BLOCK_TRANSFER) || \
92 ((__VALUE__) == LL_MDMA_REPEAT_BLOCK_TRANSFER) || \
93 ((__VALUE__) == LL_MDMA_FULL_TRANSFER))
94
95 #define IS_LL_MDMA_PADDINGALIGNEMENT(__VALUE__) (((__VALUE__) == LL_MDMA_DATAALIGN_RIGHT) || \
96 ((__VALUE__) == LL_MDMA_DATAALIGN_RIGHT_SIGNED) || \
97 ((__VALUE__) == LL_MDMA_DATAALIGN_LEFT))
98
99 #define IS_LL_MDMA_PACKMODE(__VALUE__) (((__VALUE__) == LL_MDMA_PACK_DISABLE) || \
100 ((__VALUE__) == LL_MDMA_PACK_ENABLE))
101
102 #define IS_LL_MDMA_BUFFER_XFERLENGTH(__VALUE__) ((__VALUE__) <= 0x0000007FU)
103
104 #define IS_LL_MDMA_DESTBURST(__VALUE__) (((__VALUE__) == LL_MDMA_DEST_BURST_SINGLE) || \
105 ((__VALUE__) == LL_MDMA_DEST_BURST_2BEATS) || \
106 ((__VALUE__) == LL_MDMA_DEST_BURST_4BEATS) || \
107 ((__VALUE__) == LL_MDMA_DEST_BURST_8BEATS) || \
108 ((__VALUE__) == LL_MDMA_DEST_BURST_16BEATS)|| \
109 ((__VALUE__) == LL_MDMA_DEST_BURST_32BEATS)|| \
110 ((__VALUE__) == LL_MDMA_DEST_BURST_64BEATS)|| \
111 ((__VALUE__) == LL_MDMA_DEST_BURST_128BEATS))
112
113 #define IS_LL_MDMA_SRCTBURST(__VALUE__) (((__VALUE__) == LL_MDMA_SRC_BURST_SINGLE) || \
114 ((__VALUE__) == LL_MDMA_SRC_BURST_2BEATS) || \
115 ((__VALUE__) == LL_MDMA_SRC_BURST_4BEATS) || \
116 ((__VALUE__) == LL_MDMA_SRC_BURST_8BEATS) || \
117 ((__VALUE__) == LL_MDMA_SRC_BURST_16BEATS)|| \
118 ((__VALUE__) == LL_MDMA_SRC_BURST_32BEATS)|| \
119 ((__VALUE__) == LL_MDMA_SRC_BURST_64BEATS)|| \
120 ((__VALUE__) == LL_MDMA_SRC_BURST_128BEATS))
121
122 #define IS_LL_MDMA_DESTINCSIZE(__VALUE__) (((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_BYTE) || \
123 ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_HALFWORD) || \
124 ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_WORD) || \
125 ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD))
126
127 #define IS_LL_MDMA_SRCINCSIZE(__VALUE__) (((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_BYTE) || \
128 ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_HALFWORD) || \
129 ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_WORD) || \
130 ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD))
131
132 #define IS_LL_MDMA_DESTDATASIZE(__VALUE__) (((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_BYTE) || \
133 ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_HALFWORD) || \
134 ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_WORD) || \
135 ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD))
136
137 #define IS_LL_MDMA_SRCDATASIZE(__VALUE__) (((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_BYTE) || \
138 ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_HALFWORD) || \
139 ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_WORD) || \
140 ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD))
141
142 #define IS_LL_MDMA_DESTINCMODE(__VALUE__) (((__VALUE__) == LL_MDMA_DEST_FIXED) || \
143 ((__VALUE__) == LL_MDMA_DEST_INCREMENT) || \
144 ((__VALUE__) == LL_MDMA_DEST_DECREMENT))
145
146 #define IS_LL_MDMA_SRCINCMODE(__VALUE__) (((__VALUE__) == LL_MDMA_SRC_FIXED) || \
147 ((__VALUE__) == LL_MDMA_SRC_INCREMENT) || \
148 ((__VALUE__) == LL_MDMA_SRC_DECREMENT))
149
150 #define IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE(__VALUE__) (((__VALUE__) == LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT) || \
151 ((__VALUE__) == LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT))
152
153
154 #define IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE(__VALUE__) (((__VALUE__) == LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT) || \
155 ((__VALUE__) == LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT))
156
157 #define IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
158
159 #define IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
160
161 #define IS_LL_MDMA_DEST_BUS(__VALUE__) (((__VALUE__) == LL_MDMA_DEST_BUS_SYSTEM_AXI) || \
162 ((__VALUE__) == LL_MDMA_DEST_BUS_AHB_TCM))
163
164 #define IS_LL_MDMA_SRC_BUS(__VALUE__) (((__VALUE__) == LL_MDMA_SRC_BUS_SYSTEM_AXI) || \
165 ((__VALUE__) == LL_MDMA_SRC_BUS_AHB_TCM))
166 #if defined (QUADSPI) && defined (JPEG) && defined (DSI) /* STM32H747/57 devices */
167 #define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \
168 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \
169 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \
170 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC) || \
171 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC) || \
172 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC) || \
173 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC) || \
174 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC) || \
175 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC) || \
176 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC) || \
177 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC) || \
178 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC) || \
179 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC) || \
180 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC) || \
181 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC) || \
182 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC) || \
183 ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT) || \
184 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_TH) || \
185 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_NF) || \
186 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_TH) || \
187 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_NE) || \
188 ((__VALUE__) == LL_MDMA_REQ_JPEG_END_CONVERSION) || \
189 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_FIFO_TH) || \
190 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_TC) || \
191 ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC) || \
192 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC) || \
193 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW) || \
194 ((__VALUE__) == LL_MDMA_REQ_DSI_TEARING_EFFECT) || \
195 ((__VALUE__) == LL_MDMA_REQ_DSI_END_REFRESH) || \
196 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA) || \
197 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
198 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END))
199 #elif defined (QUADSPI) && defined (JPEG) /* STM32H743/53/45/55 devices */
200 #define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \
201 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \
202 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \
203 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC) || \
204 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC) || \
205 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC) || \
206 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC) || \
207 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC) || \
208 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC) || \
209 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC) || \
210 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC) || \
211 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC) || \
212 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC) || \
213 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC) || \
214 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC) || \
215 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC) || \
216 ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT) || \
217 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_TH) || \
218 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_NF) || \
219 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_TH) || \
220 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_NE) || \
221 ((__VALUE__) == LL_MDMA_REQ_JPEG_END_CONVERSION) || \
222 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_FIFO_TH) || \
223 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_TC) || \
224 ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC) || \
225 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC) || \
226 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW) || \
227 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA) || \
228 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
229 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END))
230 #elif defined (QUADSPI) /* STM32H742 devices */
231 #define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \
232 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \
233 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \
234 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC) || \
235 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC) || \
236 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC) || \
237 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC) || \
238 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC) || \
239 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC) || \
240 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC) || \
241 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC) || \
242 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC) || \
243 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC) || \
244 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC) || \
245 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC) || \
246 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC) || \
247 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_FIFO_TH) || \
248 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_TC) || \
249 ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC) || \
250 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC) || \
251 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW) || \
252 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA) || \
253 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
254 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END))
255
256 #elif defined (OCTOSPI1) && defined (JPEG) /* STM32H7A3/B3 devices */
257 #define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \
258 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \
259 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \
260 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC) || \
261 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC) || \
262 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC) || \
263 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC) || \
264 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC) || \
265 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC) || \
266 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC) || \
267 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC) || \
268 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC) || \
269 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC) || \
270 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC) || \
271 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC) || \
272 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC) || \
273 ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT) || \
274 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_TH) || \
275 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_NF) || \
276 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_TH) || \
277 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_NE) || \
278 ((__VALUE__) == LL_MDMA_REQ_JPEG_END_CONVERSION) || \
279 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_FIFO_TH) || \
280 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_TC) || \
281 ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC) || \
282 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC) || \
283 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW) || \
284 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA) || \
285 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
286 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END) || \
287 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_FIFO_TH) || \
288 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_TC))
289 #else /* STM32H723/25/33/35 devices */
290 #define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \
291 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \
292 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \
293 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC) || \
294 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC) || \
295 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC) || \
296 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC) || \
297 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC) || \
298 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC) || \
299 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC) || \
300 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC) || \
301 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC) || \
302 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC) || \
303 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC) || \
304 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC) || \
305 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC) || \
306 ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT) || \
307 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_FIFO_TH) || \
308 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_TC) || \
309 ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC) || \
310 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC) || \
311 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW) || \
312 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA) || \
313 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
314 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END) || \
315 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_FIFO_TH) || \
316 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_TC))
317 #endif /* QUADSPI && JPEG && DSI */
318 /**
319 * @}
320 */
321
322 /* Private function prototypes -----------------------------------------------*/
323
324 /* Exported functions --------------------------------------------------------*/
325 /** @addtogroup MDMA_LL_Exported_Functions
326 * @{
327 */
328
329 /** @addtogroup MDMA_LL_EF_Init
330 * @{
331 */
332
333 /**
334 * @brief De-initialize the MDMA registers to their default reset values.
335 * @param MDMAx MDMAx Instance
336 * @param Channel This parameter can be one of the following values:
337 * @arg @ref LL_MDMA_CHANNEL_0
338 * @arg @ref LL_MDMA_CHANNEL_1
339 * @arg @ref LL_MDMA_CHANNEL_2
340 * @arg @ref LL_MDMA_CHANNEL_3
341 * @arg @ref LL_MDMA_CHANNEL_4
342 * @arg @ref LL_MDMA_CHANNEL_5
343 * @arg @ref LL_MDMA_CHANNEL_6
344 * @arg @ref LL_MDMA_CHANNEL_7
345 * @arg @ref LL_MDMA_CHANNEL_8
346 * @arg @ref LL_MDMA_CHANNEL_9
347 * @arg @ref LL_MDMA_CHANNEL_10
348 * @arg @ref LL_MDMA_CHANNEL_11
349 * @arg @ref LL_MDMA_CHANNEL_12
350 * @arg @ref LL_MDMA_CHANNEL_13
351 * @arg @ref LL_MDMA_CHANNEL_14
352 * @arg @ref LL_MDMA_CHANNEL_15
353 * @arg @ref LL_MDMA_CHANNEL_ALL
354 * @retval An ErrorStatus enumeration value:
355 * - SUCCESS: MDMA registers are de-initialized
356 * - ERROR: Not applicable
357 */
LL_MDMA_DeInit(MDMA_TypeDef * MDMAx,uint32_t Channel)358 uint32_t LL_MDMA_DeInit(MDMA_TypeDef *MDMAx, uint32_t Channel)
359 {
360 MDMA_Channel_TypeDef *tmp;
361 ErrorStatus status = SUCCESS;
362
363 /* Check the MDMA Instance MDMAx and Channel parameters*/
364 assert_param(IS_LL_MDMA_ALL_CHANNEL_INSTANCE(MDMAx, Channel));
365
366 if (Channel == LL_MDMA_CHANNEL_ALL)
367 {
368 LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_MDMA);
369 LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_MDMA);
370 }
371 else
372 {
373 /* Disable the selected Channel */
374 LL_MDMA_DisableChannel(MDMAx,Channel);
375
376 /* Get the MDMA Channel Instance */
377 tmp = (MDMA_Channel_TypeDef *)(LL_MDMA_GET_CHANNEL_INSTANCE(MDMAx, Channel));
378
379 /* Reset MDMAx_Channely control register */
380 LL_MDMA_WriteReg(tmp, CCR, 0U);
381
382 /* Reset MDMAx_Channely Configuration register */
383 LL_MDMA_WriteReg(tmp, CTCR, 0U);
384
385 /* Reset MDMAx_Channely block number of data register */
386 LL_MDMA_WriteReg(tmp, CBNDTR, 0U);
387
388 /* Reset MDMAx_Channely source address register */
389 LL_MDMA_WriteReg(tmp, CSAR, 0U);
390
391 /* Reset MDMAx_Channely destination address register */
392 LL_MDMA_WriteReg(tmp, CDAR, 0U);
393
394 /* Reset MDMAx_Channely Block Repeat address Update register */
395 LL_MDMA_WriteReg(tmp, CBRUR, 0U);
396
397 /* Reset MDMAx_Channely Link Address register */
398 LL_MDMA_WriteReg(tmp, CLAR, 0U);
399
400 /* Reset MDMAx_Channely Trigger and Bus selection register */
401 LL_MDMA_WriteReg(tmp, CTBR, 0U);
402
403 /* Reset MDMAx_Channely Mask address register */
404 LL_MDMA_WriteReg(tmp, CMAR, 0U);
405
406 /* Reset MDMAx_Channely Mask Data register */
407 LL_MDMA_WriteReg(tmp, CMDR, 0U);
408
409 /* Reset the Channel pending flags */
410 LL_MDMA_WriteReg(tmp, CIFCR, 0x0000001FU);
411 }
412
413 return (uint32_t)status;
414 }
415
416 /**
417 * @brief Initialize the MDMA registers according to the specified parameters in MDMA_InitStruct.
418 * @note To convert MDMAx_Channely Instance to MDMAx Instance and Channely, use helper macros :
419 * @arg @ref LL_MDMA_GET_INSTANCE
420 * @arg @ref LL_MDMA_GET_CHANNEL
421 * @param MDMAx MDMAx Instance
422 * @param Channel This parameter can be one of the following values:
423 * @arg @ref LL_MDMA_CHANNEL_0
424 * @arg @ref LL_MDMA_CHANNEL_1
425 * @arg @ref LL_MDMA_CHANNEL_2
426 * @arg @ref LL_MDMA_CHANNEL_3
427 * @arg @ref LL_MDMA_CHANNEL_4
428 * @arg @ref LL_MDMA_CHANNEL_5
429 * @arg @ref LL_MDMA_CHANNEL_6
430 * @arg @ref LL_MDMA_CHANNEL_7
431 * @arg @ref LL_MDMA_CHANNEL_8
432 * @arg @ref LL_MDMA_CHANNEL_9
433 * @arg @ref LL_MDMA_CHANNEL_10
434 * @arg @ref LL_MDMA_CHANNEL_11
435 * @arg @ref LL_MDMA_CHANNEL_12
436 * @arg @ref LL_MDMA_CHANNEL_13
437 * @arg @ref LL_MDMA_CHANNEL_14
438 * @arg @ref LL_MDMA_CHANNEL_15
439 * @param MDMA_InitStruct pointer to a @ref LL_MDMA_InitTypeDef structure.
440 * @retval An ErrorStatus enumeration value:
441 * - SUCCESS: MDMA registers are initialized
442 * - ERROR: Not applicable
443 */
LL_MDMA_Init(MDMA_TypeDef * MDMAx,uint32_t Channel,LL_MDMA_InitTypeDef * MDMA_InitStruct)444 uint32_t LL_MDMA_Init(MDMA_TypeDef *MDMAx, uint32_t Channel, LL_MDMA_InitTypeDef *MDMA_InitStruct)
445 {
446 /* Check the MDMA Instance MDMAx and Channel parameters*/
447 assert_param(IS_LL_MDMA_ALL_CHANNEL_INSTANCE(MDMAx, Channel));
448
449 /* Check the MDMA parameters from MDMA_InitStruct */
450 assert_param(IS_LL_MDMA_BLK_DATALENGTH(MDMA_InitStruct->BlockDataLength));
451 assert_param(IS_LL_MDMA_BLK_REPEATCOUNT(MDMA_InitStruct->BlockRepeatCount));
452 assert_param(IS_LL_MDMA_WORDENDIANESS(MDMA_InitStruct->WordEndianess));
453 assert_param(IS_LL_MDMA_HALFWORDENDIANESS(MDMA_InitStruct->HalfWordEndianess));
454 assert_param(IS_LL_MDMA_BYTEENDIANESS(MDMA_InitStruct->ByteEndianess));
455 assert_param(IS_LL_MDMA_PRIORITY(MDMA_InitStruct->Priority));
456 assert_param(IS_LL_MDMA_BUFFWRITEMODE(MDMA_InitStruct->BufferableWriteMode));
457 assert_param(IS_LL_MDMA_REQUESTMODE(MDMA_InitStruct->RequestMode));
458 assert_param(IS_LL_MDMA_TRIGGERMODE(MDMA_InitStruct->TriggerMode));
459 assert_param(IS_LL_MDMA_PADDINGALIGNEMENT(MDMA_InitStruct->PaddingAlignment));
460 assert_param(IS_LL_MDMA_PACKMODE(MDMA_InitStruct->PackMode));
461 assert_param(IS_LL_MDMA_BUFFER_XFERLENGTH(MDMA_InitStruct->BufferTransferLength));
462 assert_param(IS_LL_MDMA_DESTBURST(MDMA_InitStruct->DestBurst));
463 assert_param(IS_LL_MDMA_SRCTBURST(MDMA_InitStruct->SrctBurst));
464 assert_param(IS_LL_MDMA_DESTINCSIZE(MDMA_InitStruct->DestIncSize));
465 assert_param(IS_LL_MDMA_SRCINCSIZE(MDMA_InitStruct->SrcIncSize));
466 assert_param(IS_LL_MDMA_DESTDATASIZE(MDMA_InitStruct->DestDataSize));
467 assert_param(IS_LL_MDMA_SRCDATASIZE(MDMA_InitStruct->SrcDataSize));
468 assert_param(IS_LL_MDMA_DESTINCMODE(MDMA_InitStruct->DestIncMode));
469 assert_param(IS_LL_MDMA_SRCINCMODE(MDMA_InitStruct->SrcIncMode));
470 assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatDestAddrUpdateMode));
471 assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode));
472 assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatDestAddrUpdateVal));
473 assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal));
474 assert_param(IS_LL_MDMA_DEST_BUS(MDMA_InitStruct->DestBus));
475 assert_param(IS_LL_MDMA_SRC_BUS(MDMA_InitStruct->SrcBus));
476 assert_param(IS_LL_MDMA_HWTRIGGER(MDMA_InitStruct->HWTrigger));
477
478
479 /*-------------------------- MDMAx CCR Configuration --------------------------
480 * Configure the Transfer endianness na priority with parameter :
481 * - WordEndianess: MDMA_CCR_WEX[14] bit
482 * - HalfWordEndianess: MDMA_CCR_HEX[13] bit
483 * - WordEndianess: MDMA_CCR_BEX[12] bit
484 * - Priority: MDMA_CCR_BEX[7:6] bits
485 */
486 LL_MDMA_ConfigXferEndianness(MDMAx, Channel, MDMA_InitStruct->WordEndianess | \
487 MDMA_InitStruct->HalfWordEndianess | \
488 MDMA_InitStruct->ByteEndianess);
489
490 LL_MDMA_SetChannelPriorityLevel(MDMAx, Channel, MDMA_InitStruct->Priority);
491
492 /*-------------------------- MDMAx CTCR Configuration --------------------------
493 * Configure the Transfer parameter :
494 * - BufferableWriteMode: MDMA_CTCR_BWM[31] bit
495 * - RequestMode: MDMA_CTCR_SWRM[30] bit
496 * - TriggerMode: MDMA_CTCR_TRGM[29:28] bits
497 * - PaddingAlignment: MDMA_CTCR_PAM[27:26] bits
498 * - PackMode: MDMA_CTCR_PKE[25] bit
499 * - BufferTransferLength: MDMA_CTCR_TLEN[24:18] bits
500 * - DestBurst: MDMA_CTCR_DBURST[17:15] bits
501 * - SrctBurst: MDMA_CTCR_SBURST[14:12] bits
502 * - DestIncSize: MDMA_CTCR_DINCOS[11:10] bits
503 * - SrcIncSize: MDMA_CTCR_SINCOS[9:8] bits
504 * - DestDataSize: MDMA_CTCR_DSIZE[7:6] bits
505 * - SrcDataSize: MDMA_CTCR_SSIZE[5:4] bits
506 * - DestIncMode: MDMA_CTCR_DINC[3:2] bits
507 * - SrcIncMode: MDMA_CTCR_SINC[1:0] bits
508 */
509 LL_MDMA_ConfigTransfer(MDMAx, Channel, MDMA_InitStruct->BufferableWriteMode | \
510 MDMA_InitStruct->RequestMode | \
511 MDMA_InitStruct->TriggerMode | \
512 MDMA_InitStruct->PaddingAlignment | \
513 MDMA_InitStruct->PackMode | \
514 MDMA_InitStruct->DestBurst | \
515 MDMA_InitStruct->SrctBurst | \
516 MDMA_InitStruct->DestIncSize | \
517 MDMA_InitStruct->SrcIncSize | \
518 MDMA_InitStruct->DestDataSize | \
519 MDMA_InitStruct->SrcDataSize | \
520 MDMA_InitStruct->DestIncMode | \
521 MDMA_InitStruct->SrcIncMode, MDMA_InitStruct->BufferTransferLength);
522
523 /*-------------------------- MDMAx CBNDTR Configuration --------------------------
524 * Configure the Transfer Block counters and update mode with parameter :
525 * - BlockRepeatCount: MDMA_CBNDTR_BRC[31:20] bits
526 * - BlockDataLength: MDMA_CBNDTR_BNDT[16:0] bits
527 * - BlockRepeatDestAddrUpdateMode: MDMA_CBNDTR_BRDUM[19] bit
528 * - BlockRepeatDestAddrUpdateMode: MDMA_CBNDTR_BRSUM[18] bit
529 */
530 LL_MDMA_ConfigBlkCounters(MDMAx, Channel, MDMA_InitStruct->BlockRepeatCount, MDMA_InitStruct->BlockDataLength);
531
532 LL_MDMA_ConfigBlkRepeatAddrUpdate(MDMAx, Channel, MDMA_InitStruct->BlockRepeatDestAddrUpdateMode | \
533 MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode);
534
535
536
537 /*-------------------------- MDMAx CSAR Configuration --------------------------
538 * Configure the Transfer source address with parameter :
539 * - SrcAddress: MDMA_CSAR_SAR[31:0] bits
540 */
541 LL_MDMA_SetSourceAddress(MDMAx, Channel, MDMA_InitStruct->SrcAddress);
542
543 /*-------------------------- MDMAx CDAR Configuration --------------------------
544 * Configure the Transfer destination address with parameter :
545 * - DstAddress: MDMA_CDAR_DAR[31:0] bits
546 */
547 LL_MDMA_SetDestinationAddress(MDMAx, Channel, MDMA_InitStruct->DstAddress);
548
549 /*-------------------------- MDMAx CBRUR Configuration --------------------------
550 * Configure the Transfer Block repeat address update value with parameter :
551 * - BlockRepeatDestAddrUpdateVal: MDMA_CBRUR_DUV[31:16] bits
552 * - BlockRepeatSrcAddrUpdateVal: MDMA_CBRUR_SUV[15:0] bits
553 */
554 LL_MDMA_ConfigBlkRptAddrUpdateValue(MDMAx, Channel, MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal, \
555 MDMA_InitStruct->BlockRepeatDestAddrUpdateVal);
556
557 /*-------------------------- MDMAx CLAR Configuration --------------------------
558 * Configure the Transfer linked list address with parameter :
559 * - LinkAddress: MDMA_CLAR_LAR[31:0] bits
560 */
561 LL_MDMA_SetLinkAddress(MDMAx, Channel, MDMA_InitStruct->LinkAddress);
562
563 /*-------------------------- MDMAx CTBR Configuration --------------------------
564 * Configure the Transfer HW trigger and bus selection with parameter :
565 * - DestBus: MDMA_TBR_DBUS[17] bit
566 * - SrcBus: MDMA_TBR_SBUS[16] bit
567 * - HWTrigger: MDMA_TBR_TSEL[5:0] bits
568 */
569 LL_MDMA_ConfigBusSelection(MDMAx, Channel, MDMA_InitStruct->DestBus | MDMA_InitStruct->SrcBus);
570
571 LL_MDMA_SetHWTrigger(MDMAx, Channel, MDMA_InitStruct->HWTrigger);
572
573 /*-------------------------- MDMAx CMAR Configuration --------------------------
574 * Configure the mask address with parameter :
575 * - MaskAddress: MDMA_CMAR_MAR[31:0] bits
576 */
577 LL_MDMA_SetMaskAddress(MDMAx, Channel, MDMA_InitStruct->MaskAddress);
578
579 /*-------------------------- MDMAx CMDR Configuration --------------------------
580 * Configure the mask data with parameter :
581 * - MaskData: MDMA_CMDR_MDR[31:0] bits
582 */
583 LL_MDMA_SetMaskData(MDMAx, Channel, MDMA_InitStruct->MaskData);
584
585 return (uint32_t)SUCCESS;
586 }
587
588 /**
589 * @brief Set each @ref LL_MDMA_InitTypeDef field to default value.
590 * @param MDMA_InitStruct Pointer to a @ref LL_MDMA_InitTypeDef structure.
591 * @retval None
592 */
LL_MDMA_StructInit(LL_MDMA_InitTypeDef * MDMA_InitStruct)593 void LL_MDMA_StructInit(LL_MDMA_InitTypeDef *MDMA_InitStruct)
594 {
595 /* Set DMA_InitStruct fields to default values */
596 MDMA_InitStruct->SrcAddress = 0x00000000U;
597 MDMA_InitStruct->DstAddress = 0x00000000U;
598 MDMA_InitStruct->BlockDataLength = 0x00000000U;
599 MDMA_InitStruct->BlockRepeatCount = 0x00000000U;
600 MDMA_InitStruct->WordEndianess = LL_MDMA_WORD_ENDIANNESS_PRESERVE;
601 MDMA_InitStruct->HalfWordEndianess = LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE;
602 MDMA_InitStruct->ByteEndianess = LL_MDMA_BYTE_ENDIANNESS_PRESERVE;
603 MDMA_InitStruct->Priority = LL_MDMA_PRIORITY_LOW;
604 MDMA_InitStruct->BufferableWriteMode = LL_MDMA_BUFF_WRITE_DISABLE;
605 MDMA_InitStruct->RequestMode = LL_MDMA_REQUEST_MODE_HW;
606 MDMA_InitStruct->TriggerMode = LL_MDMA_BUFFER_TRANSFER;
607 MDMA_InitStruct->PaddingAlignment = LL_MDMA_DATAALIGN_RIGHT;
608 MDMA_InitStruct->PackMode = LL_MDMA_PACK_DISABLE;
609 MDMA_InitStruct->BufferTransferLength = 0x00000000U;
610 MDMA_InitStruct->DestBurst = LL_MDMA_DEST_BURST_SINGLE;
611 MDMA_InitStruct->SrctBurst = LL_MDMA_SRC_BURST_SINGLE;
612 MDMA_InitStruct->DestIncSize = LL_MDMA_DEST_INC_OFFSET_BYTE;
613 MDMA_InitStruct->SrcIncSize = LL_MDMA_SRC_INC_OFFSET_BYTE;
614 MDMA_InitStruct->DestDataSize = LL_MDMA_DEST_DATA_SIZE_BYTE;
615 MDMA_InitStruct->SrcDataSize = LL_MDMA_SRC_DATA_SIZE_BYTE;
616 MDMA_InitStruct->DestIncMode = LL_MDMA_DEST_FIXED;
617 MDMA_InitStruct->SrcIncMode = LL_MDMA_SRC_FIXED;
618 MDMA_InitStruct->BlockRepeatDestAddrUpdateMode = LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT;
619 MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode = LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT;
620 MDMA_InitStruct->BlockRepeatDestAddrUpdateVal = 0x00000000U;
621 MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal = 0x00000000U;
622 MDMA_InitStruct->LinkAddress = 0x00000000U;
623 MDMA_InitStruct->DestBus = LL_MDMA_DEST_BUS_SYSTEM_AXI;
624 MDMA_InitStruct->SrcBus = LL_MDMA_SRC_BUS_SYSTEM_AXI;
625 MDMA_InitStruct->HWTrigger = LL_MDMA_REQ_DMA1_STREAM0_TC;
626 MDMA_InitStruct->MaskAddress = 0x00000000U;
627 MDMA_InitStruct->MaskData = 0x00000000U;
628 }
629
630 /**
631 * @brief Initializes MDMA linked list node according to the specified
632 * parameters in the MDMA_InitStruct.
633 * @param MDMA_InitStruct Pointer to a @ref LL_MDMA_InitTypeDef structure that contains
634 * linked list node registers configurations.
635 * @param pNode Pointer to linked list node to fill according to MDMA_InitStruct parameters.
636 * @retval None
637 */
LL_MDMA_CreateLinkNode(LL_MDMA_InitTypeDef * MDMA_InitStruct,LL_MDMA_LinkNodeTypeDef * pNode)638 void LL_MDMA_CreateLinkNode(LL_MDMA_InitTypeDef *MDMA_InitStruct, LL_MDMA_LinkNodeTypeDef *pNode)
639 {
640
641 /* Check the MDMA parameters from MDMA_InitStruct */
642 assert_param(IS_LL_MDMA_BLK_DATALENGTH(MDMA_InitStruct->BlockDataLength));
643 assert_param(IS_LL_MDMA_BLK_REPEATCOUNT(MDMA_InitStruct->BlockRepeatCount));
644
645 assert_param(IS_LL_MDMA_BUFFWRITEMODE(MDMA_InitStruct->BufferableWriteMode));
646 assert_param(IS_LL_MDMA_REQUESTMODE(MDMA_InitStruct->RequestMode));
647 assert_param(IS_LL_MDMA_TRIGGERMODE(MDMA_InitStruct->TriggerMode));
648 assert_param(IS_LL_MDMA_PADDINGALIGNEMENT(MDMA_InitStruct->PaddingAlignment));
649 assert_param(IS_LL_MDMA_PACKMODE(MDMA_InitStruct->PackMode));
650 assert_param(IS_LL_MDMA_BUFFER_XFERLENGTH(MDMA_InitStruct->BufferTransferLength));
651 assert_param(IS_LL_MDMA_DESTBURST(MDMA_InitStruct->DestBurst));
652 assert_param(IS_LL_MDMA_SRCTBURST(MDMA_InitStruct->SrctBurst));
653 assert_param(IS_LL_MDMA_DESTINCSIZE(MDMA_InitStruct->DestIncSize));
654 assert_param(IS_LL_MDMA_SRCINCSIZE(MDMA_InitStruct->SrcIncSize));
655 assert_param(IS_LL_MDMA_DESTDATASIZE(MDMA_InitStruct->DestDataSize));
656 assert_param(IS_LL_MDMA_SRCDATASIZE(MDMA_InitStruct->SrcDataSize));
657 assert_param(IS_LL_MDMA_DESTINCMODE(MDMA_InitStruct->DestIncMode));
658 assert_param(IS_LL_MDMA_SRCINCMODE(MDMA_InitStruct->SrcIncMode));
659 assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatDestAddrUpdateMode));
660 assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode));
661 assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatDestAddrUpdateVal));
662 assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal));
663 assert_param(IS_LL_MDMA_DEST_BUS(MDMA_InitStruct->DestBus));
664 assert_param(IS_LL_MDMA_SRC_BUS(MDMA_InitStruct->SrcBus));
665 assert_param(IS_LL_MDMA_HWTRIGGER(MDMA_InitStruct->HWTrigger));
666
667
668 /*-------------------------- MDMAx CTCR Configuration --------------------------
669 * Configure the Transfer parameter :
670 * - BufferableWriteMode: MDMA_CTCR_BWM[31] bit
671 * - RequestMode: MDMA_CTCR_SWRM[30] bit
672 * - TriggerMode: MDMA_CTCR_TRGM[29:28] bits
673 * - PaddingAlignment: MDMA_CTCR_PAM[27:26] bits
674 * - PackMode: MDMA_CTCR_PKE[25] bit
675 * - BufferTransferLength: MDMA_CTCR_TLEN[24:18] bits
676 * - DestBurst: MDMA_CTCR_DBURST[17:15] bits
677 * - SrctBurst: MDMA_CTCR_SBURST[14:12] bits
678 * - DestIncSize: MDMA_CTCR_DINCOS[11:10] bits
679 * - SrcIncSize: MDMA_CTCR_SINCOS[9:8] bits
680 * - DestDataSize: MDMA_CTCR_DSIZE[7:6] bits
681 * - SrcDataSize: MDMA_CTCR_SSIZE[5:4] bits
682 * - DestIncMode: MDMA_CTCR_DINC[3:2] bits
683 * - SrcIncMode: MDMA_CTCR_SINC[1:0] bits
684 */
685 pNode->CTCR = MDMA_InitStruct->BufferableWriteMode | \
686 MDMA_InitStruct->RequestMode | \
687 MDMA_InitStruct->TriggerMode | \
688 MDMA_InitStruct->PaddingAlignment | \
689 MDMA_InitStruct->PackMode | \
690 MDMA_InitStruct->DestBurst | \
691 MDMA_InitStruct->SrctBurst | \
692 MDMA_InitStruct->DestIncSize | \
693 MDMA_InitStruct->SrcIncSize | \
694 MDMA_InitStruct->DestDataSize | \
695 MDMA_InitStruct->SrcDataSize | \
696 MDMA_InitStruct->DestIncMode | \
697 MDMA_InitStruct->SrcIncMode | \
698 ((MDMA_InitStruct->BufferTransferLength << MDMA_CTCR_TLEN_Pos) & MDMA_CTCR_TLEN_Msk);
699
700
701
702 /*-------------------------- MDMAx CBNDTR Configuration --------------------------
703 * Configure the Transfer Block counters and update mode with parameter :
704 * - BlockRepeatCount: MDMA_CBNDTR_BRC[31:20] bits
705 * - BlockDataLength: MDMA_CBNDTR_BNDT[16:0] bits
706 * - BlockRepeatDestAddrUpdateMode: MDMA_CBNDTR_BRDUM[19] bit
707 * - BlockRepeatDestAddrUpdateMode: MDMA_CBNDTR_BRSUM[18] bit
708 */
709 pNode->CBNDTR = ((MDMA_InitStruct->BlockRepeatCount << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC_Msk) | \
710 MDMA_InitStruct->BlockRepeatDestAddrUpdateMode | \
711 MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode | \
712 (MDMA_InitStruct->BlockDataLength & MDMA_CBNDTR_BNDT_Msk);
713
714
715 /*-------------------------- MDMAx CSAR Configuration --------------------------
716 * Configure the Transfer source address with parameter :
717 * - SrcAddress: MDMA_CSAR_SAR[31:0] bits
718 */
719 pNode->CSAR = MDMA_InitStruct->SrcAddress;
720
721
722 /*-------------------------- MDMAx CDAR Configuration --------------------------
723 * Configure the Transfer destination address with parameter :
724 * - DstAddress: MDMA_CDAR_DAR[31:0] bits
725 */
726 pNode->CDAR = MDMA_InitStruct->DstAddress;
727
728 /*-------------------------- MDMAx CBRUR Configuration --------------------------
729 * Configure the Transfer Block repeat address update value with parameter :
730 * - BlockRepeatDestAddrUpdateVal: MDMA_CBRUR_DUV[31:16] bits
731 * - BlockRepeatSrcAddrUpdateVal: MDMA_CBRUR_SUV[15:0] bits
732 */
733 pNode->CBRUR = (MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal & MDMA_CBRUR_SUV_Msk) | \
734 ((MDMA_InitStruct->BlockRepeatDestAddrUpdateVal << MDMA_CBRUR_DUV_Pos) & MDMA_CBRUR_DUV_Msk) ;
735
736 /*-------------------------- MDMAx CLAR Configuration --------------------------
737 * Configure the Transfer linked list address with parameter :
738 * - LinkAddress: MDMA_CLAR_LAR[31:0] bits
739 */
740 pNode->CLAR = MDMA_InitStruct->LinkAddress;
741
742 /*-------------------------- MDMAx CTBR Configuration --------------------------
743 * Configure the Transfer HW trigger and bus selection with parameter :
744 * - DestBus: MDMA_TBR_DBUS[17] bit
745 * - SrcBus: MDMA_TBR_SBUS[16] bit
746 * - HWTrigger: MDMA_TBR_TSEL[5:0] bits
747 */
748 pNode->CTBR = MDMA_InitStruct->DestBus | MDMA_InitStruct->SrcBus | MDMA_InitStruct->HWTrigger;
749
750 /*-------------------------- MDMAx CMAR Configuration --------------------------
751 * Configure the mask address with parameter :
752 * - MaskAddress: MDMA_CMAR_MAR[31:0] bits
753 */
754 pNode->CMAR = MDMA_InitStruct->MaskAddress;
755
756 /*-------------------------- MDMAx CMDR Configuration --------------------------
757 * Configure the mask data with parameter :
758 * - MaskData: MDMA_CMDR_MDR[31:0] bits
759 */
760 pNode->CMDR = MDMA_InitStruct->MaskData;
761
762
763 pNode->Reserved = 0;
764
765 }
766
767 /**
768 * @brief Connect Linked list Nodes.
769 * @param pPrevLinkNode Pointer to previous linked list node to be connected to new Lined list node.
770 * @param pNewLinkNode Pointer to new Linked list.
771 * @retval None
772 */
LL_MDMA_ConnectLinkNode(LL_MDMA_LinkNodeTypeDef * pPrevLinkNode,LL_MDMA_LinkNodeTypeDef * pNewLinkNode)773 void LL_MDMA_ConnectLinkNode(LL_MDMA_LinkNodeTypeDef *pPrevLinkNode, LL_MDMA_LinkNodeTypeDef *pNewLinkNode)
774 {
775 pPrevLinkNode->CLAR = (uint32_t)pNewLinkNode;
776 }
777
778 /**
779 * @brief Disconnect the next linked list node.
780 * @param pLinkNode Pointer to linked list node to be disconnected from the next one.
781 * @retval None
782 */
LL_MDMA_DisconnectNextLinkNode(LL_MDMA_LinkNodeTypeDef * pLinkNode)783 void LL_MDMA_DisconnectNextLinkNode(LL_MDMA_LinkNodeTypeDef *pLinkNode)
784 {
785 pLinkNode->CLAR = 0;
786 }
787
788 /**
789 * @}
790 */
791
792 /**
793 * @}
794 */
795
796 /**
797 * @}
798 */
799
800 #endif /* MDMA */
801
802 /**
803 * @}
804 */
805
806 #endif /* USE_FULL_LL_DRIVER */
807
808
