1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_bdma.c
4 * @author MCD Application Team
5 * @brief BDMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32h7xx_ll_bdma.h"
23 #include "stm32h7xx_ll_bus.h"
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (BDMA) || defined (BDMA1) || defined (BDMA2)
35
36 /** @addtogroup BDMA_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup BDMA_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_BDMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_BDMA_DIRECTION_PERIPH_TO_MEMORY) || \
48 ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH) || \
49 ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_MEMORY))
50
51 #define IS_LL_BDMA_MODE(__VALUE__) (((__VALUE__) == LL_BDMA_MODE_NORMAL) || \
52 ((__VALUE__) == LL_BDMA_MODE_CIRCULAR))
53
54 #define IS_LL_BDMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_BDMA_PERIPH_INCREMENT) || \
55 ((__VALUE__) == LL_BDMA_PERIPH_NOINCREMENT))
56
57 #define IS_LL_BDMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_BDMA_MEMORY_INCREMENT) || \
58 ((__VALUE__) == LL_BDMA_MEMORY_NOINCREMENT))
59
60 #define IS_LL_BDMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_BDMA_PDATAALIGN_BYTE) || \
61 ((__VALUE__) == LL_BDMA_PDATAALIGN_HALFWORD) || \
62 ((__VALUE__) == LL_BDMA_PDATAALIGN_WORD))
63
64 #define IS_LL_BDMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_BDMA_MDATAALIGN_BYTE) || \
65 ((__VALUE__) == LL_BDMA_MDATAALIGN_HALFWORD) || \
66 ((__VALUE__) == LL_BDMA_MDATAALIGN_WORD))
67
68 #define IS_LL_BDMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
69
70 #if defined(ADC3)
71 #define IS_LL_BDMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX2_REQ_ADC3)
72 #else
73 #define IS_LL_BDMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX2_REQ_DFSDM2_FLT0)
74 #endif /* ADC3 */
75
76 #define IS_LL_BDMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_BDMA_PRIORITY_LOW) || \
77 ((__VALUE__) == LL_BDMA_PRIORITY_MEDIUM) || \
78 ((__VALUE__) == LL_BDMA_PRIORITY_HIGH) || \
79 ((__VALUE__) == LL_BDMA_PRIORITY_VERYHIGH))
80
81 #define IS_LL_BDMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == BDMA) && \
82 (((CHANNEL) == LL_BDMA_CHANNEL_0) || \
83 ((CHANNEL) == LL_BDMA_CHANNEL_1) || \
84 ((CHANNEL) == LL_BDMA_CHANNEL_2) || \
85 ((CHANNEL) == LL_BDMA_CHANNEL_3) || \
86 ((CHANNEL) == LL_BDMA_CHANNEL_4) || \
87 ((CHANNEL) == LL_BDMA_CHANNEL_5) || \
88 ((CHANNEL) == LL_BDMA_CHANNEL_6) || \
89 ((CHANNEL) == LL_BDMA_CHANNEL_7))))
90
91 /**
92 * @}
93 */
94
95 /* Private function prototypes -----------------------------------------------*/
96
97 /* Exported functions --------------------------------------------------------*/
98 /** @addtogroup BDMA_LL_Exported_Functions
99 * @{
100 */
101
102 /** @addtogroup BDMA_LL_EF_Init
103 * @{
104 */
105
106 /**
107 * @brief De-initialize the DMA registers to their default reset values.
108 * @param BDMAx BDMAx Instance
109 * @param Channel This parameter can be one of the following values:
110 * @arg @ref LL_BDMA_CHANNEL_0
111 * @arg @ref LL_BDMA_CHANNEL_1
112 * @arg @ref LL_BDMA_CHANNEL_2
113 * @arg @ref LL_BDMA_CHANNEL_3
114 * @arg @ref LL_BDMA_CHANNEL_4
115 * @arg @ref LL_BDMA_CHANNEL_5
116 * @arg @ref LL_BDMA_CHANNEL_6
117 * @arg @ref LL_BDMA_CHANNEL_7
118 * @arg @ref LL_BDMA_CHANNEL_ALL
119 * @retval An ErrorStatus enumeration value:
120 * - SUCCESS: DMA registers are de-initialized
121 * - ERROR: DMA registers are not de-initialized
122 */
LL_BDMA_DeInit(BDMA_TypeDef * BDMAx,uint32_t Channel)123 uint32_t LL_BDMA_DeInit(BDMA_TypeDef *BDMAx, uint32_t Channel)
124 {
125 BDMA_Channel_TypeDef *tmp ;
126 ErrorStatus status = SUCCESS;
127
128 /* Check the DMA Instance DMAx and Channel parameters */
129 assert_param(IS_LL_BDMA_ALL_CHANNEL_INSTANCE(BDMAx, Channel) || (Channel == LL_BDMA_CHANNEL_ALL));
130
131 if (Channel == LL_BDMA_CHANNEL_ALL)
132 {
133 if (BDMAx == BDMA)
134 {
135 /* Force reset of BDMA clock */
136 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
137
138 /* Release reset of BDMA clock */
139 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
140 }
141 else
142 {
143 status = ERROR;
144 }
145 }
146 else
147 {
148 tmp = (BDMA_Channel_TypeDef *)(__LL_BDMA_GET_CHANNEL_INSTANCE(BDMAx, Channel));
149
150 /* Disable the selected DMAx_Channely */
151 CLEAR_BIT(tmp->CCR, BDMA_CCR_EN);
152
153 /* Reset DMAx_Channely control register */
154 LL_BDMA_WriteReg(tmp, CCR, 0U);
155
156 /* Reset DMAx_Channely remaining bytes register */
157 LL_BDMA_WriteReg(tmp, CNDTR, 0U);
158
159 /* Reset DMAx_Channely peripheral address register */
160 LL_BDMA_WriteReg(tmp, CPAR, 0U);
161
162 /* Reset DMAx_Channely memory 0 address register */
163 LL_BDMA_WriteReg(tmp, CM0AR, 0U);
164
165 /* Reset DMAx_Channely memory 1 address register */
166 LL_BDMA_WriteReg(tmp, CM1AR, 0U);
167
168 /* Reset Request register field for BDMAx Channel */
169 LL_BDMA_SetPeriphRequest(BDMAx, Channel, LL_DMAMUX2_REQ_MEM2MEM);
170
171 if (Channel == LL_BDMA_CHANNEL_0)
172 {
173 /* Reset interrupt pending bits for DMAx Channel0 */
174 LL_BDMA_ClearFlag_GI0(BDMAx);
175 }
176 else if (Channel == LL_BDMA_CHANNEL_1)
177 {
178 /* Reset interrupt pending bits for DMAx Channel1 */
179 LL_BDMA_ClearFlag_GI1(BDMAx);
180 }
181 else if (Channel == LL_BDMA_CHANNEL_2)
182 {
183 /* Reset interrupt pending bits for DMAx Channel2 */
184 LL_BDMA_ClearFlag_GI2(BDMAx);
185 }
186 else if (Channel == LL_BDMA_CHANNEL_3)
187 {
188 /* Reset interrupt pending bits for DMAx Channel3 */
189 LL_BDMA_ClearFlag_GI3(BDMAx);
190 }
191 else if (Channel == LL_BDMA_CHANNEL_4)
192 {
193 /* Reset interrupt pending bits for DMAx Channel4 */
194 LL_BDMA_ClearFlag_GI4(BDMAx);
195 }
196 else if (Channel == LL_BDMA_CHANNEL_5)
197 {
198 /* Reset interrupt pending bits for DMAx Channel5 */
199 LL_BDMA_ClearFlag_GI5(BDMAx);
200 }
201
202 else if (Channel == LL_BDMA_CHANNEL_6)
203 {
204 /* Reset interrupt pending bits for DMAx Channel6 */
205 LL_BDMA_ClearFlag_GI6(BDMAx);
206 }
207 else if (Channel == LL_BDMA_CHANNEL_7)
208 {
209 /* Reset interrupt pending bits for DMAx Channel7 */
210 LL_BDMA_ClearFlag_GI7(BDMAx);
211 }
212 else
213 {
214 status = ERROR;
215 }
216 }
217
218 return (uint32_t)status;
219 }
220
221 /**
222 * @brief Initialize the BDMA registers according to the specified parameters in BDMA_InitStruct.
223 * @note To convert BDMAx_Channely Instance to BDMAx Instance and Channely, use helper macros :
224 * @arg @ref __LL_BDMA_GET_INSTANCE
225 * @arg @ref __LL_BDMA_GET_CHANNEL
226 * @param BDMAx BDMAx Instance
227 * @param Channel This parameter can be one of the following values:
228 * @arg @ref LL_BDMA_CHANNEL_0
229 * @arg @ref LL_BDMA_CHANNEL_1
230 * @arg @ref LL_BDMA_CHANNEL_2
231 * @arg @ref LL_BDMA_CHANNEL_3
232 * @arg @ref LL_BDMA_CHANNEL_4
233 * @arg @ref LL_BDMA_CHANNEL_5
234 * @arg @ref LL_BDMA_CHANNEL_6
235 * @arg @ref LL_BDMA_CHANNEL_7
236 * @param BDMA_InitStruct pointer to a @ref LL_BDMA_InitTypeDef structure.
237 * @retval An ErrorStatus enumeration value:
238 * - SUCCESS: DMA registers are initialized
239 * - ERROR: Not applicable
240 */
LL_BDMA_Init(BDMA_TypeDef * BDMAx,uint32_t Channel,LL_BDMA_InitTypeDef * BDMA_InitStruct)241 uint32_t LL_BDMA_Init(BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef *BDMA_InitStruct)
242 {
243 /* Check the DMA Instance DMAx and Channel parameters */
244 assert_param(IS_LL_BDMA_ALL_CHANNEL_INSTANCE(BDMAx, Channel));
245
246 /* Check the DMA parameters from BDMA_InitStruct */
247 assert_param(IS_LL_BDMA_DIRECTION(BDMA_InitStruct->Direction));
248 assert_param(IS_LL_BDMA_MODE(BDMA_InitStruct->Mode));
249 assert_param(IS_LL_BDMA_PERIPHINCMODE(BDMA_InitStruct->PeriphOrM2MSrcIncMode));
250 assert_param(IS_LL_BDMA_MEMORYINCMODE(BDMA_InitStruct->MemoryOrM2MDstIncMode));
251 assert_param(IS_LL_BDMA_PERIPHDATASIZE(BDMA_InitStruct->PeriphOrM2MSrcDataSize));
252 assert_param(IS_LL_BDMA_MEMORYDATASIZE(BDMA_InitStruct->MemoryOrM2MDstDataSize));
253 assert_param(IS_LL_BDMA_NBDATA(BDMA_InitStruct->NbData));
254 assert_param(IS_LL_BDMA_PERIPHREQUEST(BDMA_InitStruct->PeriphRequest));
255 assert_param(IS_LL_BDMA_PRIORITY(BDMA_InitStruct->Priority));
256
257 /*---------------------------- DMAx CCR Configuration ------------------------
258 * Configure DMAx_Channely: data transfer direction, data transfer mode,
259 * peripheral and memory increment mode,
260 * data size alignment and priority level with parameters :
261 * - Direction: BDMA_CCR_DIR and BDMA_CCR_MEM2MEM bits
262 * - Mode: BDMA_CCR_CIRC bit
263 * - PeriphOrM2MSrcIncMode: BDMA_CCR_PINC bit
264 * - MemoryOrM2MDstIncMode: BDMA_CCR_MINC bit
265 * - PeriphOrM2MSrcDataSize: BDMA_CCR_PSIZE[1:0] bits
266 * - MemoryOrM2MDstDataSize: BDMA_CCR_MSIZE[1:0] bits
267 * - Priority: BDMA_CCR_PL[1:0] bits
268 */
269 LL_BDMA_ConfigTransfer(BDMAx, Channel, BDMA_InitStruct->Direction | \
270 BDMA_InitStruct->Mode | \
271 BDMA_InitStruct->PeriphOrM2MSrcIncMode | \
272 BDMA_InitStruct->MemoryOrM2MDstIncMode | \
273 BDMA_InitStruct->PeriphOrM2MSrcDataSize | \
274 BDMA_InitStruct->MemoryOrM2MDstDataSize | \
275 BDMA_InitStruct->Priority);
276
277 /*-------------------------- DMAx CMAR Configuration -------------------------
278 * Configure the memory or destination base address with parameter :
279 * - MemoryOrM2MDstAddress: BDMA_CMAR_MA[31:0] bits
280 */
281 LL_BDMA_SetMemoryAddress(BDMAx, Channel, BDMA_InitStruct->MemoryOrM2MDstAddress);
282
283 /*-------------------------- DMAx CPAR Configuration -------------------------
284 * Configure the peripheral or source base address with parameter :
285 * - PeriphOrM2MSrcAddress: BDMA_CPAR_PA[31:0] bits
286 */
287 LL_BDMA_SetPeriphAddress(BDMAx, Channel, BDMA_InitStruct->PeriphOrM2MSrcAddress);
288
289 /*--------------------------- DMAx CNDTR Configuration -----------------------
290 * Configure the peripheral base address with parameter :
291 * - NbData: BDMA_CNDTR_NDT[15:0] bits
292 */
293 LL_BDMA_SetDataLength(BDMAx, Channel, BDMA_InitStruct->NbData);
294
295 /*--------------------------- DMAMUXx CCR Configuration ----------------------
296 * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter :
297 * - PeriphRequest: BDMA_CxCR[7:0] bits
298 */
299 LL_BDMA_SetPeriphRequest(BDMAx, Channel, BDMA_InitStruct->PeriphRequest);
300
301 return (uint32_t)SUCCESS;
302 }
303
304 /**
305 * @brief Set each @ref LL_BDMA_InitTypeDef field to default value.
306 * @param BDMA_InitStruct Pointer to a @ref LL_BDMA_InitTypeDef structure.
307 * @retval None
308 */
LL_BDMA_StructInit(LL_BDMA_InitTypeDef * BDMA_InitStruct)309 void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct)
310 {
311 /* Set BDMA_InitStruct fields to default values */
312 BDMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
313 BDMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
314 BDMA_InitStruct->Direction = LL_BDMA_DIRECTION_PERIPH_TO_MEMORY;
315 BDMA_InitStruct->Mode = LL_BDMA_MODE_NORMAL;
316 BDMA_InitStruct->PeriphOrM2MSrcIncMode = LL_BDMA_PERIPH_NOINCREMENT;
317 BDMA_InitStruct->MemoryOrM2MDstIncMode = LL_BDMA_MEMORY_NOINCREMENT;
318 BDMA_InitStruct->PeriphOrM2MSrcDataSize = LL_BDMA_PDATAALIGN_BYTE;
319 BDMA_InitStruct->MemoryOrM2MDstDataSize = LL_BDMA_MDATAALIGN_BYTE;
320 BDMA_InitStruct->NbData = 0x00000000U;
321 BDMA_InitStruct->PeriphRequest = LL_DMAMUX2_REQ_MEM2MEM;
322 BDMA_InitStruct->Priority = LL_BDMA_PRIORITY_LOW;
323 }
324
325 /**
326 * @}
327 */
328
329 /**
330 * @}
331 */
332
333 /**
334 * @}
335 */
336
337 #endif /* BDMA || BDMA1 || BDMA2 */
338
339 /**
340 * @}
341 */
342
343 #endif /* USE_FULL_LL_DRIVER */
344
345
