1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32h7xx_ll_adc.h"
22 #include "stm32h7xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
35
36 /** @addtogroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup ADC_LL_Private_Constants
44 * @{
45 */
46
47 /* Definitions of ADC hardware constraints delays */
48 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
49 /* not timeout values: */
50 /* Timeout values for ADC operations are dependent to device clock */
51 /* configuration (system clock versus ADC clock), */
52 /* and therefore must be defined in user application. */
53 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
54 /* values definition. */
55 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
56 /* of device clock setting. */
57 /* In user application, ADC timeout values should be defined with */
58 /* temporal values, in function of device clock settings. */
59 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
60 /* - ADC clock from synchronous clock with AHB prescaler 512, */
61 /* APB prescaler 16, ADC prescaler 4. */
62 /* - ADC clock from asynchronous clock (PLL) with prescaler 1, */
63 /* with highest ratio CPU clock frequency vs HSI clock frequency */
64 /* Unit: CPU cycles. */
65 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
66 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
67 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
68
69 /**
70 * @}
71 */
72
73 /* Private macros ------------------------------------------------------------*/
74
75 /** @addtogroup ADC_LL_Private_Macros
76 * @{
77 */
78
79 /* Check of parameters for configuration of ADC hierarchical scope: */
80 /* common to several ADC instances. */
81 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
82 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
83 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
84 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
85 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
86 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
87 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
88 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
89 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
90 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
91 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
92 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
93 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
94 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
95 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
96 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
97 )
98
99 /* Check of parameters for configuration of ADC hierarchical scope: */
100 /* ADC instance. */
101 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
102 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_16B) \
103 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_14B) \
104 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
105 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
106 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
107 )
108
109 #define IS_LL_ADC_LEFT_BIT_SHIFT(__LEFT_BIT_SHIFT__) \
110 ( ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_NONE) \
111 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_1) \
112 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_2) \
113 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_3) \
114 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_4) \
115 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_5) \
116 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_6) \
117 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_7) \
118 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_8) \
119 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_9) \
120 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_10) \
121 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_11) \
122 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_12) \
123 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_13) \
124 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_14) \
125 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_15) \
126 )
127
128 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
129 ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
130 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
131 )
132
133 /* Check of parameters for configuration of ADC hierarchical scope: */
134 /* ADC group regular */
135 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
136 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
137 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
138 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
139 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
140 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
141 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
144 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
145 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
146 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
147 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
148 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
149 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
150 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
151 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
152 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
153 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) \
154 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) \
155 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_OUT) \
156 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM2_OUT) \
157 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM3_OUT) \
158 )
159
160 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
161 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
162 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
163 )
164
165 #define IS_LL_ADC_REG_DATA_TRANSFER_MODE(__REG_DATA_TRANSFER_MODE__) \
166 ( ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DR_TRANSFER) \
167 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
168 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
169 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DFSDM_TRANSFER) \
170 )
171
172 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
173 ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
174 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
175 )
176
177 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
178 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
179 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
180 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
181 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
182 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
183 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
184 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
185 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
186 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
187 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
188 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
189 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
190 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
191 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
192 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
193 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
194 )
195
196 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
197 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
198 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
199 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
200 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
201 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
202 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
203 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
204 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
205 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
206 )
207
208 /* Check of parameters for configuration of ADC hierarchical scope: */
209 /* ADC group injected */
210 #if defined(STM32H745xx) || defined(STM32H745xG) || defined(STM32H742xx) || defined(STM32H743xx) || defined(STM32H747xG) || defined(STM32H747xx) || defined(STM32H750xx) || defined(STM32H753xx) || defined(STM32H755xx) || defined(STM32H757xx)
211 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
212 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
213 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
214 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
215 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
216 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
217 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
218 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
219 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
220 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
221 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
222 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
223 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
224 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
225 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
226 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
227 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
228 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
229 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) \
230 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) \
231 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) \
232 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) \
233 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) \
234 )
235 #else
236 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
237 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
238 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
239 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
240 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
241 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
242 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
243 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
244 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
245 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
246 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
247 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
248 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
249 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
250 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
251 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
252 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
253 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
254 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) \
255 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) \
256 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) \
257 )
258 #endif
259
260 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
261 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
262 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
263 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
264 )
265
266 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
267 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
268 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
269 )
270
271 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
272 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
273 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
274 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
275 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
276 )
277
278 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
279 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
280 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
281 )
282
283 /* Check of parameters for configuration of ADC hierarchical scope: */
284 /* multimode. */
285 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
286 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
287 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
288 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
289 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
290 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
291 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
292 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
293 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
294 )
295
296 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
297 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
298 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_32_10B) \
299 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_8B) \
300 )
301 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
302 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5) \
303 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5) \
304 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5) \
305 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5) \
306 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS) \
307 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5) \
308 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS) \
309 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
310 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5) \
311 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS) \
312 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5) \
313 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
314 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
315 )
316
317 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
318 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
319 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
320 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
321 )
322
323 /**
324 * @}
325 */
326
327
328 /* Private function prototypes -----------------------------------------------*/
329
330 /* Exported functions --------------------------------------------------------*/
331 /** @addtogroup ADC_LL_Exported_Functions
332 * @{
333 */
334
335 /** @addtogroup ADC_LL_EF_Init
336 * @{
337 */
338
339 /**
340 * @brief De-initialize registers of all ADC instances belonging to
341 * the same ADC common instance to their default reset values.
342 * @note This function is performing a hard reset, using high level
343 * clock source RCC ADC reset.
344 * Caution: On this STM32 series, if several ADC instances are available
345 * on the selected device, RCC ADC reset will reset
346 * all ADC instances belonging to the common ADC instance.
347 * To de-initialize only 1 ADC instance, use
348 * function @ref LL_ADC_DeInit().
349 * @param ADCxy_COMMON ADC common instance
350 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
351 * @retval An ErrorStatus enumeration value:
352 * - SUCCESS: ADC common registers are de-initialized
353 * - ERROR: not applicable
354 */
LL_ADC_CommonDeInit(ADC_Common_TypeDef * ADCxy_COMMON)355 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
356 {
357 /* Check the parameters */
358 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
359
360 if (ADCxy_COMMON == ADC12_COMMON)
361 {
362 /* Force reset of ADC clock (core clock) */
363 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ADC12);
364
365 /* Release reset of ADC clock (core clock) */
366 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12);
367 }
368 else
369 {
370 #if defined (ADC3)
371 /* Force reset of ADC clock (core clock) */
372 LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_ADC3);
373
374 /* Release reset of ADC clock (core clock) */
375 LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_ADC3);
376 #endif
377 }
378
379 return SUCCESS;
380 }
381
382 /**
383 * @brief Initialize some features of ADC common parameters
384 * (all ADC instances belonging to the same ADC common instance)
385 * and multimode (for devices with several ADC instances available).
386 * @note The setting of ADC common parameters is conditioned to
387 * ADC instances state:
388 * All ADC instances belonging to the same ADC common instance
389 * must be disabled.
390 * @param ADCxy_COMMON ADC common instance
391 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
392 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
393 * @retval An ErrorStatus enumeration value:
394 * - SUCCESS: ADC common registers are initialized
395 * - ERROR: ADC common registers are not initialized
396 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)397 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
398 {
399 ErrorStatus status = SUCCESS;
400
401 /* Check the parameters */
402 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
403 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
404
405 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
406 if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
407 {
408 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
409 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
410 }
411
412 /* Note: Hardware constraint (refer to description of functions */
413 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
414 /* On this STM32 series, setting of these features is conditioned to */
415 /* ADC state: */
416 /* All ADC instances of the ADC common group must be disabled. */
417 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
418 {
419 /* Configuration of ADC hierarchical scope: */
420 /* - common to several ADC */
421 /* (all ADC instances belonging to the same ADC common instance) */
422 /* - Set ADC clock (conversion clock) */
423 /* - multimode (if several ADC instances available on the */
424 /* selected device) */
425 /* - Set ADC multimode configuration */
426 /* - Set ADC multimode DMA transfer */
427 /* - Set ADC multimode: delay between 2 sampling phases */
428 if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
429 {
430 MODIFY_REG(ADCxy_COMMON->CCR,
431 ADC_CCR_CKMODE
432 | ADC_CCR_PRESC
433 | ADC_CCR_DUAL
434 | ADC_CCR_DAMDF
435 | ADC_CCR_DELAY
436 ,
437 ADC_CommonInitStruct->CommonClock
438 | ADC_CommonInitStruct->Multimode
439 | ADC_CommonInitStruct->MultiDMATransfer
440 | ADC_CommonInitStruct->MultiTwoSamplingDelay
441 );
442 }
443 else
444 {
445 MODIFY_REG(ADCxy_COMMON->CCR,
446 ADC_CCR_CKMODE
447 | ADC_CCR_PRESC
448 | ADC_CCR_DUAL
449 | ADC_CCR_DAMDF
450 | ADC_CCR_DELAY
451 ,
452 ADC_CommonInitStruct->CommonClock
453 | LL_ADC_MULTI_INDEPENDENT
454 );
455 }
456 }
457 else
458 {
459 /* Initialization error: One or several ADC instances belonging to */
460 /* the same ADC common instance are not disabled. */
461 status = ERROR;
462 }
463
464 return status;
465 }
466
467 /**
468 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
469 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
470 * whose fields will be set to default values.
471 * @retval None
472 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)473 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
474 {
475 /* Set ADC_CommonInitStruct fields to default values */
476 /* Set fields of ADC common */
477 /* (all ADC instances belonging to the same ADC common instance) */
478 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
479
480 /* Set fields of ADC multimode */
481 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
482 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
483 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5;
484 }
485
486 /**
487 * @brief De-initialize registers of the selected ADC instance
488 * to their default reset values.
489 * @note To reset all ADC instances quickly (perform a hard reset),
490 * use function @ref LL_ADC_CommonDeInit().
491 * @note If this functions returns error status, it means that ADC instance
492 * is in an unknown state.
493 * In this case, perform a hard reset using high level
494 * clock source RCC ADC reset.
495 * Caution: On this STM32 series, if several ADC instances are available
496 * on the selected device, RCC ADC reset will reset
497 * all ADC instances belonging to the common ADC instance.
498 * Refer to function @ref LL_ADC_CommonDeInit().
499 * @param ADCx ADC instance
500 * @retval An ErrorStatus enumeration value:
501 * - SUCCESS: ADC registers are de-initialized
502 * - ERROR: ADC registers are not de-initialized
503 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)504 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
505 {
506 ErrorStatus status = SUCCESS;
507
508 __IO uint32_t timeout_cpu_cycles = 0UL;
509
510 /* Check the parameters */
511 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
512
513 /* Disable ADC instance if not already disabled. */
514 if (LL_ADC_IsEnabled(ADCx) == 1UL)
515 {
516 /* Set ADC group regular trigger source to SW start to ensure to not */
517 /* have an external trigger event occurring during the conversion stop */
518 /* ADC disable process. */
519 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
520
521 /* Stop potential ADC conversion on going on ADC group regular. */
522 if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
523 {
524 if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
525 {
526 LL_ADC_REG_StopConversion(ADCx);
527 }
528 }
529
530 /* Set ADC group injected trigger source to SW start to ensure to not */
531 /* have an external trigger event occurring during the conversion stop */
532 /* ADC disable process. */
533 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
534
535 /* Stop potential ADC conversion on going on ADC group injected. */
536 if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
537 {
538 if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
539 {
540 LL_ADC_INJ_StopConversion(ADCx);
541 }
542 }
543
544 /* Wait for ADC conversions are effectively stopped */
545 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
546 while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
547 | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
548 {
549 timeout_cpu_cycles--;
550 if (timeout_cpu_cycles == 0UL)
551 {
552 /* Time-out error */
553 status = ERROR;
554 break;
555 }
556 }
557
558 /* Flush group injected contexts queue (register JSQR): */
559 /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
560 /* contexts queue is maintained with the last active context). */
561 LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
562
563 /* Disable the ADC instance */
564 LL_ADC_Disable(ADCx);
565
566 /* Wait for ADC instance is effectively disabled */
567 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
568 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
569 {
570 timeout_cpu_cycles--;
571 if (timeout_cpu_cycles == 0UL)
572 {
573 /* Time-out error */
574 status = ERROR;
575 break;
576 }
577 }
578 }
579
580 /* Check whether ADC state is compliant with expected state */
581 if (READ_BIT(ADCx->CR,
582 (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
583 | ADC_CR_ADDIS | ADC_CR_ADEN)
584 )
585 == 0UL)
586 {
587 /* ========== Reset ADC registers ========== */
588 /* Reset register IER */
589 CLEAR_BIT(ADCx->IER,
590 (LL_ADC_IT_ADRDY
591 | LL_ADC_IT_EOC
592 | LL_ADC_IT_EOS
593 | LL_ADC_IT_OVR
594 | LL_ADC_IT_EOSMP
595 | LL_ADC_IT_JEOC
596 | LL_ADC_IT_JEOS
597 | LL_ADC_IT_JQOVF
598 | LL_ADC_IT_AWD1
599 | LL_ADC_IT_AWD2
600 | LL_ADC_IT_AWD3
601 )
602 );
603
604 /* Reset register ISR */
605 SET_BIT(ADCx->ISR,
606 (LL_ADC_FLAG_ADRDY
607 | LL_ADC_FLAG_EOC
608 | LL_ADC_FLAG_EOS
609 | LL_ADC_FLAG_OVR
610 | LL_ADC_FLAG_EOSMP
611 | LL_ADC_FLAG_JEOC
612 | LL_ADC_FLAG_JEOS
613 | LL_ADC_FLAG_JQOVF
614 | LL_ADC_FLAG_AWD1
615 | LL_ADC_FLAG_AWD2
616 | LL_ADC_FLAG_AWD3
617 )
618 );
619
620 /* Reset register CR */
621 /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
622 /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
623 /* access mode "read-set": no direct reset applicable. */
624 /* - Reset Calibration mode to default setting (single ended). */
625 /* - Disable ADC internal voltage regulator. */
626 /* - Enable ADC deep power down. */
627 /* Note: ADC internal voltage regulator disable and ADC deep power */
628 /* down enable are conditioned to ADC state disabled: */
629 /* already done above. */
630 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
631 SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
632
633 /* Reset register CFGR */
634 CLEAR_BIT(ADCx->CFGR,
635 (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
636 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
637 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
638 | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
639 | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_RES
640 | ADC_CFGR_DMNGT)
641 );
642
643 SET_BIT(ADCx->CFGR, ADC_CFGR_JQDIS);
644
645 /* Reset register CFGR2 */
646 CLEAR_BIT(ADCx->CFGR2,
647 (ADC_CFGR2_LSHIFT | ADC_CFGR2_OVSR | ADC_CFGR2_RSHIFT1
648 | ADC_CFGR2_RSHIFT4 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT2
649 | ADC_CFGR2_RSHIFT1 | ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS
650 | ADC_CFGR2_OVSS | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
651 );
652
653 /* Reset register SMPR1 */
654 CLEAR_BIT(ADCx->SMPR1,
655 (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
656 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
657 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
658 );
659
660 /* Reset register SMPR2 */
661 CLEAR_BIT(ADCx->SMPR2,
662 (ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17
663 | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14
664 | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11
665 | ADC_SMPR2_SMP10)
666 );
667
668 /* Reset register TR1 */
669 #if defined(ADC_VER_V5_V90)
670 if (ADCx == ADC3)
671 {
672 /* Reset register TR1 */
673 MODIFY_REG(ADCx->LTR1_TR1, ADC3_TR1_AWDFILT | ADC3_TR1_HT1 | ADC3_TR1_LT1, ADC3_TR1_HT1);
674
675 /* Reset register TR2 */
676 MODIFY_REG(ADCx->HTR1_TR2, ADC3_TR2_HT2 | ADC3_TR2_LT2, ADC3_TR2_HT2);
677
678 /* Reset register TR3 */
679 MODIFY_REG(ADCx->RES1_TR3, ADC3_TR3_HT3 | ADC3_TR3_LT3, ADC3_TR3_HT3);
680 }
681 else
682 {
683 CLEAR_BIT(ADCx->LTR1_TR1, ADC_LTR_LT);
684 SET_BIT(ADCx->HTR1_TR2, ADC_HTR_HT);
685
686 CLEAR_BIT(ADCx->LTR2_DIFSEL, ADC_LTR_LT);
687 SET_BIT(ADCx->HTR2_CALFACT, ADC_HTR_HT);
688 CLEAR_BIT(ADCx->LTR3_RES10, ADC_LTR_LT);
689 SET_BIT(ADCx->HTR3_RES11, ADC_HTR_HT);
690 }
691 #else
692 CLEAR_BIT(ADCx->LTR1, ADC_LTR_LT);
693 SET_BIT(ADCx->HTR1, ADC_HTR_HT);
694
695 CLEAR_BIT(ADCx->LTR2, ADC_LTR_LT);
696 SET_BIT(ADCx->HTR2, ADC_HTR_HT);
697 CLEAR_BIT(ADCx->LTR3, ADC_LTR_LT);
698 SET_BIT(ADCx->HTR3, ADC_HTR_HT);
699 #endif
700
701 /* Reset register SQR1 */
702 CLEAR_BIT(ADCx->SQR1,
703 (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
704 | ADC_SQR1_SQ1 | ADC_SQR1_L)
705 );
706
707 /* Reset register SQR2 */
708 CLEAR_BIT(ADCx->SQR2,
709 (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
710 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
711 );
712
713 /* Reset register SQR3 */
714 CLEAR_BIT(ADCx->SQR3,
715 (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
716 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
717 );
718
719 /* Reset register SQR4 */
720 CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
721
722 /* Reset register JSQR */
723 CLEAR_BIT(ADCx->JSQR,
724 (ADC_JSQR_JL
725 | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
726 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
727 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1)
728 );
729
730 /* Reset register DR */
731 /* Note: bits in access mode read only, no direct reset applicable */
732
733 /* Reset register OFR1 */
734 CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_SSATE);
735 /* Reset register OFR2 */
736 CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2 | ADC_OFR2_OFFSET2_CH | ADC_OFR2_SSATE);
737 /* Reset register OFR3 */
738 CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3 | ADC_OFR3_OFFSET3_CH | ADC_OFR3_SSATE);
739 /* Reset register OFR4 */
740 CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4 | ADC_OFR4_OFFSET4_CH | ADC_OFR4_SSATE);
741
742 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
743 /* Note: bits in access mode read only, no direct reset applicable */
744
745 /* Reset register AWD2CR */
746 CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
747
748 /* Reset register AWD3CR */
749 CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
750
751 /* Reset register DIFSEL */
752 #if defined(ADC_VER_V5_V90)
753 if (ADCx == ADC3)
754 {
755 CLEAR_BIT(ADCx->LTR2_DIFSEL, ADC_DIFSEL_DIFSEL);
756
757 /* Reset register CALFACT */
758 CLEAR_BIT(ADCx->HTR2_CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
759 }
760 else
761 {
762 CLEAR_BIT(ADCx->DIFSEL_RES12, ADC_DIFSEL_DIFSEL);
763
764 /* Reset register CALFACT */
765 CLEAR_BIT(ADCx->CALFACT_RES13, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
766
767 /* Reset register CALFACT2 */
768 CLEAR_BIT(ADCx->CALFACT2_RES14, ADC_CALFACT2_LINCALFACT);
769 }
770 #else
771 CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
772
773 /* Reset register CALFACT */
774 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
775
776 /* Reset register CALFACT2 */
777 CLEAR_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT);
778 #endif
779 }
780 else
781 {
782 /* ADC instance is in an unknown state */
783 /* Need to performing a hard reset of ADC instance, using high level */
784 /* clock source RCC ADC reset. */
785 /* Caution: On this STM32 series, if several ADC instances are available */
786 /* on the selected device, RCC ADC reset will reset */
787 /* all ADC instances belonging to the common ADC instance. */
788 /* Caution: On this STM32 series, if several ADC instances are available */
789 /* on the selected device, RCC ADC reset will reset */
790 /* all ADC instances belonging to the common ADC instance. */
791 status = ERROR;
792 }
793
794 return status;
795 }
796
797 /**
798 * @brief Initialize some features of ADC instance.
799 * @note These parameters have an impact on ADC scope: ADC instance.
800 * Affects both group regular and group injected (availability
801 * of ADC group injected depends on STM32 families).
802 * Refer to corresponding unitary functions into
803 * @ref ADC_LL_EF_Configuration_ADC_Instance .
804 * @note The setting of these parameters by function @ref LL_ADC_Init()
805 * is conditioned to ADC state:
806 * ADC instance must be disabled.
807 * This condition is applied to all ADC features, for efficiency
808 * and compatibility over all STM32 families. However, the different
809 * features can be set under different ADC state conditions
810 * (setting possible with ADC enabled without conversion on going,
811 * ADC enabled with conversion on going, ...)
812 * Each feature can be updated afterwards with a unitary function
813 * and potentially with ADC in a different state than disabled,
814 * refer to description of each function for setting
815 * conditioned to ADC state.
816 * @note After using this function, some other features must be configured
817 * using LL unitary functions.
818 * The minimum configuration remaining to be done is:
819 * - Set ADC group regular or group injected sequencer:
820 * map channel on the selected sequencer rank.
821 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
822 * - Set ADC channel sampling time
823 * Refer to function LL_ADC_SetChannelSamplingTime();
824 * @param ADCx ADC instance
825 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
826 * @retval An ErrorStatus enumeration value:
827 * - SUCCESS: ADC registers are initialized
828 * - ERROR: ADC registers are not initialized
829 */
LL_ADC_Init(ADC_TypeDef * ADCx,LL_ADC_InitTypeDef * ADC_InitStruct)830 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
831 {
832 ErrorStatus status = SUCCESS;
833
834 /* Check the parameters */
835 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
836
837 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
838 assert_param(IS_LL_ADC_LEFT_BIT_SHIFT(ADC_InitStruct->LeftBitShift));
839 assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
840
841 /* Note: Hardware constraint (refer to description of this function): */
842 /* ADC instance must be disabled. */
843 if (LL_ADC_IsEnabled(ADCx) == 0UL)
844 {
845 /* Configuration of ADC hierarchical scope: */
846 /* - ADC instance */
847 /* - Set ADC data resolution */
848 /* - Set ADC conversion data alignment */
849 /* - Set ADC low power mode */
850 #if defined(ADC_VER_V5_V90)
851 if(ADCx==ADC3)
852 {
853 MODIFY_REG(ADCx->CFGR,
854 ADC3_CFGR_RES
855 | ADC_CFGR_AUTDLY
856 ,
857 ((__LL_ADC12_RESOLUTION_TO_ADC3(ADC_InitStruct->Resolution) & (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) << 1UL)
858 | ADC_InitStruct->LowPowerMode
859 );
860 }
861 else
862 {
863 MODIFY_REG(ADCx->CFGR,
864 ADC_CFGR_RES
865 | ADC_CFGR_AUTDLY
866 ,
867 ADC_InitStruct->Resolution
868 | ADC_InitStruct->LowPowerMode
869 );
870 }
871 #else
872 MODIFY_REG(ADCx->CFGR,
873 ADC_CFGR_RES
874 | ADC_CFGR_AUTDLY
875 ,
876 ADC_InitStruct->Resolution
877 | ADC_InitStruct->LowPowerMode
878 );
879 #endif
880
881 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LSHIFT, ADC_InitStruct->LeftBitShift);
882 }
883 else
884 {
885 /* Initialization error: ADC instance is not disabled. */
886 status = ERROR;
887 }
888 return status;
889 }
890
891 /**
892 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
893 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
894 * whose fields will be set to default values.
895 * @retval None
896 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * ADC_InitStruct)897 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
898 {
899 /* Set ADC_InitStruct fields to default values */
900 /* Set fields of ADC instance */
901 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_16B;
902 ADC_InitStruct->LeftBitShift = LL_ADC_LEFT_BIT_SHIFT_NONE;
903 ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
904
905 }
906
907 /**
908 * @brief Initialize some features of ADC group regular.
909 * @note These parameters have an impact on ADC scope: ADC group regular.
910 * Refer to corresponding unitary functions into
911 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
912 * (functions with prefix "REG").
913 * @note The setting of these parameters by function @ref LL_ADC_Init()
914 * is conditioned to ADC state:
915 * ADC instance must be disabled.
916 * This condition is applied to all ADC features, for efficiency
917 * and compatibility over all STM32 families. However, the different
918 * features can be set under different ADC state conditions
919 * (setting possible with ADC enabled without conversion on going,
920 * ADC enabled with conversion on going, ...)
921 * Each feature can be updated afterwards with a unitary function
922 * and potentially with ADC in a different state than disabled,
923 * refer to description of each function for setting
924 * conditioned to ADC state.
925 * @note After using this function, other features must be configured
926 * using LL unitary functions.
927 * The minimum configuration remaining to be done is:
928 * - Set ADC group regular or group injected sequencer:
929 * map channel on the selected sequencer rank.
930 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
931 * - Set ADC channel sampling time
932 * Refer to function LL_ADC_SetChannelSamplingTime();
933 * @param ADCx ADC instance
934 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
935 * @retval An ErrorStatus enumeration value:
936 * - SUCCESS: ADC registers are initialized
937 * - ERROR: ADC registers are not initialized
938 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)939 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
940 {
941 ErrorStatus status = SUCCESS;
942
943 /* Check the parameters */
944 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
945 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
946 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
947 if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
948 {
949 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
950
951 /* ADC group regular continuous mode and discontinuous mode */
952 /* can not be enabled simultenaeously */
953 assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
954 || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
955 }
956 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
957 assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(ADC_REG_InitStruct->DataTransferMode));
958 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
959
960 /* Note: Hardware constraint (refer to description of this function): */
961 /* ADC instance must be disabled. */
962 if (LL_ADC_IsEnabled(ADCx) == 0UL)
963 {
964 /* Configuration of ADC hierarchical scope: */
965 /* - ADC group regular */
966 /* - Set ADC group regular trigger source */
967 /* - Set ADC group regular sequencer length */
968 /* - Set ADC group regular sequencer discontinuous mode */
969 /* - Set ADC group regular continuous mode */
970 /* - Set ADC group regular conversion data transfer: no transfer or */
971 /* transfer by DMA, and DMA requests mode */
972 /* - Set ADC group regular overrun behavior */
973 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
974 /* setting of trigger source to SW start. */
975 if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
976 {
977 MODIFY_REG(ADCx->CFGR,
978 ADC_CFGR_EXTSEL
979 | ADC_CFGR_EXTEN
980 | ADC_CFGR_DISCEN
981 | ADC_CFGR_DISCNUM
982 | ADC_CFGR_CONT
983 | ADC_CFGR_DMNGT
984 | ADC_CFGR_OVRMOD
985 ,
986 ADC_REG_InitStruct->TriggerSource
987 | ADC_REG_InitStruct->SequencerDiscont
988 | ADC_REG_InitStruct->ContinuousMode
989 | ADC_REG_InitStruct->DataTransferMode
990 | ADC_REG_InitStruct->Overrun
991 );
992 }
993 else
994 {
995 MODIFY_REG(ADCx->CFGR,
996 ADC_CFGR_EXTSEL
997 | ADC_CFGR_EXTEN
998 | ADC_CFGR_DISCEN
999 | ADC_CFGR_DISCNUM
1000 | ADC_CFGR_CONT
1001 | ADC_CFGR_DMNGT
1002 | ADC_CFGR_OVRMOD
1003 ,
1004 ADC_REG_InitStruct->TriggerSource
1005 | LL_ADC_REG_SEQ_DISCONT_DISABLE
1006 | ADC_REG_InitStruct->ContinuousMode
1007 | ADC_REG_InitStruct->DataTransferMode
1008 | ADC_REG_InitStruct->Overrun
1009 );
1010 }
1011
1012 /* Set ADC group regular sequencer length and scan direction */
1013 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
1014 }
1015 else
1016 {
1017 /* Initialization error: ADC instance is not disabled. */
1018 status = ERROR;
1019 }
1020 return status;
1021 }
1022
1023 /**
1024 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
1025 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1026 * whose fields will be set to default values.
1027 * @retval None
1028 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)1029 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
1030 {
1031 /* Set ADC_REG_InitStruct fields to default values */
1032 /* Set fields of ADC group regular */
1033 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
1034 /* setting of trigger source to SW start. */
1035 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
1036 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
1037 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
1038 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
1039 ADC_REG_InitStruct->DataTransferMode = LL_ADC_REG_DR_TRANSFER;
1040 ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
1041 }
1042
1043 /**
1044 * @brief Initialize some features of ADC group injected.
1045 * @note These parameters have an impact on ADC scope: ADC group injected.
1046 * Refer to corresponding unitary functions into
1047 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
1048 * (functions with prefix "INJ").
1049 * @note The setting of these parameters by function @ref LL_ADC_Init()
1050 * is conditioned to ADC state:
1051 * ADC instance must be disabled.
1052 * This condition is applied to all ADC features, for efficiency
1053 * and compatibility over all STM32 families. However, the different
1054 * features can be set under different ADC state conditions
1055 * (setting possible with ADC enabled without conversion on going,
1056 * ADC enabled with conversion on going, ...)
1057 * Each feature can be updated afterwards with a unitary function
1058 * and potentially with ADC in a different state than disabled,
1059 * refer to description of each function for setting
1060 * conditioned to ADC state.
1061 * @note After using this function, other features must be configured
1062 * using LL unitary functions.
1063 * The minimum configuration remaining to be done is:
1064 * - Set ADC group injected sequencer:
1065 * map channel on the selected sequencer rank.
1066 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
1067 * - Set ADC channel sampling time
1068 * Refer to function LL_ADC_SetChannelSamplingTime();
1069 * @param ADCx ADC instance
1070 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1071 * @retval An ErrorStatus enumeration value:
1072 * - SUCCESS: ADC registers are initialized
1073 * - ERROR: ADC registers are not initialized
1074 */
LL_ADC_INJ_Init(ADC_TypeDef * ADCx,LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct)1075 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1076 {
1077 ErrorStatus status = SUCCESS;
1078
1079 /* Check the parameters */
1080 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1081 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
1082 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
1083 if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
1084 {
1085 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
1086 }
1087 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
1088
1089 /* Note: Hardware constraint (refer to description of this function): */
1090 /* ADC instance must be disabled. */
1091 if (LL_ADC_IsEnabled(ADCx) == 0UL)
1092 {
1093 /* Configuration of ADC hierarchical scope: */
1094 /* - ADC group injected */
1095 /* - Set ADC group injected trigger source */
1096 /* - Set ADC group injected sequencer length */
1097 /* - Set ADC group injected sequencer discontinuous mode */
1098 /* - Set ADC group injected conversion trigger: independent or */
1099 /* from ADC group regular */
1100 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
1101 /* setting of trigger source to SW start. */
1102 if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1103 {
1104 MODIFY_REG(ADCx->CFGR,
1105 ADC_CFGR_JDISCEN
1106 | ADC_CFGR_JAUTO
1107 ,
1108 ADC_INJ_InitStruct->SequencerDiscont
1109 | ADC_INJ_InitStruct->TrigAuto
1110 );
1111 }
1112 else
1113 {
1114 MODIFY_REG(ADCx->CFGR,
1115 ADC_CFGR_JDISCEN
1116 | ADC_CFGR_JAUTO
1117 ,
1118 LL_ADC_REG_SEQ_DISCONT_DISABLE
1119 | ADC_INJ_InitStruct->TrigAuto
1120 );
1121 }
1122
1123 MODIFY_REG(ADCx->JSQR,
1124 ADC_JSQR_JEXTSEL
1125 | ADC_JSQR_JEXTEN
1126 | ADC_JSQR_JL
1127 ,
1128 ADC_INJ_InitStruct->TriggerSource
1129 | ADC_INJ_InitStruct->SequencerLength
1130 );
1131 }
1132 else
1133 {
1134 /* Initialization error: ADC instance is not disabled. */
1135 status = ERROR;
1136 }
1137 return status;
1138 }
1139
1140 /**
1141 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
1142 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1143 * whose fields will be set to default values.
1144 * @retval None
1145 */
LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct)1146 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1147 {
1148 /* Set ADC_INJ_InitStruct fields to default values */
1149 /* Set fields of ADC group injected */
1150 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
1151 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
1152 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
1153 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
1154 }
1155
1156 /**
1157 * @}
1158 */
1159
1160 /**
1161 * @}
1162 */
1163
1164 /**
1165 * @}
1166 */
1167
1168 #endif /* ADC1 || ADC2 || ADC3 */
1169
1170 /**
1171 * @}
1172 */
1173
1174 #endif /* USE_FULL_LL_DRIVER */
1175
1176
