1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_rcc.c
4 * @author MCD Application Team
5 * @brief RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Reset and Clock Control (RCC) peripheral:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 *
11 @verbatim
12 ==============================================================================
13 ##### RCC specific features #####
14 ==============================================================================
15 [..]
16 After reset the device is running from Internal High Speed oscillator
17 (HSI 64MHz) with Flash 0 wait state,and all peripherals are off except
18 internal SRAM, Flash, JTAG and PWR
19 (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses;
20 all peripherals mapped on these buses are running at HSI speed.
21 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
22 (+) All GPIOs are in analogue mode , except the JTAG pins which
23 are assigned to be used for debug purpose.
24
25 [..]
26 Once the device started from reset, the user application has to:
27 (+) Configure the clock source to be used to drive the System clock
28 (if the application needs higher frequency/performance)
29 (+) Configure the System clock frequency and Flash settings
30 (+) Configure the AHB and APB buses pre-scalers
31 (+) Enable the clock for the peripheral(s) to be used
32 (+) Configure the clock kernel source(s) for peripherals which clocks are not
33 derived from the System clock through :RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R
34 and RCC_D3CCIPR registers
35
36 ##### RCC Limitations #####
37 ==============================================================================
38 [..]
39 A delay between an RCC peripheral clock enable and the effective peripheral
40 enabling should be taken into account in order to manage the peripheral read/write
41 from/to registers.
42 (+) This delay depends on the peripheral mapping.
43 (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
44 after the clock enable bit is set on the hardware register
45 (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
46 after the clock enable bit is set on the hardware register
47
48 [..]
49 Implemented Workaround:
50 (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
51 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
52
53 @endverbatim
54 ******************************************************************************
55 * @attention
56 *
57 * Copyright (c) 2017 STMicroelectronics.
58 * All rights reserved.
59 *
60 * This software is licensed under terms that can be found in the LICENSE file in
61 * the root directory of this software component.
62 * If no LICENSE file comes with this software, it is provided AS-IS.
63 ******************************************************************************
64 */
65
66 /* Includes ------------------------------------------------------------------*/
67 #include "stm32h7xx_hal.h"
68
69 /** @addtogroup STM32H7xx_HAL_Driver
70 * @{
71 */
72
73 /** @defgroup RCC RCC
74 * @brief RCC HAL module driver
75 * @{
76 */
77
78 #ifdef HAL_RCC_MODULE_ENABLED
79
80 /* Private typedef -----------------------------------------------------------*/
81 /* Private define ------------------------------------------------------------*/
82 /* Private macro -------------------------------------------------------------*/
83 /** @defgroup RCC_Private_Macros RCC Private Macros
84 * @{
85 */
86 #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
87 #define MCO1_GPIO_PORT GPIOA
88 #define MCO1_PIN GPIO_PIN_8
89
90 #define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
91 #define MCO2_GPIO_PORT GPIOC
92 #define MCO2_PIN GPIO_PIN_9
93
94 /**
95 * @}
96 */
97 /* Private variables ---------------------------------------------------------*/
98 /** @defgroup RCC_Private_Variables RCC Private Variables
99 * @{
100 */
101
102 /**
103 * @}
104 */
105 /* Private function prototypes -----------------------------------------------*/
106 /* Exported functions --------------------------------------------------------*/
107
108 /** @defgroup RCC_Exported_Functions RCC Exported Functions
109 * @{
110 */
111
112 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
113 * @brief Initialization and Configuration functions
114 *
115 @verbatim
116 ===============================================================================
117 ##### Initialization and de-initialization functions #####
118 ===============================================================================
119 [..]
120 This section provides functions allowing to configure the internal/external oscillators
121 (HSE, HSI, LSE,CSI, LSI,HSI48, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB3, AHB1
122 AHB2,AHB4,APB3, APB1L, APB1H, APB2, and APB4).
123
124 [..] Internal/external clock and PLL configuration
125 (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through
126 the PLL as System clock source.
127 (#) CSI is a low-power RC oscillator which can be used directly as system clock, peripheral
128 clock, or PLL input.But even with frequency calibration, is less accurate than an
129 external crystal oscillator or ceramic resonator.
130 (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
131 clock source.
132
133 (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or
134 through the PLL as System clock source. Can be used also as RTC clock source.
135
136 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
137
138 (#) PLL , The RCC features three independent PLLs (clocked by HSI , HSE or CSI),
139 featuring three different output clocks and able to work either in integer or Fractional mode.
140 (++) A main PLL, PLL1, which is generally used to provide clocks to the CPU
141 and to some peripherals.
142 (++) Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for peripherals.
143
144
145 (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
146 (HSE used directly or through PLL as System clock source), the System clock
147 is automatically switched to HSI and an interrupt is generated if enabled.
148 The interrupt is linked to the Cortex-M NMI (Non-Mask-able Interrupt)
149 exception vector.
150
151 (#) MCO1 (micro controller clock output), used to output HSI, LSE, HSE, PLL1(PLL1_Q)
152 or HSI48 clock (through a configurable pre-scaler) on PA8 pin.
153
154 (#) MCO2 (micro controller clock output), used to output HSE, PLL2(PLL2_P), SYSCLK,
155 LSI, CSI, or PLL1(PLL1_P) clock (through a configurable pre-scaler) on PC9 pin.
156
157 [..] System, AHB and APB buses clocks configuration
158 (#) Several clock sources can be used to drive the System clock (SYSCLK): CSI,HSI,
159 HSE and PLL.
160 The AHB clock (HCLK) is derived from System core clock through configurable
161 pre-scaler and used to clock the CPU, memory and peripherals mapped
162 on AHB and APB bus of the 3 Domains (D1, D2, D3)* through configurable pre-scalers
163 and used to clock the peripherals mapped on these buses. You can use
164 "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency.
165
166 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except those
167 with dual clock domain where kernel source clock could be selected through
168 RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R and RCC_D3CCIPR registers.
169
170 (*) : 2 Domains (CD and SRD) for stm32h7a3xx and stm32h7b3xx family lines.
171 @endverbatim
172 * @{
173 */
174
175 /**
176 * @brief Resets the RCC clock configuration to the default reset state.
177 * @note The default reset state of the clock configuration is given below:
178 * - HSI ON and used as system clock source
179 * - HSE, PLL1, PLL2 and PLL3 OFF
180 * - AHB, APB Bus pre-scaler set to 1.
181 * - CSS, MCO1 and MCO2 OFF
182 * - All interrupts disabled
183 * @note This function doesn't modify the configuration of the
184 * - Peripheral clocks
185 * - LSI, LSE and RTC clocks
186 * @retval HAL status
187 */
HAL_RCC_DeInit(void)188 HAL_StatusTypeDef HAL_RCC_DeInit(void)
189 {
190 uint32_t tickstart;
191
192 /* Increasing the CPU frequency */
193 if (FLASH_LATENCY_DEFAULT > __HAL_FLASH_GET_LATENCY())
194 {
195 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
196 __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
197
198 /* Check that the new number of wait states is taken into account to access the Flash
199 memory by reading the FLASH_ACR register */
200 if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
201 {
202 return HAL_ERROR;
203 }
204
205 }
206
207
208 /* Get Start Tick */
209 tickstart = HAL_GetTick();
210
211 /* Set HSION bit */
212 SET_BIT(RCC->CR, RCC_CR_HSION);
213
214 /* Wait till HSI is ready */
215 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
216 {
217 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
218 {
219 return HAL_TIMEOUT;
220 }
221 }
222
223 /* Set HSITRIM[6:0] bits to the reset value */
224 SET_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM_6);
225
226 /* Reset CFGR register */
227 CLEAR_REG(RCC->CFGR);
228
229 /* Update the SystemCoreClock and SystemD2Clock global variables */
230 SystemCoreClock = HSI_VALUE;
231 SystemD2Clock = HSI_VALUE;
232
233 /* Adapt Systick interrupt period */
234 if (HAL_InitTick(uwTickPrio) != HAL_OK)
235 {
236 return HAL_ERROR;
237 }
238
239 /* Get Start Tick */
240 tickstart = HAL_GetTick();
241
242 /* Wait till clock switch is ready */
243 while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U)
244 {
245 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
246 {
247 return HAL_TIMEOUT;
248 }
249 }
250
251 /* Get Start Tick */
252 tickstart = HAL_GetTick();
253
254 /* Reset CSION, CSIKERON, HSEON, HSI48ON, HSECSSON, HSIDIV bits */
255 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON | RCC_CR_HSIDIV | RCC_CR_HSIDIVF | RCC_CR_CSION | RCC_CR_CSIKERON \
256 | RCC_CR_HSI48ON | RCC_CR_CSSHSEON);
257
258 /* Wait till HSE is disabled */
259 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
260 {
261 if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
262 {
263 return HAL_TIMEOUT;
264 }
265 }
266
267 /* Get Start Tick */
268 tickstart = HAL_GetTick();
269
270 /* Clear PLLON bit */
271 CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
272
273 /* Wait till PLL is disabled */
274 while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U)
275 {
276 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
277 {
278 return HAL_TIMEOUT;
279 }
280 }
281
282 /* Get Start Tick */
283 tickstart = HAL_GetTick();
284
285 /* Reset PLL2ON bit */
286 CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
287
288 /* Wait till PLL2 is disabled */
289 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
290 {
291 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
292 {
293 return HAL_TIMEOUT;
294 }
295 }
296
297 /* Get Start Tick */
298 tickstart = HAL_GetTick();
299
300 /* Reset PLL3 bit */
301 CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
302
303 /* Wait till PLL3 is disabled */
304 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
305 {
306 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
307 {
308 return HAL_TIMEOUT;
309 }
310 }
311
312 #if defined(RCC_D1CFGR_HPRE)
313 /* Reset D1CFGR register */
314 CLEAR_REG(RCC->D1CFGR);
315
316 /* Reset D2CFGR register */
317 CLEAR_REG(RCC->D2CFGR);
318
319 /* Reset D3CFGR register */
320 CLEAR_REG(RCC->D3CFGR);
321 #else
322 /* Reset CDCFGR1 register */
323 CLEAR_REG(RCC->CDCFGR1);
324
325 /* Reset CDCFGR2 register */
326 CLEAR_REG(RCC->CDCFGR2);
327
328 /* Reset SRDCFGR register */
329 CLEAR_REG(RCC->SRDCFGR);
330 #endif
331
332 /* Reset PLLCKSELR register to default value */
333 RCC->PLLCKSELR = RCC_PLLCKSELR_DIVM1_5 | RCC_PLLCKSELR_DIVM2_5 | RCC_PLLCKSELR_DIVM3_5;
334
335 /* Reset PLLCFGR register to default value */
336 WRITE_REG(RCC->PLLCFGR, 0x01FF0000U);
337
338 /* Reset PLL1DIVR register to default value */
339 WRITE_REG(RCC->PLL1DIVR, 0x01010280U);
340
341 /* Reset PLL1FRACR register */
342 CLEAR_REG(RCC->PLL1FRACR);
343
344 /* Reset PLL2DIVR register to default value */
345 WRITE_REG(RCC->PLL2DIVR, 0x01010280U);
346
347 /* Reset PLL2FRACR register */
348 CLEAR_REG(RCC->PLL2FRACR);
349
350 /* Reset PLL3DIVR register to default value */
351 WRITE_REG(RCC->PLL3DIVR, 0x01010280U);
352
353 /* Reset PLL3FRACR register */
354 CLEAR_REG(RCC->PLL3FRACR);
355
356 #if defined(RCC_CR_HSEEXT)
357 /* Reset HSEEXT */
358 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);
359 #endif /* RCC_CR_HSEEXT */
360
361 /* Reset HSEBYP bit */
362 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
363
364 /* Disable all interrupts */
365 CLEAR_REG(RCC->CIER);
366
367 /* Clear all interrupts flags */
368 WRITE_REG(RCC->CICR, 0xFFFFFFFFU);
369
370 /* Reset all RSR flags */
371 SET_BIT(RCC->RSR, RCC_RSR_RMVF);
372
373 /* Decreasing the number of wait states because of lower CPU frequency */
374 if (FLASH_LATENCY_DEFAULT < __HAL_FLASH_GET_LATENCY())
375 {
376 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
377 __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
378
379 /* Check that the new number of wait states is taken into account to access the Flash
380 memory by reading the FLASH_ACR register */
381 if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
382 {
383 return HAL_ERROR;
384 }
385
386 }
387
388 return HAL_OK;
389 }
390
391 /**
392 * @brief Initializes the RCC Oscillators according to the specified parameters in the
393 * RCC_OscInitTypeDef.
394 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
395 * contains the configuration information for the RCC Oscillators.
396 * @note The PLL is not disabled when used as system clock.
397 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
398 * supported by this function. User should request a transition to LSE Off
399 * first and then LSE On or LSE Bypass.
400 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
401 * supported by this function. User should request a transition to HSE Off
402 * first and then HSE On or HSE Bypass.
403 * @retval HAL status
404 */
HAL_RCC_OscConfig(RCC_OscInitTypeDef * RCC_OscInitStruct)405 __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
406 {
407 uint32_t tickstart;
408 uint32_t temp1_pllckcfg, temp2_pllckcfg;
409
410 /* Check Null pointer */
411 if (RCC_OscInitStruct == NULL)
412 {
413 return HAL_ERROR;
414 }
415
416 /* Check the parameters */
417 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
418 /*------------------------------- HSE Configuration ------------------------*/
419 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
420 {
421 /* Check the parameters */
422 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
423
424 const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
425 const uint32_t temp_pllckselr = RCC->PLLCKSELR;
426 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
427 if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
428 {
429 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
430 {
431 return HAL_ERROR;
432 }
433 }
434 else
435 {
436 /* Set the new HSE configuration ---------------------------------------*/
437 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
438
439 /* Check the HSE State */
440 if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
441 {
442 /* Get Start Tick*/
443 tickstart = HAL_GetTick();
444
445 /* Wait till HSE is ready */
446 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
447 {
448 if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
449 {
450 return HAL_TIMEOUT;
451 }
452 }
453 }
454 else
455 {
456 /* Get Start Tick*/
457 tickstart = HAL_GetTick();
458
459 /* Wait till HSE is disabled */
460 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
461 {
462 if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
463 {
464 return HAL_TIMEOUT;
465 }
466 }
467 }
468 }
469 }
470 /*----------------------------- HSI Configuration --------------------------*/
471 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
472 {
473 /* Check the parameters */
474 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
475 assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
476
477 /* When the HSI is used as system clock it will not be disabled */
478 const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
479 const uint32_t temp_pllckselr = RCC->PLLCKSELR;
480 if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
481 {
482 /* When HSI is used as system clock it will not be disabled */
483 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
484 {
485 return HAL_ERROR;
486 }
487 /* Otherwise, only HSI division and calibration are allowed */
488 else
489 {
490 /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */
491 __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
492
493 /* Get Start Tick*/
494 tickstart = HAL_GetTick();
495
496 /* Wait till HSI is ready */
497 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
498 {
499 if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
500 {
501 return HAL_TIMEOUT;
502 }
503 }
504 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
505 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
506 }
507 }
508
509 else
510 {
511 /* Check the HSI State */
512 if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
513 {
514 /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
515 __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
516
517 /* Get Start Tick*/
518 tickstart = HAL_GetTick();
519
520 /* Wait till HSI is ready */
521 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
522 {
523 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
524 {
525 return HAL_TIMEOUT;
526 }
527 }
528
529 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
530 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
531 }
532 else
533 {
534 /* Disable the Internal High Speed oscillator (HSI). */
535 __HAL_RCC_HSI_DISABLE();
536
537 /* Get Start Tick*/
538 tickstart = HAL_GetTick();
539
540 /* Wait till HSI is disabled */
541 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
542 {
543 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
544 {
545 return HAL_TIMEOUT;
546 }
547 }
548 }
549 }
550 }
551 /*----------------------------- CSI Configuration --------------------------*/
552 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
553 {
554 /* Check the parameters */
555 assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState));
556 assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue));
557
558 /* When the CSI is used as system clock it will not disabled */
559 const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
560 const uint32_t temp_pllckselr = RCC->PLLCKSELR;
561 if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
562 {
563 /* When CSI is used as system clock it will not disabled */
564 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
565 {
566 return HAL_ERROR;
567 }
568 /* Otherwise, just the calibration is allowed */
569 else
570 {
571 /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
572 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
573 }
574 }
575 else
576 {
577 /* Check the CSI State */
578 if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF)
579 {
580 /* Enable the Internal High Speed oscillator (CSI). */
581 __HAL_RCC_CSI_ENABLE();
582
583 /* Get Start Tick*/
584 tickstart = HAL_GetTick();
585
586 /* Wait till CSI is ready */
587 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
588 {
589 if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
590 {
591 return HAL_TIMEOUT;
592 }
593 }
594
595 /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
596 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
597 }
598 else
599 {
600 /* Disable the Internal High Speed oscillator (CSI). */
601 __HAL_RCC_CSI_DISABLE();
602
603 /* Get Start Tick*/
604 tickstart = HAL_GetTick();
605
606 /* Wait till CSI is disabled */
607 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
608 {
609 if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
610 {
611 return HAL_TIMEOUT;
612 }
613 }
614 }
615 }
616 }
617 /*------------------------------ LSI Configuration -------------------------*/
618 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
619 {
620 /* Check the parameters */
621 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
622
623 /* Check the LSI State */
624 if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
625 {
626 /* Enable the Internal Low Speed oscillator (LSI). */
627 __HAL_RCC_LSI_ENABLE();
628
629 /* Get Start Tick*/
630 tickstart = HAL_GetTick();
631
632 /* Wait till LSI is ready */
633 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
634 {
635 if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
636 {
637 return HAL_TIMEOUT;
638 }
639 }
640 }
641 else
642 {
643 /* Disable the Internal Low Speed oscillator (LSI). */
644 __HAL_RCC_LSI_DISABLE();
645
646 /* Get Start Tick*/
647 tickstart = HAL_GetTick();
648
649 /* Wait till LSI is ready */
650 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
651 {
652 if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
653 {
654 return HAL_TIMEOUT;
655 }
656 }
657 }
658 }
659
660 /*------------------------------ HSI48 Configuration -------------------------*/
661 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
662 {
663 /* Check the parameters */
664 assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
665
666 /* Check the HSI48 State */
667 if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF)
668 {
669 /* Enable the Internal Low Speed oscillator (HSI48). */
670 __HAL_RCC_HSI48_ENABLE();
671
672 /* Get time-out */
673 tickstart = HAL_GetTick();
674
675 /* Wait till HSI48 is ready */
676 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
677 {
678 if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
679 {
680 return HAL_TIMEOUT;
681 }
682 }
683 }
684 else
685 {
686 /* Disable the Internal Low Speed oscillator (HSI48). */
687 __HAL_RCC_HSI48_DISABLE();
688
689 /* Get time-out */
690 tickstart = HAL_GetTick();
691
692 /* Wait till HSI48 is ready */
693 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
694 {
695 if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
696 {
697 return HAL_TIMEOUT;
698 }
699 }
700 }
701 }
702 /*------------------------------ LSE Configuration -------------------------*/
703 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
704 {
705 /* Check the parameters */
706 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
707
708 /* Enable write access to Backup domain */
709 PWR->CR1 |= PWR_CR1_DBP;
710
711 /* Wait for Backup domain Write protection disable */
712 tickstart = HAL_GetTick();
713
714 while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
715 {
716 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
717 {
718 return HAL_TIMEOUT;
719 }
720 }
721
722 /* Set the new LSE configuration -----------------------------------------*/
723 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
724 /* Check the LSE State */
725 if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
726 {
727 /* Get Start Tick*/
728 tickstart = HAL_GetTick();
729
730 /* Wait till LSE is ready */
731 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
732 {
733 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
734 {
735 return HAL_TIMEOUT;
736 }
737 }
738 }
739 else
740 {
741 /* Get Start Tick*/
742 tickstart = HAL_GetTick();
743
744 /* Wait till LSE is disabled */
745 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
746 {
747 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
748 {
749 return HAL_TIMEOUT;
750 }
751 }
752 }
753 }
754 /*-------------------------------- PLL Configuration -----------------------*/
755 /* Check the parameters */
756 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
757 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
758 {
759 /* Check if the PLL is used as system clock or not */
760 if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
761 {
762 if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
763 {
764 /* Check the parameters */
765 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
766 assert_param(IS_RCC_PLLRGE_VALUE(RCC_OscInitStruct->PLL.PLLRGE));
767 assert_param(IS_RCC_PLLVCO_VALUE(RCC_OscInitStruct->PLL.PLLVCOSEL));
768 assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
769 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
770 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
771 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
772 assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
773 assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));
774
775 /* Disable the main PLL. */
776 __HAL_RCC_PLL_DISABLE();
777
778 /* Get Start Tick*/
779 tickstart = HAL_GetTick();
780
781 /* Wait till PLL is disabled */
782 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
783 {
784 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
785 {
786 return HAL_TIMEOUT;
787 }
788 }
789
790 /* Configure the main PLL clock source, multiplication and division factors. */
791 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
792 RCC_OscInitStruct->PLL.PLLM,
793 RCC_OscInitStruct->PLL.PLLN,
794 RCC_OscInitStruct->PLL.PLLP,
795 RCC_OscInitStruct->PLL.PLLQ,
796 RCC_OscInitStruct->PLL.PLLR);
797
798 /* Disable PLLFRACN . */
799 __HAL_RCC_PLLFRACN_DISABLE();
800
801 /* Configure PLL PLL1FRACN */
802 __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
803
804 /* Select PLL1 input reference frequency range: VCI */
805 __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;
806
807 /* Select PLL1 output frequency range : VCO */
808 __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;
809
810 /* Enable PLL System Clock output. */
811 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
812
813 /* Enable PLL1Q Clock output. */
814 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
815
816 /* Enable PLL1R Clock output. */
817 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
818
819 /* Enable PLL1FRACN . */
820 __HAL_RCC_PLLFRACN_ENABLE();
821
822 /* Enable the main PLL. */
823 __HAL_RCC_PLL_ENABLE();
824
825 /* Get Start Tick*/
826 tickstart = HAL_GetTick();
827
828 /* Wait till PLL is ready */
829 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
830 {
831 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
832 {
833 return HAL_TIMEOUT;
834 }
835 }
836 }
837 else
838 {
839 /* Disable the main PLL. */
840 __HAL_RCC_PLL_DISABLE();
841
842 /* Get Start Tick*/
843 tickstart = HAL_GetTick();
844
845 /* Wait till PLL is disabled */
846 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
847 {
848 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
849 {
850 return HAL_TIMEOUT;
851 }
852 }
853 }
854 }
855 else
856 {
857 /* Do not return HAL_ERROR if request repeats the current configuration */
858 temp1_pllckcfg = RCC->PLLCKSELR;
859 temp2_pllckcfg = RCC->PLL1DIVR;
860 if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
861 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
862 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
863 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
864 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
865 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
866 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
867 {
868 return HAL_ERROR;
869 }
870 else
871 {
872 /* Check if only fractional part needs to be updated */
873 temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos);
874 if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg)
875 {
876 assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));
877 /* Disable PLL1FRACEN */
878 __HAL_RCC_PLLFRACN_DISABLE();
879 /* Get Start Tick*/
880 tickstart = HAL_GetTick();
881 /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */
882 while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE)
883 {
884 }
885 /* Configure PLL1 PLL1FRACN */
886 __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
887 /* Enable PLL1FRACEN to latch new value. */
888 __HAL_RCC_PLLFRACN_ENABLE();
889 }
890 }
891 }
892 }
893 return HAL_OK;
894 }
895
896 /**
897 * @brief Initializes the CPU, AHB and APB buses clocks according to the specified
898 * parameters in the RCC_ClkInitStruct.
899 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
900 * contains the configuration information for the RCC peripheral.
901 * @param FLatency: FLASH Latency, this parameter depend on device selected
902 *
903 * @note The SystemCoreClock CMSIS variable is used to store System Core Clock Frequency
904 * and updated by HAL_InitTick() function called within this function
905 *
906 * @note The HSI is used (enabled by hardware) as system clock source after
907 * start-up from Reset, wake-up from STOP and STANDBY mode, or in case
908 * of failure of the HSE used directly or indirectly as system clock
909 * (if the Clock Security System CSS is enabled).
910 *
911 * @note A switch from one clock source to another occurs only if the target
912 * clock source is ready (clock stable after start-up delay or PLL locked).
913 * If a clock source which is not yet ready is selected, the switch will
914 * occur when the clock source will be ready.
915 * You can use HAL_RCC_GetClockConfig() function to know which clock is
916 * currently used as system clock source.
917 * @note Depending on the device voltage range, the software has to set correctly
918 * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency
919 * (for more details refer to section above "Initialization/de-initialization functions")
920 * @retval None
921 */
HAL_RCC_ClockConfig(RCC_ClkInitTypeDef * RCC_ClkInitStruct,uint32_t FLatency)922 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
923 {
924 HAL_StatusTypeDef halstatus;
925 uint32_t tickstart;
926 uint32_t common_system_clock;
927
928 /* Check Null pointer */
929 if (RCC_ClkInitStruct == NULL)
930 {
931 return HAL_ERROR;
932 }
933
934 /* Check the parameters */
935 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
936 assert_param(IS_FLASH_LATENCY(FLatency));
937
938 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
939 must be correctly programmed according to the frequency of the CPU clock
940 (HCLK) and the supply voltage of the device. */
941
942 /* Increasing the CPU frequency */
943 if (FLatency > __HAL_FLASH_GET_LATENCY())
944 {
945 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
946 __HAL_FLASH_SET_LATENCY(FLatency);
947
948 /* Check that the new number of wait states is taken into account to access the Flash
949 memory by reading the FLASH_ACR register */
950 if (__HAL_FLASH_GET_LATENCY() != FLatency)
951 {
952 return HAL_ERROR;
953 }
954
955 }
956
957 /* Increasing the BUS frequency divider */
958 /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/
959 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
960 {
961 #if defined (RCC_D1CFGR_D1PPRE)
962 if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
963 {
964 assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
965 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
966 }
967 #else
968 if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
969 {
970 assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider));
971 MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
972 }
973 #endif
974 }
975
976 /*-------------------------- PCLK1 Configuration ---------------------------*/
977 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
978 {
979 #if defined (RCC_D2CFGR_D2PPRE1)
980 if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
981 {
982 assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
983 MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
984 }
985 #else
986 if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
987 {
988 assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
989 MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
990 }
991 #endif
992 }
993 /*-------------------------- PCLK2 Configuration ---------------------------*/
994 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
995 {
996 #if defined(RCC_D2CFGR_D2PPRE2)
997 if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
998 {
999 assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
1000 MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
1001 }
1002 #else
1003 if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
1004 {
1005 assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
1006 MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
1007 }
1008 #endif
1009 }
1010
1011 /*-------------------------- D3PCLK1 Configuration ---------------------------*/
1012 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
1013 {
1014 #if defined(RCC_D3CFGR_D3PPRE)
1015 if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
1016 {
1017 assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
1018 MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider));
1019 }
1020 #else
1021 if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
1022 {
1023 assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
1024 MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider));
1025 }
1026 #endif
1027 }
1028
1029 /*-------------------------- HCLK Configuration --------------------------*/
1030 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
1031 {
1032 #if defined (RCC_D1CFGR_HPRE)
1033 if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE))
1034 {
1035 /* Set the new HCLK clock divider */
1036 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
1037 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
1038 }
1039 #else
1040 if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
1041 {
1042 /* Set the new HCLK clock divider */
1043 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
1044 MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
1045 }
1046 #endif
1047 }
1048
1049 /*------------------------- SYSCLK Configuration -------------------------*/
1050 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
1051 {
1052 assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
1053 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
1054 #if defined(RCC_D1CFGR_D1CPRE)
1055 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
1056 #else
1057 MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider);
1058 #endif
1059 /* HSE is selected as System Clock Source */
1060 if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
1061 {
1062 /* Check the HSE ready flag */
1063 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
1064 {
1065 return HAL_ERROR;
1066 }
1067 }
1068 /* PLL is selected as System Clock Source */
1069 else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
1070 {
1071 /* Check the PLL ready flag */
1072 if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
1073 {
1074 return HAL_ERROR;
1075 }
1076 }
1077 /* CSI is selected as System Clock Source */
1078 else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
1079 {
1080 /* Check the PLL ready flag */
1081 if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
1082 {
1083 return HAL_ERROR;
1084 }
1085 }
1086 /* HSI is selected as System Clock Source */
1087 else
1088 {
1089 /* Check the HSI ready flag */
1090 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
1091 {
1092 return HAL_ERROR;
1093 }
1094 }
1095 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
1096
1097 /* Get Start Tick*/
1098 tickstart = HAL_GetTick();
1099
1100 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
1101 {
1102 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1103 {
1104 return HAL_TIMEOUT;
1105 }
1106 }
1107
1108 }
1109
1110 /* Decreasing the BUS frequency divider */
1111 /*-------------------------- HCLK Configuration --------------------------*/
1112 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
1113 {
1114 #if defined(RCC_D1CFGR_HPRE)
1115 if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE))
1116 {
1117 /* Set the new HCLK clock divider */
1118 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
1119 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
1120 }
1121 #else
1122 if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
1123 {
1124 /* Set the new HCLK clock divider */
1125 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
1126 MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
1127 }
1128 #endif
1129 }
1130
1131 /* Decreasing the number of wait states because of lower CPU frequency */
1132 if (FLatency < __HAL_FLASH_GET_LATENCY())
1133 {
1134 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
1135 __HAL_FLASH_SET_LATENCY(FLatency);
1136
1137 /* Check that the new number of wait states is taken into account to access the Flash
1138 memory by reading the FLASH_ACR register */
1139 if (__HAL_FLASH_GET_LATENCY() != FLatency)
1140 {
1141 return HAL_ERROR;
1142 }
1143 }
1144
1145 /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/
1146 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
1147 {
1148 #if defined(RCC_D1CFGR_D1PPRE)
1149 if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
1150 {
1151 assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
1152 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
1153 }
1154 #else
1155 if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
1156 {
1157 assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider));
1158 MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
1159 }
1160 #endif
1161 }
1162
1163 /*-------------------------- PCLK1 Configuration ---------------------------*/
1164 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
1165 {
1166 #if defined(RCC_D2CFGR_D2PPRE1)
1167 if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
1168 {
1169 assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
1170 MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
1171 }
1172 #else
1173 if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
1174 {
1175 assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
1176 MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
1177 }
1178 #endif
1179 }
1180
1181 /*-------------------------- PCLK2 Configuration ---------------------------*/
1182 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
1183 {
1184 #if defined (RCC_D2CFGR_D2PPRE2)
1185 if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
1186 {
1187 assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
1188 MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
1189 }
1190 #else
1191 if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
1192 {
1193 assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
1194 MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
1195 }
1196 #endif
1197 }
1198
1199 /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/
1200 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
1201 {
1202 #if defined(RCC_D3CFGR_D3PPRE)
1203 if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
1204 {
1205 assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
1206 MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider));
1207 }
1208 #else
1209 if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
1210 {
1211 assert_param(IS_RCC_SRDPCLK1(RCC_ClkInitStruct->APB4CLKDivider));
1212 MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider));
1213 }
1214 #endif
1215 }
1216
1217 /* Update the SystemCoreClock global variable */
1218 #if defined(RCC_D1CFGR_D1CPRE)
1219 common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
1220 #else
1221 common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
1222 #endif
1223
1224 #if defined(RCC_D1CFGR_HPRE)
1225 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
1226 #else
1227 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
1228 #endif
1229
1230 #if defined(DUAL_CORE) && defined(CORE_CM4)
1231 SystemCoreClock = SystemD2Clock;
1232 #else
1233 SystemCoreClock = common_system_clock;
1234 #endif /* DUAL_CORE && CORE_CM4 */
1235
1236 /* Configure the source of time base considering new system clocks settings*/
1237 halstatus = HAL_InitTick(uwTickPrio);
1238
1239 return halstatus;
1240 }
1241
1242 /**
1243 * @}
1244 */
1245
1246 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
1247 * @brief RCC clocks control functions
1248 *
1249 @verbatim
1250 ===============================================================================
1251 ##### Peripheral Control functions #####
1252 ===============================================================================
1253 [..]
1254 This subsection provides a set of functions allowing to control the RCC Clocks
1255 frequencies.
1256
1257 @endverbatim
1258 * @{
1259 */
1260
1261 /**
1262 * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
1263 * @note PA8/PC9 should be configured in alternate function mode.
1264 * @param RCC_MCOx: specifies the output direction for the clock source.
1265 * This parameter can be one of the following values:
1266 * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
1267 * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
1268 * @param RCC_MCOSource: specifies the clock source to output.
1269 * This parameter can be one of the following values:
1270 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
1271 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
1272 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
1273 * @arg RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source
1274 * @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source
1275 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
1276 * @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source
1277 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
1278 * @arg RCC_MCO2SOURCE_PLLCLK: PLL1P clock selected as MCO2 source
1279 * @arg RCC_MCO2SOURCE_CSICLK: CSI clock selected as MCO2 source
1280 * @arg RCC_MCO2SOURCE_LSICLK: LSI clock selected as MCO2 source
1281 * @param RCC_MCODiv: specifies the MCOx pre-scaler.
1282 * This parameter can be one of the following values:
1283 * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCOx clock
1284 * @retval None
1285 */
HAL_RCC_MCOConfig(uint32_t RCC_MCOx,uint32_t RCC_MCOSource,uint32_t RCC_MCODiv)1286 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
1287 {
1288 GPIO_InitTypeDef GPIO_InitStruct;
1289 /* Check the parameters */
1290 assert_param(IS_RCC_MCO(RCC_MCOx));
1291 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
1292 /* RCC_MCO1 */
1293 if (RCC_MCOx == RCC_MCO1)
1294 {
1295 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
1296
1297 /* MCO1 Clock Enable */
1298 MCO1_CLK_ENABLE();
1299
1300 /* Configure the MCO1 pin in alternate function mode */
1301 GPIO_InitStruct.Pin = MCO1_PIN;
1302 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
1303 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
1304 GPIO_InitStruct.Pull = GPIO_NOPULL;
1305 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
1306 HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
1307
1308 /* Mask MCO1 and MCO1PRE[3:0] bits then Select MCO1 clock source and pre-scaler */
1309 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
1310 }
1311 else
1312 {
1313 assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
1314
1315 /* MCO2 Clock Enable */
1316 MCO2_CLK_ENABLE();
1317
1318 /* Configure the MCO2 pin in alternate function mode */
1319 GPIO_InitStruct.Pin = MCO2_PIN;
1320 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
1321 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
1322 GPIO_InitStruct.Pull = GPIO_NOPULL;
1323 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
1324 HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
1325
1326 /* Mask MCO2 and MCO2PRE[3:0] bits then Select MCO2 clock source and pre-scaler */
1327 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 7U)));
1328 }
1329 }
1330
1331 /**
1332 * @brief Enables the Clock Security System.
1333 * @note If a failure is detected on the HSE oscillator clock, this oscillator
1334 * is automatically disabled and an interrupt is generated to inform the
1335 * software about the failure (Clock Security System Interrupt, CSSI),
1336 * allowing the MCU to perform rescue operations. The CSSI is linked to
1337 * the Cortex-M NMI (Non-Mask-able Interrupt) exception vector.
1338 * @retval None
1339 */
HAL_RCC_EnableCSS(void)1340 void HAL_RCC_EnableCSS(void)
1341 {
1342 SET_BIT(RCC->CR, RCC_CR_CSSHSEON) ;
1343 }
1344
1345 /**
1346 * @brief Disables the Clock Security System.
1347 * @retval None
1348 */
HAL_RCC_DisableCSS(void)1349 void HAL_RCC_DisableCSS(void)
1350 {
1351 CLEAR_BIT(RCC->CR, RCC_CR_CSSHSEON);
1352 }
1353
1354 /**
1355 * @brief Returns the SYSCLK frequency
1356 *
1357 * @note The system frequency computed by this function is not the real
1358 * frequency in the chip. It is calculated based on the predefined
1359 * constant and the selected clock source:
1360 * @note If SYSCLK source is CSI, function returns values based on CSI_VALUE(*)
1361 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
1362 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
1363 * @note If SYSCLK source is PLL, function returns values based on CSI_VALUE(*),
1364 * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
1365 * @note (*) CSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
1366 * 4 MHz) but the real value may vary depending on the variations
1367 * in voltage and temperature.
1368 * @note (**) HSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
1369 * 64 MHz) but the real value may vary depending on the variations
1370 * in voltage and temperature.
1371 * @note (***) HSE_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
1372 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
1373 * frequency of the crystal used. Otherwise, this function may
1374 * have wrong result.
1375 *
1376 * @note The result of this function could be not correct when using fractional
1377 * value for HSE crystal.
1378 *
1379 * @note This function can be used by the user application to compute the
1380 * baud rate for the communication peripherals or configure other parameters.
1381 *
1382 * @note Each time SYSCLK changes, this function must be called to update the
1383 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
1384 *
1385 *
1386 * @retval SYSCLK frequency
1387 */
HAL_RCC_GetSysClockFreq(void)1388 uint32_t HAL_RCC_GetSysClockFreq(void)
1389 {
1390 uint32_t pllp, pllsource, pllm, pllfracen, hsivalue;
1391 float_t fracn1, pllvco;
1392 uint32_t sysclockfreq;
1393
1394 /* Get SYSCLK source -------------------------------------------------------*/
1395
1396 switch (RCC->CFGR & RCC_CFGR_SWS)
1397 {
1398 case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
1399
1400 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
1401 {
1402 sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
1403 }
1404 else
1405 {
1406 sysclockfreq = (uint32_t) HSI_VALUE;
1407 }
1408
1409 break;
1410
1411 case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
1412 sysclockfreq = CSI_VALUE;
1413 break;
1414
1415 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
1416 sysclockfreq = HSE_VALUE;
1417 break;
1418
1419 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
1420
1421 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
1422 SYSCLK = PLL_VCO / PLLR
1423 */
1424 pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
1425 pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ;
1426 pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
1427 fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
1428
1429 if (pllm != 0U)
1430 {
1431 switch (pllsource)
1432 {
1433 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1434
1435 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
1436 {
1437 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
1438 pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
1439 }
1440 else
1441 {
1442 pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
1443 }
1444 break;
1445
1446 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */
1447 pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
1448 break;
1449
1450 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1451 pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
1452 break;
1453
1454 default:
1455 pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
1456 break;
1457 }
1458 pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ;
1459 sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp);
1460 }
1461 else
1462 {
1463 sysclockfreq = 0U;
1464 }
1465 break;
1466
1467 default:
1468 sysclockfreq = CSI_VALUE;
1469 break;
1470 }
1471
1472 return sysclockfreq;
1473 }
1474
1475
1476 /**
1477 * @brief Returns the HCLK frequency
1478 * @note Each time HCLK changes, this function must be called to update the
1479 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
1480 *
1481 * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency
1482 * and updated within this function
1483 * @retval HCLK frequency
1484 */
HAL_RCC_GetHCLKFreq(void)1485 uint32_t HAL_RCC_GetHCLKFreq(void)
1486 {
1487 uint32_t common_system_clock;
1488
1489 #if defined(RCC_D1CFGR_D1CPRE)
1490 common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
1491 #else
1492 common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
1493 #endif
1494
1495 #if defined(RCC_D1CFGR_HPRE)
1496 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
1497 #else
1498 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
1499 #endif
1500
1501 #if defined(DUAL_CORE) && defined(CORE_CM4)
1502 SystemCoreClock = SystemD2Clock;
1503 #else
1504 SystemCoreClock = common_system_clock;
1505 #endif /* DUAL_CORE && CORE_CM4 */
1506
1507 return SystemD2Clock;
1508 }
1509
1510
1511 /**
1512 * @brief Returns the PCLK1 frequency
1513 * @note Each time PCLK1 changes, this function must be called to update the
1514 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
1515 * @retval PCLK1 frequency
1516 */
HAL_RCC_GetPCLK1Freq(void)1517 uint32_t HAL_RCC_GetPCLK1Freq(void)
1518 {
1519 #if defined (RCC_D2CFGR_D2PPRE1)
1520 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
1521 return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));
1522 #else
1523 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
1524 return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU));
1525 #endif
1526 }
1527
1528
1529 /**
1530 * @brief Returns the D2 PCLK2 frequency
1531 * @note Each time PCLK2 changes, this function must be called to update the
1532 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
1533 * @retval PCLK1 frequency
1534 */
HAL_RCC_GetPCLK2Freq(void)1535 uint32_t HAL_RCC_GetPCLK2Freq(void)
1536 {
1537 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
1538 #if defined(RCC_D2CFGR_D2PPRE2)
1539 return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU));
1540 #else
1541 return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU));
1542 #endif
1543 }
1544
1545 /**
1546 * @brief Configures the RCC_OscInitStruct according to the internal
1547 * RCC configuration registers.
1548 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
1549 * will be configured.
1550 * @retval None
1551 */
HAL_RCC_GetOscConfig(RCC_OscInitTypeDef * RCC_OscInitStruct)1552 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
1553 {
1554 /* Set all possible values for the Oscillator type parameter ---------------*/
1555 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_CSI | \
1556 RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48;
1557
1558 /* Get the HSE configuration -----------------------------------------------*/
1559 #if defined(RCC_CR_HSEEXT)
1560 if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP)
1561 {
1562 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
1563 }
1564 else if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT))
1565 {
1566 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL;
1567 }
1568 else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
1569 {
1570 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
1571 }
1572 else
1573 {
1574 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
1575 }
1576 #else
1577 if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
1578 {
1579 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
1580 }
1581 else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
1582 {
1583 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
1584 }
1585 else
1586 {
1587 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
1588 }
1589 #endif /* RCC_CR_HSEEXT */
1590
1591 /* Get the CSI configuration -----------------------------------------------*/
1592 if ((RCC->CR & RCC_CR_CSION) == RCC_CR_CSION)
1593 {
1594 RCC_OscInitStruct->CSIState = RCC_CSI_ON;
1595 }
1596 else
1597 {
1598 RCC_OscInitStruct->CSIState = RCC_CSI_OFF;
1599 }
1600
1601 #if defined(RCC_VER_X)
1602 if (HAL_GetREVID() <= REV_ID_Y)
1603 {
1604 RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk) >> HAL_RCC_REV_Y_CSITRIM_Pos);
1605 }
1606 else
1607 {
1608 RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
1609 }
1610 #else
1611 RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
1612 #endif /*RCC_VER_X*/
1613
1614 /* Get the HSI configuration -----------------------------------------------*/
1615 if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
1616 {
1617 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
1618 }
1619 else
1620 {
1621 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
1622 }
1623
1624 #if defined(RCC_VER_X)
1625 if (HAL_GetREVID() <= REV_ID_Y)
1626 {
1627 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk) >> HAL_RCC_REV_Y_HSITRIM_Pos);
1628 }
1629 else
1630 {
1631 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
1632 }
1633 #else
1634 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
1635 #endif /*RCC_VER_X*/
1636
1637 /* Get the LSE configuration -----------------------------------------------*/
1638 #if defined(RCC_BDCR_LSEEXT)
1639 if ((RCC->BDCR & (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT)) == RCC_BDCR_LSEBYP)
1640 {
1641 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
1642 }
1643 else if ((RCC->BDCR & (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT)) == (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT))
1644 {
1645 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_DIGITAL;
1646 }
1647 else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
1648 {
1649 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
1650 }
1651 else
1652 {
1653 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
1654 }
1655 #else
1656 if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
1657 {
1658 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
1659 }
1660 else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
1661 {
1662 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
1663 }
1664 else
1665 {
1666 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
1667 }
1668 #endif /* RCC_BDCR_LSEEXT */
1669
1670 /* Get the LSI configuration -----------------------------------------------*/
1671 if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
1672 {
1673 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
1674 }
1675 else
1676 {
1677 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
1678 }
1679
1680 /* Get the HSI48 configuration ---------------------------------------------*/
1681 if ((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON)
1682 {
1683 RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
1684 }
1685 else
1686 {
1687 RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
1688 }
1689
1690 /* Get the PLL configuration -----------------------------------------------*/
1691 if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
1692 {
1693 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
1694 }
1695 else
1696 {
1697 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
1698 }
1699 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
1700 RCC_OscInitStruct->PLL.PLLM = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos);
1701 RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos) + 1U;
1702 RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) + 1U;
1703 RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) + 1U;
1704 RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) + 1U;
1705 RCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1RGE));
1706 RCC_OscInitStruct->PLL.PLLVCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1VCOSEL) >> RCC_PLLCFGR_PLL1VCOSEL_Pos);
1707 RCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos));
1708 }
1709
1710 /**
1711 * @brief Configures the RCC_ClkInitStruct according to the internal
1712 * RCC configuration registers.
1713 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
1714 * will be configured.
1715 * @param pFLatency: Pointer on the Flash Latency.
1716 * @retval None
1717 */
HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef * RCC_ClkInitStruct,uint32_t * pFLatency)1718 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
1719 {
1720 /* Set all possible values for the Clock type parameter --------------------*/
1721 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 |
1722 RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 ;
1723
1724 /* Get the SYSCLK configuration --------------------------------------------*/
1725 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
1726
1727 #if defined(RCC_D1CFGR_D1CPRE)
1728 /* Get the SYSCLK configuration ----------------------------------------------*/
1729 RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE);
1730
1731 /* Get the D1HCLK configuration ----------------------------------------------*/
1732 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE);
1733
1734 /* Get the APB3 configuration ----------------------------------------------*/
1735 RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE);
1736
1737 /* Get the APB1 configuration ----------------------------------------------*/
1738 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1);
1739
1740 /* Get the APB2 configuration ----------------------------------------------*/
1741 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2);
1742
1743 /* Get the APB4 configuration ----------------------------------------------*/
1744 RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE);
1745 #else
1746 /* Get the SYSCLK configuration ----------------------------------------------*/
1747 RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE);
1748
1749 /* Get the D1HCLK configuration ----------------------------------------------*/
1750 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE);
1751
1752 /* Get the APB3 configuration ----------------------------------------------*/
1753 RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE);
1754
1755 /* Get the APB1 configuration ----------------------------------------------*/
1756 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1);
1757
1758 /* Get the APB2 configuration ----------------------------------------------*/
1759 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2);
1760
1761 /* Get the APB4 configuration ----------------------------------------------*/
1762 RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE);
1763 #endif
1764
1765 /* Get the Flash Wait State (Latency) configuration ------------------------*/
1766 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
1767 }
1768
1769 /**
1770 * @brief This function handles the RCC CSS interrupt request.
1771 * @note This API should be called under the NMI_Handler().
1772 * @retval None
1773 */
HAL_RCC_NMI_IRQHandler(void)1774 void HAL_RCC_NMI_IRQHandler(void)
1775 {
1776 /* Check RCC CSSF flag */
1777 if (__HAL_RCC_GET_IT(RCC_IT_CSS))
1778 {
1779 /* RCC Clock Security System interrupt user callback */
1780 HAL_RCC_CSSCallback();
1781
1782 /* Clear RCC CSS pending bit */
1783 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
1784 }
1785 }
1786
1787 /**
1788 * @brief RCC Clock Security System interrupt callback
1789 * @retval none
1790 */
HAL_RCC_CSSCallback(void)1791 __weak void HAL_RCC_CSSCallback(void)
1792 {
1793 /* NOTE : This function Should not be modified, when the callback is needed,
1794 the HAL_RCC_CSSCallback could be implemented in the user file
1795 */
1796 }
1797
1798 /**
1799 * @}
1800 */
1801
1802 /**
1803 * @}
1804 */
1805
1806 #endif /* HAL_RCC_MODULE_ENABLED */
1807 /**
1808 * @}
1809 */
1810
1811 /**
1812 * @}
1813 */
1814
1815
