1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_hrtim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the High Resolution Timer (HRTIM) peripheral:
8 * + HRTIM Initialization
9 * + Timer Time Base Unit Configuration
10 * + Simple Time Base Start/Stop
11 * + Simple Time Base Start/Stop Interrupt
12 * + Simple Time Base Start/Stop DMA Request
13 * + Simple Output Compare/PWM Channel Configuration
14 * + Simple Output Compare/PWM Channel Start/Stop Interrupt
15 * + Simple Output Compare/PWM Channel Start/Stop DMA Request
16 * + Simple Input Capture Channel Configuration
17 * + Simple Input Capture Channel Start/Stop Interrupt
18 * + Simple Input Capture Channel Start/Stop DMA Request
19 * + Simple One Pulse Channel Configuration
20 * + Simple One Pulse Channel Start/Stop Interrupt
21 * + HRTIM External Synchronization Configuration
22 * + HRTIM Burst Mode Controller Configuration
23 * + HRTIM Burst Mode Controller Enabling
24 * + HRTIM External Events Conditioning Configuration
25 * + HRTIM Faults Conditioning Configuration
26 * + HRTIM Faults Enabling
27 * + HRTIM ADC trigger Configuration
28 * + Waveform Timer Configuration
29 * + Waveform Event Filtering Configuration
30 * + Waveform Dead Time Insertion Configuration
31 * + Waveform Chopper Mode Configuration
32 * + Waveform Compare Unit Configuration
33 * + Waveform Capture Unit Configuration
34 * + Waveform Output Configuration
35 * + Waveform Counter Start/Stop
36 * + Waveform Counter Start/Stop Interrupt
37 * + Waveform Counter Start/Stop DMA Request
38 * + Waveform Output Enabling
39 * + Waveform Output Level Set/Get
40 * + Waveform Output State Get
41 * + Waveform Burst DMA Operation Configuration
42 * + Waveform Burst DMA Operation Start
43 * + Waveform Timer Counter Software Reset
44 * + Waveform Capture Software Trigger
45 * + Waveform Burst Mode Controller Software Trigger
46 * + Waveform Timer Pre-loadable Registers Update Enabling
47 * + Waveform Timer Pre-loadable Registers Software Update
48 * + Waveform Timer Delayed Protection Status Get
49 * + Waveform Timer Burst Status Get
50 * + Waveform Timer Push-Pull Status Get
51 * + Peripheral State Get
52 *
53 ******************************************************************************
54 * @attention
55 *
56 * Copyright (c) 2017 STMicroelectronics.
57 * All rights reserved.
58 *
59 * This software is licensed under terms that can be found in the LICENSE file
60 * in the root directory of this software component.
61 * If no LICENSE file comes with this software, it is provided AS-IS.
62 *
63 ******************************************************************************
64 @verbatim
65 ==============================================================================
66 ##### Simple mode v.s. waveform mode #####
67 ==============================================================================
68 [..] The HRTIM HAL API is split into 2 categories:
69 (#)Simple functions: these functions allow for using a HRTIM timer as a
70 general purpose timer with high resolution capabilities.
71 HRTIM simple modes are managed through the set of functions named
72 HAL_HRTIM_Simple<Function>. These functions are similar in name and usage
73 to the one defined for the TIM peripheral. When a HRTIM timer operates in
74 simple mode, only a very limited set of HRTIM features are used.
75 Following simple modes are proposed:
76 (++)Output compare mode,
77 (++)PWM output mode,
78 (++)Input capture mode,
79 (++)One pulse mode.
80 (#)Waveform functions: These functions allow taking advantage of the HRTIM
81 flexibility to produce numerous types of control signal. When a HRTIM timer
82 operates in waveform mode, all the HRTIM features are accessible without
83 any restriction. HRTIM waveform modes are managed through the set of
84 functions named HAL_HRTIM_Waveform<Function>
85
86 ==============================================================================
87 ##### How to use this driver #####
88 ==============================================================================
89 [..]
90 (#)Initialize the HRTIM low level resources by implementing the
91 HAL_HRTIM_MspInit() function:
92 (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
93 (##)Connect HRTIM pins to MCU I/Os
94 (+++) Enable the clock for the HRTIM GPIOs using the following
95 function: __HAL_RCC_GPIOx_CLK_ENABLE()
96 (+++) Configure these GPIO pins in Alternate Function mode using
97 HAL_GPIO_Init()
98 (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
99 (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
100 (+++)Initialize the DMA handle
101 (+++)Associate the initialized DMA handle to the appropriate DMA
102 handle of the HRTIM handle using __HAL_LINKDMA()
103 (+++)Initialize the DMA channel using HAL_DMA_Init()
104 (+++)Configure the priority and enable the NVIC for the transfer
105 complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
106 and HAL_NVIC_EnableIRQ()
107 (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
108 (+++)Configure the priority and enable the NVIC for the concerned
109 HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
110
111 (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
112 structure (field of the HRTIM handle) specifies which global interrupt of
113 whole HRTIM must be enabled (Burst mode period, System fault, Faults).
114 It also contains the HRTIM external synchronization configuration. HRTIM
115 can act as a master (generating a synchronization signal) or as a slave
116 (waiting for a trigger to be synchronized).
117
118 (#) Configure HRTIM resources shared by all HRTIM timers
119 (##)Burst Mode Controller:
120 (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
121 controller: operating mode (continuous or one-shot mode), clock
122 (source, prescaler) , trigger(s), period, idle duration.
123 (##)External Events Conditioning:
124 (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
125 external event channel: source, polarity, edge-sensitivity.
126 External event can be used as triggers (timer reset, input
127 capture, burst mode, ADC triggers, delayed protection)
128 They can also be used to set or reset timer outputs. Up to
129 10 event channels are available.
130 (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
131 event sampling clock (used for digital filtering).
132 (##)Fault Conditioning:
133 (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
134 fault channel: source, polarity, edge-sensitivity. Fault
135 channels are used to disable the outputs in case of an
136 abnormal operation. Up to 5 fault channels are available.
137 (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
138 sampling clock (used for digital filtering).
139 (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
140 circuitry. By default all fault inputs are disabled.
141 (##)ADC trigger:
142 (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
143 the update of the ADC trigger register and the ADC trigger.
144 4 independent triggers are available to start both the regular
145 and the injected sequencers of the 2 ADCs
146
147 (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
148 function must be called whatever the HRTIM timer operating mode is
149 (simple v.s. waveform). It configures mainly:
150 (##)The HRTIM timer counter operating mode (continuous v.s. one shot)
151 (##)The HRTIM timer clock prescaler
152 (##)The HRTIM timer period
153 (##)The HRTIM timer repetition counter
154
155 *** If the HRTIM timer operates in simple mode ***
156 ===================================================
157 [..]
158 (#) Start or Stop simple timers
159 (++)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
160 HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
161 HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
162 (++)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
163 HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
164 HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
165 HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
166 (++)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
167 HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
168 HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
169 HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
170 (++)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
171 HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
172 HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
173 HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
174 (++)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
175 HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
176 HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().
177
178 *** If the HRTIM timer operates in waveform mode ***
179 ====================================================
180 [..]
181 (#) Completes waveform timer configuration
182 (++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM timer
183 operating in wave form mode mainly consists in:
184 (+++)Enabling the HRTIM timer interrupts and DMA requests.
185 (+++)Enabling the half mode for the HRTIM timer.
186 (+++)Defining how the HRTIM timer reacts to external synchronization input.
187 (+++)Enabling the push-pull mode for the HRTIM timer.
188 (+++)Enabling the fault channels for the HRTIM timer.
189 (+++)Enabling the dead-time insertion for the HRTIM timer.
190 (+++)Setting the delayed protection mode for the HRTIM timer (source and outputs
191 on which the delayed protection are applied).
192 (+++)Specifying the HRTIM timer update and reset triggers.
193 (+++)Specifying the HRTIM timer registers update policy (e.g. pre-load enabling).
194 (++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
195 event blanking and windowing circuitry of a HRTIM timer:
196 (+++)Blanking: to mask external events during a defined time period a defined time period
197 (+++)Windowing, to enable external events only during a defined time period
198 (++)HAL_HRTIM_DeadTimeConfig(): configures the dead-time insertion
199 unit for a HRTIM timer. Allows to generate a couple of
200 complementary signals from a single reference waveform,
201 with programmable delays between active state.
202 (++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
203 the high-frequency carrier signal added on top of the timing
204 unit output. Chopper mode can be enabled or disabled for each
205 timer output separately (see HAL_HRTIM_WaveformOutputConfig()).
206 (++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
207 controller. Allows having multiple HRTIM registers updated
208 with a single DMA request. The burst DMA operation is started
209 by calling HAL_HRTIM_BurstDMATransfer().
210 (++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
211 of a HRTIM timer. This operation consists in setting the
212 compare value and possibly specifying the auto delayed mode
213 for compare units 2 and 4 (allows to have compare events
214 generated relatively to capture events). Note that when auto
215 delayed mode is needed, the capture unit associated to the
216 compare unit must be configured separately.
217 (++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
218 of a HRTIM timer. This operation consists in specifying the
219 source(s) triggering the capture (timer register update event,
220 external event, timer output set/reset event, other HRTIM
221 timer related events).
222 (++)HAL_HRTIM_WaveformOutputConfig(): configuration of a HRTIM timer
223 output mainly consists in:
224 (+++)Setting the output polarity (active high or active low),
225 (+++)Defining the set/reset crossbar for the output,
226 (+++)Specifying the fault level (active or inactive) in IDLE and FAULT states.,
227
228 (#) Set waveform timer output(s) level
229 (++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
230 active or inactive level. For example, when deadtime insertion
231 is enabled it is necessary to force the output level by software
232 to have the outputs in a complementary state as soon as the RUN mode is entered.
233
234 (#) Enable or Disable waveform timer output(s)
235 (++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().
236
237 (#) Start or Stop waveform HRTIM timer(s).
238 (++)HAL_HRTIM_WaveformCountStart(),HAL_HRTIM_WaveformCountStop(),
239 (++)HAL_HRTIM_WaveformCountStart_IT(),HAL_HRTIM_WaveformCountStop_IT(),
240 (++)HAL_HRTIM_WaveformCountStart_DMA(),HAL_HRTIM_WaveformCountStop_DMA(),
241 (#) Burst mode controller enabling:
242 (++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
243 burst mode controller.
244
245 (#) Some HRTIM operations can be triggered by software:
246 (++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
247 trigs the burst operation.
248 (++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
249 capture of the HRTIM timer counter.
250 (++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
251 update of the pre-loadable registers of the HRTIM timer
252 (++)HAL_HRTIM_SoftwareReset():calling this function resets the
253 HRTIM timer counter.
254
255 (#) Some functions can be used any time to retrieve HRTIM timer related
256 information
257 (++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
258 capture register of the designated capture unit.
259 (++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
260 (ACTIVE/INACTIVE) of the designated timer output.
261 (++)HAL_HRTIM_WaveformGetOutputState():returns actual state
262 (IDLE/RUN/FAULT) of the designated timer output.
263 (++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
264 (ACTIVE/INACTIVE) of the designated output when the delayed
265 protection was triggered.
266 (++)HAL_HRTIM_GetBurstStatus(): returns the actual status
267 (ACTIVE/INACTIVE) of the burst mode controller.
268 (++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
269 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
270 the push-pull status indicates on which output the signal is currently
271 active (e.g signal applied on output 1 and output 2 forced
272 inactive or vice versa).
273 (++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
274 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
275 the idle push-pull status indicates during which period the
276 delayed protection request occurred (e.g. protection occurred
277 when the output 1 was active and output 2 forced inactive or
278 vice versa).
279
280 (#) Some functions can be used any time to retrieve actual HRTIM status
281 (++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.
282
283 *** Callback registration ***
284 =============================
285 [..]
286 The compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS when set to 1
287 allows the user to configure dynamically the driver callbacks.
288 Use Functions HAL_HRTIM_RegisterCallback() or HAL_HRTIM_TIMxRegisterCallback()
289 to register an interrupt callback.
290
291 [..]
292 Function HAL_HRTIM_RegisterCallback() allows to register following callbacks:
293 (+) Fault1Callback : Fault 1 interrupt callback function
294 (+) Fault2Callback : Fault 2 interrupt callback function
295 (+) Fault3Callback : Fault 3 interrupt callback function
296 (+) Fault4Callback : Fault 4 interrupt callback function
297 (+) Fault5Callback : Fault 5 interrupt callback function
298 (+) SystemFaultCallback : System fault interrupt callback function
299 (+) BurstModePeriodCallback : Burst mode period interrupt callback function
300 (+) SynchronizationEventCallback : Sync Input interrupt callback function
301 (+) ErrorCallback : DMA error callback function
302 (+) MspInitCallback : HRTIM MspInit callback function
303 (+) MspDeInitCallback : HRTIM MspInit callback function
304
305 [..]
306 Function HAL_HRTIM_TIMxRegisterCallback() allows to register following callbacks:
307 (+) RegistersUpdateCallback : Timer x Update interrupt callback function
308 (+) RepetitionEventCallback : Timer x Repetition interrupt callback function
309 (+) Compare1EventCallback : Timer x Compare 1 match interrupt callback function
310 (+) Compare2EventCallback : Timer x Compare 2 match interrupt callback function
311 (+) Compare3EventCallback : Timer x Compare 3 match interrupt callback function
312 (+) Compare4EventCallback : Timer x Compare 4 match interrupt callback function
313 (+) Capture1EventCallback : Timer x Capture 1 interrupts callback function
314 (+) Capture2EventCallback : Timer x Capture 2 interrupts callback function
315 (+) DelayedProtectionCallback : Timer x Delayed protection interrupt callback function
316 (+) CounterResetCallback : Timer x counter reset/roll-over interrupt callback function
317 (+) Output1SetCallback : Timer x output 1 set interrupt callback function
318 (+) Output1ResetCallback : Timer x output 1 reset interrupt callback function
319 (+) Output2SetCallback : Timer x output 2 set interrupt callback function
320 (+) Output2ResetCallback : Timer x output 2 reset interrupt callback function
321 (+) BurstDMATransferCallback : Timer x Burst DMA completed interrupt callback function
322
323 [..]
324 Both functions take as parameters the HAL peripheral handle, the Callback ID
325 and a pointer to the user callback function.
326
327 [..]
328 Use function HAL_HRTIM_UnRegisterCallback or HAL_HRTIM_TIMxUnRegisterCallback
329 to reset a callback to the default weak function. Both functions take as parameters
330 the HAL peripheral handle and the Callback ID.
331
332 [..]
333 By default, after the HAL_HRTIM_Init() and when the state is HAL_HRTIM_STATE_RESET
334 all callbacks are set to the corresponding weak functions (e.g HAL_HRTIM_Fault1Callback)
335 Exception done for MspInit and MspDeInit functions that are reset to the legacy
336 weak functions in the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() only when these
337 callbacks are null (not registered beforehand). If MspInit or MspDeInit are
338 not null, the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() keep and use the user
339 MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
340
341 [..]
342 Callbacks can be registered/unregistered in HAL_HRTIM_STATE_READY state only.
343 Exception done MspInit/MspDeInit functions that can be registered/unregistered
344 in HAL_HRTIM_STATE_READY or HAL_HRTIM_STATE_RESET states, thus registered
345 (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
346 Then, the user first registers the MspInit/MspDeInit user callbacks
347 using HAL_HRTIM_RegisterCallback() before calling HAL_HRTIM_DeInit()
348 or HAL_HRTIM_Init() function.
349
350 [..]
351 When the compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS is set to 0 or
352 not defined, the callback registration feature is not available and all
353 callbacks are set to the corresponding weak functions.
354
355 @endverbatim
356 ******************************************************************************
357 */
358
359 /* Includes ------------------------------------------------------------------*/
360 #include "stm32h7xx_hal.h"
361
362 /** @addtogroup STM32H7xx_HAL_Driver
363 * @{
364 */
365
366 #ifdef HAL_HRTIM_MODULE_ENABLED
367
368 #if defined(HRTIM1)
369
370 /** @defgroup HRTIM HRTIM
371 * @brief HRTIM HAL module driver
372 * @{
373 */
374
375 /* Private typedef -----------------------------------------------------------*/
376 /* Private define ------------------------------------------------------------*/
377 /** @defgroup HRTIM_Private_Defines HRTIM Private Define
378 * @{
379 */
380 #define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
381 HRTIM_FLTR_FLT2EN |\
382 HRTIM_FLTR_FLT3EN |\
383 HRTIM_FLTR_FLT4EN | \
384 HRTIM_FLTR_FLT5EN)
385
386 #define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
387 HRTIM_TIMUPDATETRIGGER_TIMER_A |\
388 HRTIM_TIMUPDATETRIGGER_TIMER_B |\
389 HRTIM_TIMUPDATETRIGGER_TIMER_C |\
390 HRTIM_TIMUPDATETRIGGER_TIMER_D |\
391 HRTIM_TIMUPDATETRIGGER_TIMER_E)
392
393 #define HRTIM_FLTINR1_FLTxLCK ((HRTIM_FAULTLOCK_READONLY) | \
394 (HRTIM_FAULTLOCK_READONLY << 8U) | \
395 (HRTIM_FAULTLOCK_READONLY << 16U) | \
396 (HRTIM_FAULTLOCK_READONLY << 24U))
397
398 #define HRTIM_FLTINR2_FLTxLCK ((HRTIM_FAULTLOCK_READONLY) | \
399 (HRTIM_FAULTLOCK_READONLY << 8U))
400 /**
401 * @}
402 */
403
404 /* Private macro -------------------------------------------------------------*/
405 /* Private variables ---------------------------------------------------------*/
406 /** @defgroup HRTIM_Private_Variables HRTIM Private Variables
407 * @{
408 */
409 static uint32_t TimerIdxToTimerId[] =
410 {
411 HRTIM_TIMERID_TIMER_A,
412 HRTIM_TIMERID_TIMER_B,
413 HRTIM_TIMERID_TIMER_C,
414 HRTIM_TIMERID_TIMER_D,
415 HRTIM_TIMERID_TIMER_E,
416 HRTIM_TIMERID_MASTER,
417 };
418 /**
419 * @}
420 */
421
422 /* Private function prototypes -----------------------------------------------*/
423 /** @defgroup HRTIM_Private_Functions HRTIM Private Functions
424 * @{
425 */
426 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
427 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
428
429 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
430 uint32_t TimerIdx,
431 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
432
433 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
434 const HRTIM_TimerCfgTypeDef * pTimerCfg);
435
436 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
437 uint32_t TimerIdx,
438 const HRTIM_TimerCfgTypeDef * pTimerCfg);
439
440
441 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
442 uint32_t TimerIdx,
443 uint32_t CaptureUnit,
444 uint32_t Event);
445
446 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
447 uint32_t TimerIdx,
448 uint32_t Output,
449 const HRTIM_OutputCfgTypeDef * pOutputCfg);
450
451 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
452 uint32_t Event,
453 const HRTIM_EventCfgTypeDef * pEventCfg);
454
455 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
456 uint32_t TimerIdx,
457 uint32_t Event);
458
459 static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
460 uint32_t TimerIdx,
461 uint32_t OCChannel);
462
463 static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
464 uint32_t TimerIdx,
465 uint32_t OCChannel);
466
467 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim,
468 uint32_t TimerIdx);
469
470 static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim,
471 const DMA_HandleTypeDef * hdma);
472
473 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
474 uint32_t TimerIdx);
475
476 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim);
477
478 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim);
479
480 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
481 uint32_t TimerIdx);
482
483 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma);
484
485 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma);
486
487 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma);
488
489 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
490 /**
491 * @}
492 */
493
494 /* Exported functions ---------------------------------------------------------*/
495 /** @defgroup HRTIM_Exported_Functions HRTIM Exported Functions
496 * @{
497 */
498
499 /** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
500 * @brief Initialization and Configuration functions
501 @verbatim
502 ===============================================================================
503 ##### Initialization and Time Base Configuration functions #####
504 ===============================================================================
505 [..] This section provides functions allowing to:
506 (+) Initialize a HRTIM instance
507 (+) De-initialize a HRTIM instance
508 (+) Initialize the HRTIM MSP
509 (+) De-initialize the HRTIM MSP
510 (+) Configure the time base unit of a HRTIM timer
511
512 @endverbatim
513 * @{
514 */
515
516 /**
517 * @brief Initialize a HRTIM instance
518 * @param hhrtim pointer to HAL HRTIM handle
519 * @retval HAL status
520 */
HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)521 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)
522 {
523 uint8_t timer_idx;
524 uint32_t hrtim_mcr;
525
526 /* Check the HRTIM handle allocation */
527 if(hhrtim == NULL)
528 {
529 return HAL_ERROR;
530 }
531
532 /* Check the parameters */
533 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
534 assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests));
535
536 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
537 if (hhrtim->State == HAL_HRTIM_STATE_RESET)
538 {
539 /* Initialize callback function pointers to their default values */
540 hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
541 hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
542 hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
543 hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
544 hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
545 hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
546 hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
547 hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
548 hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
549 hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
550 hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
551 hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
552 hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
553 hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
554 hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
555 hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
556 hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
557 hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
558 hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
559 hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
560 hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
561 hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
562 hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
563 hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
564
565 if (hhrtim->MspInitCallback == NULL)
566 {
567 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
568 }
569 }
570 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
571
572 /* Set the HRTIM state */
573 hhrtim->State = HAL_HRTIM_STATE_BUSY;
574
575 /* Initialize the DMA handles */
576 hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL;
577 hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL;
578 hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL;
579 hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL;
580 hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL;
581 hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL;
582
583 /* HRTIM output synchronization configuration (if required) */
584 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != (uint32_t)RESET)
585 {
586 /* Check parameters */
587 assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(hhrtim->Init.SyncOutputSource));
588 assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
589
590 /* The synchronization output initialization procedure must be done prior
591 to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit)
592 */
593 if (hhrtim->Instance == HRTIM1)
594 {
595 /* Enable the HRTIM peripheral clock */
596 __HAL_RCC_HRTIM1_CLK_ENABLE();
597 }
598
599 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
600
601 /* Set the event to be sent on the synchronization output */
602 hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
603 hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
604
605 /* Set the polarity of the synchronization output */
606 hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
607 hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
608
609 /* Update the HRTIM registers */
610 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
611 }
612
613 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
614 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
615 hhrtim->MspInitCallback(hhrtim);
616 #else
617 HAL_HRTIM_MspInit(hhrtim);
618 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
619
620 /* HRTIM input synchronization configuration (if required) */
621 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != (uint32_t)RESET)
622 {
623 /* Check parameters */
624 assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
625
626 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
627
628 /* Set the synchronization input source */
629 hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
630 hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
631
632 /* Update the HRTIM registers */
633 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
634 }
635
636 /* Initialize the HRTIM state*/
637 hhrtim->State = HAL_HRTIM_STATE_READY;
638
639 /* Initialize the lock status of the HRTIM HAL API */
640 __HAL_UNLOCK(hhrtim);
641
642 /* Initialize timer related parameters */
643 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
644 timer_idx <= HRTIM_TIMERINDEX_MASTER ;
645 timer_idx++)
646 {
647 hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
648 hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
649 hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
650 hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
651 hhrtim->TimerParam[timer_idx].DMASrcAddress = 0U;
652 hhrtim->TimerParam[timer_idx].DMASize = 0U;
653 }
654
655 return HAL_OK;
656 }
657
658 /**
659 * @brief De-initialize a HRTIM instance
660 * @param hhrtim pointer to HAL HRTIM handle
661 * @retval HAL status
662 */
HAL_HRTIM_DeInit(HRTIM_HandleTypeDef * hhrtim)663 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim)
664 {
665 /* Check the HRTIM handle allocation */
666 if(hhrtim == NULL)
667 {
668 return HAL_ERROR;
669 }
670
671 /* Check the parameters */
672 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
673
674 /* Set the HRTIM state */
675 hhrtim->State = HAL_HRTIM_STATE_BUSY;
676
677 /* DeInit the low level hardware */
678 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
679 if (hhrtim->MspDeInitCallback == NULL)
680 {
681 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
682 }
683
684 hhrtim->MspDeInitCallback(hhrtim);
685 #else
686 HAL_HRTIM_MspDeInit(hhrtim);
687 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
688
689 hhrtim->State = HAL_HRTIM_STATE_READY;
690
691 return HAL_OK;
692 }
693
694 /**
695 * @brief MSP initialization for a HRTIM instance
696 * @param hhrtim pointer to HAL HRTIM handle
697 * @retval None
698 */
HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)699 __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)
700 {
701 /* Prevent unused argument(s) compilation warning */
702 UNUSED(hhrtim);
703
704 /* NOTE: This function should not be modified, when the callback is needed,
705 the HAL_HRTIM_MspInit could be implemented in the user file
706 */
707 }
708
709 /**
710 * @brief MSP de-initialization of a HRTIM instance
711 * @param hhrtim pointer to HAL HRTIM handle
712 * @retval None
713 */
HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)714 __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)
715 {
716 /* Prevent unused argument(s) compilation warning */
717 UNUSED(hhrtim);
718
719 /* NOTE: This function should not be modified, when the callback is needed,
720 the HAL_HRTIM_MspDeInit could be implemented in the user file
721 */
722 }
723
724 /**
725 * @brief Configure the time base unit of a timer
726 * @param hhrtim pointer to HAL HRTIM handle
727 * @param TimerIdx Timer index
728 * This parameter can be one of the following values:
729 * @arg HRTIM_TIMERINDEX_MASTER for master timer
730 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
731 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
732 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
733 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
734 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
735 * @param pTimeBaseCfg pointer to the time base configuration structure
736 * @note This function must be called prior starting the timer
737 * @note The time-base unit initialization parameters specify:
738 * The timer counter operating mode (continuous, one shot),
739 * The timer clock prescaler,
740 * The timer period,
741 * The timer repetition counter.
742 * @retval HAL status
743 */
HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)744 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
745 uint32_t TimerIdx,
746 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
747 {
748 /* Check the parameters */
749 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
750 assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
751 assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
752
753 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
754 {
755 return HAL_BUSY;
756 }
757
758 /* Set the HRTIM state */
759 hhrtim->State = HAL_HRTIM_STATE_BUSY;
760
761 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
762 {
763 /* Configure master timer time base unit */
764 HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
765 }
766 else
767 {
768 /* Configure timing unit time base unit */
769 HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
770 }
771
772 /* Set HRTIM state */
773 hhrtim->State = HAL_HRTIM_STATE_READY;
774
775 return HAL_OK;
776 }
777
778 /**
779 * @}
780 */
781
782 /** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
783 * @brief Simple time base mode functions.
784 @verbatim
785 ===============================================================================
786 ##### Simple time base mode functions #####
787 ===============================================================================
788 [..] This section provides functions allowing to:
789 (+) Start simple time base
790 (+) Stop simple time base
791 (+) Start simple time base and enable interrupt
792 (+) Stop simple time base and disable interrupt
793 (+) Start simple time base and enable DMA transfer
794 (+) Stop simple time base and disable DMA transfer
795 -@- When a HRTIM timer operates in simple time base mode, the timer
796 counter counts from 0 to the period value.
797
798 @endverbatim
799 * @{
800 */
801
802 /**
803 * @brief Start the counter of a timer operating in simple time base mode.
804 * @param hhrtim pointer to HAL HRTIM handle
805 * @param TimerIdx Timer index.
806 * This parameter can be one of the following values:
807 * @arg HRTIM_TIMERINDEX_MASTER for master timer
808 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
809 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
810 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
811 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
812 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
813 * @retval HAL status
814 */
HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)815 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,
816 uint32_t TimerIdx)
817 {
818 /* Check the parameters */
819 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
820
821 /* Process Locked */
822 __HAL_LOCK(hhrtim);
823
824 hhrtim->State = HAL_HRTIM_STATE_BUSY;
825
826 /* Enable the timer counter */
827 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
828
829 hhrtim->State = HAL_HRTIM_STATE_READY;
830
831 /* Process Unlocked */
832 __HAL_UNLOCK(hhrtim);
833
834 return HAL_OK;
835 }
836
837 /**
838 * @brief Stop the counter of a timer operating in simple time base mode.
839 * @param hhrtim pointer to HAL HRTIM handle
840 * @param TimerIdx Timer index.
841 * This parameter can be one of the following values:
842 * @arg HRTIM_TIMERINDEX_MASTER for master timer
843 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
844 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
845 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
846 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
847 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
848 * @retval HAL status
849 */
HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)850 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,
851 uint32_t TimerIdx)
852 {
853 /* Check the parameters */
854 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
855
856 /* Process Locked */
857 __HAL_LOCK(hhrtim);
858
859 hhrtim->State = HAL_HRTIM_STATE_BUSY;
860
861 /* Disable the timer counter */
862 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
863
864 hhrtim->State = HAL_HRTIM_STATE_READY;
865
866 /* Process Unlocked */
867 __HAL_UNLOCK(hhrtim);
868
869 return HAL_OK;
870 }
871
872 /**
873 * @brief Start the counter of a timer operating in simple time base mode
874 * (Timer repetition interrupt is enabled).
875 * @param hhrtim pointer to HAL HRTIM handle
876 * @param TimerIdx Timer index.
877 * This parameter can be one of the following values:
878 * @arg HRTIM_TIMERINDEX_MASTER for master timer
879 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
880 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
881 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
882 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
883 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
884 * @retval HAL status
885 */
HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)886 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,
887 uint32_t TimerIdx)
888 {
889 /* Check the parameters */
890 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
891
892 /* Process Locked */
893 __HAL_LOCK(hhrtim);
894
895 hhrtim->State = HAL_HRTIM_STATE_BUSY;
896
897 /* Enable the repetition interrupt */
898 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
899 {
900 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
901 }
902 else
903 {
904 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
905 }
906
907 /* Enable the timer counter */
908 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
909
910 hhrtim->State = HAL_HRTIM_STATE_READY;
911
912 /* Process Unlocked */
913 __HAL_UNLOCK(hhrtim);
914
915 return HAL_OK;
916 }
917
918 /**
919 * @brief Stop the counter of a timer operating in simple time base mode
920 * (Timer repetition interrupt is disabled).
921 * @param hhrtim pointer to HAL HRTIM handle
922 * @param TimerIdx Timer index.
923 * This parameter can be one of the following values:
924 * @arg HRTIM_TIMERINDEX_MASTER for master timer
925 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
926 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
927 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
928 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
929 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
930 * @retval HAL status
931 */
HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)932 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,
933 uint32_t TimerIdx)
934 {
935 /* Check the parameters */
936 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
937
938 /* Process Locked */
939 __HAL_LOCK(hhrtim);
940
941 hhrtim->State = HAL_HRTIM_STATE_BUSY;
942
943 /* Disable the repetition interrupt */
944 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
945 {
946 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
947 }
948 else
949 {
950 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
951 }
952
953 /* Disable the timer counter */
954 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
955
956 hhrtim->State = HAL_HRTIM_STATE_READY;
957
958 /* Process Unlocked */
959 __HAL_UNLOCK(hhrtim);
960
961 return HAL_OK;
962 }
963
964 /**
965 * @brief Start the counter of a timer operating in simple time base mode
966 * (Timer repetition DMA request is enabled).
967 * @param hhrtim pointer to HAL HRTIM handle
968 * @param TimerIdx Timer index.
969 * This parameter can be one of the following values:
970 * @arg HRTIM_TIMERINDEX_MASTER for master timer
971 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
972 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
973 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
974 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
975 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
976 * @param SrcAddr DMA transfer source address
977 * @param DestAddr DMA transfer destination address
978 * @param Length The length of data items (data size) to be transferred
979 * from source to destination
980 */
HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)981 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,
982 uint32_t TimerIdx,
983 uint32_t SrcAddr,
984 uint32_t DestAddr,
985 uint32_t Length)
986 {
987 DMA_HandleTypeDef * hdma;
988
989 /* Check the parameters */
990 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
991
992 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
993 {
994 return HAL_BUSY;
995 }
996 if(hhrtim->State == HAL_HRTIM_STATE_READY)
997 {
998 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
999 {
1000 return HAL_ERROR;
1001 }
1002 else
1003 {
1004 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1005 }
1006 }
1007
1008 /* Process Locked */
1009 __HAL_LOCK(hhrtim);
1010
1011 /* Get the timer DMA handler */
1012 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1013
1014 if (hdma == NULL)
1015 {
1016 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1017
1018 /* Process Unlocked */
1019 __HAL_UNLOCK(hhrtim);
1020
1021 return HAL_ERROR;
1022 }
1023
1024 /* Set the DMA transfer completed callback */
1025 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1026 {
1027 hdma->XferCpltCallback = HRTIM_DMAMasterCplt;
1028 }
1029 else
1030 {
1031 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1032 }
1033
1034 /* Set the DMA error callback */
1035 hdma->XferErrorCallback = HRTIM_DMAError ;
1036
1037 /* Enable the DMA channel */
1038 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
1039 {
1040 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1041
1042 /* Process Unlocked */
1043 __HAL_UNLOCK(hhrtim);
1044
1045 return HAL_ERROR;
1046 }
1047
1048 /* Enable the timer repetition DMA request */
1049 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1050 {
1051 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1052 }
1053 else
1054 {
1055 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1056 }
1057
1058 /* Enable the timer counter */
1059 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1060
1061 hhrtim->State = HAL_HRTIM_STATE_READY;
1062
1063 /* Process Unlocked */
1064 __HAL_UNLOCK(hhrtim);
1065
1066 return HAL_OK;
1067 }
1068
1069 /**
1070 * @brief Stop the counter of a timer operating in simple time base mode
1071 * (Timer repetition DMA request is disabled).
1072 * @param hhrtim pointer to HAL HRTIM handle
1073 * @param TimerIdx Timer index.
1074 * This parameter can be one of the following values:
1075 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1076 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1077 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1078 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1079 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1080 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1081 * @retval HAL status
1082 */
HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)1083 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
1084 uint32_t TimerIdx)
1085 {
1086 DMA_HandleTypeDef * hdma;
1087
1088 /* Check the parameters */
1089 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1090
1091 /* Process Locked */
1092 __HAL_LOCK(hhrtim);
1093
1094 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1095 {
1096 hhrtim->State = HAL_HRTIM_STATE_READY;
1097
1098 /* Disable the DMA */
1099 if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
1100 {
1101 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1102 }
1103 /* Disable the timer repetition DMA request */
1104 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1105 }
1106 else
1107 {
1108 /* Get the timer DMA handler */
1109 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1110
1111 if (hdma == NULL)
1112 {
1113 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1114 }
1115 else
1116 {
1117 hhrtim->State = HAL_HRTIM_STATE_READY;
1118
1119 /* Disable the DMA */
1120 if (HAL_DMA_Abort(hdma) != HAL_OK)
1121 {
1122 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1123 }
1124
1125 /* Disable the timer repetition DMA request */
1126 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1127 }
1128 }
1129
1130 /* Disable the timer counter */
1131 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1132
1133 /* Process Unlocked */
1134 __HAL_UNLOCK(hhrtim);
1135
1136 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
1137 {
1138 return HAL_ERROR;
1139 }
1140 else
1141 {
1142 return HAL_OK;
1143 }
1144 }
1145
1146 /**
1147 * @}
1148 */
1149
1150 /** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
1151 * @brief Simple output compare functions
1152 @verbatim
1153 ===============================================================================
1154 ##### Simple output compare functions #####
1155 ===============================================================================
1156 [..] This section provides functions allowing to:
1157 (+) Configure simple output channel
1158 (+) Start simple output compare
1159 (+) Stop simple output compare
1160 (+) Start simple output compare and enable interrupt
1161 (+) Stop simple output compare and disable interrupt
1162 (+) Start simple output compare and enable DMA transfer
1163 (+) Stop simple output compare and disable DMA transfer
1164 -@- When a HRTIM timer operates in simple output compare mode
1165 the output level is set to a programmable value when a match
1166 is found between the compare register and the counter.
1167 Compare unit 1 is automatically associated to output 1
1168 Compare unit 2 is automatically associated to output 2
1169 @endverbatim
1170 * @{
1171 */
1172
1173 /**
1174 * @brief Configure an output in simple output compare mode
1175 * @param hhrtim pointer to HAL HRTIM handle
1176 * @param TimerIdx Timer index
1177 * This parameter can be one of the following values:
1178 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1179 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1180 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1181 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1182 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1183 * @param OCChannel Timer output
1184 * This parameter can be one of the following values:
1185 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1186 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1187 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1188 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1189 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1190 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1191 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1192 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1193 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1194 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1195 * @param pSimpleOCChannelCfg pointer to the simple output compare output configuration structure
1196 * @note When the timer operates in simple output compare mode:
1197 * Output 1 is implicitly controlled by the compare unit 1
1198 * Output 2 is implicitly controlled by the compare unit 2
1199 * Output Set/Reset crossbar is set according to the selected output compare mode:
1200 * Toggle: SETxyR = RSTxyR = CMPy
1201 * Active: SETxyR = CMPy, RSTxyR = 0
1202 * Inactive: SETxy =0, RSTxy = CMPy
1203 * @retval HAL status
1204 */
HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel,const HRTIM_SimpleOCChannelCfgTypeDef * pSimpleOCChannelCfg)1205 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
1206 uint32_t TimerIdx,
1207 uint32_t OCChannel,
1208 const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg)
1209 {
1210 uint32_t CompareUnit = (uint32_t)RESET;
1211 HRTIM_OutputCfgTypeDef OutputCfg;
1212
1213 /* Check parameters */
1214 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1215 assert_param(IS_HRTIM_BASICOCMODE(pSimpleOCChannelCfg->Mode));
1216 assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOCChannelCfg->Pulse));
1217 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity));
1218 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel));
1219
1220 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1221 {
1222 return HAL_BUSY;
1223 }
1224
1225 /* Process Locked */
1226 __HAL_LOCK(hhrtim);
1227
1228 /* Set HRTIM state */
1229 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1230
1231 /* Configure timer compare unit */
1232 switch (OCChannel)
1233 {
1234 case HRTIM_OUTPUT_TA1:
1235 case HRTIM_OUTPUT_TB1:
1236 case HRTIM_OUTPUT_TC1:
1237 case HRTIM_OUTPUT_TD1:
1238 case HRTIM_OUTPUT_TE1:
1239 {
1240 CompareUnit = HRTIM_COMPAREUNIT_1;
1241 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOCChannelCfg->Pulse;
1242 break;
1243 }
1244 case HRTIM_OUTPUT_TA2:
1245 case HRTIM_OUTPUT_TB2:
1246 case HRTIM_OUTPUT_TC2:
1247 case HRTIM_OUTPUT_TD2:
1248 case HRTIM_OUTPUT_TE2:
1249 {
1250 CompareUnit = HRTIM_COMPAREUNIT_2;
1251 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOCChannelCfg->Pulse;
1252 break;
1253 }
1254 default:
1255 {
1256 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1257
1258 /* Process Unlocked */
1259 __HAL_UNLOCK(hhrtim);
1260
1261 break;
1262 }
1263 }
1264
1265 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
1266 {
1267 return HAL_ERROR;
1268 }
1269
1270 /* Configure timer output */
1271 OutputCfg.Polarity = (pSimpleOCChannelCfg->Polarity & HRTIM_OUTR_POL1);
1272 OutputCfg.IdleLevel = (pSimpleOCChannelCfg->IdleLevel & HRTIM_OUTR_IDLES1);
1273 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
1274 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1275 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
1276 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
1277
1278 switch (pSimpleOCChannelCfg->Mode)
1279 {
1280 case HRTIM_BASICOCMODE_TOGGLE:
1281 {
1282 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1283 {
1284 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1285 }
1286 else
1287 {
1288 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1289 }
1290 OutputCfg.ResetSource = OutputCfg.SetSource;
1291 break;
1292 }
1293
1294 case HRTIM_BASICOCMODE_ACTIVE:
1295 {
1296 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1297 {
1298 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1299 }
1300 else
1301 {
1302 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1303 }
1304 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1305 break;
1306 }
1307
1308 case HRTIM_BASICOCMODE_INACTIVE:
1309 {
1310 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1311 {
1312 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
1313 }
1314 else
1315 {
1316 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
1317 }
1318 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1319 break;
1320 }
1321
1322 default:
1323 {
1324 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1325 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1326
1327 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1328
1329 /* Process Unlocked */
1330 __HAL_UNLOCK(hhrtim);
1331
1332 break;
1333 }
1334 }
1335
1336 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
1337 {
1338 return HAL_ERROR;
1339 }
1340
1341 HRTIM_OutputConfig(hhrtim,
1342 TimerIdx,
1343 OCChannel,
1344 &OutputCfg);
1345
1346 /* Set HRTIM state */
1347 hhrtim->State = HAL_HRTIM_STATE_READY;
1348
1349 /* Process Unlocked */
1350 __HAL_UNLOCK(hhrtim);
1351
1352 return HAL_OK;
1353 }
1354
1355 /**
1356 * @brief Start the output compare signal generation on the designed timer output
1357 * @param hhrtim pointer to HAL HRTIM handle
1358 * @param TimerIdx Timer index
1359 * This parameter can be one of the following values:
1360 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1361 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1362 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1363 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1364 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1365 * @param OCChannel Timer output
1366 * This parameter can be one of the following values:
1367 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1368 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1369 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1370 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1371 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1372 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1373 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1374 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1375 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1376 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1377 * @retval HAL status
1378 */
HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1379 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,
1380 uint32_t TimerIdx,
1381 uint32_t OCChannel)
1382 {
1383 /* Check the parameters */
1384 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1385
1386 /* Process Locked */
1387 __HAL_LOCK(hhrtim);
1388
1389 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1390
1391 /* Enable the timer output */
1392 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1393
1394 /* Enable the timer counter */
1395 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1396
1397 hhrtim->State = HAL_HRTIM_STATE_READY;
1398
1399 /* Process Unlocked */
1400 __HAL_UNLOCK(hhrtim);
1401
1402 return HAL_OK;
1403 }
1404
1405 /**
1406 * @brief Stop the output compare signal generation on the designed timer output
1407 * @param hhrtim pointer to HAL HRTIM handle
1408 * @param TimerIdx Timer index
1409 * This parameter can be one of the following values:
1410 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1411 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1412 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1413 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1414 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1415 * @param OCChannel Timer output
1416 * This parameter can be one of the following values:
1417 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1418 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1419 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1420 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1421 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1422 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1423 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1424 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1425 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1426 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1427 * @retval HAL status
1428 */
HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1429 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,
1430 uint32_t TimerIdx,
1431 uint32_t OCChannel)
1432 {
1433 /* Check the parameters */
1434 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1435
1436 /* Process Locked */
1437 __HAL_LOCK(hhrtim);
1438
1439 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1440
1441 /* Disable the timer output */
1442 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1443
1444 /* Disable the timer counter */
1445 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1446
1447 hhrtim->State = HAL_HRTIM_STATE_READY;
1448
1449 /* Process Unlocked */
1450 __HAL_UNLOCK(hhrtim);
1451
1452 return HAL_OK;
1453 }
1454
1455 /**
1456 * @brief Start the output compare signal generation on the designed timer output
1457 * (Interrupt is enabled (see note note below)).
1458 * @param hhrtim pointer to HAL HRTIM handle
1459 * @param TimerIdx Timer index
1460 * This parameter can be one of the following values:
1461 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1462 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1463 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1464 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1465 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1466 * @param OCChannel Timer output
1467 * This parameter can be one of the following values:
1468 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1469 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1470 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1471 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1472 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1473 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1474 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1475 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1476 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1477 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1478 * @note Interrupt enabling depends on the chosen output compare mode
1479 * Output toggle: compare match interrupt is enabled
1480 * Output set active: output set interrupt is enabled
1481 * Output set inactive: output reset interrupt is enabled
1482 * @retval HAL status
1483 */
HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1484 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,
1485 uint32_t TimerIdx,
1486 uint32_t OCChannel)
1487 {
1488 uint32_t interrupt;
1489
1490 /* Check the parameters */
1491 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1492
1493 /* Process Locked */
1494 __HAL_LOCK(hhrtim);
1495
1496 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1497
1498 /* Get the interrupt to enable (depends on the output compare mode) */
1499 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1500
1501 /* Enable the timer output */
1502 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1503
1504 /* Enable the timer interrupt (depends on the output compare mode) */
1505 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, interrupt);
1506
1507 /* Enable the timer counter */
1508 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1509
1510 hhrtim->State = HAL_HRTIM_STATE_READY;
1511
1512 /* Process Unlocked */
1513 __HAL_UNLOCK(hhrtim);
1514
1515 return HAL_OK;
1516 }
1517
1518 /**
1519 * @brief Stop the output compare signal generation on the designed timer output
1520 * (Interrupt is disabled).
1521 * @param hhrtim pointer to HAL HRTIM handle
1522 * @param TimerIdx Timer index
1523 * This parameter can be one of the following values:
1524 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1525 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1526 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1527 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1528 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1529 * @param OCChannel Timer output
1530 * This parameter can be one of the following values:
1531 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1532 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1533 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1534 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1535 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1536 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1537 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1538 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1539 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1540 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1541 * @retval HAL status
1542 */
HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1543 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,
1544 uint32_t TimerIdx,
1545 uint32_t OCChannel)
1546 {
1547 uint32_t interrupt;
1548
1549 /* Check the parameters */
1550 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1551
1552 /* Process Locked */
1553 __HAL_LOCK(hhrtim);
1554
1555 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1556
1557 /* Disable the timer output */
1558 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1559
1560 /* Get the interrupt to disable (depends on the output compare mode) */
1561 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1562
1563 /* Disable the timer interrupt */
1564 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, interrupt);
1565
1566 /* Disable the timer counter */
1567 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1568
1569 hhrtim->State = HAL_HRTIM_STATE_READY;
1570
1571 /* Process Unlocked */
1572 __HAL_UNLOCK(hhrtim);
1573
1574 return HAL_OK;
1575 }
1576
1577 /**
1578 * @brief Start the output compare signal generation on the designed timer output
1579 * (DMA request is enabled (see note below)).
1580 * @param hhrtim pointer to HAL HRTIM handle
1581 * @param TimerIdx Timer index
1582 * This parameter can be one of the following values:
1583 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1584 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1585 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1586 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1587 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1588 * @param OCChannel Timer output
1589 * This parameter can be one of the following values:
1590 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1591 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1592 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1593 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1594 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1595 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1596 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1597 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1598 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1599 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1600 * @param SrcAddr DMA transfer source address
1601 * @param DestAddr DMA transfer destination address
1602 * @param Length The length of data items (data size) to be transferred
1603 * from source to destination
1604 * @note DMA request enabling depends on the chosen output compare mode
1605 * Output toggle: compare match DMA request is enabled
1606 * Output set active: output set DMA request is enabled
1607 * Output set inactive: output reset DMA request is enabled
1608 * @retval HAL status
1609 */
HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)1610 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
1611 uint32_t TimerIdx,
1612 uint32_t OCChannel,
1613 uint32_t SrcAddr,
1614 uint32_t DestAddr,
1615 uint32_t Length)
1616 {
1617 DMA_HandleTypeDef * hdma;
1618 uint32_t dma_request;
1619
1620 /* Check the parameters */
1621 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1622
1623 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1624 {
1625 return HAL_BUSY;
1626 }
1627 if(hhrtim->State == HAL_HRTIM_STATE_READY)
1628 {
1629 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
1630 {
1631 return HAL_ERROR;
1632 }
1633 else
1634 {
1635 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1636 }
1637 }
1638
1639 /* Process Locked */
1640 __HAL_LOCK(hhrtim);
1641
1642 /* Enable the timer output */
1643 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1644
1645 /* Get the DMA request to enable */
1646 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1647
1648 /* Get the timer DMA handler */
1649 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1650
1651 if (hdma == NULL)
1652 {
1653 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1654
1655 /* Process Unlocked */
1656 __HAL_UNLOCK(hhrtim);
1657
1658 return HAL_ERROR;
1659 }
1660
1661 /* Set the DMA error callback */
1662 hdma->XferErrorCallback = HRTIM_DMAError ;
1663
1664 /* Set the DMA transfer completed callback */
1665 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1666
1667 /* Enable the DMA channel */
1668 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
1669 {
1670 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1671
1672 /* Process Unlocked */
1673 __HAL_UNLOCK(hhrtim);
1674
1675 return HAL_ERROR;
1676 }
1677
1678 /* Enable the timer DMA request */
1679 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request);
1680
1681 /* Enable the timer counter */
1682 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1683
1684 hhrtim->State = HAL_HRTIM_STATE_READY;
1685
1686 /* Process Unlocked */
1687 __HAL_UNLOCK(hhrtim);
1688
1689 return HAL_OK;
1690 }
1691
1692 /**
1693 * @brief Stop the output compare signal generation on the designed timer output
1694 * (DMA request is disabled).
1695 * @param hhrtim pointer to HAL HRTIM handle
1696 * @param TimerIdx Timer index
1697 * This parameter can be one of the following values:
1698 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1699 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1700 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1701 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1702 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1703 * @param OCChannel Timer output
1704 * This parameter can be one of the following values:
1705 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1706 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1707 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1708 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1709 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1710 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1711 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1712 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1713 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1714 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1715 * @retval HAL status
1716 */
HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1717 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
1718 uint32_t TimerIdx,
1719 uint32_t OCChannel)
1720 {
1721 uint32_t dma_request;
1722
1723 /* Check the parameters */
1724 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1725
1726 /* Process Locked */
1727 __HAL_LOCK(hhrtim);
1728
1729 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1730
1731 /* Disable the timer output */
1732 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1733
1734 /* Get the timer DMA handler */
1735 /* Disable the DMA */
1736 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
1737 {
1738 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1739
1740 /* Process Unlocked */
1741 __HAL_UNLOCK(hhrtim);
1742
1743 return HAL_ERROR;
1744 }
1745
1746 /* Get the DMA request to disable */
1747 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1748
1749 /* Disable the timer DMA request */
1750 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, dma_request);
1751
1752 /* Disable the timer counter */
1753 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1754
1755 hhrtim->State = HAL_HRTIM_STATE_READY;
1756
1757 /* Process Unlocked */
1758 __HAL_UNLOCK(hhrtim);
1759
1760 return HAL_OK;
1761 }
1762
1763 /**
1764 * @}
1765 */
1766
1767 /** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
1768 * @brief Simple PWM output functions
1769 @verbatim
1770 ===============================================================================
1771 ##### Simple PWM output functions #####
1772 ===============================================================================
1773 [..] This section provides functions allowing to:
1774 (+) Configure simple PWM output channel
1775 (+) Start simple PWM output
1776 (+) Stop simple PWM output
1777 (+) Start simple PWM output and enable interrupt
1778 (+) Stop simple PWM output and disable interrupt
1779 (+) Start simple PWM output and enable DMA transfer
1780 (+) Stop simple PWM output and disable DMA transfer
1781 -@- When a HRTIM timer operates in simple PWM output mode
1782 the output level is set to a programmable value when a match is
1783 found between the compare register and the counter and reset when
1784 the timer period is reached. Duty cycle is determined by the
1785 comparison value.
1786 Compare unit 1 is automatically associated to output 1
1787 Compare unit 2 is automatically associated to output 2
1788 @endverbatim
1789 * @{
1790 */
1791
1792 /**
1793 * @brief Configure an output in simple PWM mode
1794 * @param hhrtim pointer to HAL HRTIM handle
1795 * @param TimerIdx Timer index
1796 * This parameter can be one of the following values:
1797 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1798 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1799 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1800 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1801 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1802 * @param PWMChannel Timer output
1803 * This parameter can be one of the following values:
1804 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1805 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1806 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1807 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1808 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1809 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1810 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1811 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1812 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1813 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1814 * @param pSimplePWMChannelCfg pointer to the simple PWM output configuration structure
1815 * @note When the timer operates in simple PWM output mode:
1816 * Output 1 is implicitly controlled by the compare unit 1
1817 * Output 2 is implicitly controlled by the compare unit 2
1818 * Output Set/Reset crossbar is set as follows:
1819 * Output 1: SETx1R = CMP1, RSTx1R = PER
1820 * Output 2: SETx2R = CMP2, RST2R = PER
1821 * @note When Simple PWM mode is used the registers preload mechanism is
1822 * enabled (otherwise the behavior is not guaranteed).
1823 * @retval HAL status
1824 */
HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel,const HRTIM_SimplePWMChannelCfgTypeDef * pSimplePWMChannelCfg)1825 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
1826 uint32_t TimerIdx,
1827 uint32_t PWMChannel,
1828 const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg)
1829 {
1830 HRTIM_OutputCfgTypeDef OutputCfg;
1831 uint32_t hrtim_timcr;
1832
1833 /* Check parameters */
1834 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1835 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimplePWMChannelCfg->Polarity));
1836 assert_param(IS_HRTIM_OUTPUTPULSE(pSimplePWMChannelCfg->Pulse));
1837 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel));
1838
1839 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1840 {
1841 return HAL_BUSY;
1842 }
1843
1844 /* Process Locked */
1845 __HAL_LOCK(hhrtim);
1846
1847 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1848
1849 /* Configure timer compare unit */
1850 switch (PWMChannel)
1851 {
1852 case HRTIM_OUTPUT_TA1:
1853 case HRTIM_OUTPUT_TB1:
1854 case HRTIM_OUTPUT_TC1:
1855 case HRTIM_OUTPUT_TD1:
1856 case HRTIM_OUTPUT_TE1:
1857 {
1858 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimplePWMChannelCfg->Pulse;
1859 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1860 break;
1861 }
1862
1863 case HRTIM_OUTPUT_TA2:
1864 case HRTIM_OUTPUT_TB2:
1865 case HRTIM_OUTPUT_TC2:
1866 case HRTIM_OUTPUT_TD2:
1867 case HRTIM_OUTPUT_TE2:
1868 {
1869 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimplePWMChannelCfg->Pulse;
1870 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1871 break;
1872 }
1873 default:
1874 {
1875 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1876 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1877
1878 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1879
1880 /* Process Unlocked */
1881 __HAL_UNLOCK(hhrtim);
1882
1883 break;
1884 }
1885 }
1886
1887 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
1888 {
1889 return HAL_ERROR;
1890 }
1891
1892 /* Configure timer output */
1893 OutputCfg.Polarity = (pSimplePWMChannelCfg->Polarity & HRTIM_OUTR_POL1);
1894 OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel& HRTIM_OUTR_IDLES1);
1895 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
1896 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1897 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
1898 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
1899 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
1900
1901 HRTIM_OutputConfig(hhrtim,
1902 TimerIdx,
1903 PWMChannel,
1904 &OutputCfg);
1905
1906 /* Enable the registers preload mechanism */
1907 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
1908 hrtim_timcr |= HRTIM_TIMCR_PREEN;
1909 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
1910
1911 hhrtim->State = HAL_HRTIM_STATE_READY;
1912
1913 /* Process Unlocked */
1914 __HAL_UNLOCK(hhrtim);
1915
1916 return HAL_OK;
1917 }
1918
1919 /**
1920 * @brief Start the PWM output signal generation on the designed timer output
1921 * @param hhrtim pointer to HAL HRTIM handle
1922 * @param TimerIdx Timer index
1923 * This parameter can be one of the following values:
1924 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1925 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1926 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1927 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1928 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1929 * @param PWMChannel Timer output
1930 * This parameter can be one of the following values:
1931 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1932 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1933 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1934 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1935 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1936 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1937 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1938 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1939 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1940 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1941 * @retval HAL status
1942 */
HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)1943 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,
1944 uint32_t TimerIdx,
1945 uint32_t PWMChannel)
1946 {
1947 /* Check the parameters */
1948 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1949
1950 /* Process Locked */
1951 __HAL_LOCK(hhrtim);
1952
1953 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1954
1955 /* Enable the timer output */
1956 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
1957
1958 /* Enable the timer counter */
1959 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1960
1961 hhrtim->State = HAL_HRTIM_STATE_READY;
1962
1963 /* Process Unlocked */
1964 __HAL_UNLOCK(hhrtim);
1965
1966 return HAL_OK;
1967 }
1968
1969 /**
1970 * @brief Stop the PWM output signal generation on the designed timer output
1971 * @param hhrtim pointer to HAL HRTIM handle
1972 * @param TimerIdx Timer index
1973 * This parameter can be one of the following values:
1974 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1975 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1976 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1977 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1978 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1979 * @param PWMChannel Timer output
1980 * This parameter can be one of the following values:
1981 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1982 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1983 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1984 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1985 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1986 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1987 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1988 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1989 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1990 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1991 * @retval HAL status
1992 */
HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)1993 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,
1994 uint32_t TimerIdx,
1995 uint32_t PWMChannel)
1996 {
1997 /* Check the parameters */
1998 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1999
2000 /* Process Locked */
2001 __HAL_LOCK(hhrtim);
2002
2003 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2004
2005 /* Disable the timer output */
2006 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2007
2008 /* Disable the timer counter */
2009 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2010
2011 hhrtim->State = HAL_HRTIM_STATE_READY;
2012
2013 /* Process Unlocked */
2014 __HAL_UNLOCK(hhrtim);
2015
2016 return HAL_OK;
2017 }
2018
2019 /**
2020 * @brief Start the PWM output signal generation on the designed timer output
2021 * (The compare interrupt is enabled).
2022 * @param hhrtim pointer to HAL HRTIM handle
2023 * @param TimerIdx Timer index
2024 * This parameter can be one of the following values:
2025 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2026 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2027 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2028 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2029 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2030 * @param PWMChannel Timer output
2031 * This parameter can be one of the following values:
2032 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2033 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2034 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2035 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2036 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2037 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2038 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2039 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2040 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2041 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2042 * @retval HAL status
2043 */
HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2044 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,
2045 uint32_t TimerIdx,
2046 uint32_t PWMChannel)
2047 {
2048 /* Check the parameters */
2049 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2050
2051 /* Process Locked */
2052 __HAL_LOCK(hhrtim);
2053
2054 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2055
2056 /* Enable the timer output */
2057 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2058
2059 /* Enable the timer interrupt (depends on the PWM output) */
2060 switch (PWMChannel)
2061 {
2062 case HRTIM_OUTPUT_TA1:
2063 case HRTIM_OUTPUT_TB1:
2064 case HRTIM_OUTPUT_TC1:
2065 case HRTIM_OUTPUT_TD1:
2066 case HRTIM_OUTPUT_TE1:
2067 {
2068 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2069 break;
2070 }
2071
2072 case HRTIM_OUTPUT_TA2:
2073 case HRTIM_OUTPUT_TB2:
2074 case HRTIM_OUTPUT_TC2:
2075 case HRTIM_OUTPUT_TD2:
2076 case HRTIM_OUTPUT_TE2:
2077 {
2078 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2079 break;
2080 }
2081
2082 default:
2083 {
2084 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2085
2086 /* Process Unlocked */
2087 __HAL_UNLOCK(hhrtim);
2088
2089 break;
2090 }
2091 }
2092
2093 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2094 {
2095 return HAL_ERROR;
2096 }
2097
2098 /* Enable the timer counter */
2099 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2100
2101 hhrtim->State = HAL_HRTIM_STATE_READY;
2102
2103 /* Process Unlocked */
2104 __HAL_UNLOCK(hhrtim);
2105
2106 return HAL_OK;
2107 }
2108
2109 /**
2110 * @brief Stop the PWM output signal generation on the designed timer output
2111 * (The compare interrupt is disabled).
2112 * @param hhrtim pointer to HAL HRTIM handle
2113 * @param TimerIdx Timer index
2114 * This parameter can be one of the following values:
2115 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2116 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2117 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2118 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2119 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2120 * @param PWMChannel Timer output
2121 * This parameter can be one of the following values:
2122 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2123 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2124 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2125 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2126 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2127 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2128 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2129 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2130 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2131 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2132 * @retval HAL status
2133 */
HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2134 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,
2135 uint32_t TimerIdx,
2136 uint32_t PWMChannel)
2137 {
2138 /* Check the parameters */
2139 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2140
2141 /* Process Locked */
2142 __HAL_LOCK(hhrtim);
2143
2144 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2145
2146 /* Disable the timer output */
2147 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2148
2149 /* Disable the timer interrupt (depends on the PWM output) */
2150 switch (PWMChannel)
2151 {
2152 case HRTIM_OUTPUT_TA1:
2153 case HRTIM_OUTPUT_TB1:
2154 case HRTIM_OUTPUT_TC1:
2155 case HRTIM_OUTPUT_TD1:
2156 case HRTIM_OUTPUT_TE1:
2157 {
2158 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2159 break;
2160 }
2161
2162 case HRTIM_OUTPUT_TA2:
2163 case HRTIM_OUTPUT_TB2:
2164 case HRTIM_OUTPUT_TC2:
2165 case HRTIM_OUTPUT_TD2:
2166 case HRTIM_OUTPUT_TE2:
2167 {
2168 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2169 break;
2170 }
2171
2172 default:
2173 {
2174 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2175
2176 /* Process Unlocked */
2177 __HAL_UNLOCK(hhrtim);
2178
2179 break;
2180 }
2181 }
2182
2183 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2184 {
2185 return HAL_ERROR;
2186 }
2187
2188 /* Disable the timer counter */
2189 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2190
2191 hhrtim->State = HAL_HRTIM_STATE_READY;
2192
2193 /* Process Unlocked */
2194 __HAL_UNLOCK(hhrtim);
2195
2196 return HAL_OK;
2197 }
2198
2199 /**
2200 * @brief Start the PWM output signal generation on the designed timer output
2201 * (The compare DMA request is enabled).
2202 * @param hhrtim pointer to HAL HRTIM handle
2203 * @param TimerIdx Timer index
2204 * This parameter can be one of the following values:
2205 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2206 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2207 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2208 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2209 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2210 * @param PWMChannel Timer output
2211 * This parameter can be one of the following values:
2212 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2213 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2214 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2215 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2216 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2217 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2218 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2219 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2220 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2221 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2222 * @param SrcAddr DMA transfer source address
2223 * @param DestAddr DMA transfer destination address
2224 * @param Length The length of data items (data size) to be transferred
2225 * from source to destination
2226 * @retval HAL status
2227 */
HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)2228 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
2229 uint32_t TimerIdx,
2230 uint32_t PWMChannel,
2231 uint32_t SrcAddr,
2232 uint32_t DestAddr,
2233 uint32_t Length)
2234 {
2235 DMA_HandleTypeDef * hdma;
2236
2237 /* Check the parameters */
2238 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2239
2240 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
2241 {
2242 return HAL_BUSY;
2243 }
2244 if(hhrtim->State == HAL_HRTIM_STATE_READY)
2245 {
2246 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
2247 {
2248 return HAL_ERROR;
2249 }
2250 else
2251 {
2252 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2253 }
2254 }
2255
2256 /* Process Locked */
2257 __HAL_LOCK(hhrtim);
2258
2259 /* Enable the timer output */
2260 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2261
2262 /* Get the timer DMA handler */
2263 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2264
2265 if (hdma == NULL)
2266 {
2267 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2268
2269 /* Process Unlocked */
2270 __HAL_UNLOCK(hhrtim);
2271
2272 return HAL_ERROR;
2273 }
2274
2275 /* Set the DMA error callback */
2276 hdma->XferErrorCallback = HRTIM_DMAError ;
2277
2278 /* Set the DMA transfer completed callback */
2279 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
2280
2281 /* Enable the DMA channel */
2282 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
2283 {
2284 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2285
2286 /* Process Unlocked */
2287 __HAL_UNLOCK(hhrtim);
2288
2289 return HAL_ERROR;
2290 }
2291
2292 /* Enable the timer DMA request */
2293 switch (PWMChannel)
2294 {
2295 case HRTIM_OUTPUT_TA1:
2296 case HRTIM_OUTPUT_TB1:
2297 case HRTIM_OUTPUT_TC1:
2298 case HRTIM_OUTPUT_TD1:
2299 case HRTIM_OUTPUT_TE1:
2300 {
2301 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2302 break;
2303 }
2304
2305 case HRTIM_OUTPUT_TA2:
2306 case HRTIM_OUTPUT_TB2:
2307 case HRTIM_OUTPUT_TC2:
2308 case HRTIM_OUTPUT_TD2:
2309 case HRTIM_OUTPUT_TE2:
2310 {
2311 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2312 break;
2313 }
2314
2315 default:
2316 {
2317 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2318
2319 /* Process Unlocked */
2320 __HAL_UNLOCK(hhrtim);
2321
2322 break;
2323 }
2324 }
2325
2326 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2327 {
2328 return HAL_ERROR;
2329 }
2330
2331 /* Enable the timer counter */
2332 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2333
2334 hhrtim->State = HAL_HRTIM_STATE_READY;
2335
2336 /* Process Unlocked */
2337 __HAL_UNLOCK(hhrtim);
2338
2339 return HAL_OK;
2340 }
2341
2342 /**
2343 * @brief Stop the PWM output signal generation on the designed timer output
2344 * (The compare DMA request is disabled).
2345 * @param hhrtim pointer to HAL HRTIM handle
2346 * @param TimerIdx Timer index
2347 * This parameter can be one of the following values:
2348 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2349 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2350 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2351 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2352 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2353 * @param PWMChannel Timer output
2354 * This parameter can be one of the following values:
2355 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2356 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2357 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2358 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2359 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2360 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2361 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2362 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2363 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2364 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2365 * @retval HAL status
2366 */
HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2367 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
2368 uint32_t TimerIdx,
2369 uint32_t PWMChannel)
2370 {
2371 /* Check the parameters */
2372 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2373
2374 /* Process Locked */
2375 __HAL_LOCK(hhrtim);
2376
2377 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2378
2379 /* Disable the timer output */
2380 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2381
2382 /* Get the timer DMA handler */
2383 /* Disable the DMA */
2384 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
2385 {
2386 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2387
2388 /* Process Unlocked */
2389 __HAL_UNLOCK(hhrtim);
2390
2391 return HAL_ERROR;
2392 }
2393
2394 /* Disable the timer DMA request */
2395 switch (PWMChannel)
2396 {
2397 case HRTIM_OUTPUT_TA1:
2398 case HRTIM_OUTPUT_TB1:
2399 case HRTIM_OUTPUT_TC1:
2400 case HRTIM_OUTPUT_TD1:
2401 case HRTIM_OUTPUT_TE1:
2402 {
2403 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2404 break;
2405 }
2406
2407 case HRTIM_OUTPUT_TA2:
2408 case HRTIM_OUTPUT_TB2:
2409 case HRTIM_OUTPUT_TC2:
2410 case HRTIM_OUTPUT_TD2:
2411 case HRTIM_OUTPUT_TE2:
2412 {
2413 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2414 break;
2415 }
2416
2417 default:
2418 {
2419 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2420
2421 /* Process Unlocked */
2422 __HAL_UNLOCK(hhrtim);
2423
2424 break;
2425 }
2426 }
2427
2428 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2429 {
2430 return HAL_ERROR;
2431 }
2432
2433 /* Disable the timer counter */
2434 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2435
2436 hhrtim->State = HAL_HRTIM_STATE_READY;
2437
2438 /* Process Unlocked */
2439 __HAL_UNLOCK(hhrtim);
2440
2441 return HAL_OK;
2442 }
2443
2444 /**
2445 * @}
2446 */
2447
2448 /** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions
2449 * @brief Simple input capture functions
2450 @verbatim
2451 ===============================================================================
2452 ##### Simple input capture functions #####
2453 ===============================================================================
2454 [..] This section provides functions allowing to:
2455 (+) Configure simple input capture channel
2456 (+) Start simple input capture
2457 (+) Stop simple input capture
2458 (+) Start simple input capture and enable interrupt
2459 (+) Stop simple input capture and disable interrupt
2460 (+) Start simple input capture and enable DMA transfer
2461 (+) Stop simple input capture and disable DMA transfer
2462 -@- When a HRTIM timer operates in simple input capture mode
2463 the Capture Register (HRTIM_CPT1/2xR) is used to latch the
2464 value of the timer counter counter after a transition detected
2465 on a given external event input.
2466 @endverbatim
2467 * @{
2468 */
2469
2470 /**
2471 * @brief Configure a simple capture
2472 * @param hhrtim pointer to HAL HRTIM handle
2473 * @param TimerIdx Timer index
2474 * This parameter can be one of the following values:
2475 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2476 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2477 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2478 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2479 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2480 * @param CaptureChannel Capture unit
2481 * This parameter can be one of the following values:
2482 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2483 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2484 * @param pSimpleCaptureChannelCfg pointer to the simple capture configuration structure
2485 * @note When the timer operates in simple capture mode the capture is triggered
2486 * by the designated external event and GPIO input is implicitly used as event source.
2487 * The cature can be triggered by a rising edge, a falling edge or both
2488 * edges on event channel.
2489 * @retval HAL status
2490 */
HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel,const HRTIM_SimpleCaptureChannelCfgTypeDef * pSimpleCaptureChannelCfg)2491 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,
2492 uint32_t TimerIdx,
2493 uint32_t CaptureChannel,
2494 const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg)
2495 {
2496 HRTIM_EventCfgTypeDef EventCfg;
2497
2498 /* Check parameters */
2499 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2500 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2501 assert_param(IS_HRTIM_EVENT(pSimpleCaptureChannelCfg->Event));
2502 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleCaptureChannelCfg->EventSensitivity,
2503 pSimpleCaptureChannelCfg->EventPolarity));
2504 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleCaptureChannelCfg->EventSensitivity));
2505 assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event,
2506 pSimpleCaptureChannelCfg->EventFilter));
2507
2508 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
2509 {
2510 return HAL_BUSY;
2511 }
2512
2513 /* Process Locked */
2514 __HAL_LOCK(hhrtim);
2515
2516 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2517
2518 /* Configure external event channel */
2519 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
2520 EventCfg.Filter = (pSimpleCaptureChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
2521 EventCfg.Polarity = (pSimpleCaptureChannelCfg->EventPolarity & HRTIM_EECR1_EE1POL);
2522 EventCfg.Sensitivity = (pSimpleCaptureChannelCfg->EventSensitivity & HRTIM_EECR1_EE1SNS);
2523 EventCfg.Source = HRTIM_EVENTSRC_1;
2524
2525 HRTIM_EventConfig(hhrtim,
2526 pSimpleCaptureChannelCfg->Event,
2527 &EventCfg);
2528
2529 /* Memorize capture trigger (will be configured when the capture is started */
2530 HRTIM_CaptureUnitConfig(hhrtim,
2531 TimerIdx,
2532 CaptureChannel,
2533 pSimpleCaptureChannelCfg->Event);
2534
2535 hhrtim->State = HAL_HRTIM_STATE_READY;
2536
2537 /* Process Unlocked */
2538 __HAL_UNLOCK(hhrtim);
2539
2540 return HAL_OK;
2541 }
2542
2543 /**
2544 * @brief Enable a simple capture on the designed capture unit
2545 * @param hhrtim pointer to HAL HRTIM handle
2546 * @param TimerIdx Timer index
2547 * This parameter can be one of the following values:
2548 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2549 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2550 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2551 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2552 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2553 * @param CaptureChannel Timer output
2554 * This parameter can be one of the following values:
2555 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2556 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2557 * @retval HAL status
2558 * @note The external event triggering the capture is available for all timing
2559 * units. It can be used directly and is active as soon as the timing
2560 * unit counter is enabled.
2561 */
HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2562 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,
2563 uint32_t TimerIdx,
2564 uint32_t CaptureChannel)
2565 {
2566 /* Check the parameters */
2567 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2568 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2569
2570 /* Process Locked */
2571 __HAL_LOCK(hhrtim);
2572
2573 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2574
2575 /* Set the capture unit trigger */
2576 switch (CaptureChannel)
2577 {
2578 case HRTIM_CAPTUREUNIT_1:
2579 {
2580 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2581 break;
2582 }
2583
2584 case HRTIM_CAPTUREUNIT_2:
2585 {
2586 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2587 break;
2588 }
2589
2590 default:
2591 {
2592 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2593
2594 /* Process Unlocked */
2595 __HAL_UNLOCK(hhrtim);
2596
2597 break;
2598 }
2599 }
2600
2601 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2602 {
2603 return HAL_ERROR;
2604 }
2605
2606 /* Enable the timer counter */
2607 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2608
2609 hhrtim->State = HAL_HRTIM_STATE_READY;
2610
2611 /* Process Unlocked */
2612 __HAL_UNLOCK(hhrtim);
2613
2614 return HAL_OK;
2615 }
2616
2617 /**
2618 * @brief Disable a simple capture on the designed capture unit
2619 * @param hhrtim pointer to HAL HRTIM handle
2620 * @param TimerIdx Timer index
2621 * This parameter can be one of the following values:
2622 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2623 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2624 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2625 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2626 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2627 * @param CaptureChannel Timer output
2628 * This parameter can be one of the following values:
2629 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2630 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2631 * @retval HAL status
2632 */
HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2633 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,
2634 uint32_t TimerIdx,
2635 uint32_t CaptureChannel)
2636 {
2637 uint32_t hrtim_cpt1cr;
2638 uint32_t hrtim_cpt2cr;
2639
2640 /* Check the parameters */
2641 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2642 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2643
2644 /* Process Locked */
2645 __HAL_LOCK(hhrtim);
2646
2647 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2648
2649 /* Set the capture unit trigger */
2650 switch (CaptureChannel)
2651 {
2652 case HRTIM_CAPTUREUNIT_1:
2653 {
2654 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2655 break;
2656 }
2657
2658 case HRTIM_CAPTUREUNIT_2:
2659 {
2660 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2661 break;
2662 }
2663
2664 default:
2665 {
2666 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2667
2668 /* Process Unlocked */
2669 __HAL_UNLOCK(hhrtim);
2670
2671 break;
2672 }
2673 }
2674
2675 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2676 {
2677 return HAL_ERROR;
2678 }
2679
2680 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
2681 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
2682
2683 /* Disable the timer counter */
2684 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
2685 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
2686 {
2687 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2688 }
2689
2690 hhrtim->State = HAL_HRTIM_STATE_READY;
2691
2692 /* Process Unlocked */
2693 __HAL_UNLOCK(hhrtim);
2694
2695 return HAL_OK;
2696 }
2697
2698 /**
2699 * @brief Enable a simple capture on the designed capture unit
2700 * (Capture interrupt is enabled).
2701 * @param hhrtim pointer to HAL HRTIM handle
2702 * @param TimerIdx Timer index
2703 * This parameter can be one of the following values:
2704 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2705 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2706 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2707 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2708 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2709 * @param CaptureChannel Timer output
2710 * This parameter can be one of the following values:
2711 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2712 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2713 * @retval HAL status
2714 */
HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2715 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,
2716 uint32_t TimerIdx,
2717 uint32_t CaptureChannel)
2718 {
2719 /* Check the parameters */
2720 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2721 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2722
2723 /* Process Locked */
2724 __HAL_LOCK(hhrtim);
2725
2726 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2727
2728 /* Set the capture unit trigger */
2729 switch (CaptureChannel)
2730 {
2731 case HRTIM_CAPTUREUNIT_1:
2732 {
2733 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2734
2735 /* Enable the capture unit 1 interrupt */
2736 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
2737 break;
2738 }
2739
2740 case HRTIM_CAPTUREUNIT_2:
2741 {
2742 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2743
2744 /* Enable the capture unit 2 interrupt */
2745 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
2746 break;
2747 }
2748
2749 default:
2750 {
2751 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2752
2753 /* Process Unlocked */
2754 __HAL_UNLOCK(hhrtim);
2755
2756 break;
2757 }
2758 }
2759
2760 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2761 {
2762 return HAL_ERROR;
2763 }
2764
2765 /* Enable the timer counter */
2766 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2767
2768 hhrtim->State = HAL_HRTIM_STATE_READY;
2769
2770 /* Process Unlocked */
2771 __HAL_UNLOCK(hhrtim);
2772
2773 return HAL_OK;
2774 }
2775
2776 /**
2777 * @brief Disable a simple capture on the designed capture unit
2778 * (Capture interrupt is disabled).
2779 * @param hhrtim pointer to HAL HRTIM handle
2780 * @param TimerIdx Timer index
2781 * This parameter can be one of the following values:
2782 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2783 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2784 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2785 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2786 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2787 * @param CaptureChannel Timer output
2788 * This parameter can be one of the following values:
2789 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2790 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2791 * @retval HAL status
2792 */
HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2793 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,
2794 uint32_t TimerIdx,
2795 uint32_t CaptureChannel)
2796 {
2797
2798 uint32_t hrtim_cpt1cr;
2799 uint32_t hrtim_cpt2cr;
2800
2801 /* Check the parameters */
2802 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2803 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2804
2805 /* Process Locked */
2806 __HAL_LOCK(hhrtim);
2807
2808 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2809
2810 /* Set the capture unit trigger */
2811 switch (CaptureChannel)
2812 {
2813 case HRTIM_CAPTUREUNIT_1:
2814 {
2815 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2816
2817 /* Disable the capture unit 1 interrupt */
2818 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
2819 break;
2820 }
2821
2822 case HRTIM_CAPTUREUNIT_2:
2823 {
2824 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2825
2826 /* Disable the capture unit 2 interrupt */
2827 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
2828 break;
2829 }
2830
2831 default:
2832 {
2833 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2834
2835 /* Process Unlocked */
2836 __HAL_UNLOCK(hhrtim);
2837
2838 break;
2839 }
2840 }
2841
2842 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2843 {
2844 return HAL_ERROR;
2845 }
2846
2847 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
2848 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
2849
2850 /* Disable the timer counter */
2851 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
2852 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
2853 {
2854 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2855 }
2856
2857 hhrtim->State = HAL_HRTIM_STATE_READY;
2858
2859 /* Process Unlocked */
2860 __HAL_UNLOCK(hhrtim);
2861
2862 return HAL_OK;
2863 }
2864
2865 /**
2866 * @brief Enable a simple capture on the designed capture unit
2867 * (Capture DMA request is enabled).
2868 * @param hhrtim pointer to HAL HRTIM handle
2869 * @param TimerIdx Timer index
2870 * This parameter can be one of the following values:
2871 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2872 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2873 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2874 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2875 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2876 * @param CaptureChannel Timer output
2877 * This parameter can be one of the following values:
2878 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2879 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2880 * @param SrcAddr DMA transfer source address
2881 * @param DestAddr DMA transfer destination address
2882 * @param Length The length of data items (data size) to be transferred
2883 * from source to destination
2884 * @retval HAL status
2885 */
HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)2886 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,
2887 uint32_t TimerIdx,
2888 uint32_t CaptureChannel,
2889 uint32_t SrcAddr,
2890 uint32_t DestAddr,
2891 uint32_t Length)
2892 {
2893 DMA_HandleTypeDef * hdma;
2894
2895 /* Check the parameters */
2896 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2897 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2898
2899 /* Process Locked */
2900 __HAL_LOCK(hhrtim);
2901
2902 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2903
2904 /* Get the timer DMA handler */
2905 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2906
2907 if (hdma == NULL)
2908 {
2909 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2910
2911 /* Process Unlocked */
2912 __HAL_UNLOCK(hhrtim);
2913
2914 return HAL_ERROR;
2915 }
2916
2917 /* Set the DMA error callback */
2918 hdma->XferErrorCallback = HRTIM_DMAError ;
2919
2920 /* Set the DMA transfer completed callback */
2921 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
2922
2923 /* Enable the DMA channel */
2924 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
2925 {
2926 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2927
2928 /* Process Unlocked */
2929 __HAL_UNLOCK(hhrtim);
2930
2931 return HAL_ERROR;
2932 }
2933
2934 switch (CaptureChannel)
2935 {
2936 case HRTIM_CAPTUREUNIT_1:
2937 {
2938 /* Set the capture unit trigger */
2939 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2940
2941 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
2942 break;
2943 }
2944
2945 case HRTIM_CAPTUREUNIT_2:
2946 {
2947 /* Set the capture unit trigger */
2948 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2949
2950 /* Enable the timer DMA request */
2951 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
2952 break;
2953 }
2954
2955 default:
2956 {
2957 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2958
2959 /* Process Unlocked */
2960 __HAL_UNLOCK(hhrtim);
2961
2962 break;
2963 }
2964 }
2965
2966 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2967 {
2968 return HAL_ERROR;
2969 }
2970
2971 /* Enable the timer counter */
2972 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2973
2974 hhrtim->State = HAL_HRTIM_STATE_READY;
2975
2976 /* Process Unlocked */
2977 __HAL_UNLOCK(hhrtim);
2978
2979 return HAL_OK;
2980 }
2981
2982 /**
2983 * @brief Disable a simple capture on the designed capture unit
2984 * (Capture DMA request is disabled).
2985 * @param hhrtim pointer to HAL HRTIM handle
2986 * @param TimerIdx Timer index
2987 * This parameter can be one of the following values:
2988 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2989 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2990 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2991 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2992 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2993 * @param CaptureChannel Timer output
2994 * This parameter can be one of the following values:
2995 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2996 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2997 * @retval HAL status
2998 */
HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2999 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
3000 uint32_t TimerIdx,
3001 uint32_t CaptureChannel)
3002 {
3003
3004 uint32_t hrtim_cpt1cr;
3005 uint32_t hrtim_cpt2cr;
3006
3007 /* Check the parameters */
3008 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3009 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
3010
3011 /* Process Locked */
3012 __HAL_LOCK(hhrtim);
3013
3014 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3015
3016 /* Get the timer DMA handler */
3017 /* Disable the DMA */
3018 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
3019 {
3020 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3021
3022 /* Process Unlocked */
3023 __HAL_UNLOCK(hhrtim);
3024
3025 return HAL_ERROR;
3026 }
3027
3028 switch (CaptureChannel)
3029 {
3030 case HRTIM_CAPTUREUNIT_1:
3031 {
3032 /* Reset the capture unit trigger */
3033 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
3034
3035 /* Disable the capture unit 1 DMA request */
3036 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
3037 break;
3038 }
3039
3040 case HRTIM_CAPTUREUNIT_2:
3041 {
3042 /* Reset the capture unit trigger */
3043 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
3044
3045 /* Disable the capture unit 2 DMA request */
3046 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
3047 break;
3048 }
3049
3050 default:
3051 {
3052 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3053
3054 /* Process Unlocked */
3055 __HAL_UNLOCK(hhrtim);
3056
3057 break;
3058 }
3059 }
3060
3061 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3062 {
3063 return HAL_ERROR;
3064 }
3065
3066 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
3067 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
3068
3069 /* Disable the timer counter */
3070 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
3071 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
3072 {
3073 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3074 }
3075
3076 hhrtim->State = HAL_HRTIM_STATE_READY;
3077
3078 /* Process Unlocked */
3079 __HAL_UNLOCK(hhrtim);
3080
3081 return HAL_OK;
3082 }
3083
3084 /**
3085 * @}
3086 */
3087
3088 /** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
3089 * @brief Simple one pulse functions
3090 @verbatim
3091 ===============================================================================
3092 ##### Simple one pulse functions #####
3093 ===============================================================================
3094 [..] This section provides functions allowing to:
3095 (+) Configure one pulse channel
3096 (+) Start one pulse generation
3097 (+) Stop one pulse generation
3098 (+) Start one pulse generation and enable interrupt
3099 (+) Stop one pulse generation and disable interrupt
3100 -@- When a HRTIM timer operates in simple one pulse mode
3101 the timer counter is started in response to transition detected
3102 on a given external event input to generate a pulse with a
3103 programmable length after a programmable delay.
3104 @endverbatim
3105 * @{
3106 */
3107
3108 /**
3109 * @brief Configure an output simple one pulse mode
3110 * @param hhrtim pointer to HAL HRTIM handle
3111 * @param TimerIdx Timer index
3112 * This parameter can be one of the following values:
3113 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3114 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3115 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3116 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3117 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3118 * @param OnePulseChannel Timer output
3119 * This parameter can be one of the following values:
3120 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3121 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3122 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3123 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3124 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3125 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3126 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3127 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3128 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3129 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3130 * @param pSimpleOnePulseChannelCfg pointer to the simple one pulse output configuration structure
3131 * @note When the timer operates in simple one pulse mode:
3132 * the timer counter is implicitly started by the reset event,
3133 * the reset of the timer counter is triggered by the designated external event
3134 * GPIO input is implicitly used as event source,
3135 * Output 1 is implicitly controlled by the compare unit 1,
3136 * Output 2 is implicitly controlled by the compare unit 2.
3137 * Output Set/Reset crossbar is set as follows:
3138 * Output 1: SETx1R = CMP1, RSTx1R = PER
3139 * Output 2: SETx2R = CMP2, RST2R = PER
3140 * @retval HAL status
3141 * @note If HAL_HRTIM_SimpleOnePulseChannelConfig is called for both timer
3142 * outputs, the reset event related configuration data provided in the
3143 * second call will override the reset event related configuration data
3144 * provided in the first call.
3145 */
HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel,const HRTIM_SimpleOnePulseChannelCfgTypeDef * pSimpleOnePulseChannelCfg)3146 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,
3147 uint32_t TimerIdx,
3148 uint32_t OnePulseChannel,
3149 const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg)
3150 {
3151 HRTIM_OutputCfgTypeDef OutputCfg;
3152 HRTIM_EventCfgTypeDef EventCfg;
3153
3154 /* Check parameters */
3155 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3156 assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOnePulseChannelCfg->Pulse));
3157 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOnePulseChannelCfg->OutputPolarity));
3158 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOnePulseChannelCfg->OutputIdleLevel));
3159 assert_param(IS_HRTIM_EVENT(pSimpleOnePulseChannelCfg->Event));
3160 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleOnePulseChannelCfg->EventSensitivity,
3161 pSimpleOnePulseChannelCfg->EventPolarity));
3162 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleOnePulseChannelCfg->EventSensitivity));
3163 assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event,
3164 pSimpleOnePulseChannelCfg->EventFilter));
3165
3166 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3167 {
3168 return HAL_BUSY;
3169 }
3170
3171 /* Process Locked */
3172 __HAL_LOCK(hhrtim);
3173
3174 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3175
3176 /* Configure timer compare unit */
3177 switch (OnePulseChannel)
3178 {
3179 case HRTIM_OUTPUT_TA1:
3180 case HRTIM_OUTPUT_TB1:
3181 case HRTIM_OUTPUT_TC1:
3182 case HRTIM_OUTPUT_TD1:
3183 case HRTIM_OUTPUT_TE1:
3184 {
3185 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOnePulseChannelCfg->Pulse;
3186 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
3187 break;
3188 }
3189
3190 case HRTIM_OUTPUT_TA2:
3191 case HRTIM_OUTPUT_TB2:
3192 case HRTIM_OUTPUT_TC2:
3193 case HRTIM_OUTPUT_TD2:
3194 case HRTIM_OUTPUT_TE2:
3195 {
3196 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOnePulseChannelCfg->Pulse;
3197 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
3198 break;
3199 }
3200
3201 default:
3202 {
3203 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
3204 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
3205
3206 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3207
3208 /* Process Unlocked */
3209 __HAL_UNLOCK(hhrtim);
3210
3211 break;
3212 }
3213 }
3214
3215 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3216 {
3217 return HAL_ERROR;
3218 }
3219
3220 /* Configure timer output */
3221 OutputCfg.Polarity = (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1);
3222 OutputCfg.IdleLevel = (pSimpleOnePulseChannelCfg->OutputIdleLevel & HRTIM_OUTR_IDLES1);
3223 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
3224 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
3225 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
3226 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
3227 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
3228
3229 HRTIM_OutputConfig(hhrtim,
3230 TimerIdx,
3231 OnePulseChannel,
3232 &OutputCfg);
3233
3234 /* Configure external event channel */
3235 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
3236 EventCfg.Filter = (pSimpleOnePulseChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
3237 EventCfg.Polarity = (pSimpleOnePulseChannelCfg->EventPolarity & HRTIM_OUTR_POL1);
3238 EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity &HRTIM_EECR1_EE1SNS);
3239 EventCfg.Source = HRTIM_EVENTSRC_1;
3240
3241 HRTIM_EventConfig(hhrtim,
3242 pSimpleOnePulseChannelCfg->Event,
3243 &EventCfg);
3244
3245 /* Configure the timer reset register */
3246 HRTIM_TIM_ResetConfig(hhrtim,
3247 TimerIdx,
3248 pSimpleOnePulseChannelCfg->Event);
3249
3250 hhrtim->State = HAL_HRTIM_STATE_READY;
3251
3252 /* Process Unlocked */
3253 __HAL_UNLOCK(hhrtim);
3254
3255 return HAL_OK;
3256 }
3257
3258 /**
3259 * @brief Enable the simple one pulse signal generation on the designed output
3260 * @param hhrtim pointer to HAL HRTIM handle
3261 * @param TimerIdx Timer index
3262 * This parameter can be one of the following values:
3263 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3264 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3265 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3266 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3267 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3268 * @param OnePulseChannel Timer output
3269 * This parameter can be one of the following values:
3270 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3271 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3272 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3273 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3274 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3275 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3276 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3277 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3278 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3279 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3280 * @retval HAL status
3281 */
HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3282 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,
3283 uint32_t TimerIdx,
3284 uint32_t OnePulseChannel)
3285 {
3286 /* Check the parameters */
3287 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3288
3289 /* Process Locked */
3290 __HAL_LOCK(hhrtim);
3291
3292 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3293
3294 /* Enable the timer output */
3295 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3296
3297 /* Enable the timer counter */
3298 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3299
3300 hhrtim->State = HAL_HRTIM_STATE_READY;
3301
3302 /* Process Unlocked */
3303 __HAL_UNLOCK(hhrtim);
3304
3305 return HAL_OK;
3306 }
3307
3308 /**
3309 * @brief Disable the simple one pulse signal generation on the designed output
3310 * @param hhrtim pointer to HAL HRTIM handle
3311 * @param TimerIdx Timer index
3312 * This parameter can be one of the following values:
3313 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3314 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3315 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3316 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3317 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3318 * @param OnePulseChannel Timer output
3319 * This parameter can be one of the following values:
3320 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3321 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3322 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3323 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3324 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3325 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3326 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3327 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3328 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3329 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3330 * @retval HAL status
3331 */
HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3332 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,
3333 uint32_t TimerIdx,
3334 uint32_t OnePulseChannel)
3335 {
3336 /* Check the parameters */
3337 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3338
3339 /* Process Locked */
3340 __HAL_LOCK(hhrtim);
3341
3342 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3343
3344 /* Disable the timer output */
3345 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3346
3347 /* Disable the timer counter */
3348 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3349
3350 hhrtim->State = HAL_HRTIM_STATE_READY;
3351
3352 /* Process Unlocked */
3353 __HAL_UNLOCK(hhrtim);
3354
3355 return HAL_OK;
3356 }
3357
3358 /**
3359 * @brief Enable the simple one pulse signal generation on the designed output
3360 * (The compare interrupt is enabled (pulse start)).
3361 * @param hhrtim pointer to HAL HRTIM handle
3362 * @param TimerIdx Timer index
3363 * This parameter can be one of the following values:
3364 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3365 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3366 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3367 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3368 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3369 * @param OnePulseChannel Timer output
3370 * This parameter can be one of the following values:
3371 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3372 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3373 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3374 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3375 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3376 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3377 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3378 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3379 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3380 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3381 * @retval HAL status
3382 */
HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3383 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,
3384 uint32_t TimerIdx,
3385 uint32_t OnePulseChannel)
3386 {
3387 /* Check the parameters */
3388 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3389
3390 /* Process Locked */
3391 __HAL_LOCK(hhrtim);
3392
3393 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3394
3395 /* Enable the timer output */
3396 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3397
3398 /* Enable the timer interrupt (depends on the OnePulse output) */
3399 switch (OnePulseChannel)
3400 {
3401 case HRTIM_OUTPUT_TA1:
3402 case HRTIM_OUTPUT_TB1:
3403 case HRTIM_OUTPUT_TC1:
3404 case HRTIM_OUTPUT_TD1:
3405 case HRTIM_OUTPUT_TE1:
3406 {
3407 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3408 break;
3409 }
3410
3411 case HRTIM_OUTPUT_TA2:
3412 case HRTIM_OUTPUT_TB2:
3413 case HRTIM_OUTPUT_TC2:
3414 case HRTIM_OUTPUT_TD2:
3415 case HRTIM_OUTPUT_TE2:
3416 {
3417 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3418 break;
3419 }
3420
3421 default:
3422 {
3423 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3424
3425 /* Process Unlocked */
3426 __HAL_UNLOCK(hhrtim);
3427
3428 break;
3429 }
3430 }
3431
3432 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3433 {
3434 return HAL_ERROR;
3435 }
3436
3437 /* Enable the timer counter */
3438 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3439
3440 hhrtim->State = HAL_HRTIM_STATE_READY;
3441
3442 /* Process Unlocked */
3443 __HAL_UNLOCK(hhrtim);
3444
3445 return HAL_OK;
3446 }
3447
3448 /**
3449 * @brief Disable the simple one pulse signal generation on the designed output
3450 * (The compare interrupt is disabled).
3451 * @param hhrtim pointer to HAL HRTIM handle
3452 * @param TimerIdx Timer index
3453 * This parameter can be one of the following values:
3454 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3455 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3456 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3457 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3458 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3459 * @param OnePulseChannel Timer output
3460 * This parameter can be one of the following values:
3461 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3462 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3463 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3464 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3465 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3466 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3467 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3468 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3469 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3470 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3471 * @retval HAL status
3472 */
HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3473 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,
3474 uint32_t TimerIdx,
3475 uint32_t OnePulseChannel)
3476 {
3477 /* Check the parameters */
3478 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3479
3480 /* Process Locked */
3481 __HAL_LOCK(hhrtim);
3482
3483 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3484
3485 /* Disable the timer output */
3486 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3487
3488 /* Disable the timer interrupt (depends on the OnePulse output) */
3489 switch (OnePulseChannel)
3490 {
3491 case HRTIM_OUTPUT_TA1:
3492 case HRTIM_OUTPUT_TB1:
3493 case HRTIM_OUTPUT_TC1:
3494 case HRTIM_OUTPUT_TD1:
3495 case HRTIM_OUTPUT_TE1:
3496 {
3497 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3498 break;
3499 }
3500
3501 case HRTIM_OUTPUT_TA2:
3502 case HRTIM_OUTPUT_TB2:
3503 case HRTIM_OUTPUT_TC2:
3504 case HRTIM_OUTPUT_TD2:
3505 case HRTIM_OUTPUT_TE2:
3506 {
3507 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3508 break;
3509 }
3510
3511 default:
3512 {
3513 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3514
3515 /* Process Unlocked */
3516 __HAL_UNLOCK(hhrtim);
3517
3518 break;
3519 }
3520 }
3521
3522 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3523 {
3524 return HAL_ERROR;
3525 }
3526
3527 /* Disable the timer counter */
3528 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3529
3530 hhrtim->State = HAL_HRTIM_STATE_READY;
3531
3532 /* Process Unlocked */
3533 __HAL_UNLOCK(hhrtim);
3534
3535 return HAL_OK;
3536 }
3537
3538 /**
3539 * @}
3540 */
3541
3542 /** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions
3543 * @brief HRTIM configuration functions
3544 @verbatim
3545 ===============================================================================
3546 ##### HRTIM configuration functions #####
3547 ===============================================================================
3548 [..] This section provides functions allowing to configure the HRTIM
3549 resources shared by all the HRTIM timers operating in waveform mode:
3550 (+) Configure the burst mode controller
3551 (+) Configure an external event conditioning
3552 (+) Configure the external events sampling clock
3553 (+) Configure a fault conditioning
3554 (+) Enable or disable fault inputs
3555 (+) Configure the faults sampling clock
3556 (+) Configure an ADC trigger
3557
3558 @endverbatim
3559 * @{
3560 */
3561
3562 /**
3563 * @brief Configure the burst mode feature of the HRTIM
3564 * @param hhrtim pointer to HAL HRTIM handle
3565 * @param pBurstModeCfg pointer to the burst mode configuration structure
3566 * @retval HAL status
3567 * @note This function must be called before starting the burst mode
3568 * controller
3569 */
HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,const HRTIM_BurstModeCfgTypeDef * pBurstModeCfg)3570 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
3571 const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
3572 {
3573 uint32_t hrtim_bmcr;
3574
3575 /* Check parameters */
3576 assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
3577 assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
3578 assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
3579 assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
3580 assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger));
3581
3582 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3583 {
3584 return HAL_BUSY;
3585 }
3586
3587 /* Process Locked */
3588 __HAL_LOCK(hhrtim);
3589
3590 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3591
3592 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
3593
3594 /* Set the burst mode operating mode */
3595 hrtim_bmcr &= ~(HRTIM_BMCR_BMOM);
3596 hrtim_bmcr |= (pBurstModeCfg->Mode & HRTIM_BMCR_BMOM);
3597
3598 /* Set the burst mode clock source */
3599 hrtim_bmcr &= ~(HRTIM_BMCR_BMCLK);
3600 hrtim_bmcr |= (pBurstModeCfg->ClockSource & HRTIM_BMCR_BMCLK);
3601
3602 /* Set the burst mode prescaler */
3603 hrtim_bmcr &= ~(HRTIM_BMCR_BMPRSC);
3604 hrtim_bmcr |= pBurstModeCfg->Prescaler;
3605
3606 /* Enable/disable burst mode registers preload */
3607 hrtim_bmcr &= ~(HRTIM_BMCR_BMPREN);
3608 hrtim_bmcr |= (pBurstModeCfg->PreloadEnable & HRTIM_BMCR_BMPREN);
3609
3610 /* Set the burst mode trigger */
3611 hhrtim->Instance->sCommonRegs.BMTRGR = pBurstModeCfg->Trigger;
3612
3613 /* Set the burst mode compare value */
3614 hhrtim->Instance->sCommonRegs.BMCMPR = pBurstModeCfg->IdleDuration;
3615
3616 /* Set the burst mode period */
3617 hhrtim->Instance->sCommonRegs.BMPER = pBurstModeCfg->Period;
3618
3619 /* Update the HRTIM registers */
3620 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
3621
3622 hhrtim->State = HAL_HRTIM_STATE_READY;
3623
3624 /* Process Unlocked */
3625 __HAL_UNLOCK(hhrtim);
3626
3627 return HAL_OK;
3628 }
3629
3630 /**
3631 * @brief Configure the conditioning of an external event
3632 * @param hhrtim pointer to HAL HRTIM handle
3633 * @param Event external event to configure
3634 * This parameter can be one of the following values:
3635 * @arg HRTIM_EVENT_NONE: no external Event
3636 * @arg HRTIM_EVENT_1: External event 1
3637 * @arg HRTIM_EVENT_2: External event 2
3638 * @arg HRTIM_EVENT_3: External event 3
3639 * @arg HRTIM_EVENT_4: External event 4
3640 * @arg HRTIM_EVENT_5: External event 5
3641 * @arg HRTIM_EVENT_6: External event 6
3642 * @arg HRTIM_EVENT_7: External event 7
3643 * @arg HRTIM_EVENT_8: External event 8
3644 * @arg HRTIM_EVENT_9: External event 9
3645 * @arg HRTIM_EVENT_10: External event 10
3646 * @param pEventCfg pointer to the event conditioning configuration structure
3647 * @note This function must be called before starting the timer
3648 * @retval HAL status
3649 */
HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Event,const HRTIM_EventCfgTypeDef * pEventCfg)3650 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
3651 uint32_t Event,
3652 const HRTIM_EventCfgTypeDef* pEventCfg)
3653 {
3654 /* Check parameters */
3655 assert_param(IS_HRTIM_EVENT(Event));
3656 assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
3657 assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
3658 assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
3659 assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
3660 assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
3661
3662 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3663 {
3664 return HAL_BUSY;
3665 }
3666
3667 /* Process Locked */
3668 __HAL_LOCK(hhrtim);
3669
3670 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3671
3672 /* Configure the event channel */
3673 HRTIM_EventConfig(hhrtim, Event, pEventCfg);
3674
3675 hhrtim->State = HAL_HRTIM_STATE_READY;
3676
3677 /* Process Unlocked */
3678 __HAL_UNLOCK(hhrtim);
3679
3680 return HAL_OK;
3681 }
3682
3683 /**
3684 * @brief Configure the external event conditioning block prescaler
3685 * @param hhrtim pointer to HAL HRTIM handle
3686 * @param Prescaler Prescaler value
3687 * This parameter can be one of the following values:
3688 * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
3689 * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
3690 * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIM / 4
3691 * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIM / 8
3692 * @note This function must be called before starting the timer
3693 * @retval HAL status
3694 */
HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Prescaler)3695 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
3696 uint32_t Prescaler)
3697 {
3698 /* Check parameters */
3699 assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
3700
3701 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3702 {
3703 return HAL_BUSY;
3704 }
3705
3706 /* Process Locked */
3707 __HAL_LOCK(hhrtim);
3708
3709 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3710
3711 /* Set the external event prescaler */
3712 MODIFY_REG(hhrtim->Instance->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, (Prescaler & HRTIM_EECR3_EEVSD));
3713
3714 hhrtim->State = HAL_HRTIM_STATE_READY;
3715
3716 /* Process Unlocked */
3717 __HAL_UNLOCK(hhrtim);
3718
3719 return HAL_OK;
3720 }
3721
3722 /**
3723 * @brief Configure the conditioning of fault input
3724 * @param hhrtim pointer to HAL HRTIM handle
3725 * @param Fault fault input to configure
3726 * This parameter can be one of the following values:
3727 * @arg HRTIM_FAULT_1: Fault input 1
3728 * @arg HRTIM_FAULT_2: Fault input 2
3729 * @arg HRTIM_FAULT_3: Fault input 3
3730 * @arg HRTIM_FAULT_4: Fault input 4
3731 * @arg HRTIM_FAULT_5: Fault input 5
3732 * @param pFaultCfg pointer to the fault conditioning configuration structure
3733 * @note This function must be called before starting the timer and before
3734 * enabling faults inputs
3735 * @retval HAL status
3736 */
HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Fault,const HRTIM_FaultCfgTypeDef * pFaultCfg)3737 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,
3738 uint32_t Fault,
3739 const HRTIM_FaultCfgTypeDef* pFaultCfg)
3740 {
3741 uint32_t hrtim_fltinr1;
3742 uint32_t hrtim_fltinr2;
3743
3744 /* Check parameters */
3745 assert_param(IS_HRTIM_FAULT(Fault));
3746 assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
3747 assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
3748 assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
3749 assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
3750
3751 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3752 {
3753 return HAL_BUSY;
3754 }
3755
3756 /* Process Locked */
3757 __HAL_LOCK(hhrtim);
3758
3759 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3760
3761 /* Configure fault channel */
3762 hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
3763 hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
3764
3765 switch (Fault)
3766 {
3767 case HRTIM_FAULT_1:
3768 {
3769 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
3770 hrtim_fltinr1 |= (pFaultCfg->Polarity & HRTIM_FLTINR1_FLT1P);
3771 hrtim_fltinr1 |= (pFaultCfg->Source & HRTIM_FLTINR1_FLT1SRC);
3772 hrtim_fltinr1 |= (pFaultCfg->Filter & HRTIM_FLTINR1_FLT1F);
3773 hrtim_fltinr1 |= (pFaultCfg->Lock & HRTIM_FLTINR1_FLT1LCK);
3774 break;
3775 }
3776
3777 case HRTIM_FAULT_2:
3778 {
3779 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
3780 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR1_FLT2P);
3781 hrtim_fltinr1 |= ((pFaultCfg->Source << 8U) & HRTIM_FLTINR1_FLT2SRC);
3782 hrtim_fltinr1 |= ((pFaultCfg->Filter << 8U) & HRTIM_FLTINR1_FLT2F);
3783 hrtim_fltinr1 |= ((pFaultCfg->Lock << 8U) & HRTIM_FLTINR1_FLT2LCK);
3784 break;
3785 }
3786
3787 case HRTIM_FAULT_3:
3788 {
3789 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
3790 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 16U) & HRTIM_FLTINR1_FLT3P);
3791 hrtim_fltinr1 |= ((pFaultCfg->Source << 16U) & HRTIM_FLTINR1_FLT3SRC);
3792 hrtim_fltinr1 |= ((pFaultCfg->Filter << 16U) & HRTIM_FLTINR1_FLT3F);
3793 hrtim_fltinr1 |= ((pFaultCfg->Lock << 16U) & HRTIM_FLTINR1_FLT3LCK);
3794 break;
3795 }
3796
3797 case HRTIM_FAULT_4:
3798 {
3799 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
3800 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 24U) & HRTIM_FLTINR1_FLT4P);
3801 hrtim_fltinr1 |= ((pFaultCfg->Source << 24U) & HRTIM_FLTINR1_FLT4SRC);
3802 hrtim_fltinr1 |= ((pFaultCfg->Filter << 24U) & HRTIM_FLTINR1_FLT4F);
3803 hrtim_fltinr1 |= ((pFaultCfg->Lock << 24U) & HRTIM_FLTINR1_FLT4LCK);
3804 break;
3805 }
3806
3807 case HRTIM_FAULT_5:
3808 {
3809 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
3810 hrtim_fltinr2 |= (pFaultCfg->Polarity & HRTIM_FLTINR2_FLT5P);
3811 hrtim_fltinr2 |= (pFaultCfg->Source & HRTIM_FLTINR2_FLT5SRC);
3812 hrtim_fltinr2 |= (pFaultCfg->Filter & HRTIM_FLTINR2_FLT5F);
3813 hrtim_fltinr2 |= (pFaultCfg->Lock & HRTIM_FLTINR2_FLT5LCK);
3814 break;
3815 }
3816
3817 default:
3818 {
3819 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3820
3821 /* Process Unlocked */
3822 __HAL_UNLOCK(hhrtim);
3823
3824 break;
3825 }
3826 }
3827
3828 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3829 {
3830 return HAL_ERROR;
3831 }
3832
3833 /* Update the HRTIM registers except LOCK bit */
3834 hhrtim->Instance->sCommonRegs.FLTINR1 = (hrtim_fltinr1 & (~(HRTIM_FLTINR1_FLTxLCK)));
3835 hhrtim->Instance->sCommonRegs.FLTINR2 = (hrtim_fltinr2 & (~(HRTIM_FLTINR2_FLTxLCK)));
3836
3837 /* Update the HRTIM registers LOCK bit */
3838 SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1,(hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK));
3839 SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2,(hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK));
3840
3841 hhrtim->State = HAL_HRTIM_STATE_READY;
3842
3843 /* Process Unlocked */
3844 __HAL_UNLOCK(hhrtim);
3845
3846 return HAL_OK;
3847 }
3848
3849 /**
3850 * @brief Configure the fault conditioning block prescaler
3851 * @param hhrtim pointer to HAL HRTIM handle
3852 * @param Prescaler Prescaler value
3853 * This parameter can be one of the following values:
3854 * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
3855 * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
3856 * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIM / 4
3857 * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIM / 8
3858 * @retval HAL status
3859 * @note This function must be called before starting the timer and before
3860 * enabling faults inputs
3861 */
HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Prescaler)3862 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
3863 uint32_t Prescaler)
3864 {
3865 /* Check parameters */
3866 assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
3867
3868 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3869 {
3870 return HAL_BUSY;
3871 }
3872
3873 /* Process Locked */
3874 __HAL_LOCK(hhrtim);
3875
3876 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3877
3878 /* Set the external event prescaler */
3879 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, (Prescaler & HRTIM_FLTINR2_FLTSD));
3880
3881 hhrtim->State = HAL_HRTIM_STATE_READY;
3882
3883 /* Process Unlocked */
3884 __HAL_UNLOCK(hhrtim);
3885
3886 return HAL_OK;
3887 }
3888
3889 /**
3890 * @brief Enable or disables the HRTIMx Fault mode.
3891 * @param hhrtim pointer to HAL HRTIM handle
3892 * @param Faults fault input(s) to enable or disable
3893 * This parameter can be any combination of the following values:
3894 * @arg HRTIM_FAULT_1: Fault input 1
3895 * @arg HRTIM_FAULT_2: Fault input 2
3896 * @arg HRTIM_FAULT_3: Fault input 3
3897 * @arg HRTIM_FAULT_4: Fault input 4
3898 * @arg HRTIM_FAULT_5: Fault input 5
3899 * @param Enable Fault(s) enabling
3900 * This parameter can be one of the following values:
3901 * @arg HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
3902 * @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
3903 * @retval None
3904 */
HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,uint32_t Faults,uint32_t Enable)3905 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
3906 uint32_t Faults,
3907 uint32_t Enable)
3908 {
3909 /* Check parameters */
3910 assert_param(IS_HRTIM_FAULT(Faults));
3911 assert_param(IS_HRTIM_FAULTMODECTL(Enable));
3912
3913 if ((Faults & HRTIM_FAULT_1) != (uint32_t)RESET)
3914 {
3915 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT1E, (Enable & HRTIM_FLTINR1_FLT1E));
3916 }
3917 if ((Faults & HRTIM_FAULT_2) != (uint32_t)RESET)
3918 {
3919 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT2E, ((Enable << 8U) & HRTIM_FLTINR1_FLT2E));
3920 }
3921 if ((Faults & HRTIM_FAULT_3) != (uint32_t)RESET)
3922 {
3923 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT3E, ((Enable << 16U) & HRTIM_FLTINR1_FLT3E));
3924 }
3925 if ((Faults & HRTIM_FAULT_4) != (uint32_t)RESET)
3926 {
3927 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT4E, ((Enable << 24U) & HRTIM_FLTINR1_FLT4E));
3928 }
3929 if ((Faults & HRTIM_FAULT_5) != (uint32_t)RESET)
3930 {
3931 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLT5E, ((Enable) & HRTIM_FLTINR2_FLT5E));
3932 }
3933 }
3934
3935 /**
3936 * @brief Configure both the ADC trigger register update source and the ADC
3937 * trigger source.
3938 * @param hhrtim pointer to HAL HRTIM handle
3939 * @param ADCTrigger ADC trigger to configure
3940 * This parameter can be one of the following values:
3941 * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
3942 * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
3943 * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
3944 * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
3945 * @param pADCTriggerCfg pointer to the ADC trigger configuration structure
3946 * @retval HAL status
3947 * @note This function must be called before starting the timer
3948 */
HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t ADCTrigger,const HRTIM_ADCTriggerCfgTypeDef * pADCTriggerCfg)3949 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
3950 uint32_t ADCTrigger,
3951 const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
3952 {
3953 uint32_t hrtim_cr1;
3954
3955 /* Check parameters */
3956 assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
3957 assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
3958
3959 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3960 {
3961 return HAL_BUSY;
3962 }
3963
3964 /* Process Locked */
3965 __HAL_LOCK(hhrtim);
3966
3967 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3968
3969 /* Set the ADC trigger update source */
3970 hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1;
3971
3972 switch (ADCTrigger)
3973 {
3974 case HRTIM_ADCTRIGGER_1:
3975 {
3976 hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC);
3977 hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC);
3978
3979 /* Set the ADC trigger 1 source */
3980 hhrtim->Instance->sCommonRegs.ADC1R = pADCTriggerCfg->Trigger;
3981 break;
3982 }
3983
3984 case HRTIM_ADCTRIGGER_2:
3985 {
3986 hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
3987 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC);
3988
3989 /* Set the ADC trigger 2 source */
3990 hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
3991 break;
3992 }
3993
3994 case HRTIM_ADCTRIGGER_3:
3995 {
3996 hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
3997 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC);
3998
3999 /* Set the ADC trigger 3 source */
4000 hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
4001 break;
4002 }
4003
4004 case HRTIM_ADCTRIGGER_4:
4005 {
4006 hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
4007 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC);
4008
4009 /* Set the ADC trigger 4 source */
4010 hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
4011 break;
4012 }
4013
4014 default:
4015 {
4016 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4017
4018 /* Process Unlocked */
4019 __HAL_UNLOCK(hhrtim);
4020
4021 break;
4022 }
4023 }
4024
4025 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4026 {
4027 return HAL_ERROR;
4028 }
4029
4030 /* Update the HRTIM registers */
4031 hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1;
4032
4033 hhrtim->State = HAL_HRTIM_STATE_READY;
4034
4035 /* Process Unlocked */
4036 __HAL_UNLOCK(hhrtim);
4037
4038 return HAL_OK;
4039 }
4040
4041
4042 /**
4043 * @}
4044 */
4045
4046 /** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
4047 * @brief HRTIM timer configuration and control functions
4048 @verbatim
4049 ===============================================================================
4050 ##### HRTIM timer configuration and control functions #####
4051 ===============================================================================
4052 [..] This section provides functions used to configure and control a
4053 HRTIM timer operating in waveform mode:
4054 (+) Configure HRTIM timer general behavior
4055 (+) Configure HRTIM timer event filtering
4056 (+) Configure HRTIM timer deadtime insertion
4057 (+) Configure HRTIM timer chopper mode
4058 (+) Configure HRTIM timer burst DMA
4059 (+) Configure HRTIM timer compare unit
4060 (+) Configure HRTIM timer capture unit
4061 (+) Configure HRTIM timer output
4062 (+) Set HRTIM timer output level
4063 (+) Enable HRTIM timer output
4064 (+) Disable HRTIM timer output
4065 (+) Start HRTIM timer
4066 (+) Stop HRTIM timer
4067 (+) Start HRTIM timer and enable interrupt
4068 (+) Stop HRTIM timer and disable interrupt
4069 (+) Start HRTIM timer and enable DMA transfer
4070 (+) Stop HRTIM timer and disable DMA transfer
4071 (+) Enable or disable the burst mode controller
4072 (+) Start the burst mode controller (by software)
4073 (+) Trigger a Capture (by software)
4074 (+) Update the HRTIM timer preloadable registers (by software)
4075 (+) Reset the HRTIM timer counter (by software)
4076 (+) Start a burst DMA transfer
4077 (+) Enable timer register update
4078 (+) Disable timer register update
4079
4080 @endverbatim
4081 * @{
4082 */
4083
4084 /**
4085 * @brief Configure the general behavior of a timer operating in waveform mode
4086 * @param hhrtim pointer to HAL HRTIM handle
4087 * @param TimerIdx Timer index
4088 * This parameter can be one of the following values:
4089 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4090 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4091 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4092 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4093 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4094 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4095 * @param pTimerCfg pointer to the timer configuration structure
4096 * @note When the timer operates in waveform mode, all the features supported by
4097 * the HRTIM are available without any limitation.
4098 * @retval HAL status
4099 * @note This function must be called before starting the timer
4100 */
HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimerCfgTypeDef * pTimerCfg)4101 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
4102 uint32_t TimerIdx,
4103 const HRTIM_TimerCfgTypeDef * pTimerCfg)
4104 {
4105 /* Check parameters */
4106 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
4107
4108 /* Relevant for all HRTIM timers, including the master */
4109 assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable));
4110 assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync));
4111 assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync));
4112 assert_param(IS_HRTIM_DACSYNC(pTimerCfg->DACSynchro));
4113 assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
4114 assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
4115 assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
4116
4117 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4118 {
4119 return HAL_BUSY;
4120 }
4121
4122 /* Process Locked */
4123 __HAL_LOCK(hhrtim);
4124
4125 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4126
4127 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
4128 {
4129 /* Check parameters */
4130 assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
4131 assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
4132 assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
4133
4134 /* Configure master timer */
4135 HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
4136 }
4137 else
4138 {
4139 /* Check parameters */
4140 assert_param(IS_HRTIM_UPDATEGATING_TIM(pTimerCfg->UpdateGating));
4141 assert_param(IS_HRTIM_TIM_IT(pTimerCfg->InterruptRequests));
4142 assert_param(IS_HRTIM_TIM_DMA(pTimerCfg->DMARequests));
4143 assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
4144 assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
4145 assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
4146 assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->PushPull,
4147 pTimerCfg->DeadTimeInsertion));
4148 assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->PushPull,
4149 pTimerCfg->DelayedProtectionMode));
4150 assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
4151 assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
4152 assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
4153
4154 /* Configure timing unit */
4155 HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
4156 }
4157
4158 /* Update timer parameters */
4159 hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
4160 hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
4161 hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
4162 hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
4163 hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
4164
4165 /* Force a software update */
4166 HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
4167
4168 hhrtim->State = HAL_HRTIM_STATE_READY;
4169
4170 /* Process Unlocked */
4171 __HAL_UNLOCK(hhrtim);
4172
4173 return HAL_OK;
4174 }
4175
4176 /**
4177 * @brief Configure the event filtering capabilities of a timer (blanking, windowing)
4178 * @param hhrtim pointer to HAL HRTIM handle
4179 * @param TimerIdx Timer index
4180 * This parameter can be one of the following values:
4181 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4182 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4183 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4184 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4185 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4186 * @param Event external event for which timer event filtering must be configured
4187 * This parameter can be one of the following values:
4188 * @arg HRTIM_EVENT_1: External event 1
4189 * @arg HRTIM_EVENT_2: External event 2
4190 * @arg HRTIM_EVENT_3: External event 3
4191 * @arg HRTIM_EVENT_4: External event 4
4192 * @arg HRTIM_EVENT_5: External event 5
4193 * @arg HRTIM_EVENT_6: External event 6
4194 * @arg HRTIM_EVENT_7: External event 7
4195 * @arg HRTIM_EVENT_8: External event 8
4196 * @arg HRTIM_EVENT_9: External event 9
4197 * @arg HRTIM_EVENT_10: External event 10
4198 * @param pTimerEventFilteringCfg pointer to the timer event filtering configuration structure
4199 * @note This function must be called before starting the timer
4200 * @retval HAL status
4201 */
HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Event,const HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg)4202 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,
4203 uint32_t TimerIdx,
4204 uint32_t Event,
4205 const HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
4206 {
4207 /* Check parameters */
4208 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4209 assert_param(IS_HRTIM_EVENT(Event));
4210 assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
4211
4212 assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
4213
4214 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4215 {
4216 return HAL_BUSY;
4217 }
4218
4219 /* Process Locked */
4220 __HAL_LOCK(hhrtim);
4221
4222 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4223
4224 /* Configure timer event filtering capabilities */
4225 switch (Event)
4226 {
4227 case HRTIM_EVENT_NONE:
4228 {
4229 CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1);
4230 CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2);
4231 break;
4232 }
4233
4234 case HRTIM_EVENT_1:
4235 {
4236 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch));
4237 break;
4238 }
4239
4240 case HRTIM_EVENT_2:
4241 {
4242 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) );
4243 break;
4244 }
4245
4246 case HRTIM_EVENT_3:
4247 {
4248 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) );
4249 break;
4250 }
4251
4252 case HRTIM_EVENT_4:
4253 {
4254 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) );
4255 break;
4256 }
4257
4258 case HRTIM_EVENT_5:
4259 {
4260 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) );
4261 break;
4262 }
4263
4264 case HRTIM_EVENT_6:
4265 {
4266 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) );
4267 break;
4268 }
4269
4270 case HRTIM_EVENT_7:
4271 {
4272 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) );
4273 break;
4274 }
4275
4276 case HRTIM_EVENT_8:
4277 {
4278 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) );
4279 break;
4280 }
4281
4282 case HRTIM_EVENT_9:
4283 {
4284 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) );
4285 break;
4286 }
4287
4288 case HRTIM_EVENT_10:
4289 {
4290 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) );
4291 break;
4292 }
4293
4294 default:
4295 {
4296 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4297
4298 /* Process Unlocked */
4299 __HAL_UNLOCK(hhrtim);
4300
4301 break;
4302 }
4303 }
4304
4305 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4306 {
4307 return HAL_ERROR;
4308 }
4309
4310 hhrtim->State = HAL_HRTIM_STATE_READY;
4311
4312 /* Process Unlocked */
4313 __HAL_UNLOCK(hhrtim);
4314
4315 return HAL_OK;
4316 }
4317
4318 /**
4319 * @brief Configure the dead-time insertion feature for a timer
4320 * @param hhrtim pointer to HAL HRTIM handle
4321 * @param TimerIdx Timer index
4322 * This parameter can be one of the following values:
4323 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4324 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4325 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4326 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4327 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4328 * @param pDeadTimeCfg pointer to the deadtime insertion configuration structure
4329 * @retval HAL status
4330 * @note This function must be called before starting the timer
4331 */
HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_DeadTimeCfgTypeDef * pDeadTimeCfg)4332 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,
4333 uint32_t TimerIdx,
4334 const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
4335 {
4336 uint32_t hrtim_dtr;
4337
4338 /* Check parameters */
4339 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4340 assert_param(IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(pDeadTimeCfg->Prescaler));
4341 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
4342 assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
4343 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
4344 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
4345 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
4346 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
4347
4348 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4349 {
4350 return HAL_BUSY;
4351 }
4352
4353 /* Process Locked */
4354 __HAL_LOCK(hhrtim);
4355
4356 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4357
4358 /* Set timer deadtime configuration */
4359 hrtim_dtr = (pDeadTimeCfg->Prescaler & HRTIM_DTR_DTPRSC);
4360 hrtim_dtr |= (pDeadTimeCfg->RisingValue & HRTIM_DTR_DTR);
4361 hrtim_dtr |= (pDeadTimeCfg->RisingSign & HRTIM_DTR_SDTR);
4362 hrtim_dtr |= (pDeadTimeCfg->RisingSignLock & HRTIM_DTR_DTRSLK);
4363 hrtim_dtr |= (pDeadTimeCfg->RisingLock & HRTIM_DTR_DTRLK);
4364 hrtim_dtr |= ((pDeadTimeCfg->FallingValue << 16U) & HRTIM_DTR_DTF);
4365 hrtim_dtr |= (pDeadTimeCfg->FallingSign & HRTIM_DTR_SDTF);
4366 hrtim_dtr |= (pDeadTimeCfg->FallingSignLock & HRTIM_DTR_DTFSLK);
4367 hrtim_dtr |= (pDeadTimeCfg->FallingLock & HRTIM_DTR_DTFLK);
4368
4369 /* Update the HRTIM registers */
4370 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR, (
4371 HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
4372 HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
4373 HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr);
4374
4375 hhrtim->State = HAL_HRTIM_STATE_READY;
4376
4377 /* Process Unlocked */
4378 __HAL_UNLOCK(hhrtim);
4379
4380 return HAL_OK;
4381 }
4382
4383 /**
4384 * @brief Configure the chopper mode feature for a timer
4385 * @param hhrtim pointer to HAL HRTIM handle
4386 * @param TimerIdx Timer index
4387 * This parameter can be one of the following values:
4388 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4389 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4390 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4391 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4392 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4393 * @param pChopperModeCfg pointer to the chopper mode configuration structure
4394 * @retval HAL status
4395 * @note This function must be called before configuring the timer output(s)
4396 */
HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_ChopperModeCfgTypeDef * pChopperModeCfg)4397 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
4398 uint32_t TimerIdx,
4399 const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
4400 {
4401 uint32_t hrtim_chpr;
4402
4403 /* Check parameters */
4404 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4405 assert_param(IS_HRTIM_CHOPPER_PRESCALERRATIO(pChopperModeCfg->CarrierFreq));
4406 assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle));
4407 assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse));
4408
4409 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4410 {
4411 return HAL_BUSY;
4412 }
4413
4414 /* Process Locked */
4415 __HAL_LOCK(hhrtim);
4416
4417 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4418
4419 /* Set timer choppe mode configuration */
4420 hrtim_chpr = (pChopperModeCfg->CarrierFreq & HRTIM_CHPR_CARFRQ);
4421 hrtim_chpr |= (pChopperModeCfg->DutyCycle & HRTIM_CHPR_CARDTY);
4422 hrtim_chpr |= (pChopperModeCfg->StartPulse & HRTIM_CHPR_STRPW);
4423
4424 /* Update the HRTIM registers */
4425 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR,
4426 (HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW),
4427 hrtim_chpr);
4428
4429 hhrtim->State = HAL_HRTIM_STATE_READY;
4430
4431 /* Process Unlocked */
4432 __HAL_UNLOCK(hhrtim);
4433
4434 return HAL_OK;
4435 }
4436
4437 /**
4438 * @brief Configure the burst DMA controller for a timer
4439 * @param hhrtim pointer to HAL HRTIM handle
4440 * @param TimerIdx Timer index
4441 * This parameter can be one of the following values:
4442 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4443 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4444 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4445 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4446 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4447 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4448 * @param RegistersToUpdate registers to be written by DMA
4449 * This parameter can be any combination of the following values:
4450 * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
4451 * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
4452 * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
4453 * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
4454 * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
4455 * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
4456 * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
4457 * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
4458 * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
4459 * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
4460 * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
4461 * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
4462 * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
4463 * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
4464 * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
4465 * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
4466 * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
4467 * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
4468 * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
4469 * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
4470 * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
4471 * @retval HAL status
4472 * @note This function must be called before starting the timer
4473 */
HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t RegistersToUpdate)4474 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
4475 uint32_t TimerIdx,
4476 uint32_t RegistersToUpdate)
4477 {
4478 /* Check parameters */
4479 assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
4480
4481 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4482 {
4483 return HAL_BUSY;
4484 }
4485
4486 /* Process Locked */
4487 __HAL_LOCK(hhrtim);
4488
4489 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4490
4491 /* Set the burst DMA timer update register */
4492 switch (TimerIdx)
4493 {
4494 case HRTIM_TIMERINDEX_TIMER_A:
4495 {
4496 hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate;
4497 break;
4498 }
4499
4500 case HRTIM_TIMERINDEX_TIMER_B:
4501 {
4502 hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate;
4503 break;
4504 }
4505
4506 case HRTIM_TIMERINDEX_TIMER_C:
4507 {
4508 hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate;
4509 break;
4510 }
4511
4512 case HRTIM_TIMERINDEX_TIMER_D:
4513 {
4514 hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate;
4515 break;
4516 }
4517
4518 case HRTIM_TIMERINDEX_TIMER_E:
4519 {
4520 hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate;
4521 break;
4522 }
4523
4524 case HRTIM_TIMERINDEX_MASTER:
4525 {
4526 hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
4527 break;
4528 }
4529
4530 default:
4531 {
4532 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4533
4534 /* Process Unlocked */
4535 __HAL_UNLOCK(hhrtim);
4536
4537 break;
4538 }
4539 }
4540
4541 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4542 {
4543 return HAL_ERROR;
4544 }
4545
4546 hhrtim->State = HAL_HRTIM_STATE_READY;
4547
4548 /* Process Unlocked */
4549 __HAL_UNLOCK(hhrtim);
4550
4551 return HAL_OK;
4552 }
4553
4554 /**
4555 * @brief Configure the compare unit of a timer operating in waveform mode
4556 * @param hhrtim pointer to HAL HRTIM handle
4557 * @param TimerIdx Timer index
4558 * This parameter can be one of the following values:
4559 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4560 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4561 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4562 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4563 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4564 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4565 * @param CompareUnit Compare unit to configure
4566 * This parameter can be one of the following values:
4567 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
4568 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
4569 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
4570 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
4571 * @param pCompareCfg pointer to the compare unit configuration structure
4572 * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
4573 * application has to configure separately the capture unit. Capture unit
4574 * to configure in that case depends on the compare unit auto delayed mode
4575 * is applied to (see below):
4576 * Auto delayed on output compare 2: capture unit 1 must be configured
4577 * Auto delayed on output compare 4: capture unit 2 must be configured
4578 * @retval HAL status
4579 * @note This function must be called before starting the timer
4580 */
HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CompareUnit,const HRTIM_CompareCfgTypeDef * pCompareCfg)4581 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
4582 uint32_t TimerIdx,
4583 uint32_t CompareUnit,
4584 const HRTIM_CompareCfgTypeDef* pCompareCfg)
4585 {
4586 /* Check parameters */
4587 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
4588
4589 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4590 {
4591 return HAL_BUSY;
4592 }
4593
4594 /* Process Locked */
4595 __HAL_LOCK(hhrtim);
4596
4597 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4598
4599 /* Configure the compare unit */
4600 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
4601 {
4602 switch (CompareUnit)
4603 {
4604 case HRTIM_COMPAREUNIT_1:
4605 {
4606 hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
4607 break;
4608 }
4609
4610 case HRTIM_COMPAREUNIT_2:
4611 {
4612 hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
4613 break;
4614 }
4615
4616 case HRTIM_COMPAREUNIT_3:
4617 {
4618 hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
4619 break;
4620 }
4621
4622 case HRTIM_COMPAREUNIT_4:
4623 {
4624 hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
4625 break;
4626 }
4627
4628 default:
4629 {
4630 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4631
4632 /* Process Unlocked */
4633 __HAL_UNLOCK(hhrtim);
4634
4635 break;
4636 }
4637 }
4638
4639 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4640 {
4641 return HAL_ERROR;
4642 }
4643
4644 }
4645 else
4646 {
4647 switch (CompareUnit)
4648 {
4649 case HRTIM_COMPAREUNIT_1:
4650 {
4651 /* Set the compare value */
4652 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
4653 break;
4654 }
4655
4656 case HRTIM_COMPAREUNIT_2:
4657 {
4658 /* Check parameters */
4659 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
4660
4661 /* Set the compare value */
4662 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
4663
4664 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
4665 {
4666 /* Configure auto-delayed mode */
4667 /* DELCMP2 bitfield must be reset when reprogrammed from one value */
4668 /* to the other to reinitialize properly the auto-delayed mechanism */
4669 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
4670 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
4671
4672 /* Set the compare value for timeout compare unit (if any) */
4673 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
4674 {
4675 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
4676 }
4677 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
4678 {
4679 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
4680 }
4681 else
4682 {
4683 /* nothing to do */
4684 }
4685 }
4686 else
4687 {
4688 /* Clear HRTIM_TIMxCR.DELCMP2 bitfield */
4689 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U);
4690 }
4691 break;
4692 }
4693
4694 case HRTIM_COMPAREUNIT_3:
4695 {
4696 /* Set the compare value */
4697 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
4698 break;
4699 }
4700
4701 case HRTIM_COMPAREUNIT_4:
4702 {
4703 /* Check parameters */
4704 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
4705
4706 /* Set the compare value */
4707 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
4708
4709 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
4710 {
4711 /* Configure auto-delayed mode */
4712 /* DELCMP4 bitfield must be reset when reprogrammed from one value */
4713 /* to the other to reinitialize properly the auto-delayed mechanism */
4714 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
4715 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2U);
4716
4717 /* Set the compare value for timeout compare unit (if any) */
4718 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
4719 {
4720 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
4721 }
4722 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
4723 {
4724 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
4725 }
4726 else
4727 {
4728 /* nothing to do */
4729 }
4730 }
4731 else
4732 {
4733 /* Clear HRTIM_TIMxCR.DELCMP4 bitfield */
4734 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U);
4735 }
4736 break;
4737 }
4738
4739 default:
4740 {
4741 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4742
4743 /* Process Unlocked */
4744 __HAL_UNLOCK(hhrtim);
4745
4746 break;
4747 }
4748 }
4749
4750 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4751 {
4752 return HAL_ERROR;
4753 }
4754
4755 }
4756 hhrtim->State = HAL_HRTIM_STATE_READY;
4757
4758 /* Process Unlocked */
4759 __HAL_UNLOCK(hhrtim);
4760
4761 return HAL_OK;
4762 }
4763
4764 /**
4765 * @brief Configure the capture unit of a timer operating in waveform mode
4766 * @param hhrtim pointer to HAL HRTIM handle
4767 * @param TimerIdx Timer index
4768 * This parameter can be one of the following values:
4769 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4770 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4771 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4772 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4773 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4774 * @param CaptureUnit Capture unit to configure
4775 * This parameter can be one of the following values:
4776 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
4777 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
4778 * @param pCaptureCfg pointer to the compare unit configuration structure
4779 * @retval HAL status
4780 * @note This function must be called before starting the timer
4781 */
HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit,const HRTIM_CaptureCfgTypeDef * pCaptureCfg)4782 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
4783 uint32_t TimerIdx,
4784 uint32_t CaptureUnit,
4785 const HRTIM_CaptureCfgTypeDef* pCaptureCfg)
4786 {
4787 /* Check parameters */
4788 assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger));
4789
4790
4791 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4792 {
4793 return HAL_BUSY;
4794 }
4795
4796 /* Process Locked */
4797 __HAL_LOCK(hhrtim);
4798
4799 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4800
4801 /* Configure the capture unit */
4802 switch (CaptureUnit)
4803 {
4804 case HRTIM_CAPTUREUNIT_1:
4805 {
4806 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, pCaptureCfg->Trigger);
4807 break;
4808 }
4809
4810 case HRTIM_CAPTUREUNIT_2:
4811 {
4812 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, pCaptureCfg->Trigger);
4813 break;
4814 }
4815
4816 default:
4817 {
4818 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4819
4820 /* Process Unlocked */
4821 __HAL_UNLOCK(hhrtim);
4822
4823 break;
4824 }
4825 }
4826
4827 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4828 {
4829 return HAL_ERROR;
4830 }
4831
4832
4833 hhrtim->State = HAL_HRTIM_STATE_READY;
4834
4835 /* Process Unlocked */
4836 __HAL_UNLOCK(hhrtim);
4837
4838 return HAL_OK;
4839 }
4840
4841 /**
4842 * @brief Configure the output of a timer operating in waveform mode
4843 * @param hhrtim pointer to HAL HRTIM handle
4844 * @param TimerIdx Timer index
4845 * This parameter can be one of the following values:
4846 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4847 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4848 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4849 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4850 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4851 * @param Output Timer output
4852 * This parameter can be one of the following values:
4853 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
4854 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
4855 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
4856 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
4857 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
4858 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
4859 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
4860 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
4861 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
4862 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
4863 * @param pOutputCfg pointer to the timer output configuration structure
4864 * @retval HAL status
4865 * @note This function must be called before configuring the timer and after
4866 * configuring the deadtime insertion feature (if required).
4867 */
HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output,const HRTIM_OutputCfgTypeDef * pOutputCfg)4868 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,
4869 uint32_t TimerIdx,
4870 uint32_t Output,
4871 const HRTIM_OutputCfgTypeDef * pOutputCfg)
4872 {
4873 /* Check parameters */
4874 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
4875 assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
4876 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pOutputCfg->IdleLevel));
4877 assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
4878 assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
4879 assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
4880 assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
4881
4882 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4883 {
4884 return HAL_BUSY;
4885 }
4886
4887 /* Process Locked */
4888 __HAL_LOCK(hhrtim);
4889
4890 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4891
4892 /* Configure the timer output */
4893 HRTIM_OutputConfig(hhrtim,
4894 TimerIdx,
4895 Output,
4896 pOutputCfg);
4897
4898 hhrtim->State = HAL_HRTIM_STATE_READY;
4899
4900 /* Process Unlocked */
4901 __HAL_UNLOCK(hhrtim);
4902
4903 return HAL_OK;
4904 }
4905
4906 /**
4907 * @brief Force the timer output to its active or inactive state
4908 * @param hhrtim pointer to HAL HRTIM handle
4909 * @param TimerIdx Timer index
4910 * This parameter can be one of the following values:
4911 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4912 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4913 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4914 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4915 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4916 * @param Output Timer output
4917 * This parameter can be one of the following values:
4918 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
4919 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
4920 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
4921 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
4922 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
4923 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
4924 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
4925 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
4926 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
4927 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
4928 * @param OutputLevel indicates whether the output is forced to its active or inactive level
4929 * This parameter can be one of the following values:
4930 * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
4931 * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
4932 * @retval HAL status
4933 * @note The 'software set/reset trigger' bit in the output set/reset registers
4934 * is automatically reset by hardware
4935 */
HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output,uint32_t OutputLevel)4936 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
4937 uint32_t TimerIdx,
4938 uint32_t Output,
4939 uint32_t OutputLevel)
4940 {
4941 /* Check parameters */
4942 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
4943 assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
4944
4945 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4946 {
4947 return HAL_BUSY;
4948 }
4949
4950 /* Process Locked */
4951 __HAL_LOCK(hhrtim);
4952
4953 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4954
4955 /* Force timer output level */
4956 switch (Output)
4957 {
4958 case HRTIM_OUTPUT_TA1:
4959 case HRTIM_OUTPUT_TB1:
4960 case HRTIM_OUTPUT_TC1:
4961 case HRTIM_OUTPUT_TD1:
4962 case HRTIM_OUTPUT_TE1:
4963 {
4964 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
4965 {
4966 /* Force output to its active state */
4967 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R,HRTIM_SET1R_SST);
4968 }
4969 else
4970 {
4971 /* Force output to its inactive state */
4972 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R, HRTIM_RST1R_SRT);
4973 }
4974 break;
4975 }
4976
4977 case HRTIM_OUTPUT_TA2:
4978 case HRTIM_OUTPUT_TB2:
4979 case HRTIM_OUTPUT_TC2:
4980 case HRTIM_OUTPUT_TD2:
4981 case HRTIM_OUTPUT_TE2:
4982 {
4983 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
4984 {
4985 /* Force output to its active state */
4986 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R, HRTIM_SET2R_SST);
4987 }
4988 else
4989 {
4990 /* Force output to its inactive state */
4991 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R, HRTIM_RST2R_SRT);
4992 }
4993 break;
4994 }
4995
4996 default:
4997 {
4998 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4999
5000 /* Process Unlocked */
5001 __HAL_UNLOCK(hhrtim);
5002
5003 break;
5004 }
5005 }
5006
5007 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
5008 {
5009 return HAL_ERROR;
5010 }
5011
5012 hhrtim->State = HAL_HRTIM_STATE_READY;
5013
5014 /* Process Unlocked */
5015 __HAL_UNLOCK(hhrtim);
5016
5017 return HAL_OK;
5018 }
5019
5020 /**
5021 * @brief Enable the generation of the waveform signal on the designated output(s)
5022 * Outputs can be combined (ORed) to allow for simultaneous output enabling.
5023 * @param hhrtim pointer to HAL HRTIM handle
5024 * @param OutputsToStart Timer output(s) to enable
5025 * This parameter can be any combination of the following values:
5026 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
5027 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
5028 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
5029 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
5030 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
5031 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
5032 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
5033 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
5034 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
5035 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
5036 * @retval HAL status
5037 */
HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,uint32_t OutputsToStart)5038 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,
5039 uint32_t OutputsToStart)
5040 {
5041 /* Check the parameters */
5042 assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
5043
5044 /* Process Locked */
5045 __HAL_LOCK(hhrtim);
5046
5047 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5048
5049 /* Enable the HRTIM outputs */
5050 hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
5051
5052 hhrtim->State = HAL_HRTIM_STATE_READY;
5053
5054 /* Process Unlocked */
5055 __HAL_UNLOCK(hhrtim);
5056
5057 return HAL_OK;
5058 }
5059
5060 /**
5061 * @brief Disable the generation of the waveform signal on the designated output(s)
5062 * Outputs can be combined (ORed) to allow for simultaneous output disabling.
5063 * @param hhrtim pointer to HAL HRTIM handle
5064 * @param OutputsToStop Timer output(s) to disable
5065 * This parameter can be any combination of the following values:
5066 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
5067 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
5068 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
5069 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
5070 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
5071 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
5072 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
5073 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
5074 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
5075 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
5076 * @retval HAL status
5077 */
HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,uint32_t OutputsToStop)5078 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,
5079 uint32_t OutputsToStop)
5080 {
5081 /* Check the parameters */
5082 assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
5083
5084 /* Process Locked */
5085 __HAL_LOCK(hhrtim);
5086
5087 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5088
5089 /* Enable the HRTIM outputs */
5090 hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
5091
5092 hhrtim->State = HAL_HRTIM_STATE_READY;
5093
5094 /* Process Unlocked */
5095 __HAL_UNLOCK(hhrtim);
5096
5097 return HAL_OK;
5098 }
5099
5100 /**
5101 * @brief Start the counter of the designated timer(s) operating in waveform mode
5102 * Timers can be combined (ORed) to allow for simultaneous counter start.
5103 * @param hhrtim pointer to HAL HRTIM handle
5104 * @param Timers Timer counter(s) to start
5105 * This parameter can be any combination of the following values:
5106 * @arg HRTIM_TIMERID_MASTER
5107 * @arg HRTIM_TIMERID_TIMER_A
5108 * @arg HRTIM_TIMERID_TIMER_B
5109 * @arg HRTIM_TIMERID_TIMER_C
5110 * @arg HRTIM_TIMERID_TIMER_D
5111 * @arg HRTIM_TIMERID_TIMER_E
5112 * @retval HAL status
5113 */
HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5114 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim,
5115 uint32_t Timers)
5116 {
5117 /* Check the parameters */
5118 assert_param(IS_HRTIM_TIMERID(Timers));
5119
5120 /* Process Locked */
5121 __HAL_LOCK(hhrtim);
5122
5123 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5124
5125 /* Enable timer(s) counter */
5126 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
5127
5128 hhrtim->State = HAL_HRTIM_STATE_READY;
5129
5130 /* Process Unlocked */
5131 __HAL_UNLOCK(hhrtim);
5132
5133 return HAL_OK;
5134 }
5135
5136 /**
5137 * @brief Stop the counter of the designated timer(s) operating in waveform mode
5138 * Timers can be combined (ORed) to allow for simultaneous counter stop.
5139 * @param hhrtim pointer to HAL HRTIM handle
5140 * @param Timers Timer counter(s) to stop
5141 * This parameter can be any combination of the following values:
5142 * @arg HRTIM_TIMERID_MASTER
5143 * @arg HRTIM_TIMERID_TIMER_A
5144 * @arg HRTIM_TIMERID_TIMER_B
5145 * @arg HRTIM_TIMERID_TIMER_C
5146 * @arg HRTIM_TIMERID_TIMER_D
5147 * @arg HRTIM_TIMERID_TIMER_E
5148 * @retval HAL status
5149 * @note The counter of a timer is stopped only if all timer outputs are disabled
5150 */
HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5151 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim,
5152 uint32_t Timers)
5153 {
5154 /* Check the parameters */
5155 assert_param(IS_HRTIM_TIMERID(Timers));
5156
5157 /* Process Locked */
5158 __HAL_LOCK(hhrtim);
5159
5160 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5161
5162 /* Disable timer(s) counter */
5163 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
5164
5165 hhrtim->State = HAL_HRTIM_STATE_READY;
5166
5167 /* Process Unlocked */
5168 __HAL_UNLOCK(hhrtim);
5169
5170 return HAL_OK;
5171 }
5172
5173 /**
5174 * @brief Start the counter of the designated timer(s) operating in waveform mode
5175 * Timers can be combined (ORed) to allow for simultaneous counter start.
5176 * @param hhrtim pointer to HAL HRTIM handle
5177 * @param Timers Timer counter(s) to start
5178 * This parameter can be any combination of the following values:
5179 * @arg HRTIM_TIMERID_MASTER
5180 * @arg HRTIM_TIMERID_TIMER_A
5181 * @arg HRTIM_TIMERID_TIMER_B
5182 * @arg HRTIM_TIMERID_TIMER_C
5183 * @arg HRTIM_TIMERID_TIMER_D
5184 * @arg HRTIM_TIMERID_TIMER_E
5185 * @note HRTIM interrupts (e.g. faults interrupts) and interrupts related
5186 * to the timers to start are enabled within this function.
5187 * Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig
5188 * function.
5189 * @retval HAL status
5190 */
HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5191 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim,
5192 uint32_t Timers)
5193 {
5194 uint8_t timer_idx;
5195
5196 /* Check the parameters */
5197 assert_param(IS_HRTIM_TIMERID(Timers));
5198
5199 /* Process Locked */
5200 __HAL_LOCK(hhrtim);
5201
5202 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5203
5204 /* Enable HRTIM interrupts (if required) */
5205 __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
5206
5207 /* Enable master timer related interrupts (if required) */
5208 if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
5209 {
5210 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim,
5211 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
5212 }
5213
5214 /* Enable timing unit related interrupts (if required) */
5215 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5216 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5217 timer_idx++)
5218 {
5219 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
5220 {
5221 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim,
5222 timer_idx,
5223 hhrtim->TimerParam[timer_idx].InterruptRequests);
5224 }
5225 }
5226
5227 /* Enable timer(s) counter */
5228 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
5229
5230 hhrtim->State = HAL_HRTIM_STATE_READY;
5231
5232 /* Process Unlocked */
5233 __HAL_UNLOCK(hhrtim);
5234
5235 return HAL_OK;}
5236
5237 /**
5238 * @brief Stop the counter of the designated timer(s) operating in waveform mode
5239 * Timers can be combined (ORed) to allow for simultaneous counter stop.
5240 * @param hhrtim pointer to HAL HRTIM handle
5241 * @param Timers Timer counter(s) to stop
5242 * This parameter can be any combination of the following values:
5243 * @arg HRTIM_TIMERID_MASTER
5244 * @arg HRTIM_TIMERID_TIMER_A
5245 * @arg HRTIM_TIMERID_TIMER_B
5246 * @arg HRTIM_TIMERID_TIMER_C
5247 * @arg HRTIM_TIMERID_TIMER_D
5248 * @arg HRTIM_TIMERID_TIMER_E
5249 * @retval HAL status
5250 * @note The counter of a timer is stopped only if all timer outputs are disabled
5251 * @note All enabled timer related interrupts are disabled.
5252 */
HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5253 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim,
5254 uint32_t Timers)
5255 {
5256 /* ++ WA */
5257 __IO uint32_t delai = (uint32_t)(0x17FU);
5258 /* -- WA */
5259
5260 uint8_t timer_idx;
5261
5262 /* Check the parameters */
5263 assert_param(IS_HRTIM_TIMERID(Timers));
5264
5265 /* Process Locked */
5266 __HAL_LOCK(hhrtim);
5267
5268 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5269
5270 /* Disable HRTIM interrupts (if required) */
5271 __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
5272
5273 /* Disable master timer related interrupts (if required) */
5274 if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
5275 {
5276 /* Interrupts enable flag must be cleared one by one */
5277 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
5278 }
5279
5280 /* Disable timing unit related interrupts (if required) */
5281 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5282 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5283 timer_idx++)
5284 {
5285 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
5286 {
5287 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, timer_idx, hhrtim->TimerParam[timer_idx].InterruptRequests);
5288 }
5289 }
5290
5291 /* ++ WA */
5292 do { delai--; } while (delai != 0U);
5293 /* -- WA */
5294
5295 /* Disable timer(s) counter */
5296 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
5297
5298 hhrtim->State = HAL_HRTIM_STATE_READY;
5299
5300 /* Process Unlocked */
5301 __HAL_UNLOCK(hhrtim);
5302
5303 return HAL_OK;
5304 }
5305
5306 /**
5307 * @brief Start the counter of the designated timer(s) operating in waveform mode
5308 * Timers can be combined (ORed) to allow for simultaneous counter start.
5309 * @param hhrtim pointer to HAL HRTIM handle
5310 * @param Timers Timer counter(s) to start
5311 * This parameter can be any combination of the following values:
5312 * @arg HRTIM_TIMERID_MASTER
5313 * @arg HRTIM_TIMERID_TIMER_A
5314 * @arg HRTIM_TIMERID_TIMER_B
5315 * @arg HRTIM_TIMERID_TIMER_C
5316 * @arg HRTIM_TIMERID_TIMER_D
5317 * @arg HRTIM_TIMERID_TIMER_E
5318 * @retval HAL status
5319 * @note This function enables the dma request(s) mentioned in the timer
5320 * configuration data structure for every timers to start.
5321 * @note The source memory address, the destination memory address and the
5322 * size of each DMA transfer are specified at timer configuration time
5323 * (see HAL_HRTIM_WaveformTimerConfig)
5324 */
HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5325 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim,
5326 uint32_t Timers)
5327 {
5328 uint8_t timer_idx;
5329 DMA_HandleTypeDef * hdma;
5330
5331 /* Check the parameters */
5332 assert_param(IS_HRTIM_TIMERID(Timers));
5333
5334 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5335 {
5336 return HAL_BUSY;
5337 }
5338
5339 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5340
5341 /* Process Locked */
5342 __HAL_LOCK(hhrtim);
5343
5344 if (((Timers & HRTIM_TIMERID_MASTER) != (uint32_t)RESET) &&
5345 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
5346 {
5347 /* Set the DMA error callback */
5348 hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
5349
5350 /* Set the DMA transfer completed callback */
5351 hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt;
5352
5353 /* Enable the DMA channel */
5354 if (HAL_DMA_Start_IT(hhrtim->hdmaMaster,
5355 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress,
5356 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress,
5357 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK)
5358 {
5359 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5360
5361 /* Process Unlocked */
5362 __HAL_UNLOCK(hhrtim);
5363
5364 return HAL_ERROR;
5365 }
5366
5367 /* Enable the timer DMA request */
5368 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim,
5369 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
5370 }
5371
5372 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5373 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5374 timer_idx++)
5375 {
5376 if (((Timers & TimerIdxToTimerId[timer_idx]) != (uint32_t)RESET) &&
5377 (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
5378 {
5379 /* Get the timer DMA handler */
5380 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
5381
5382 if (hdma == NULL)
5383 {
5384 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5385
5386 /* Process Unlocked */
5387 __HAL_UNLOCK(hhrtim);
5388
5389 return HAL_ERROR;
5390 }
5391
5392 /* Set the DMA error callback */
5393 hdma->XferErrorCallback = HRTIM_DMAError ;
5394
5395 /* Set the DMA transfer completed callback */
5396 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
5397
5398 /* Enable the DMA channel */
5399 if (HAL_DMA_Start_IT(hdma,
5400 hhrtim->TimerParam[timer_idx].DMASrcAddress,
5401 hhrtim->TimerParam[timer_idx].DMADstAddress,
5402 hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK)
5403 {
5404 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5405
5406 /* Process Unlocked */
5407 __HAL_UNLOCK(hhrtim);
5408
5409 return HAL_ERROR;
5410 }
5411
5412 /* Enable the timer DMA request */
5413 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim,
5414 timer_idx,
5415 hhrtim->TimerParam[timer_idx].DMARequests);
5416 }
5417 }
5418
5419 /* Enable the timer counter */
5420 __HAL_HRTIM_ENABLE(hhrtim, Timers);
5421
5422 hhrtim->State = HAL_HRTIM_STATE_READY;
5423
5424 /* Process Unlocked */
5425 __HAL_UNLOCK(hhrtim);
5426
5427 return HAL_OK;
5428 }
5429
5430 /**
5431 * @brief Stop the counter of the designated timer(s) operating in waveform mode
5432 * Timers can be combined (ORed) to allow for simultaneous counter stop.
5433 * @param hhrtim pointer to HAL HRTIM handle
5434 * @param Timers Timer counter(s) to stop
5435 * This parameter can be any combination of the following values:
5436 * @arg HRTIM_TIMERID_MASTER
5437 * @arg HRTIM_TIMERID_TIMER_A
5438 * @arg HRTIM_TIMERID_TIMER_B
5439 * @arg HRTIM_TIMERID_TIMER_C
5440 * @arg HRTIM_TIMERID_TIMER_D
5441 * @arg HRTIM_TIMERID_TIMER_E
5442 * @retval HAL status
5443 * @note The counter of a timer is stopped only if all timer outputs are disabled
5444 * @note All enabled timer related DMA requests are disabled.
5445 */
HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5446 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim,
5447 uint32_t Timers)
5448 {
5449 uint8_t timer_idx;
5450
5451 /* Check the parameters */
5452 assert_param(IS_HRTIM_TIMERID(Timers));
5453
5454 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5455
5456 if (((Timers & HRTIM_TIMERID_MASTER) != 0U) &&
5457 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
5458 {
5459 /* Disable the DMA */
5460 if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
5461 {
5462 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5463 }
5464 else
5465 {
5466 hhrtim->State = HAL_HRTIM_STATE_READY;
5467 /* Disable the DMA request(s) */
5468 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim,
5469 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
5470 }
5471 }
5472
5473 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5474 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5475 timer_idx++)
5476 {
5477 if (((Timers & TimerIdxToTimerId[timer_idx]) != 0U) &&
5478 (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
5479 {
5480 /* Get the timer DMA handler */
5481 /* Disable the DMA */
5482 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx)) != HAL_OK)
5483 {
5484 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5485 }
5486 else
5487 {
5488 hhrtim->State = HAL_HRTIM_STATE_READY;
5489
5490 /* Disable the DMA request(s) */
5491 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
5492 timer_idx,
5493 hhrtim->TimerParam[timer_idx].DMARequests);
5494 }
5495 }
5496 }
5497
5498 /* Disable the timer counter */
5499 __HAL_HRTIM_DISABLE(hhrtim, Timers);
5500
5501 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
5502 {
5503 return HAL_ERROR;
5504 }
5505 else
5506 {
5507 return HAL_OK;
5508 }
5509 }
5510
5511 /**
5512 * @brief Enable or disables the HRTIM burst mode controller.
5513 * @param hhrtim pointer to HAL HRTIM handle
5514 * @param Enable Burst mode controller enabling
5515 * This parameter can be one of the following values:
5516 * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
5517 * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
5518 * @retval HAL status
5519 * @note This function must be called after starting the timer(s)
5520 */
HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,uint32_t Enable)5521 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,
5522 uint32_t Enable)
5523 {
5524 /* Check parameters */
5525 assert_param(IS_HRTIM_BURSTMODECTL(Enable));
5526
5527 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5528 {
5529 return HAL_BUSY;
5530 }
5531
5532 /* Process Locked */
5533 __HAL_LOCK(hhrtim);
5534
5535 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5536
5537 /* Enable/Disable the burst mode controller */
5538 MODIFY_REG(hhrtim->Instance->sCommonRegs.BMCR, HRTIM_BMCR_BME, Enable);
5539
5540 hhrtim->State = HAL_HRTIM_STATE_READY;
5541
5542 /* Process Unlocked */
5543 __HAL_UNLOCK(hhrtim);
5544
5545 return HAL_OK;
5546 }
5547
5548 /**
5549 * @brief Trig the burst mode operation.
5550 * @param hhrtim pointer to HAL HRTIM handle
5551 * @retval HAL status
5552 */
HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef * hhrtim)5553 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
5554 {
5555 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5556 {
5557 return HAL_BUSY;
5558 }
5559
5560 /* Process Locked */
5561 __HAL_LOCK(hhrtim);
5562
5563 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5564
5565 /* Software trigger of the burst mode controller */
5566 SET_BIT(hhrtim->Instance->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
5567
5568 hhrtim->State = HAL_HRTIM_STATE_READY;
5569
5570 /* Process Unlocked */
5571 __HAL_UNLOCK(hhrtim);
5572
5573 return HAL_OK;
5574 }
5575
5576 /**
5577 * @brief Trig a software capture on the designed capture unit
5578 * @param hhrtim pointer to HAL HRTIM handle
5579 * @param TimerIdx Timer index
5580 * This parameter can be one of the following values:
5581 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5582 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5583 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5584 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5585 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5586 * @param CaptureUnit Capture unit to trig
5587 * This parameter can be one of the following values:
5588 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
5589 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
5590 * @retval HAL status
5591 * @note The 'software capture' bit in the capure configuration register is
5592 * automatically reset by hardware
5593 */
HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit)5594 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,
5595 uint32_t TimerIdx,
5596 uint32_t CaptureUnit)
5597 {
5598 /* Check parameters */
5599 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5600 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
5601
5602 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5603 {
5604 return HAL_BUSY;
5605 }
5606
5607 /* Process Locked */
5608 __HAL_LOCK(hhrtim);
5609
5610 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5611
5612 /* Force a software capture on concerned capture unit */
5613 switch (CaptureUnit)
5614 {
5615 case HRTIM_CAPTUREUNIT_1:
5616 {
5617 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, HRTIM_CPT1CR_SWCPT);
5618 break;
5619 }
5620
5621 case HRTIM_CAPTUREUNIT_2:
5622 {
5623 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, HRTIM_CPT2CR_SWCPT);
5624 break;
5625 }
5626
5627 default:
5628 {
5629 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5630
5631 /* Process Unlocked */
5632 __HAL_UNLOCK(hhrtim);
5633
5634 break;
5635 }
5636 }
5637
5638 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
5639 {
5640 return HAL_ERROR;
5641 }
5642
5643 hhrtim->State = HAL_HRTIM_STATE_READY;
5644
5645 /* Process Unlocked */
5646 __HAL_UNLOCK(hhrtim);
5647
5648 return HAL_OK;
5649 }
5650
5651 /**
5652 * @brief Trig the update of the registers of one or several timers
5653 * @param hhrtim pointer to HAL HRTIM handle
5654 * @param Timers timers concerned with the software register update
5655 * This parameter can be any combination of the following values:
5656 * @arg HRTIM_TIMERUPDATE_MASTER
5657 * @arg HRTIM_TIMERUPDATE_A
5658 * @arg HRTIM_TIMERUPDATE_B
5659 * @arg HRTIM_TIMERUPDATE_C
5660 * @arg HRTIM_TIMERUPDATE_D
5661 * @arg HRTIM_TIMERUPDATE_E
5662 * @retval HAL status
5663 * @note The 'software update' bits in the HRTIM control register 2 register are
5664 * automatically reset by hardware
5665 */
HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5666 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,
5667 uint32_t Timers)
5668 {
5669 /* Check parameters */
5670 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
5671
5672 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5673 {
5674 return HAL_BUSY;
5675 }
5676
5677 /* Process Locked */
5678 __HAL_LOCK(hhrtim);
5679
5680 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5681
5682 /* Force timer(s) registers update */
5683 hhrtim->Instance->sCommonRegs.CR2 |= Timers;
5684
5685 hhrtim->State = HAL_HRTIM_STATE_READY;
5686
5687 /* Process Unlocked */
5688 __HAL_UNLOCK(hhrtim);
5689
5690 return HAL_OK;
5691 }
5692
5693 /**
5694 * @brief Trig the reset of one or several timers
5695 * @param hhrtim pointer to HAL HRTIM handle
5696 * @param Timers timers concerned with the software counter reset
5697 * This parameter can be any combination of the following values:
5698 * @arg HRTIM_TIMERRESET_MASTER
5699 * @arg HRTIM_TIMERRESET_TIMER_A
5700 * @arg HRTIM_TIMERRESET_TIMER_B
5701 * @arg HRTIM_TIMERRESET_TIMER_C
5702 * @arg HRTIM_TIMERRESET_TIMER_D
5703 * @arg HRTIM_TIMERRESET_TIMER_E
5704 * @retval HAL status
5705 * @note The 'software reset' bits in the HRTIM control register 2 are
5706 * automatically reset by hardware
5707 */
HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5708 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,
5709 uint32_t Timers)
5710 {
5711 /* Check parameters */
5712 assert_param(IS_HRTIM_TIMERRESET(Timers));
5713
5714 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5715 {
5716 return HAL_BUSY;
5717 }
5718
5719 /* Process Locked */
5720 __HAL_LOCK(hhrtim);
5721
5722 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5723
5724 /* Force timer(s) registers reset */
5725 hhrtim->Instance->sCommonRegs.CR2 = Timers;
5726
5727 hhrtim->State = HAL_HRTIM_STATE_READY;
5728
5729 /* Process Unlocked */
5730 __HAL_UNLOCK(hhrtim);
5731
5732 return HAL_OK;
5733 }
5734
5735 /**
5736 * @brief Start a burst DMA operation to update HRTIM control registers content
5737 * @param hhrtim pointer to HAL HRTIM handle
5738 * @param TimerIdx Timer index
5739 * This parameter can be one of the following values:
5740 * @arg HRTIM_TIMERINDEX_MASTER for master timer
5741 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5742 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5743 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5744 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5745 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5746 * @param BurstBufferAddress address of the buffer the HRTIM control registers
5747 * content will be updated from.
5748 * @param BurstBufferLength size (in WORDS) of the burst buffer.
5749 * @retval HAL status
5750 * @note The TimerIdx parameter determines the dma channel to be used by the
5751 * DMA burst controller (see below)
5752 * HRTIM_TIMERINDEX_MASTER: DMA channel 2 is used by the DMA burst controller
5753 * HRTIM_TIMERINDEX_TIMER_A: DMA channel 3 is used by the DMA burst controller
5754 * HRTIM_TIMERINDEX_TIMER_B: DMA channel 4 is used by the DMA burst controller
5755 * HRTIM_TIMERINDEX_TIMER_C: DMA channel 5 is used by the DMA burst controller
5756 * HRTIM_TIMERINDEX_TIMER_D: DMA channel 6 is used by the DMA burst controller
5757 * HRTIM_TIMERINDEX_TIMER_E: DMA channel 7 is used by the DMA burst controller
5758 */
HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t BurstBufferAddress,uint32_t BurstBufferLength)5759 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
5760 uint32_t TimerIdx,
5761 uint32_t BurstBufferAddress,
5762 uint32_t BurstBufferLength)
5763 {
5764 DMA_HandleTypeDef * hdma;
5765
5766 /* Check the parameters */
5767 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
5768
5769 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5770 {
5771 return HAL_BUSY;
5772 }
5773 if(hhrtim->State == HAL_HRTIM_STATE_READY)
5774 {
5775 if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U))
5776 {
5777 return HAL_ERROR;
5778 }
5779 else
5780 {
5781 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5782 }
5783 }
5784
5785 /* Process Locked */
5786 __HAL_LOCK(hhrtim);
5787
5788 /* Get the timer DMA handler */
5789 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
5790
5791 if (hdma == NULL)
5792 {
5793 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5794
5795 /* Process Unlocked */
5796 __HAL_UNLOCK(hhrtim);
5797
5798 return HAL_ERROR;
5799 }
5800
5801 /* Set the DMA transfer completed callback */
5802 hdma->XferCpltCallback = HRTIM_BurstDMACplt;
5803
5804 /* Set the DMA error callback */
5805 hdma->XferErrorCallback = HRTIM_DMAError ;
5806
5807 /* Enable the DMA channel */
5808 if (HAL_DMA_Start_IT(hdma,
5809 BurstBufferAddress,
5810 (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR),
5811 BurstBufferLength) != HAL_OK)
5812 {
5813 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5814
5815 /* Process Unlocked */
5816 __HAL_UNLOCK(hhrtim);
5817
5818 return HAL_ERROR;
5819 }
5820
5821 hhrtim->State = HAL_HRTIM_STATE_READY;
5822
5823 /* Process Unlocked */
5824 __HAL_UNLOCK(hhrtim);
5825
5826 return HAL_OK;
5827 }
5828
5829 /**
5830 * @brief Enable the transfer from preload to active registers for one
5831 * or several timing units (including master timer).
5832 * @param hhrtim pointer to HAL HRTIM handle
5833 * @param Timers Timer(s) concerned by the register preload enabling command
5834 * This parameter can be any combination of the following values:
5835 * @arg HRTIM_TIMERUPDATE_MASTER
5836 * @arg HRTIM_TIMERUPDATE_A
5837 * @arg HRTIM_TIMERUPDATE_B
5838 * @arg HRTIM_TIMERUPDATE_C
5839 * @arg HRTIM_TIMERUPDATE_D
5840 * @arg HRTIM_TIMERUPDATE_E
5841 * @retval HAL status
5842 */
HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5843 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
5844 uint32_t Timers)
5845 {
5846 /* Check the parameters */
5847 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
5848
5849 /* Process Locked */
5850 __HAL_LOCK(hhrtim);
5851
5852 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5853
5854 /* Enable timer(s) registers update */
5855 hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);
5856
5857 hhrtim->State = HAL_HRTIM_STATE_READY;
5858
5859 /* Process Unlocked */
5860 __HAL_UNLOCK(hhrtim);
5861
5862 return HAL_OK;
5863 }
5864
5865 /**
5866 * @brief Disable the transfer from preload to active registers for one
5867 * or several timing units (including master timer).
5868 * @param hhrtim pointer to HAL HRTIM handle
5869 * @param Timers Timer(s) concerned by the register preload disabling command
5870 * This parameter can be any combination of the following values:
5871 * @arg HRTIM_TIMERUPDATE_MASTER
5872 * @arg HRTIM_TIMERUPDATE_A
5873 * @arg HRTIM_TIMERUPDATE_B
5874 * @arg HRTIM_TIMERUPDATE_C
5875 * @arg HRTIM_TIMERUPDATE_D
5876 * @arg HRTIM_TIMERUPDATE_E
5877 * @retval HAL status
5878 */
HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5879 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
5880 uint32_t Timers)
5881 {
5882 /* Check the parameters */
5883 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
5884
5885 /* Process Locked */
5886 __HAL_LOCK(hhrtim);
5887
5888 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5889
5890 /* Enable timer(s) registers update */
5891 hhrtim->Instance->sCommonRegs.CR1 |= (Timers);
5892
5893 hhrtim->State = HAL_HRTIM_STATE_READY;
5894
5895 /* Process Unlocked */
5896 __HAL_UNLOCK(hhrtim);
5897
5898 return HAL_OK;
5899 }
5900
5901 /**
5902 * @}
5903 */
5904
5905 /** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions
5906 * @brief Peripheral State functions
5907 @verbatim
5908 ===============================================================================
5909 ##### Peripheral State functions #####
5910 ===============================================================================
5911 [..] This section provides functions used to get HRTIM or HRTIM timer
5912 specific information:
5913 (+) Get HRTIM HAL state
5914 (+) Get captured value
5915 (+) Get HRTIM timer output level
5916 (+) Get HRTIM timer output state
5917 (+) Get delayed protection status
5918 (+) Get burst status
5919 (+) Get current push-pull status
5920 (+) Get idle push-pull status
5921
5922 @endverbatim
5923 * @{
5924 */
5925
5926 /**
5927 * @brief Return the HRTIM HAL state
5928 * @param hhrtim pointer to HAL HRTIM handle
5929 * @retval HAL state
5930 */
HAL_HRTIM_GetState(const HRTIM_HandleTypeDef * hhrtim)5931 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim)
5932 {
5933 /* Return HRTIM state */
5934 return hhrtim->State;
5935 }
5936
5937 /**
5938 * @brief Return actual value of the capture register of the designated capture unit
5939 * @param hhrtim pointer to HAL HRTIM handle
5940 * @param TimerIdx Timer index
5941 * This parameter can be one of the following values:
5942 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5943 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5944 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5945 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5946 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5947 * @param CaptureUnit Capture unit to trig
5948 * This parameter can be one of the following values:
5949 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
5950 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
5951 * @retval Captured value
5952 */
HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit)5953 uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim,
5954 uint32_t TimerIdx,
5955 uint32_t CaptureUnit)
5956 {
5957 uint32_t captured_value;
5958
5959 /* Check parameters */
5960 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5961 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
5962
5963 /* Read captured value */
5964 switch (CaptureUnit)
5965 {
5966 case HRTIM_CAPTUREUNIT_1:
5967 {
5968 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR;
5969 break;
5970 }
5971
5972 case HRTIM_CAPTUREUNIT_2:
5973 {
5974 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
5975 break;
5976 }
5977
5978 default:
5979 {
5980 captured_value = 0xFFFFFFFFUL;
5981 break;
5982 }
5983
5984 }
5985
5986 return captured_value;
5987 }
5988
5989
5990 /**
5991 * @brief Return actual level (active or inactive) of the designated output
5992 * @param hhrtim pointer to HAL HRTIM handle
5993 * @param TimerIdx Timer index
5994 * This parameter can be one of the following values:
5995 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5996 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5997 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5998 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5999 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6000 * @param Output Timer output
6001 * This parameter can be one of the following values:
6002 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6003 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6004 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6005 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6006 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6007 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6008 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6009 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6010 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6011 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6012 * @retval Output level
6013 * @note Returned output level is taken before the output stage (chopper,
6014 * polarity).
6015 */
HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output)6016 uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim,
6017 uint32_t TimerIdx,
6018 uint32_t Output)
6019 {
6020 uint32_t output_level;
6021
6022 /* Check parameters */
6023 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6024
6025 /* Read the output level */
6026 switch (Output)
6027 {
6028 case HRTIM_OUTPUT_TA1:
6029 case HRTIM_OUTPUT_TB1:
6030 case HRTIM_OUTPUT_TC1:
6031 case HRTIM_OUTPUT_TD1:
6032 case HRTIM_OUTPUT_TE1:
6033 {
6034 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != (uint32_t)RESET)
6035 {
6036 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
6037 }
6038 else
6039 {
6040 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
6041 }
6042 break;
6043 }
6044
6045 case HRTIM_OUTPUT_TA2:
6046 case HRTIM_OUTPUT_TB2:
6047 case HRTIM_OUTPUT_TC2:
6048 case HRTIM_OUTPUT_TD2:
6049 case HRTIM_OUTPUT_TE2:
6050 {
6051 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != (uint32_t)RESET)
6052 {
6053 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
6054 }
6055 else
6056 {
6057 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
6058 }
6059 break;
6060 }
6061
6062 default:
6063 {
6064 output_level = 0xFFFFFFFFUL;
6065 break;
6066 }
6067 }
6068
6069 return output_level;
6070 }
6071
6072 /**
6073 * @brief Return actual state (RUN, IDLE, FAULT) of the designated output
6074 * @param hhrtim pointer to HAL HRTIM handle
6075 * @param TimerIdx Timer index
6076 * This parameter can be one of the following values:
6077 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6078 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6079 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6080 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6081 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6082 * @param Output Timer output
6083 * This parameter can be one of the following values:
6084 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6085 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6086 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6087 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6088 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6089 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6090 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6091 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6092 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6093 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6094 * @retval Output state
6095 */
HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output)6096 uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim,
6097 uint32_t TimerIdx,
6098 uint32_t Output)
6099 {
6100 uint32_t output_bit;
6101 uint32_t output_state;
6102
6103 /* Check parameters */
6104 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6105
6106 /* Prevent unused argument(s) compilation warning */
6107 UNUSED(TimerIdx);
6108
6109 /* Set output state according to output control status and output disable status */
6110 switch (Output)
6111 {
6112 case HRTIM_OUTPUT_TA1:
6113 {
6114 output_bit = HRTIM_OENR_TA1OEN;
6115 break;
6116 }
6117
6118 case HRTIM_OUTPUT_TA2:
6119 {
6120 output_bit = HRTIM_OENR_TA2OEN;
6121 break;
6122 }
6123
6124 case HRTIM_OUTPUT_TB1:
6125 {
6126 output_bit = HRTIM_OENR_TB1OEN;
6127 break;
6128 }
6129
6130 case HRTIM_OUTPUT_TB2:
6131 {
6132 output_bit = HRTIM_OENR_TB2OEN;
6133 break;
6134 }
6135
6136 case HRTIM_OUTPUT_TC1:
6137 {
6138 output_bit = HRTIM_OENR_TC1OEN;
6139 break;
6140 }
6141
6142 case HRTIM_OUTPUT_TC2:
6143 {
6144 output_bit = HRTIM_OENR_TC2OEN;
6145 break;
6146 }
6147
6148 case HRTIM_OUTPUT_TD1:
6149 {
6150 output_bit = HRTIM_OENR_TD1OEN;
6151 break;
6152 }
6153
6154 case HRTIM_OUTPUT_TD2:
6155 {
6156 output_bit = HRTIM_OENR_TD2OEN;
6157 break;
6158 }
6159
6160 case HRTIM_OUTPUT_TE1:
6161 {
6162 output_bit = HRTIM_OENR_TE1OEN;
6163 break;
6164 }
6165
6166 case HRTIM_OUTPUT_TE2:
6167 {
6168 output_bit = HRTIM_OENR_TE2OEN;
6169 break;
6170 }
6171
6172 default:
6173 {
6174 output_bit = 0UL;
6175 break;
6176 }
6177 }
6178
6179 if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != (uint32_t)RESET)
6180 {
6181 /* Output is enabled: output in RUN state (whatever output disable status is)*/
6182 output_state = HRTIM_OUTPUTSTATE_RUN;
6183 }
6184 else
6185 {
6186 if ((hhrtim->Instance->sCommonRegs.ODSR & output_bit) != (uint32_t)RESET)
6187 {
6188 /* Output is disabled: output in FAULT state */
6189 output_state = HRTIM_OUTPUTSTATE_FAULT;
6190 }
6191 else
6192 {
6193 /* Output is disabled: output in IDLE state */
6194 output_state = HRTIM_OUTPUTSTATE_IDLE;
6195 }
6196 }
6197
6198 return(output_state);
6199 }
6200
6201 /**
6202 * @brief Return the level (active or inactive) of the designated output
6203 * when the delayed protection was triggered.
6204 * @param hhrtim pointer to HAL HRTIM handle
6205 * @param TimerIdx Timer index
6206 * This parameter can be one of the following values:
6207 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6208 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6209 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6210 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6211 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6212 * @param Output Timer output
6213 * This parameter can be one of the following values:
6214 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6215 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6216 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6217 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6218 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6219 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6220 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6221 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6222 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6223 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6224 * @retval Delayed protection status
6225 */
HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output)6226 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim,
6227 uint32_t TimerIdx,
6228 uint32_t Output)
6229 {
6230 uint32_t delayed_protection_status;
6231
6232 /* Check parameters */
6233 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6234
6235 /* Read the delayed protection status */
6236 switch (Output)
6237 {
6238 case HRTIM_OUTPUT_TA1:
6239 case HRTIM_OUTPUT_TB1:
6240 case HRTIM_OUTPUT_TC1:
6241 case HRTIM_OUTPUT_TD1:
6242 case HRTIM_OUTPUT_TE1:
6243 {
6244 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != (uint32_t)RESET)
6245 {
6246 /* Output 1 was active when the delayed idle protection was triggered */
6247 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
6248 }
6249 else
6250 {
6251 /* Output 1 was inactive when the delayed idle protection was triggered */
6252 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
6253 }
6254 break;
6255 }
6256
6257 case HRTIM_OUTPUT_TA2:
6258 case HRTIM_OUTPUT_TB2:
6259 case HRTIM_OUTPUT_TC2:
6260 case HRTIM_OUTPUT_TD2:
6261 case HRTIM_OUTPUT_TE2:
6262 {
6263 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != (uint32_t)RESET)
6264 {
6265 /* Output 2 was active when the delayed idle protection was triggered */
6266 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
6267 }
6268 else
6269 {
6270 /* Output 2 was inactive when the delayed idle protection was triggered */
6271 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
6272 }
6273 break;
6274 }
6275
6276 default:
6277 {
6278 delayed_protection_status = 0xFFFFFFFFUL;
6279 break;
6280 }
6281 }
6282
6283 return delayed_protection_status;
6284 }
6285
6286 /**
6287 * @brief Return the actual status (active or inactive) of the burst mode controller
6288 * @param hhrtim pointer to HAL HRTIM handle
6289 * @retval Burst mode controller status
6290 */
HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim)6291 uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim)
6292 {
6293 uint32_t burst_mode_status;
6294
6295 /* Read burst mode status */
6296 burst_mode_status = (hhrtim->Instance->sCommonRegs.BMCR & HRTIM_BMCR_BMSTAT);
6297
6298 return burst_mode_status;
6299 }
6300
6301 /**
6302 * @brief Indicate on which output the signal is currently active (when the
6303 * push pull mode is enabled).
6304 * @param hhrtim pointer to HAL HRTIM handle
6305 * @param TimerIdx Timer index
6306 * This parameter can be one of the following values:
6307 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6308 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6309 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6310 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6311 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6312 * @retval Burst mode controller status
6313 */
HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6314 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim,
6315 uint32_t TimerIdx)
6316 {
6317 uint32_t current_pushpull_status;
6318
6319 /* Check the parameters */
6320 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
6321
6322 /* Read current push pull status */
6323 current_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
6324
6325 return current_pushpull_status;
6326 }
6327
6328
6329 /**
6330 * @brief Indicate on which output the signal was applied, in push-pull mode,
6331 balanced fault mode or delayed idle mode, when the protection was triggered.
6332 * @param hhrtim pointer to HAL HRTIM handle
6333 * @param TimerIdx Timer index
6334 * This parameter can be one of the following values:
6335 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6336 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6337 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6338 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6339 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6340 * @retval Idle Push Pull Status
6341 */
HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6342 uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim,
6343 uint32_t TimerIdx)
6344 {
6345 uint32_t idle_pushpull_status;
6346
6347 /* Check the parameters */
6348 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
6349
6350 /* Read current push pull status */
6351 idle_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
6352
6353 return idle_pushpull_status;
6354 }
6355
6356 /**
6357 * @}
6358 */
6359
6360 /** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling
6361 * @brief Functions called when HRTIM generates an interrupt
6362 * 7 interrupts can be generated by the master timer:
6363 * - Master timer registers update
6364 * - Synchronization event received
6365 * - Master timer repetition event
6366 * - Master Compare 1 to 4 event
6367 * 14 interrupts can be generated by each timing unit:
6368 * - Delayed protection triggered
6369 * - Counter reset or roll-over event
6370 * - Output 1 and output 2 reset (transition active to inactive)
6371 * - Output 1 and output 2 set (transition inactive to active)
6372 * - Capture 1 and 2 events
6373 * - Timing unit registers update
6374 * - Repetition event
6375 * - Compare 1 to 4 event
6376 * 7 global interrupts are generated for the whole HRTIM:
6377 * - System fault and Fault 1 to 5 (regardless of the timing unit attribution)
6378 * - Burst mode period completed
6379 @verbatim
6380 ===============================================================================
6381 ##### HRTIM interrupts handling #####
6382 ===============================================================================
6383 [..]
6384 This subsection provides a set of functions allowing to manage the HRTIM
6385 interrupts:
6386 (+) HRTIM interrupt handler
6387 (+) Callback function called when Fault1 interrupt occurs
6388 (+) Callback function called when Fault2 interrupt occurs
6389 (+) Callback function called when Fault3 interrupt occurs
6390 (+) Callback function called when Fault4 interrupt occurs
6391 (+) Callback function called when Fault5 interrupt occurs
6392 (+) Callback function called when system Fault interrupt occurs
6393 (+) Callback function called when burst mode period interrupt occurs
6394 (+) Callback function called when synchronization input interrupt occurs
6395 (+) Callback function called when a timer register update interrupt occurs
6396 (+) Callback function called when a timer repetition interrupt occurs
6397 (+) Callback function called when a compare 1 match interrupt occurs
6398 (+) Callback function called when a compare 2 match interrupt occurs
6399 (+) Callback function called when a compare 3 match interrupt occurs
6400 (+) Callback function called when a compare 4 match interrupt occurs
6401 (+) Callback function called when a capture 1 interrupt occurs
6402 (+) Callback function called when a capture 2 interrupt occurs
6403 (+) Callback function called when a delayed protection interrupt occurs
6404 (+) Callback function called when a timer counter reset interrupt occurs
6405 (+) Callback function called when a timer output 1 set interrupt occurs
6406 (+) Callback function called when a timer output 1 reset interrupt occurs
6407 (+) Callback function called when a timer output 2 set interrupt occurs
6408 (+) Callback function called when a timer output 2 reset interrupt occurs
6409 (+) Callback function called when a timer output 2 reset interrupt occurs
6410 (+) Callback function called upon completion of a burst DMA transfer
6411 (+) HRTIM callback function registration
6412 (+) HRTIM callback function unregistration
6413 (+) HRTIM Timer x callback function registration
6414 (+) HRTIM Timer x callback function unregistration
6415
6416 @endverbatim
6417 * @{
6418 */
6419
6420 /**
6421 * @brief This function handles HRTIM interrupt request.
6422 * @param hhrtim pointer to HAL HRTIM handle
6423 * @param TimerIdx Timer index
6424 * This parameter can be any value of HRTIM_Timer_Index
6425 * @retval None
6426 */
HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6427 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,
6428 uint32_t TimerIdx)
6429 {
6430 /* HRTIM interrupts handling */
6431 if (TimerIdx == HRTIM_TIMERINDEX_COMMON)
6432 {
6433 HRTIM_HRTIM_ISR(hhrtim);
6434 }
6435 else if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
6436 {
6437 /* Master related interrupts handling */
6438 HRTIM_Master_ISR(hhrtim);
6439 }
6440 else
6441 {
6442 /* Timing unit related interrupts handling */
6443 HRTIM_Timer_ISR(hhrtim, TimerIdx);
6444 }
6445
6446 }
6447
6448 /**
6449 * @brief Callback function invoked when a fault 1 interrupt occurred
6450 * @param hhrtim pointer to HAL HRTIM handle * @retval None
6451 * @retval None
6452 */
HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)6453 __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)
6454 {
6455 /* Prevent unused argument(s) compilation warning */
6456 UNUSED(hhrtim);
6457
6458 /* NOTE : This function should not be modified, when the callback is needed,
6459 the HAL_HRTIM_Fault1Callback could be implemented in the user file
6460 */
6461 }
6462
6463 /**
6464 * @brief Callback function invoked when a fault 2 interrupt occurred
6465 * @param hhrtim pointer to HAL HRTIM handle
6466 * @retval None
6467 */
HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)6468 __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)
6469 {
6470 /* Prevent unused argument(s) compilation warning */
6471 UNUSED(hhrtim);
6472
6473 /* NOTE : This function should not be modified, when the callback is needed,
6474 the HAL_HRTIM_Fault2Callback could be implemented in the user file
6475 */
6476 }
6477
6478 /**
6479 * @brief Callback function invoked when a fault 3 interrupt occurred
6480 * @param hhrtim pointer to HAL HRTIM handle
6481 * @retval None
6482 */
HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)6483 __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)
6484 {
6485 /* Prevent unused argument(s) compilation warning */
6486 UNUSED(hhrtim);
6487
6488 /* NOTE : This function should not be modified, when the callback is needed,
6489 the HAL_HRTIM_Fault3Callback could be implemented in the user file
6490 */
6491 }
6492
6493 /**
6494 * @brief Callback function invoked when a fault 4 interrupt occurred
6495 * @param hhrtim pointer to HAL HRTIM handle
6496 * @retval None
6497 */
HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)6498 __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)
6499 {
6500 /* Prevent unused argument(s) compilation warning */
6501 UNUSED(hhrtim);
6502
6503 /* NOTE : This function should not be modified, when the callback is needed,
6504 the HAL_HRTIM_Fault4Callback could be implemented in the user file
6505 */
6506 }
6507
6508 /**
6509 * @brief Callback function invoked when a fault 5 interrupt occurred
6510 * @param hhrtim pointer to HAL HRTIM handle
6511 * @retval None
6512 */
HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)6513 __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)
6514 {
6515 /* Prevent unused argument(s) compilation warning */
6516 UNUSED(hhrtim);
6517
6518 /* NOTE : This function should not be modified, when the callback is needed,
6519 the HAL_HRTIM_Fault5Callback could be implemented in the user file
6520 */
6521 }
6522
6523 /**
6524 * @brief Callback function invoked when a system fault interrupt occurred
6525 * @param hhrtim pointer to HAL HRTIM handle
6526 * @retval None
6527 */
HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)6528 __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)
6529 {
6530 /* Prevent unused argument(s) compilation warning */
6531 UNUSED(hhrtim);
6532
6533 /* NOTE : This function should not be modified, when the callback is needed,
6534 the HAL_HRTIM_SystemFaultCallback could be implemented in the user file
6535 */
6536 }
6537
6538 /**
6539 * @brief Callback function invoked when the end of the burst mode period is reached
6540 * @param hhrtim pointer to HAL HRTIM handle
6541 * @retval None
6542 */
HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)6543 __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)
6544 {
6545 /* Prevent unused argument(s) compilation warning */
6546 UNUSED(hhrtim);
6547
6548 /* NOTE : This function should not be modified, when the callback is needed,
6549 the HAL_HRTIM_BurstModeCallback could be implemented in the user file
6550 */
6551 }
6552
6553 /**
6554 * @brief Callback function invoked when a synchronization input event is received
6555 * @param hhrtim pointer to HAL HRTIM handle
6556 * @retval None
6557 */
HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)6558 __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)
6559 {
6560 /* Prevent unused argument(s) compilation warning */
6561 UNUSED(hhrtim);
6562
6563 /* NOTE : This function should not be modified, when the callback is needed,
6564 the HAL_HRTIM_SynchronizationEventCallback could be implemented in the user file
6565 */
6566 }
6567
6568 /**
6569 * @brief Callback function invoked when timer registers are updated
6570 * @param hhrtim pointer to HAL HRTIM handle
6571 * @param TimerIdx Timer index
6572 * This parameter can be one of the following values:
6573 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6574 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6575 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6576 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6577 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6578 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6579 * @retval None
6580 */
HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6581 __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,
6582 uint32_t TimerIdx)
6583 {
6584 /* Prevent unused argument(s) compilation warning */
6585 UNUSED(hhrtim);
6586 UNUSED(TimerIdx);
6587
6588 /* NOTE : This function should not be modified, when the callback is needed,
6589 the HAL_HRTIM_Master_RegistersUpdateCallback could be implemented in the user file
6590 */
6591 }
6592
6593 /**
6594 * @brief Callback function invoked when timer repetition period has elapsed
6595 * @param hhrtim pointer to HAL HRTIM handle
6596 * @param TimerIdx Timer index
6597 * This parameter can be one of the following values:
6598 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6599 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6600 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6601 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6602 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6603 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6604 * @retval None
6605 */
HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6606 __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,
6607 uint32_t TimerIdx)
6608 {
6609 /* Prevent unused argument(s) compilation warning */
6610 UNUSED(hhrtim);
6611 UNUSED(TimerIdx);
6612
6613 /* NOTE : This function should not be modified, when the callback is needed,
6614 the HAL_HRTIM_Master_RepetitionEventCallback could be implemented in the user file
6615 */
6616 }
6617
6618 /**
6619 * @brief Callback function invoked when the timer counter matches the value
6620 * programmed in the compare 1 register
6621 * @param hhrtim pointer to HAL HRTIM handle
6622 * @param TimerIdx Timer index
6623 * This parameter can be one of the following values:
6624 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6625 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6626 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6627 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6628 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6629 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6630 * @retval None
6631 */
HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6632 __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,
6633 uint32_t TimerIdx)
6634 {
6635 /* Prevent unused argument(s) compilation warning */
6636 UNUSED(hhrtim);
6637 UNUSED(TimerIdx);
6638
6639 /* NOTE : This function should not be modified, when the callback is needed,
6640 the HAL_HRTIM_Master_Compare1EventCallback could be implemented in the user file
6641 */
6642 }
6643
6644 /**
6645 * @brief Callback function invoked when the timer counter matches the value
6646 * programmed in the compare 2 register
6647 * @param hhrtim pointer to HAL HRTIM handle
6648 * @retval None
6649 * @param TimerIdx Timer index
6650 * This parameter can be one of the following values:
6651 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6652 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6653 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6654 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6655 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6656 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6657 */
HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6658 __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,
6659 uint32_t TimerIdx)
6660 {
6661 /* Prevent unused argument(s) compilation warning */
6662 UNUSED(hhrtim);
6663 UNUSED(TimerIdx);
6664
6665 /* NOTE : This function should not be modified, when the callback is needed,
6666 the HAL_HRTIM_Master_Compare2EventCallback could be implemented in the user file
6667 */
6668 }
6669
6670 /**
6671 * @brief Callback function invoked when the timer counter matches the value
6672 * programmed in the compare 3 register
6673 * @param hhrtim pointer to HAL HRTIM handle
6674 * @param TimerIdx Timer index
6675 * This parameter can be one of the following values:
6676 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6677 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6678 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6679 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6680 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6681 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6682 * @retval None
6683 */
HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6684 __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,
6685 uint32_t TimerIdx)
6686 {
6687 /* Prevent unused argument(s) compilation warning */
6688 UNUSED(hhrtim);
6689 UNUSED(TimerIdx);
6690
6691 /* NOTE : This function should not be modified, when the callback is needed,
6692 the HAL_HRTIM_Master_Compare3EventCallback could be implemented in the user file
6693 */
6694 }
6695
6696 /**
6697 * @brief Callback function invoked when the timer counter matches the value
6698 * programmed in the compare 4 register.
6699 * @param hhrtim pointer to HAL HRTIM handle
6700 * @param TimerIdx Timer index
6701 * This parameter can be one of the following values:
6702 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6703 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6704 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6705 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6706 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6707 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6708 * @retval None
6709 */
HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6710 __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,
6711 uint32_t TimerIdx)
6712 {
6713 /* Prevent unused argument(s) compilation warning */
6714 UNUSED(hhrtim);
6715 UNUSED(TimerIdx);
6716
6717 /* NOTE : This function should not be modified, when the callback is needed,
6718 the HAL_HRTIM_Master_Compare4EventCallback could be implemented in the user file
6719 */
6720 }
6721
6722 /**
6723 * @brief Callback function invoked when the timer x capture 1 event occurs
6724 * @param hhrtim pointer to HAL HRTIM handle
6725 * @param TimerIdx Timer index
6726 * This parameter can be one of the following values:
6727 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6728 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6729 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6730 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6731 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6732 * @retval None
6733 */
HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6734 __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,
6735 uint32_t TimerIdx)
6736 {
6737 /* Prevent unused argument(s) compilation warning */
6738 UNUSED(hhrtim);
6739 UNUSED(TimerIdx);
6740
6741 /* NOTE : This function should not be modified, when the callback is needed,
6742 the HAL_HRTIM_Timer_Capture1EventCallback could be implemented in the user file
6743 */
6744 }
6745
6746 /**
6747 * @brief Callback function invoked when the timer x capture 2 event occurs
6748 * @param hhrtim pointer to HAL HRTIM handle
6749 * @param TimerIdx Timer index
6750 * This parameter can be one of the following values:
6751 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6752 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6753 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6754 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6755 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6756 * @retval None
6757 */
HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6758 __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,
6759 uint32_t TimerIdx)
6760 {
6761 /* Prevent unused argument(s) compilation warning */
6762 UNUSED(hhrtim);
6763 UNUSED(TimerIdx);
6764
6765 /* NOTE : This function should not be modified, when the callback is needed,
6766 the HAL_HRTIM_Timer_Capture2EventCallback could be implemented in the user file
6767 */
6768 }
6769
6770 /**
6771 * @brief Callback function invoked when the delayed idle or balanced idle mode is
6772 * entered.
6773 * @param hhrtim pointer to HAL HRTIM handle
6774 * @param TimerIdx Timer index
6775 * This parameter can be one of the following values:
6776 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6777 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6778 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6779 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6780 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6781 * @retval None
6782 */
HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6783 __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,
6784 uint32_t TimerIdx)
6785 {
6786 /* Prevent unused argument(s) compilation warning */
6787 UNUSED(hhrtim);
6788 UNUSED(TimerIdx);
6789
6790 /* NOTE : This function should not be modified, when the callback is needed,
6791 the HAL_HRTIM_Timer_DelayedProtectionCallback could be implemented in the user file
6792 */
6793 }
6794
6795 /**
6796 * @brief Callback function invoked when the timer x counter reset/roll-over
6797 * event occurs.
6798 * @param hhrtim pointer to HAL HRTIM handle
6799 * @param TimerIdx Timer index
6800 * This parameter can be one of the following values:
6801 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6802 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6803 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6804 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6805 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6806 * @retval None
6807 */
HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6808 __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,
6809 uint32_t TimerIdx)
6810 {
6811 /* Prevent unused argument(s) compilation warning */
6812 UNUSED(hhrtim);
6813 UNUSED(TimerIdx);
6814
6815 /* NOTE : This function should not be modified, when the callback is needed,
6816 the HAL_HRTIM_Timer_CounterResetCallback could be implemented in the user file
6817 */
6818 }
6819
6820 /**
6821 * @brief Callback function invoked when the timer x output 1 is set
6822 * @param hhrtim pointer to HAL HRTIM handle
6823 * @param TimerIdx Timer index
6824 * This parameter can be one of the following values:
6825 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6826 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6827 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6828 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6829 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6830 * @retval None
6831 */
HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6832 __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,
6833 uint32_t TimerIdx)
6834 {
6835 /* Prevent unused argument(s) compilation warning */
6836 UNUSED(hhrtim);
6837 UNUSED(TimerIdx);
6838
6839 /* NOTE : This function should not be modified, when the callback is needed,
6840 the HAL_HRTIM_Timer_Output1SetCallback could be implemented in the user file
6841 */
6842 }
6843
6844 /**
6845 * @brief Callback function invoked when the timer x output 1 is reset
6846 * @param hhrtim pointer to HAL HRTIM handle
6847 * @param TimerIdx Timer index
6848 * This parameter can be one of the following values:
6849 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6850 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6851 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6852 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6853 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6854 * @retval None
6855 */
HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6856 __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,
6857 uint32_t TimerIdx)
6858 {
6859 /* Prevent unused argument(s) compilation warning */
6860 UNUSED(hhrtim);
6861 UNUSED(TimerIdx);
6862
6863 /* NOTE : This function should not be modified, when the callback is needed,
6864 the HAL_HRTIM_Timer_Output1ResetCallback could be implemented in the user file
6865 */
6866 }
6867
6868 /**
6869 * @brief Callback function invoked when the timer x output 2 is set
6870 * @param hhrtim pointer to HAL HRTIM handle
6871 * @param TimerIdx Timer index
6872 * This parameter can be one of the following values:
6873 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6874 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6875 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6876 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6877 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6878 * @retval None
6879 */
HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6880 __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,
6881 uint32_t TimerIdx)
6882 {
6883 /* Prevent unused argument(s) compilation warning */
6884 UNUSED(hhrtim);
6885 UNUSED(TimerIdx);
6886
6887 /* NOTE : This function should not be modified, when the callback is needed,
6888 the HAL_HRTIM_Timer_Output2SetCallback could be implemented in the user file
6889 */
6890 }
6891
6892 /**
6893 * @brief Callback function invoked when the timer x output 2 is reset
6894 * @param hhrtim pointer to HAL HRTIM handle
6895 * @param TimerIdx Timer index
6896 * This parameter can be one of the following values:
6897 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6898 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6899 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6900 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6901 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6902 * @retval None
6903 */
HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6904 __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,
6905 uint32_t TimerIdx)
6906 {
6907 /* Prevent unused argument(s) compilation warning */
6908 UNUSED(hhrtim);
6909 UNUSED(TimerIdx);
6910
6911 /* NOTE : This function should not be modified, when the callback is needed,
6912 the HAL_HRTIM_Timer_Output2ResetCallback could be implemented in the user file
6913 */
6914 }
6915
6916 /**
6917 * @brief Callback function invoked when a DMA burst transfer is completed
6918 * @param hhrtim pointer to HAL HRTIM handle
6919 * @param TimerIdx Timer index
6920 * This parameter can be one of the following values:
6921 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6922 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6923 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6924 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6925 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6926 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6927 * @retval None
6928 */
HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6929 __weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,
6930 uint32_t TimerIdx)
6931 {
6932 /* Prevent unused argument(s) compilation warning */
6933 UNUSED(hhrtim);
6934 UNUSED(TimerIdx);
6935
6936 /* NOTE : This function should not be modified, when the callback is needed,
6937 the HAL_HRTIM_BurstDMATransferCallback could be implemented in the user file
6938 */
6939 }
6940
6941 /**
6942 * @brief Callback function invoked when a DMA error occurs
6943 * @param hhrtim pointer to HAL HRTIM handle
6944 * @retval None
6945 */
HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef * hhrtim)6946 __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
6947 {
6948 /* Prevent unused argument(s) compilation warning */
6949 UNUSED(hhrtim);
6950
6951 /* NOTE : This function should not be modified, when the callback is needed,
6952 the HAL_HRTIM_ErrorCallback could be implemented in the user file
6953 */
6954 }
6955
6956 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
6957 /**
6958 * @brief HRTIM callback function registration
6959 * @param hhrtim pointer to HAL HRTIM handle
6960 * @param CallbackID ID of the HRTIM callback function to register
6961 * This parameter can be one of the following values:
6962 * @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
6963 * @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
6964 * @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
6965 * @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
6966 * @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
6967 * @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
6968 * @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
6969 * @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
6970 * @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
6971 * @arg HAL_HRTIM_MSPINIT_CB_ID
6972 * @arg HAL_HRTIM_MSPDEINIT_CB_ID
6973 * @param pCallback Callback function pointer
6974 * @retval HAL status
6975 */
HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID,pHRTIM_CallbackTypeDef pCallback)6976 HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim,
6977 HAL_HRTIM_CallbackIDTypeDef CallbackID,
6978 pHRTIM_CallbackTypeDef pCallback)
6979 {
6980 HAL_StatusTypeDef status = HAL_OK;
6981
6982 if (pCallback == NULL)
6983 {
6984 /* Update the state */
6985 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
6986
6987 return HAL_ERROR;
6988 }
6989
6990 /* Process locked */
6991 __HAL_LOCK(hhrtim);
6992
6993 if (HAL_HRTIM_STATE_READY == hhrtim->State)
6994 {
6995 switch (CallbackID)
6996 {
6997 case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
6998 hhrtim->Fault1Callback = pCallback;
6999 break;
7000
7001 case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
7002 hhrtim->Fault2Callback = pCallback;
7003 break;
7004
7005 case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
7006 hhrtim->Fault3Callback = pCallback;
7007 break;
7008
7009 case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
7010 hhrtim->Fault4Callback = pCallback;
7011 break;
7012
7013 case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
7014 hhrtim->Fault5Callback = pCallback;
7015 break;
7016
7017 case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
7018 hhrtim->SystemFaultCallback = pCallback;
7019 break;
7020
7021
7022 case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
7023 hhrtim->BurstModePeriodCallback = pCallback;
7024 break;
7025
7026 case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
7027 hhrtim->SynchronizationEventCallback = pCallback;
7028 break;
7029
7030 case HAL_HRTIM_ERRORCALLBACK_CB_ID :
7031 hhrtim->ErrorCallback = pCallback;
7032 break;
7033
7034 case HAL_HRTIM_MSPINIT_CB_ID :
7035 hhrtim->MspInitCallback = pCallback;
7036 break;
7037
7038 case HAL_HRTIM_MSPDEINIT_CB_ID :
7039 hhrtim->MspDeInitCallback = pCallback;
7040 break;
7041
7042 default :
7043 /* Update the state */
7044 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7045
7046 /* Return error status */
7047 status = HAL_ERROR;
7048 break;
7049 }
7050 }
7051 else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
7052 {
7053 switch (CallbackID)
7054 {
7055 case HAL_HRTIM_MSPINIT_CB_ID :
7056 hhrtim->MspInitCallback = pCallback;
7057 break;
7058
7059 case HAL_HRTIM_MSPDEINIT_CB_ID :
7060 hhrtim->MspDeInitCallback = pCallback;
7061 break;
7062
7063 default :
7064 /* Update the state */
7065 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7066
7067 /* Return error status */
7068 status = HAL_ERROR;
7069 break;
7070 }
7071 }
7072 else
7073 {
7074 /* Update the state */
7075 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7076
7077 /* Return error status */
7078 status = HAL_ERROR;
7079 }
7080
7081 /* Release Lock */
7082 __HAL_UNLOCK(hhrtim);
7083
7084 return status;
7085 }
7086
7087 /**
7088 * @brief HRTIM callback function un-registration
7089 * @param hhrtim pointer to HAL HRTIM handle
7090 * @param CallbackID ID of the HRTIM callback function to unregister
7091 * This parameter can be one of the following values:
7092 * @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
7093 * @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
7094 * @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
7095 * @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
7096 * @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
7097 * @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
7098 * @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
7099 * @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
7100 * @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
7101 * @arg HAL_HRTIM_MSPINIT_CB_ID
7102 * @arg HAL_HRTIM_MSPDEINIT_CB_ID
7103 * @retval HAL status
7104 */
HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID)7105 HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
7106 HAL_HRTIM_CallbackIDTypeDef CallbackID)
7107 {
7108 HAL_StatusTypeDef status = HAL_OK;
7109
7110 /* Process locked */
7111 __HAL_LOCK(hhrtim);
7112
7113 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7114 {
7115 switch (CallbackID)
7116 {
7117 case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
7118 hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
7119 break;
7120
7121 case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
7122 hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
7123 break;
7124
7125 case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
7126 hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
7127 break;
7128
7129 case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
7130 hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
7131 break;
7132
7133 case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
7134 hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
7135 break;
7136
7137 case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
7138 hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
7139 break;
7140
7141
7142 case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
7143 hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
7144 break;
7145
7146 case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
7147 hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
7148 break;
7149
7150 case HAL_HRTIM_ERRORCALLBACK_CB_ID :
7151 hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
7152 break;
7153
7154 case HAL_HRTIM_MSPINIT_CB_ID :
7155 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
7156 break;
7157
7158 case HAL_HRTIM_MSPDEINIT_CB_ID :
7159 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
7160 break;
7161
7162 default :
7163 /* Update the state */
7164 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7165
7166 /* Return error status */
7167 status = HAL_ERROR;
7168 break;
7169 }
7170 }
7171 else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
7172 {
7173 switch (CallbackID)
7174 {
7175 case HAL_HRTIM_MSPINIT_CB_ID :
7176 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
7177 break;
7178
7179 case HAL_HRTIM_MSPDEINIT_CB_ID :
7180 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
7181 break;
7182
7183 default :
7184 /* Update the state */
7185 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7186
7187 /* Return error status */
7188 status = HAL_ERROR;
7189 break;
7190 }
7191 }
7192 else
7193 {
7194 /* Update the state */
7195 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7196
7197 /* Return error status */
7198 status = HAL_ERROR;
7199 }
7200
7201 /* Release Lock */
7202 __HAL_UNLOCK(hhrtim);
7203
7204 return status;
7205 }
7206
7207 /**
7208 * @brief HRTIM Timer x callback function registration
7209 * @param hhrtim pointer to HAL HRTIM handle
7210 * @param CallbackID ID of the HRTIM Timer x callback function to register
7211 * This parameter can be one of the following values:
7212 * @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
7213 * @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
7214 * @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
7215 * @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
7216 * @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
7217 * @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
7218 * @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
7219 * @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
7220 * @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
7221 * @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
7222 * @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
7223 * @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
7224 * @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
7225 * @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
7226 * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
7227 * @param pCallback Callback function pointer
7228 * @retval HAL status
7229 */
HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID,pHRTIM_TIMxCallbackTypeDef pCallback)7230 HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
7231 HAL_HRTIM_CallbackIDTypeDef CallbackID,
7232 pHRTIM_TIMxCallbackTypeDef pCallback)
7233 {
7234 HAL_StatusTypeDef status = HAL_OK;
7235
7236 if (pCallback == NULL)
7237 {
7238 /* Update the state */
7239 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7240
7241 return HAL_ERROR;
7242 }
7243
7244 /* Process locked */
7245 __HAL_LOCK(hhrtim);
7246
7247 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7248 {
7249 switch (CallbackID)
7250 {
7251 case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
7252 hhrtim->RegistersUpdateCallback = pCallback;
7253 break;
7254
7255 case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
7256 hhrtim->RepetitionEventCallback = pCallback;
7257 break;
7258
7259 case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
7260 hhrtim->Compare1EventCallback = pCallback;
7261 break;
7262
7263 case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
7264 hhrtim->Compare2EventCallback = pCallback;
7265 break;
7266
7267 case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
7268 hhrtim->Compare3EventCallback = pCallback;
7269 break;
7270
7271 case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
7272 hhrtim->Compare4EventCallback = pCallback;
7273 break;
7274
7275 case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
7276 hhrtim->Capture1EventCallback = pCallback;
7277 break;
7278
7279 case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
7280 hhrtim->Capture2EventCallback = pCallback;
7281 break;
7282
7283 case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
7284 hhrtim->DelayedProtectionCallback = pCallback;
7285 break;
7286
7287 case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
7288 hhrtim->CounterResetCallback = pCallback;
7289 break;
7290
7291 case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
7292 hhrtim->Output1SetCallback = pCallback;
7293 break;
7294
7295 case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
7296 hhrtim->Output1ResetCallback = pCallback;
7297 break;
7298
7299 case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
7300 hhrtim->Output2SetCallback = pCallback;
7301 break;
7302
7303 case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
7304 hhrtim->Output2ResetCallback = pCallback;
7305 break;
7306
7307 case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
7308 hhrtim->BurstDMATransferCallback = pCallback;
7309 break;
7310
7311 default :
7312 /* Update the state */
7313 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7314
7315 /* Return error status */
7316 status = HAL_ERROR;
7317 break;
7318 }
7319 }
7320 else
7321 {
7322 /* Update the state */
7323 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7324
7325 /* Return error status */
7326 status = HAL_ERROR;
7327 }
7328
7329 /* Release Lock */
7330 __HAL_UNLOCK(hhrtim);
7331
7332 return status;
7333 }
7334
7335 /**
7336 * @brief HRTIM Timer x callback function un-registration
7337 * @param hhrtim pointer to HAL HRTIM handle
7338 * @param CallbackID ID of the HRTIM callback Timer x function to unregister
7339 * This parameter can be one of the following values:
7340 * @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
7341 * @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
7342 * @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
7343 * @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
7344 * @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
7345 * @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
7346 * @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
7347 * @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
7348 * @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
7349 * @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
7350 * @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
7351 * @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
7352 * @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
7353 * @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
7354 * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
7355 * @retval HAL status
7356 */
HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID)7357 HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
7358 HAL_HRTIM_CallbackIDTypeDef CallbackID)
7359 {
7360 HAL_StatusTypeDef status = HAL_OK;
7361
7362 /* Process locked */
7363 __HAL_LOCK(hhrtim);
7364
7365 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7366 {
7367 switch (CallbackID)
7368 {
7369 case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
7370 hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
7371 break;
7372
7373 case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
7374 hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
7375 break;
7376
7377 case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
7378 hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
7379 break;
7380
7381 case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
7382 hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
7383 break;
7384
7385 case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
7386 hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
7387 break;
7388
7389 case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
7390 hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
7391 break;
7392
7393 case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
7394 hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
7395 break;
7396
7397 case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
7398 hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
7399 break;
7400
7401 case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
7402 hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
7403 break;
7404
7405 case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
7406 hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
7407 break;
7408
7409 case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
7410 hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
7411 break;
7412
7413 case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
7414 hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
7415 break;
7416
7417 case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
7418 hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
7419 break;
7420
7421 case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
7422 hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
7423 break;
7424
7425 case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
7426 hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
7427 break;
7428
7429 default :
7430 /* Update the state */
7431 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7432
7433 /* Return error status */
7434 status = HAL_ERROR;
7435 break;
7436 }
7437 }
7438 else
7439 {
7440 /* Update the state */
7441 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7442
7443 /* Return error status */
7444 status = HAL_ERROR;
7445 }
7446
7447 /* Release Lock */
7448 __HAL_UNLOCK(hhrtim);
7449
7450 return status;
7451 }
7452 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
7453 /**
7454 * @}
7455 */
7456
7457 /**
7458 * @}
7459 */
7460
7461 /** @addtogroup HRTIM_Private_Functions
7462 * @{
7463 */
7464
7465 /**
7466 * @brief Configure the master timer time base
7467 * @param hhrtim pointer to HAL HRTIM handle
7468 * @param pTimeBaseCfg pointer to the time base configuration structure
7469 * @retval None
7470 */
HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)7471 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
7472 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
7473 {
7474 uint32_t hrtim_mcr;
7475
7476 /* Configure master timer */
7477 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
7478
7479 /* Set the prescaler ratio */
7480 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
7481 hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
7482
7483 /* Set the operating mode */
7484 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
7485 hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
7486
7487 /* Update the HRTIM registers */
7488 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
7489 hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
7490 hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
7491 }
7492
7493 /**
7494 * @brief Configure timing unit (Timer A to Timer E) time base
7495 * @param hhrtim pointer to HAL HRTIM handle
7496 * @param TimerIdx Timer index
7497 * @param pTimeBaseCfg pointer to the time base configuration structure
7498 * @retval None
7499 */
HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)7500 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
7501 uint32_t TimerIdx ,
7502 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
7503 {
7504 uint32_t hrtim_timcr;
7505
7506 /* Configure master timing unit */
7507 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
7508
7509 /* Set the prescaler ratio */
7510 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
7511 hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
7512
7513 /* Set the operating mode */
7514 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
7515 hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
7516
7517 /* Update the HRTIM registers */
7518 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
7519 hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
7520 hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
7521 }
7522
7523 /**
7524 * @brief Configure the master timer in waveform mode
7525 * @param hhrtim pointer to HAL HRTIM handle
7526 * @param pTimerCfg pointer to the timer configuration data structure
7527 * @retval None
7528 */
HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,const HRTIM_TimerCfgTypeDef * pTimerCfg)7529 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
7530 const HRTIM_TimerCfgTypeDef * pTimerCfg)
7531 {
7532 uint32_t hrtim_mcr;
7533 uint32_t hrtim_bmcr;
7534
7535 /* Configure master timer */
7536 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
7537 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
7538
7539 /* Enable/Disable the half mode */
7540 hrtim_mcr &= ~(HRTIM_MCR_HALF);
7541 hrtim_mcr |= pTimerCfg->HalfModeEnable;
7542
7543 /* Enable/Disable the timer start upon synchronization event reception */
7544 hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
7545 hrtim_mcr |= pTimerCfg->StartOnSync;
7546
7547 /* Enable/Disable the timer reset upon synchronization event reception */
7548 hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
7549 hrtim_mcr |= pTimerCfg->ResetOnSync;
7550
7551 /* Enable/Disable the DAC synchronization event generation */
7552 hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
7553 hrtim_mcr |= pTimerCfg->DACSynchro;
7554
7555 /* Enable/Disable preload mechanism for timer registers */
7556 hrtim_mcr &= ~(HRTIM_MCR_PREEN);
7557 hrtim_mcr |= pTimerCfg->PreloadEnable;
7558
7559 /* Master timer registers update handling */
7560 hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
7561 hrtim_mcr |= (pTimerCfg->UpdateGating << 2U);
7562
7563 /* Enable/Disable registers update on repetition */
7564 hrtim_mcr &= ~(HRTIM_MCR_MREPU);
7565 hrtim_mcr |= pTimerCfg->RepetitionUpdate;
7566
7567 /* Set the timer burst mode */
7568 hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
7569 hrtim_bmcr |= pTimerCfg->BurstMode;
7570
7571 /* Update the HRTIM registers */
7572 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
7573 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
7574 }
7575
7576 /**
7577 * @brief Configure timing unit (Timer A to Timer E) in waveform mode
7578 * @param hhrtim pointer to HAL HRTIM handle
7579 * @param TimerIdx Timer index
7580 * @param pTimerCfg pointer to the timer configuration data structure
7581 * @retval None
7582 */
HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimerCfgTypeDef * pTimerCfg)7583 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
7584 uint32_t TimerIdx,
7585 const HRTIM_TimerCfgTypeDef * pTimerCfg)
7586 {
7587 uint32_t hrtim_timcr;
7588 uint32_t hrtim_timfltr;
7589 uint32_t hrtim_timoutr;
7590 uint32_t hrtim_timrstr;
7591 uint32_t hrtim_bmcr;
7592
7593 /* UPDGAT bitfield must be reset before programming a new value */
7594 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
7595
7596 /* Configure timing unit (Timer A to Timer E) */
7597 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
7598 hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
7599 hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
7600 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
7601
7602 /* Enable/Disable the half mode */
7603 hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
7604 hrtim_timcr |= pTimerCfg->HalfModeEnable;
7605
7606 /* Enable/Disable the timer start upon synchronization event reception */
7607 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
7608 hrtim_timcr |= pTimerCfg->StartOnSync;
7609
7610 /* Enable/Disable the timer reset upon synchronization event reception */
7611 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
7612 hrtim_timcr |= pTimerCfg->ResetOnSync;
7613
7614 /* Enable/Disable the DAC synchronization event generation */
7615 hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
7616 hrtim_timcr |= pTimerCfg->DACSynchro;
7617
7618 /* Enable/Disable preload mechanism for timer registers */
7619 hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
7620 hrtim_timcr |= pTimerCfg->PreloadEnable;
7621
7622 /* Timing unit registers update handling */
7623 hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
7624 hrtim_timcr |= pTimerCfg->UpdateGating;
7625
7626 /* Enable/Disable registers update on repetition */
7627 hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
7628 if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
7629 {
7630 hrtim_timcr |= HRTIM_TIMCR_TREPU;
7631 }
7632
7633 /* Set the push-pull mode */
7634 hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
7635 hrtim_timcr |= pTimerCfg->PushPull;
7636
7637 /* Enable/Disable registers update on timer counter reset */
7638 hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
7639 hrtim_timcr |= pTimerCfg->ResetUpdate;
7640
7641 /* Set the timer update trigger */
7642 hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
7643 hrtim_timcr |= pTimerCfg->UpdateTrigger;
7644
7645 /* Enable/Disable the fault channel at timer level */
7646 hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
7647 hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
7648
7649 /* Lock/Unlock fault sources at timer level */
7650 hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
7651 hrtim_timfltr |= pTimerCfg->FaultLock;
7652
7653 /* The deadtime cannot be used simultaneously with the push-pull mode */
7654 if (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_DISABLED)
7655 {
7656 /* Enable/Disable dead time insertion at timer level */
7657 hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
7658 hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
7659 }
7660
7661 /* Enable/Disable delayed protection at timer level
7662 Delayed Idle is available whatever the timer operating mode (regular, push-pull)
7663 Balanced Idle is only available in push-pull mode
7664 */
7665 if ( ((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)
7666 && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))
7667 || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
7668 {
7669 hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
7670 hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
7671 }
7672
7673 /* Set the timer counter reset trigger */
7674 hrtim_timrstr = pTimerCfg->ResetTrigger;
7675
7676 /* Set the timer burst mode */
7677 switch (TimerIdx)
7678 {
7679 case HRTIM_TIMERINDEX_TIMER_A:
7680 {
7681 hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
7682 hrtim_bmcr |= ( pTimerCfg->BurstMode << 1U);
7683 break;
7684 }
7685
7686 case HRTIM_TIMERINDEX_TIMER_B:
7687 {
7688 hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
7689 hrtim_bmcr |= ( pTimerCfg->BurstMode << 2U);
7690 break;
7691 }
7692
7693 case HRTIM_TIMERINDEX_TIMER_C:
7694 {
7695 hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
7696 hrtim_bmcr |= ( pTimerCfg->BurstMode << 3U);
7697 break;
7698 }
7699
7700 case HRTIM_TIMERINDEX_TIMER_D:
7701 {
7702 hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
7703 hrtim_bmcr |= ( pTimerCfg->BurstMode << 4U);
7704 break;
7705 }
7706
7707 case HRTIM_TIMERINDEX_TIMER_E:
7708 {
7709 hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
7710 hrtim_bmcr |= ( pTimerCfg->BurstMode << 5U);
7711 break;
7712 }
7713
7714 default:
7715 break;
7716 }
7717
7718 /* Update the HRTIM registers */
7719 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
7720 hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
7721 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
7722 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
7723 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
7724 }
7725
7726 /**
7727 * @brief Configure a capture unit
7728 * @param hhrtim pointer to HAL HRTIM handle
7729 * @param TimerIdx Timer index
7730 * @param CaptureUnit Capture unit identifier
7731 * @param Event Event reference
7732 * @retval None
7733 */
HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit,uint32_t Event)7734 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
7735 uint32_t TimerIdx,
7736 uint32_t CaptureUnit,
7737 uint32_t Event)
7738 {
7739 uint32_t CaptureTrigger = 0xFFFFFFFFU;
7740
7741 switch (Event)
7742 {
7743 case HRTIM_EVENT_1:
7744 {
7745 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
7746 break;
7747 }
7748
7749 case HRTIM_EVENT_2:
7750 {
7751 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
7752 break;
7753 }
7754
7755 case HRTIM_EVENT_3:
7756 {
7757 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
7758 break;
7759 }
7760
7761 case HRTIM_EVENT_4:
7762 {
7763 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
7764 break;
7765 }
7766
7767 case HRTIM_EVENT_5:
7768 {
7769 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
7770 break;
7771 }
7772
7773 case HRTIM_EVENT_6:
7774 {
7775 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
7776 break;
7777 }
7778
7779 case HRTIM_EVENT_7:
7780 {
7781 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
7782 break;
7783 }
7784
7785 case HRTIM_EVENT_8:
7786 {
7787 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
7788 break;
7789 }
7790
7791 case HRTIM_EVENT_9:
7792 {
7793 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
7794 break;
7795 }
7796
7797 case HRTIM_EVENT_10:
7798 {
7799 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
7800 break;
7801 }
7802
7803 default:
7804 break;
7805 }
7806
7807 switch (CaptureUnit)
7808 {
7809 case HRTIM_CAPTUREUNIT_1:
7810 {
7811 hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger;
7812 break;
7813 }
7814
7815 case HRTIM_CAPTUREUNIT_2:
7816 {
7817 hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
7818 break;
7819 }
7820
7821 default:
7822 break;
7823 }
7824 }
7825
7826 /**
7827 * @brief Configure the output of a timing unit
7828 * @param hhrtim pointer to HAL HRTIM handle
7829 * @param TimerIdx Timer index
7830 * @param Output timing unit output identifier
7831 * @param pOutputCfg pointer to the output configuration data structure
7832 * @retval None
7833 */
HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output,const HRTIM_OutputCfgTypeDef * pOutputCfg)7834 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
7835 uint32_t TimerIdx,
7836 uint32_t Output,
7837 const HRTIM_OutputCfgTypeDef * pOutputCfg)
7838 {
7839 uint32_t hrtim_outr;
7840 uint32_t hrtim_dtr;
7841
7842 uint32_t shift = 0U;
7843
7844 hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
7845 hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
7846
7847 switch (Output)
7848 {
7849 case HRTIM_OUTPUT_TA1:
7850 case HRTIM_OUTPUT_TB1:
7851 case HRTIM_OUTPUT_TC1:
7852 case HRTIM_OUTPUT_TD1:
7853 case HRTIM_OUTPUT_TE1:
7854 {
7855 /* Set the output set/reset crossbar */
7856 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
7857 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
7858 break;
7859 }
7860
7861 case HRTIM_OUTPUT_TA2:
7862 case HRTIM_OUTPUT_TB2:
7863 case HRTIM_OUTPUT_TC2:
7864 case HRTIM_OUTPUT_TD2:
7865 case HRTIM_OUTPUT_TE2:
7866 {
7867 /* Set the output set/reset crossbar */
7868 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
7869 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
7870 shift = 16U;
7871 break;
7872 }
7873
7874 default:
7875 break;
7876 }
7877
7878 /* Clear output config */
7879 hrtim_outr &= ~((HRTIM_OUTR_POL1 |
7880 HRTIM_OUTR_IDLM1 |
7881 HRTIM_OUTR_IDLES1|
7882 HRTIM_OUTR_FAULT1|
7883 HRTIM_OUTR_CHP1 |
7884 HRTIM_OUTR_DIDL1) << shift);
7885
7886 /* Set the polarity */
7887 hrtim_outr |= (pOutputCfg->Polarity << shift);
7888
7889 /* Set the IDLE mode */
7890 hrtim_outr |= (pOutputCfg->IdleMode << shift);
7891
7892 /* Set the IDLE state */
7893 hrtim_outr |= (pOutputCfg->IdleLevel << shift);
7894
7895 /* Set the FAULT state */
7896 hrtim_outr |= (pOutputCfg->FaultLevel << shift);
7897
7898 /* Set the chopper mode */
7899 hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
7900
7901 /* Set the burst mode entry mode : deadtime insertion when entering the idle
7902 state during a burst mode operation is allowed only under the following
7903 conditions:
7904 - the outputs is active during the burst mode (IDLES=1U)
7905 - positive deadtimes (SDTR/SDTF set to 0U)
7906 */
7907 if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
7908 ((hrtim_dtr & HRTIM_DTR_SDTR) == (uint32_t)RESET) &&
7909 ((hrtim_dtr & HRTIM_DTR_SDTF) == (uint32_t)RESET))
7910 {
7911 hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
7912 }
7913
7914 /* Update HRTIM register */
7915 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
7916 }
7917
7918 /**
7919 * @brief Configure an external event channel
7920 * @param hhrtim pointer to HAL HRTIM handle
7921 * @param Event Event channel identifier
7922 * @param pEventCfg pointer to the event channel configuration data structure
7923 * @retval None
7924 */
HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Event,const HRTIM_EventCfgTypeDef * pEventCfg)7925 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
7926 uint32_t Event,
7927 const HRTIM_EventCfgTypeDef *pEventCfg)
7928 {
7929 uint32_t hrtim_eecr1;
7930 uint32_t hrtim_eecr2;
7931 uint32_t hrtim_eecr3;
7932
7933 /* Configure external event channel */
7934 hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
7935 hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
7936 hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
7937
7938 switch (Event)
7939 {
7940 case HRTIM_EVENT_NONE:
7941 {
7942 /* Update the HRTIM registers */
7943 hhrtim->Instance->sCommonRegs.EECR1 = 0U;
7944 hhrtim->Instance->sCommonRegs.EECR2 = 0U;
7945 hhrtim->Instance->sCommonRegs.EECR3 = 0U;
7946 break;
7947 }
7948
7949 case HRTIM_EVENT_1:
7950 {
7951 hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
7952 hrtim_eecr1 |= (pEventCfg->Source & HRTIM_EECR1_EE1SRC);
7953 hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
7954 hrtim_eecr1 |= (pEventCfg->Sensitivity & HRTIM_EECR1_EE1SNS);
7955 /* Update the HRTIM registers (all bitfields but EE1FAST bit) */
7956 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7957 /* Update the HRTIM registers (EE1FAST bit) */
7958 hrtim_eecr1 |= (pEventCfg->FastMode & HRTIM_EECR1_EE1FAST);
7959 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7960 break;
7961 }
7962
7963 case HRTIM_EVENT_2:
7964 {
7965 hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
7966 hrtim_eecr1 |= ((pEventCfg->Source << 6U) & HRTIM_EECR1_EE2SRC);
7967 hrtim_eecr1 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR1_EE2POL);
7968 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR1_EE2SNS);
7969 /* Update the HRTIM registers (all bitfields but EE2FAST bit) */
7970 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7971 /* Update the HRTIM registers (EE2FAST bit) */
7972 hrtim_eecr1 |= ((pEventCfg->FastMode << 6U) & HRTIM_EECR1_EE2FAST);
7973 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7974 break;
7975 }
7976
7977 case HRTIM_EVENT_3:
7978 {
7979 hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
7980 hrtim_eecr1 |= ((pEventCfg->Source << 12U) & HRTIM_EECR1_EE3SRC);
7981 hrtim_eecr1 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR1_EE3POL);
7982 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR1_EE3SNS);
7983 /* Update the HRTIM registers (all bitfields but EE3FAST bit) */
7984 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7985 /* Update the HRTIM registers (EE3FAST bit) */
7986 hrtim_eecr1 |= ((pEventCfg->FastMode << 12U) & HRTIM_EECR1_EE3FAST);
7987 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7988 break;
7989 }
7990
7991 case HRTIM_EVENT_4:
7992 {
7993 hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
7994 hrtim_eecr1 |= ((pEventCfg->Source << 18U) & HRTIM_EECR1_EE4SRC);
7995 hrtim_eecr1 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR1_EE4POL);
7996 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR1_EE4SNS);
7997 /* Update the HRTIM registers (all bitfields but EE4FAST bit) */
7998 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7999 /* Update the HRTIM registers (EE4FAST bit) */
8000 hrtim_eecr1 |= ((pEventCfg->FastMode << 18U) & HRTIM_EECR1_EE4FAST);
8001 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8002 break;
8003 }
8004
8005 case HRTIM_EVENT_5:
8006 {
8007 hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
8008 hrtim_eecr1 |= ((pEventCfg->Source << 24U) & HRTIM_EECR1_EE5SRC);
8009 hrtim_eecr1 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR1_EE5POL);
8010 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR1_EE5SNS);
8011 /* Update the HRTIM registers (all bitfields but EE5FAST bit) */
8012 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8013 /* Update the HRTIM registers (EE5FAST bit) */
8014 hrtim_eecr1 |= ((pEventCfg->FastMode << 24U) & HRTIM_EECR1_EE5FAST);
8015 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8016 break;
8017 }
8018
8019 case HRTIM_EVENT_6:
8020 {
8021 hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
8022 hrtim_eecr2 |= (pEventCfg->Source & HRTIM_EECR2_EE6SRC);
8023 hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
8024 hrtim_eecr2 |= (pEventCfg->Sensitivity & HRTIM_EECR2_EE6SNS);
8025 hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
8026 hrtim_eecr3 |= (pEventCfg->Filter & HRTIM_EECR3_EE6F);
8027 /* Update the HRTIM registers */
8028 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8029 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8030 break;
8031 }
8032
8033 case HRTIM_EVENT_7:
8034 {
8035 hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
8036 hrtim_eecr2 |= ((pEventCfg->Source << 6U) & HRTIM_EECR2_EE7SRC);
8037 hrtim_eecr2 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR2_EE7POL);
8038 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR2_EE7SNS);
8039 hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
8040 hrtim_eecr3 |= ((pEventCfg->Filter << 6U) & HRTIM_EECR3_EE7F);
8041 /* Update the HRTIM registers */
8042 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8043 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8044 break;
8045 }
8046
8047 case HRTIM_EVENT_8:
8048 {
8049 hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
8050 hrtim_eecr2 |= ((pEventCfg->Source << 12U) & HRTIM_EECR2_EE8SRC);
8051 hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR2_EE8POL);
8052 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR2_EE8SNS);
8053 hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
8054 hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F );
8055 /* Update the HRTIM registers */
8056 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8057 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8058 break;
8059 }
8060
8061 case HRTIM_EVENT_9:
8062 {
8063 hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
8064 hrtim_eecr2 |= ((pEventCfg->Source << 18U) & HRTIM_EECR2_EE9SRC);
8065 hrtim_eecr2 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR2_EE9POL);
8066 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR2_EE9SNS);
8067 hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
8068 hrtim_eecr3 |= ((pEventCfg->Filter << 18U) & HRTIM_EECR3_EE9F);
8069 /* Update the HRTIM registers */
8070 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8071 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8072 break;
8073 }
8074
8075 case HRTIM_EVENT_10:
8076 {
8077 hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
8078 hrtim_eecr2 |= ((pEventCfg->Source << 24U) & HRTIM_EECR2_EE10SRC);
8079 hrtim_eecr2 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR2_EE10POL);
8080 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR2_EE10SNS);
8081 hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
8082 hrtim_eecr3 |= ((pEventCfg->Filter << 24U) & HRTIM_EECR3_EE10F);
8083 /* Update the HRTIM registers */
8084 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8085 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8086 break;
8087 }
8088
8089 default:
8090 break;
8091 }
8092 }
8093
8094 /**
8095 * @brief Configure the timer counter reset
8096 * @param hhrtim pointer to HAL HRTIM handle
8097 * @param TimerIdx Timer index
8098 * @param Event Event channel identifier
8099 * @retval None
8100 */
HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Event)8101 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
8102 uint32_t TimerIdx,
8103 uint32_t Event)
8104 {
8105 switch (Event)
8106 {
8107 case HRTIM_EVENT_1:
8108 {
8109 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
8110 break;
8111 }
8112
8113 case HRTIM_EVENT_2:
8114 {
8115 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
8116 break;
8117 }
8118
8119 case HRTIM_EVENT_3:
8120 {
8121 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
8122 break;
8123 }
8124
8125 case HRTIM_EVENT_4:
8126 {
8127 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
8128 break;
8129 }
8130
8131 case HRTIM_EVENT_5:
8132 {
8133 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
8134 break;
8135 }
8136
8137 case HRTIM_EVENT_6:
8138 {
8139 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
8140 break;
8141 }
8142
8143 case HRTIM_EVENT_7:
8144 {
8145 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
8146 break;
8147 }
8148
8149 case HRTIM_EVENT_8:
8150 {
8151 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
8152 break;
8153 }
8154
8155 case HRTIM_EVENT_9:
8156 {
8157 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
8158 break;
8159 }
8160
8161 case HRTIM_EVENT_10:
8162 {
8163 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
8164 break;
8165 }
8166
8167 default:
8168 break;
8169 }
8170 }
8171
8172 /**
8173 * @brief Return the interrupt to enable or disable according to the
8174 * OC mode.
8175 * @param hhrtim pointer to HAL HRTIM handle
8176 * @param TimerIdx Timer index
8177 * @param OCChannel Timer output
8178 * This parameter can be one of the following values:
8179 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
8180 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
8181 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
8182 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
8183 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
8184 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
8185 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
8186 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
8187 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
8188 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
8189 * @retval Interrupt to enable or disable
8190 */
HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)8191 static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
8192 uint32_t TimerIdx,
8193 uint32_t OCChannel)
8194 {
8195 uint32_t hrtim_set;
8196 uint32_t hrtim_reset;
8197 uint32_t interrupt = 0U;
8198
8199 switch (OCChannel)
8200 {
8201 case HRTIM_OUTPUT_TA1:
8202 case HRTIM_OUTPUT_TB1:
8203 case HRTIM_OUTPUT_TC1:
8204 case HRTIM_OUTPUT_TD1:
8205 case HRTIM_OUTPUT_TE1:
8206 {
8207 /* Retreives actual OC mode and set interrupt accordingly */
8208 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
8209 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
8210
8211 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8212 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8213 {
8214 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
8215 interrupt = HRTIM_TIM_IT_CMP1;
8216 }
8217 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8218 (hrtim_reset == 0U))
8219 {
8220 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
8221 interrupt = HRTIM_TIM_IT_SET1;
8222 }
8223 else if ((hrtim_set == 0U) &&
8224 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8225 {
8226 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
8227 interrupt = HRTIM_TIM_IT_RST1;
8228 }
8229 else
8230 {
8231 /* nothing to do */
8232 }
8233 break;
8234 }
8235
8236 case HRTIM_OUTPUT_TA2:
8237 case HRTIM_OUTPUT_TB2:
8238 case HRTIM_OUTPUT_TC2:
8239 case HRTIM_OUTPUT_TD2:
8240 case HRTIM_OUTPUT_TE2:
8241 {
8242 /* Retreives actual OC mode and set interrupt accordingly */
8243 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
8244 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
8245
8246 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8247 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8248 {
8249 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
8250 interrupt = HRTIM_TIM_IT_CMP2;
8251 }
8252 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8253 (hrtim_reset == 0U))
8254 {
8255 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
8256 interrupt = HRTIM_TIM_IT_SET2;
8257 }
8258 else if ((hrtim_set == 0U) &&
8259 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8260 {
8261 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
8262 interrupt = HRTIM_TIM_IT_RST2;
8263 }
8264 else
8265 {
8266 /* nothing to do */
8267 }
8268 break;
8269 }
8270
8271 default:
8272 break;
8273 }
8274
8275 return interrupt;
8276 }
8277
8278 /**
8279 * @brief Return the DMA request to enable or disable according to the
8280 * OC mode.
8281 * @param hhrtim pointer to HAL HRTIM handle
8282 * @param TimerIdx Timer index
8283 * @param OCChannel Timer output
8284 * This parameter can be one of the following values:
8285 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
8286 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
8287 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
8288 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
8289 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
8290 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
8291 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
8292 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
8293 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
8294 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
8295 * @retval DMA request to enable or disable
8296 */
HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)8297 static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
8298 uint32_t TimerIdx,
8299 uint32_t OCChannel)
8300 {
8301 uint32_t hrtim_set;
8302 uint32_t hrtim_reset;
8303 uint32_t dma_request = 0U;
8304
8305 switch (OCChannel)
8306 {
8307 case HRTIM_OUTPUT_TA1:
8308 case HRTIM_OUTPUT_TB1:
8309 case HRTIM_OUTPUT_TC1:
8310 case HRTIM_OUTPUT_TD1:
8311 case HRTIM_OUTPUT_TE1:
8312 {
8313 /* Retreives actual OC mode and set dma_request accordingly */
8314 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
8315 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
8316
8317 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8318 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8319 {
8320 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
8321 dma_request = HRTIM_TIM_DMA_CMP1;
8322 }
8323 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8324 (hrtim_reset == 0U))
8325 {
8326 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
8327 dma_request = HRTIM_TIM_DMA_SET1;
8328 }
8329 else if ((hrtim_set == 0U) &&
8330 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8331 {
8332 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
8333 dma_request = HRTIM_TIM_DMA_RST1;
8334 }
8335 else
8336 {
8337 /* nothing to do */
8338 }
8339 break;
8340 }
8341
8342 case HRTIM_OUTPUT_TA2:
8343 case HRTIM_OUTPUT_TB2:
8344 case HRTIM_OUTPUT_TC2:
8345 case HRTIM_OUTPUT_TD2:
8346 case HRTIM_OUTPUT_TE2:
8347 {
8348 /* Retreives actual OC mode and set dma_request accordingly */
8349 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
8350 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
8351
8352 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8353 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8354 {
8355 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
8356 dma_request = HRTIM_TIM_DMA_CMP2;
8357 }
8358 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8359 (hrtim_reset == 0U))
8360 {
8361 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
8362 dma_request = HRTIM_TIM_DMA_SET2;
8363 }
8364 else if ((hrtim_set == 0U) &&
8365 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8366 {
8367 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
8368 dma_request = HRTIM_TIM_DMA_RST2;
8369 }
8370 else
8371 {
8372 /* nothing to do */
8373 }
8374 break;
8375 }
8376
8377 default:
8378 break;
8379 }
8380
8381 return dma_request;
8382 }
8383
HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8384 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim,
8385 uint32_t TimerIdx)
8386 {
8387 DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL;
8388
8389 switch (TimerIdx)
8390 {
8391 case HRTIM_TIMERINDEX_MASTER:
8392 {
8393 hdma = hhrtim->hdmaMaster;
8394 break;
8395 }
8396
8397 case HRTIM_TIMERINDEX_TIMER_A:
8398 {
8399 hdma = hhrtim->hdmaTimerA;
8400 break;
8401 }
8402
8403 case HRTIM_TIMERINDEX_TIMER_B:
8404 {
8405 hdma = hhrtim->hdmaTimerB;
8406 break;
8407 }
8408
8409 case HRTIM_TIMERINDEX_TIMER_C:
8410 {
8411 hdma = hhrtim->hdmaTimerC;
8412 break;
8413 }
8414
8415 case HRTIM_TIMERINDEX_TIMER_D:
8416 {
8417 hdma = hhrtim->hdmaTimerD;
8418 break;
8419 }
8420
8421 case HRTIM_TIMERINDEX_TIMER_E:
8422 {
8423 hdma = hhrtim->hdmaTimerE;
8424 break;
8425 }
8426
8427 default:
8428 break;
8429 }
8430
8431 return hdma;
8432 }
8433
GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim,const DMA_HandleTypeDef * hdma)8434 static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim,
8435 const DMA_HandleTypeDef * hdma)
8436 {
8437 uint32_t timed_idx = 0xFFFFFFFFU;
8438
8439 if (hdma == hhrtim->hdmaMaster)
8440 {
8441 timed_idx = HRTIM_TIMERINDEX_MASTER;
8442 }
8443 else if (hdma == hhrtim->hdmaTimerA)
8444 {
8445 timed_idx = HRTIM_TIMERINDEX_TIMER_A;
8446 }
8447 else if (hdma == hhrtim->hdmaTimerB)
8448 {
8449 timed_idx = HRTIM_TIMERINDEX_TIMER_B;
8450 }
8451 else if (hdma == hhrtim->hdmaTimerC)
8452 {
8453 timed_idx = HRTIM_TIMERINDEX_TIMER_C;
8454 }
8455 else if (hdma == hhrtim->hdmaTimerD)
8456 {
8457 timed_idx = HRTIM_TIMERINDEX_TIMER_D;
8458 }
8459 else if (hdma == hhrtim->hdmaTimerE)
8460 {
8461 timed_idx = HRTIM_TIMERINDEX_TIMER_E;
8462 }
8463 else
8464 {
8465 /* nothing to do */
8466 }
8467 return timed_idx;
8468 }
8469
8470 /**
8471 * @brief Force an immediate transfer from the preload to the active
8472 * registers.
8473 * @param hhrtim pointer to HAL HRTIM handle
8474 * @param TimerIdx Timer index
8475 * @retval None
8476 */
HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8477 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
8478 uint32_t TimerIdx)
8479 {
8480 switch (TimerIdx)
8481 {
8482 case HRTIM_TIMERINDEX_MASTER:
8483 {
8484 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
8485 break;
8486 }
8487
8488 case HRTIM_TIMERINDEX_TIMER_A:
8489 {
8490 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
8491 break;
8492 }
8493
8494 case HRTIM_TIMERINDEX_TIMER_B:
8495 {
8496 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
8497 break;
8498 }
8499
8500 case HRTIM_TIMERINDEX_TIMER_C:
8501 {
8502 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
8503 break;
8504 }
8505
8506 case HRTIM_TIMERINDEX_TIMER_D:
8507 {
8508 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
8509 break;
8510 }
8511
8512 case HRTIM_TIMERINDEX_TIMER_E:
8513 {
8514 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
8515 break;
8516 }
8517
8518 default:
8519 break;
8520 }
8521 }
8522
8523
8524 /**
8525 * @brief HRTIM interrupts service routine
8526 * @param hhrtim pointer to HAL HRTIM handle
8527 * @retval None
8528 */
HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)8529 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
8530 {
8531 uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
8532 uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER);
8533
8534 /* Fault 1 event */
8535 if((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET)
8536 {
8537 if((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET)
8538 {
8539 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
8540
8541 /* Invoke Fault 1 event callback */
8542 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8543 hhrtim->Fault1Callback(hhrtim);
8544 #else
8545 HAL_HRTIM_Fault1Callback(hhrtim);
8546 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8547 }
8548 }
8549
8550 /* Fault 2 event */
8551 if((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET)
8552 {
8553 if((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET)
8554 {
8555 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
8556
8557 /* Invoke Fault 2 event callback */
8558 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8559 hhrtim->Fault2Callback(hhrtim);
8560 #else
8561 HAL_HRTIM_Fault2Callback(hhrtim);
8562 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8563 }
8564 }
8565
8566 /* Fault 3 event */
8567 if((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET)
8568 {
8569 if((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET)
8570 {
8571 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
8572
8573 /* Invoke Fault 3 event callback */
8574 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8575 hhrtim->Fault3Callback(hhrtim);
8576 #else
8577 HAL_HRTIM_Fault3Callback(hhrtim);
8578 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8579 }
8580 }
8581
8582 /* Fault 4 event */
8583 if((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET)
8584 {
8585 if((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET)
8586 {
8587 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
8588
8589 /* Invoke Fault 4 event callback */
8590 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8591 hhrtim->Fault4Callback(hhrtim);
8592 #else
8593 HAL_HRTIM_Fault4Callback(hhrtim);
8594 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8595 }
8596 }
8597
8598 /* Fault 5 event */
8599 if((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET)
8600 {
8601 if((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET)
8602 {
8603 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
8604
8605 /* Invoke Fault 5 event callback */
8606 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8607 hhrtim->Fault5Callback(hhrtim);
8608 #else
8609 HAL_HRTIM_Fault5Callback(hhrtim);
8610 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8611 }
8612 }
8613
8614 /* System fault event */
8615 if((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET)
8616 {
8617 if((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET)
8618 {
8619 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
8620
8621 /* Invoke System fault event callback */
8622 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8623 hhrtim->SystemFaultCallback(hhrtim);
8624 #else
8625 HAL_HRTIM_SystemFaultCallback(hhrtim);
8626 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8627 }
8628 }
8629 }
8630
8631 /**
8632 * @brief Master timer interrupts service routine
8633 * @param hhrtim pointer to HAL HRTIM handle
8634 * @retval None
8635 */
HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)8636 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
8637 {
8638 uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
8639 uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER);
8640 uint32_t misrflags = READ_REG(hhrtim->Instance->sMasterRegs.MISR);
8641 uint32_t mdierits = READ_REG(hhrtim->Instance->sMasterRegs.MDIER);
8642
8643 /* Burst mode period event */
8644 if((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET)
8645 {
8646 if((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET)
8647 {
8648 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
8649
8650 /* Invoke Burst mode period event callback */
8651 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8652 hhrtim->BurstModePeriodCallback(hhrtim);
8653 #else
8654 HAL_HRTIM_BurstModePeriodCallback(hhrtim);
8655 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8656 }
8657 }
8658
8659 /* Master timer compare 1 event */
8660 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET)
8661 {
8662 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET)
8663 {
8664 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
8665
8666 /* Invoke compare 1 event callback */
8667 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8668 hhrtim->Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8669 #else
8670 HAL_HRTIM_Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8671 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8672 }
8673 }
8674
8675 /* Master timer compare 2 event */
8676 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET)
8677 {
8678 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET)
8679 {
8680 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
8681
8682 /* Invoke compare 2 event callback */
8683 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8684 hhrtim->Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8685 #else
8686 HAL_HRTIM_Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8687 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8688 }
8689 }
8690
8691 /* Master timer compare 3 event */
8692 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET)
8693 {
8694 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET)
8695 {
8696 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
8697
8698 /* Invoke compare 3 event callback */
8699 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8700 hhrtim->Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8701 #else
8702 HAL_HRTIM_Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8703 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8704 }
8705 }
8706
8707 /* Master timer compare 4 event */
8708 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET)
8709 {
8710 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET)
8711 {
8712 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
8713
8714 /* Invoke compare 4 event callback */
8715 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8716 hhrtim->Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8717 #else
8718 HAL_HRTIM_Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8719 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8720 }
8721 }
8722
8723 /* Master timer repetition event */
8724 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET)
8725 {
8726 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET)
8727 {
8728 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
8729
8730 /* Invoke repetition event callback */
8731 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8732 hhrtim->RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8733 #else
8734 HAL_HRTIM_RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8735 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8736 }
8737 }
8738
8739 /* Synchronization input event */
8740 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET)
8741 {
8742 if((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET)
8743 {
8744 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
8745
8746 /* Invoke synchronization event callback */
8747 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8748 hhrtim->SynchronizationEventCallback(hhrtim);
8749 #else
8750 HAL_HRTIM_SynchronizationEventCallback(hhrtim);
8751 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8752 }
8753 }
8754
8755 /* Master timer registers update event */
8756 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET)
8757 {
8758 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET)
8759 {
8760 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
8761
8762 /* Invoke registers update event callback */
8763 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8764 hhrtim->RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8765 #else
8766 HAL_HRTIM_RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8767 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8768 }
8769 }
8770 }
8771
8772 /**
8773 * @brief Timer interrupts service routine
8774 * @param hhrtim pointer to HAL HRTIM handle
8775 * @param TimerIdx Timer index
8776 * This parameter can be one of the following values:
8777 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8778 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8779 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8780 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8781 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8782 * @retval None
8783 */
HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8784 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
8785 uint32_t TimerIdx)
8786 {
8787 uint32_t tisrflags = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR);
8788 uint32_t tdierits = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxDIER);
8789
8790 /* Timer compare 1 event */
8791 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET)
8792 {
8793 if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET)
8794 {
8795 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
8796
8797 /* Invoke compare 1 event callback */
8798 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8799 hhrtim->Compare1EventCallback(hhrtim, TimerIdx);
8800 #else
8801 HAL_HRTIM_Compare1EventCallback(hhrtim, TimerIdx);
8802 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8803 }
8804 }
8805
8806 /* Timer compare 2 event */
8807 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET)
8808 {
8809 if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET)
8810 {
8811 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
8812
8813 /* Invoke compare 2 event callback */
8814 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8815 hhrtim->Compare2EventCallback(hhrtim, TimerIdx);
8816 #else
8817 HAL_HRTIM_Compare2EventCallback(hhrtim, TimerIdx);
8818 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8819 }
8820 }
8821
8822 /* Timer compare 3 event */
8823 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET)
8824 {
8825 if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET)
8826 {
8827 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
8828
8829 /* Invoke compare 3 event callback */
8830 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8831 hhrtim->Compare3EventCallback(hhrtim, TimerIdx);
8832 #else
8833 HAL_HRTIM_Compare3EventCallback(hhrtim, TimerIdx);
8834 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8835 }
8836 }
8837
8838 /* Timer compare 4 event */
8839 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET)
8840 {
8841 if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET)
8842 {
8843 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
8844
8845 /* Invoke compare 4 event callback */
8846 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8847 hhrtim->Compare4EventCallback(hhrtim, TimerIdx);
8848 #else
8849 HAL_HRTIM_Compare4EventCallback(hhrtim, TimerIdx);
8850 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8851 }
8852 }
8853
8854 /* Timer repetition event */
8855 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET)
8856 {
8857 if((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET)
8858 {
8859 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
8860
8861 /* Invoke repetition event callback */
8862 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8863 hhrtim->RepetitionEventCallback(hhrtim, TimerIdx);
8864 #else
8865 HAL_HRTIM_RepetitionEventCallback(hhrtim, TimerIdx);
8866 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8867 }
8868 }
8869
8870 /* Timer registers update event */
8871 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET)
8872 {
8873 if((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET)
8874 {
8875 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
8876
8877 /* Invoke registers update event callback */
8878 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8879 hhrtim->RegistersUpdateCallback(hhrtim, TimerIdx);
8880 #else
8881 HAL_HRTIM_RegistersUpdateCallback(hhrtim, TimerIdx);
8882 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8883 }
8884 }
8885
8886 /* Timer capture 1 event */
8887 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET)
8888 {
8889 if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET)
8890 {
8891 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
8892
8893 /* Invoke capture 1 event callback */
8894 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8895 hhrtim->Capture1EventCallback(hhrtim, TimerIdx);
8896 #else
8897 HAL_HRTIM_Capture1EventCallback(hhrtim, TimerIdx);
8898 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8899 }
8900 }
8901
8902 /* Timer capture 2 event */
8903 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET)
8904 {
8905 if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET)
8906 {
8907 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
8908
8909 /* Invoke capture 2 event callback */
8910 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8911 hhrtim->Capture2EventCallback(hhrtim, TimerIdx);
8912 #else
8913 HAL_HRTIM_Capture2EventCallback(hhrtim, TimerIdx);
8914 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8915 }
8916 }
8917
8918 /* Timer output 1 set event */
8919 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET)
8920 {
8921 if((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET)
8922 {
8923 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
8924
8925 /* Invoke output 1 set event callback */
8926 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8927 hhrtim->Output1SetCallback(hhrtim, TimerIdx);
8928 #else
8929 HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx);
8930 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8931 }
8932 }
8933
8934 /* Timer output 1 reset event */
8935 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET)
8936 {
8937 if((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET)
8938 {
8939 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
8940
8941 /* Invoke output 1 reset event callback */
8942 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8943 hhrtim->Output1ResetCallback(hhrtim, TimerIdx);
8944 #else
8945 HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx);
8946 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8947 }
8948 }
8949
8950 /* Timer output 2 set event */
8951 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET)
8952 {
8953 if((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET)
8954 {
8955 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
8956
8957 /* Invoke output 2 set event callback */
8958 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8959 hhrtim->Output2SetCallback(hhrtim, TimerIdx);
8960 #else
8961 HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx);
8962 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8963 }
8964 }
8965
8966 /* Timer output 2 reset event */
8967 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET)
8968 {
8969 if((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET)
8970 {
8971 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
8972
8973 /* Invoke output 2 reset event callback */
8974 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8975 hhrtim->Output2ResetCallback(hhrtim, TimerIdx);
8976 #else
8977 HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx);
8978 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8979 }
8980 }
8981
8982 /* Timer reset event */
8983 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET)
8984 {
8985 if((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET)
8986 {
8987 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
8988
8989 /* Invoke timer reset callback */
8990 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8991 hhrtim->CounterResetCallback(hhrtim, TimerIdx);
8992 #else
8993 HAL_HRTIM_CounterResetCallback(hhrtim, TimerIdx);
8994 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8995 }
8996 }
8997
8998 /* Delayed protection event */
8999 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET)
9000 {
9001 if((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET)
9002 {
9003 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
9004
9005 /* Invoke delayed protection callback */
9006 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9007 hhrtim->DelayedProtectionCallback(hhrtim, TimerIdx);
9008 #else
9009 HAL_HRTIM_DelayedProtectionCallback(hhrtim, TimerIdx);
9010 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9011 }
9012 }
9013 }
9014
9015 /**
9016 * @brief DMA callback invoked upon master timer related DMA request completion
9017 * @param hdma pointer to DMA handle.
9018 * @retval None
9019 */
HRTIM_DMAMasterCplt(DMA_HandleTypeDef * hdma)9020 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
9021 {
9022 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
9023
9024 if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != (uint32_t)RESET)
9025 {
9026 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9027 hrtim->Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9028 #else
9029 HAL_HRTIM_Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9030 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9031 }
9032 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != (uint32_t)RESET)
9033 {
9034 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9035 hrtim->Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9036 #else
9037 HAL_HRTIM_Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9038 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9039 }
9040 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != (uint32_t)RESET)
9041 {
9042 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9043 hrtim->Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9044 #else
9045 HAL_HRTIM_Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9046 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9047 }
9048 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != (uint32_t)RESET)
9049 {
9050 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9051 hrtim->Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9052 #else
9053 HAL_HRTIM_Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9054 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9055 }
9056 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != (uint32_t)RESET)
9057 {
9058 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9059 hrtim->SynchronizationEventCallback(hrtim);
9060 #else
9061 HAL_HRTIM_SynchronizationEventCallback(hrtim);
9062 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9063 }
9064 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != (uint32_t)RESET)
9065 {
9066 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9067 hrtim->RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9068 #else
9069 HAL_HRTIM_RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9070 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9071 }
9072 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != (uint32_t)RESET)
9073 {
9074 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9075 hrtim->RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9076 #else
9077 HAL_HRTIM_RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9078 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9079 }
9080 else
9081 {
9082 /* nothing to do */
9083 }
9084 }
9085
9086 /**
9087 * @brief DMA callback invoked upon timer A..E related DMA request completion
9088 * @param hdma pointer to DMA handle.
9089 * @retval None
9090 */
HRTIM_DMATimerxCplt(DMA_HandleTypeDef * hdma)9091 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
9092 {
9093 uint8_t timer_idx;
9094
9095 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
9096
9097 timer_idx = (uint8_t)GetTimerIdxFromDMAHandle(hrtim, hdma);
9098
9099 if ( !IS_HRTIM_TIMING_UNIT(timer_idx) ) {return;}
9100
9101 if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != (uint32_t)RESET)
9102 {
9103 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9104 hrtim->Compare1EventCallback(hrtim, timer_idx);
9105 #else
9106 HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
9107 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9108 }
9109 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != (uint32_t)RESET)
9110 {
9111 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9112 hrtim->Compare2EventCallback(hrtim, timer_idx);
9113 #else
9114 HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
9115 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9116 }
9117 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != (uint32_t)RESET)
9118 {
9119 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9120 hrtim->Compare3EventCallback(hrtim, timer_idx);
9121 #else
9122 HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
9123 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9124 }
9125 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != (uint32_t)RESET)
9126 {
9127 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9128 hrtim->Compare4EventCallback(hrtim, timer_idx);
9129 #else
9130 HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
9131 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9132 }
9133 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != (uint32_t)RESET)
9134 {
9135 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9136 hrtim->RegistersUpdateCallback(hrtim, timer_idx);
9137 #else
9138 HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
9139 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9140 }
9141 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != (uint32_t)RESET)
9142 {
9143 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9144 hrtim->Capture1EventCallback(hrtim, timer_idx);
9145 #else
9146 HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
9147 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9148 }
9149 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != (uint32_t)RESET)
9150 {
9151 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9152 hrtim->Capture2EventCallback(hrtim, timer_idx);
9153 #else
9154 HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
9155 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9156 }
9157 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != (uint32_t)RESET)
9158 {
9159 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9160 hrtim->Output1SetCallback(hrtim, timer_idx);
9161 #else
9162 HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
9163 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9164 }
9165 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != (uint32_t)RESET)
9166 {
9167 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9168 hrtim->Output1ResetCallback(hrtim, timer_idx);
9169 #else
9170 HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
9171 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9172 }
9173 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != (uint32_t)RESET)
9174 {
9175 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9176 hrtim->Output2SetCallback(hrtim, timer_idx);
9177 #else
9178 HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
9179 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9180 }
9181 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != (uint32_t)RESET)
9182 {
9183 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9184 hrtim->Output2ResetCallback(hrtim, timer_idx);
9185 #else
9186 HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
9187 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9188 }
9189 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != (uint32_t)RESET)
9190 {
9191 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9192 hrtim->CounterResetCallback(hrtim, timer_idx);
9193 #else
9194 HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
9195 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9196 }
9197 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != (uint32_t)RESET)
9198 {
9199 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9200 hrtim->DelayedProtectionCallback(hrtim, timer_idx);
9201 #else
9202 HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
9203 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9204 }
9205 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != (uint32_t)RESET)
9206 {
9207 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9208 hrtim->RepetitionEventCallback(hrtim, timer_idx);
9209 #else
9210 HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
9211 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9212 }
9213 else
9214 {
9215 /* nothing to do */
9216 }
9217 }
9218
9219 /**
9220 * @brief DMA error callback
9221 * @param hdma pointer to DMA handle.
9222 * @retval None
9223 */
HRTIM_DMAError(DMA_HandleTypeDef * hdma)9224 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
9225 {
9226 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
9227
9228 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9229 hrtim->ErrorCallback(hrtim);
9230 #else
9231 HAL_HRTIM_ErrorCallback(hrtim);
9232 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9233 }
9234
9235 /**
9236 * @brief DMA callback invoked upon burst DMA transfer completion
9237 * @param hdma pointer to DMA handle.
9238 * @retval None
9239 */
HRTIM_BurstDMACplt(DMA_HandleTypeDef * hdma)9240 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
9241 {
9242 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
9243
9244 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9245 hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
9246 #else
9247 HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
9248 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9249 }
9250
9251 /**
9252 * @}
9253 */
9254
9255 /**
9256 * @}
9257 */
9258
9259 #endif /* HRTIM1 */
9260
9261 #endif /* HAL_HRTIM_MODULE_ENABLED */
9262
9263 /**
9264 * @}
9265 */
9266
