1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_swpmi.h
4 * @author MCD Application Team
5 * @brief Header file of SWPMI LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7xx_LL_SWPMI_H
21 #define STM32H7xx_LL_SWPMI_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7xx.h"
29
30 /** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34
35 /** @defgroup SWPMI_LL SWPMI
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /* Private constants ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43 #if defined(USE_FULL_LL_DRIVER)
44 /** @defgroup SWPMI_LL_Private_Macros SWPMI Private Macros
45 * @{
46 */
47 /**
48 * @}
49 */
50 #endif /*USE_FULL_LL_DRIVER*/
51
52 /* Exported types ------------------------------------------------------------*/
53 #if defined(USE_FULL_LL_DRIVER)
54 /** @defgroup SWPMI_LL_ES_INIT SWPMI Exported Init structure
55 * @{
56 */
57
58 /**
59 * @brief SWPMI Init structures definition
60 */
61 typedef struct
62 {
63 uint32_t VoltageClass; /*!< Specifies the SWP Voltage Class.
64 This parameter can be a value of @ref SWPMI_LL_EC_VOLTAGE_CLASS
65
66 This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetVoltageClass. */
67
68 uint32_t BitRatePrescaler; /*!< Specifies the SWPMI bitrate prescaler.
69 This parameter must be a number between Min_Data=0 and Max_Data=255U.
70
71 The value can be calculated thanks to helper macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER
72
73 This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetBitRatePrescaler. */
74
75 uint32_t TxBufferingMode; /*!< Specifies the transmission buffering mode.
76 This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_TX
77
78 This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetTransmissionMode. */
79
80 uint32_t RxBufferingMode; /*!< Specifies the reception buffering mode.
81 This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_RX
82
83 This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetReceptionMode. */
84 } LL_SWPMI_InitTypeDef;
85
86 /**
87 * @}
88 */
89 #endif /* USE_FULL_LL_DRIVER */
90
91 /* Exported constants --------------------------------------------------------*/
92 /** @defgroup SWPMI_LL_Exported_Constants SWPMI Exported Constants
93 * @{
94 */
95
96 /** @defgroup SWPMI_LL_EC_CLEAR_FLAG Clear Flags Defines
97 * @brief Flags defines which can be used with LL_SWPMI_WriteReg function
98 * @{
99 */
100 #define LL_SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF /*!< Clear receive buffer full flag */
101 #define LL_SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF /*!< Clear transmit buffer empty flag */
102 #define LL_SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF /*!< Clear receive CRC error flag */
103 #define LL_SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF /*!< Clear receive overrun error flag */
104 #define LL_SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF /*!< Clear transmit underrun error flag */
105 #define LL_SWPMI_ICR_CTCF SWPMI_ICR_CTCF /*!< Clear transfer complete flag */
106 #define LL_SWPMI_ICR_CSRF SWPMI_ICR_CSRF /*!< Clear slave resume flag */
107 /**
108 * @}
109 */
110
111 /** @defgroup SWPMI_LL_EC_GET_FLAG Get Flags Defines
112 * @brief Flags defines which can be used with LL_SWPMI_ReadReg function
113 * @{
114 */
115 #define LL_SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF /*!< Receive buffer full flag */
116 #define LL_SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF /*!< Transmit buffer empty flag */
117 #define LL_SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF /*!< Receive CRC error flag */
118 #define LL_SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF /*!< Receive overrun error flag */
119 #define LL_SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF /*!< Transmit underrun error flag */
120 #define LL_SWPMI_ISR_RXNE SWPMI_ISR_RXNE /*!< Receive data register not empty */
121 #define LL_SWPMI_ISR_TXE SWPMI_ISR_TXE /*!< Transmit data register empty */
122 #define LL_SWPMI_ISR_TCF SWPMI_ISR_TCF /*!< Transfer complete flag */
123 #define LL_SWPMI_ISR_SRF SWPMI_ISR_SRF /*!< Slave resume flag */
124 #define LL_SWPMI_ISR_SUSP SWPMI_ISR_SUSP /*!< SUSPEND flag */
125 #define LL_SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF /*!< DEACTIVATED flag */
126 /**
127 * @}
128 */
129
130 /** @defgroup SWPMI_LL_EC_IT IT Defines
131 * @brief IT defines which can be used with LL_SWPMI_ReadReg and LL_SWPMI_WriteReg functions
132 * @{
133 */
134 #define LL_SWPMI_IER_SRIE SWPMI_IER_SRIE /*!< Slave resume interrupt enable */
135 #define LL_SWPMI_IER_TCIE SWPMI_IER_TCIE /*!< Transmit complete interrupt enable */
136 #define LL_SWPMI_IER_TIE SWPMI_IER_TIE /*!< Transmit interrupt enable */
137 #define LL_SWPMI_IER_RIE SWPMI_IER_RIE /*!< Receive interrupt enable */
138 #define LL_SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE /*!< Transmit underrun error interrupt enable */
139 #define LL_SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE /*!< Receive overrun error interrupt enable */
140 #define LL_SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE /*!< Receive CRC error interrupt enable */
141 #define LL_SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE /*!< Transmit buffer empty interrupt enable */
142 #define LL_SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE /*!< Receive buffer full interrupt enable */
143 /**
144 * @}
145 */
146
147 /** @defgroup SWPMI_LL_EC_SW_BUFFER_RX SW BUFFER RX
148 * @{
149 */
150 #define LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000) /*!< Single software buffer mode for reception */
151 #define LL_SWPMI_SW_BUFFER_RX_MULTI SWPMI_CR_RXMODE /*!< Multi software buffermode for reception */
152 /**
153 * @}
154 */
155
156 /** @defgroup SWPMI_LL_EC_SW_BUFFER_TX SW BUFFER TX
157 * @{
158 */
159 #define LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000) /*!< Single software buffer mode for transmission */
160 #define LL_SWPMI_SW_BUFFER_TX_MULTI SWPMI_CR_TXMODE /*!< Multi software buffermode for transmission */
161 /**
162 * @}
163 */
164
165 /** @defgroup SWPMI_LL_EC_VOLTAGE_CLASS VOLTAGE CLASS
166 * @{
167 */
168 #define LL_SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000) /*!< SWPMI_IO uses directly VDD voltage to operate in class C */
169 #define LL_SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS /*!< SWPMI_IO uses an internal voltage regulator to operate in class B */
170 /**
171 * @}
172 */
173
174 /** @defgroup SWPMI_LL_EC_DMA_REG_DATA DMA register data
175 * @{
176 */
177 #define LL_SWPMI_DMA_REG_DATA_TRANSMIT (uint32_t)0 /*!< Get address of data register used for transmission */
178 #define LL_SWPMI_DMA_REG_DATA_RECEIVE (uint32_t)1 /*!< Get address of data register used for reception */
179 /**
180 * @}
181 */
182
183 /**
184 * @}
185 */
186
187 /* Exported macro ------------------------------------------------------------*/
188 /** @defgroup SWPMI_LL_Exported_Macros SWPMI Exported Macros
189 * @{
190 */
191
192 /** @defgroup SWPMI_LL_EM_WRITE_READ Common Write and read registers Macros
193 * @{
194 */
195
196 /**
197 * @brief Write a value in SWPMI register
198 * @param __INSTANCE__ SWPMI Instance
199 * @param __REG__ Register to be written
200 * @param __VALUE__ Value to be written in the register
201 * @retval None
202 */
203 #define LL_SWPMI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
204
205 /**
206 * @brief Read a value in SWPMI register
207 * @param __INSTANCE__ SWPMI Instance
208 * @param __REG__ Register to be read
209 * @retval Register value
210 */
211 #define LL_SWPMI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
212 /**
213 * @}
214 */
215
216 /** @defgroup SWPMI_LL_EM_BitRate Bit rate calculation helper Macros
217 * @{
218 */
219
220 /**
221 * @brief Helper macro to calculate bit rate value to set in BRR register (@ref LL_SWPMI_SetBitRatePrescaler function)
222 * @note ex: @ref __LL_SWPMI_CALC_BITRATE_PRESCALER(2000000, 80000000);
223 * @param __FSWP__ Within the following range: from 100 Kbit/s up to 2Mbit/s (in bit/s)
224 * @param __FSWPCLK__ PCLK or HSI frequency (in Hz)
225 * @retval Bitrate prescaler (BRR register)
226 */
227 #define __LL_SWPMI_CALC_BITRATE_PRESCALER(__FSWP__, __FSWPCLK__) ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1))
228
229 /**
230 * @}
231 */
232
233 /**
234 * @}
235 */
236
237 /* Exported functions --------------------------------------------------------*/
238 /** @defgroup SWPMI_LL_Exported_Functions SWPMI Exported Functions
239 * @{
240 */
241
242 /** @defgroup SWPMI_LL_EF_Configuration Configuration
243 * @{
244 */
245
246 /**
247 * @brief Set Reception buffering mode
248 * @note If Multi software buffer mode is chosen, RXDMA bits must also be set.
249 * @rmtoll CR RXMODE LL_SWPMI_SetReceptionMode
250 * @param SWPMIx SWPMI Instance
251 * @param RxBufferingMode This parameter can be one of the following values:
252 * @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE
253 * @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI
254 * @retval None
255 */
LL_SWPMI_SetReceptionMode(SWPMI_TypeDef * SWPMIx,uint32_t RxBufferingMode)256 __STATIC_INLINE void LL_SWPMI_SetReceptionMode(SWPMI_TypeDef *SWPMIx, uint32_t RxBufferingMode)
257 {
258 MODIFY_REG(SWPMIx->CR, SWPMI_CR_RXMODE, RxBufferingMode);
259 }
260
261 /**
262 * @brief Get Reception buffering mode
263 * @rmtoll CR RXMODE LL_SWPMI_GetReceptionMode
264 * @param SWPMIx SWPMI Instance
265 * @retval Returned value can be one of the following values:
266 * @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE
267 * @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI
268 */
LL_SWPMI_GetReceptionMode(SWPMI_TypeDef * SWPMIx)269 __STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(SWPMI_TypeDef *SWPMIx)
270 {
271 return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_RXMODE));
272 }
273
274 /**
275 * @brief Set Transmission buffering mode
276 * @note If Multi software buffer mode is chosen, TXDMA bits must also be set.
277 * @rmtoll CR TXMODE LL_SWPMI_SetTransmissionMode
278 * @param SWPMIx SWPMI Instance
279 * @param TxBufferingMode This parameter can be one of the following values:
280 * @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE
281 * @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI
282 * @retval None
283 */
LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef * SWPMIx,uint32_t TxBufferingMode)284 __STATIC_INLINE void LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef *SWPMIx, uint32_t TxBufferingMode)
285 {
286 MODIFY_REG(SWPMIx->CR, SWPMI_CR_TXMODE, TxBufferingMode);
287 }
288
289 /**
290 * @brief Get Transmission buffering mode
291 * @rmtoll CR TXMODE LL_SWPMI_GetTransmissionMode
292 * @param SWPMIx SWPMI Instance
293 * @retval Returned value can be one of the following values:
294 * @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE
295 * @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI
296 */
LL_SWPMI_GetTransmissionMode(SWPMI_TypeDef * SWPMIx)297 __STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(SWPMI_TypeDef *SWPMIx)
298 {
299 return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_TXMODE));
300 }
301
302 /**
303 * @brief Enable loopback mode
304 * @rmtoll CR LPBK LL_SWPMI_EnableLoopback
305 * @param SWPMIx SWPMI Instance
306 * @retval None
307 */
LL_SWPMI_EnableLoopback(SWPMI_TypeDef * SWPMIx)308 __STATIC_INLINE void LL_SWPMI_EnableLoopback(SWPMI_TypeDef *SWPMIx)
309 {
310 SET_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
311 }
312
313 /**
314 * @brief Disable loopback mode
315 * @rmtoll CR LPBK LL_SWPMI_DisableLoopback
316 * @param SWPMIx SWPMI Instance
317 * @retval None
318 */
LL_SWPMI_DisableLoopback(SWPMI_TypeDef * SWPMIx)319 __STATIC_INLINE void LL_SWPMI_DisableLoopback(SWPMI_TypeDef *SWPMIx)
320 {
321 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
322 }
323
324 /**
325 * @brief Enable SWPMI transceiver
326 * @note SWPMI_IO pin is controlled by SWPMI
327 * @rmtoll CR SWPEN LL_SWPMI_EnableTransceiver
328 * @param SWPMIx SWPMI Instance
329 * @retval None
330 */
LL_SWPMI_EnableTransceiver(SWPMI_TypeDef * SWPMIx)331 __STATIC_INLINE void LL_SWPMI_EnableTransceiver(SWPMI_TypeDef *SWPMIx)
332 {
333 SET_BIT(SWPMIx->CR, SWPMI_CR_SWPEN);
334 }
335
336 /**
337 * @brief Disable SWPMI transceiver
338 * @note SWPMI_IO pin is controlled by GPIO controller
339 * @rmtoll CR SWPEN LL_SWPMI_DisableTransceiver
340 * @param SWPMIx SWPMI Instance
341 * @retval None
342 */
LL_SWPMI_DisableTransceiver(SWPMI_TypeDef * SWPMIx)343 __STATIC_INLINE void LL_SWPMI_DisableTransceiver(SWPMI_TypeDef *SWPMIx)
344 {
345 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPEN);
346 }
347
348 /**
349 * @brief Check if SWPMI transceiver is enabled
350 * @rmtoll CR SWPEN LL_SWPMI_IsEnabledTransceiver
351 * @param SWPMIx SWPMI Instance
352 * @retval State of bit (1 or 0).
353 */
LL_SWPMI_IsEnabledTransceiver(SWPMI_TypeDef * SWPMIx)354 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledTransceiver(SWPMI_TypeDef *SWPMIx)
355 {
356 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPEN) == (SWPMI_CR_SWPEN)) ? 1UL : 0UL);
357 }
358
359 /**
360 * @brief Activate Single wire protocol bus (SUSPENDED or ACTIVATED state)
361 * @note SWP bus stays in the ACTIVATED state as long as there is a communication
362 * with the slave, either in transmission or in reception. The SWP bus switches back
363 * to the SUSPENDED state as soon as there is no more transmission or reception
364 * activity, after 7 idle bits.
365 * @rmtoll CR SWPACT LL_SWPMI_Activate
366 * @param SWPMIx SWPMI Instance
367 * @retval None
368 */
LL_SWPMI_Activate(SWPMI_TypeDef * SWPMIx)369 __STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx)
370 {
371 /* In order to activate SWP again, the software must clear DEACT bit*/
372 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
373
374 /* Set SWACT bit */
375 SET_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
376 }
377
378 /**
379 * @brief Check if Single wire protocol bus is in ACTIVATED state.
380 * @rmtoll CR SWPACT LL_SWPMI_Activate
381 * @param SWPMIx SWPMI Instance
382 * @retval State of bit (1 or 0).
383 */
LL_SWPMI_IsActivated(SWPMI_TypeDef * SWPMIx)384 __STATIC_INLINE uint32_t LL_SWPMI_IsActivated(SWPMI_TypeDef *SWPMIx)
385 {
386 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT)) ? 1UL : 0UL);
387 }
388
389 /**
390 * @brief Deactivate immediately Single wire protocol bus (immediate transition to
391 * DEACTIVATED state)
392 * @rmtoll CR SWPACT LL_SWPMI_Deactivate
393 * @param SWPMIx SWPMI Instance
394 * @retval None
395 */
LL_SWPMI_Deactivate(SWPMI_TypeDef * SWPMIx)396 __STATIC_INLINE void LL_SWPMI_Deactivate(SWPMI_TypeDef *SWPMIx)
397 {
398 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
399 }
400
401 /**
402 * @brief Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED
403 * state if no resume from slave)
404 * @rmtoll CR DEACT LL_SWPMI_RequestDeactivation
405 * @param SWPMIx SWPMI Instance
406 * @retval None
407 */
LL_SWPMI_RequestDeactivation(SWPMI_TypeDef * SWPMIx)408 __STATIC_INLINE void LL_SWPMI_RequestDeactivation(SWPMI_TypeDef *SWPMIx)
409 {
410 SET_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
411 }
412
413 /**
414 * @brief Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4)
415 * @rmtoll BRR BR LL_SWPMI_SetBitRatePrescaler
416 * @param SWPMIx SWPMI Instance
417 * @param BitRatePrescaler A number between Min_Data=0 and Max_Data=255U
418 * @retval None
419 */
LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef * SWPMIx,uint32_t BitRatePrescaler)420 __STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler)
421 {
422 WRITE_REG(SWPMIx->BRR, BitRatePrescaler);
423 }
424
425 /**
426 * @brief Get Bitrate prescaler
427 * @rmtoll BRR BR LL_SWPMI_GetBitRatePrescaler
428 * @param SWPMIx SWPMI Instance
429 * @retval A number between Min_Data=0 and Max_Data=255U
430 */
LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef * SWPMIx)431 __STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef *SWPMIx)
432 {
433 return (uint32_t)(READ_BIT(SWPMIx->BRR, SWPMI_BRR_BR));
434 }
435
436 /**
437 * @brief Set SWP Voltage Class
438 * @rmtoll OR CLASS LL_SWPMI_SetVoltageClass
439 * @param SWPMIx SWPMI Instance
440 * @param VoltageClass This parameter can be one of the following values:
441 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_C
442 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_B
443 * @retval None
444 */
LL_SWPMI_SetVoltageClass(SWPMI_TypeDef * SWPMIx,uint32_t VoltageClass)445 __STATIC_INLINE void LL_SWPMI_SetVoltageClass(SWPMI_TypeDef *SWPMIx, uint32_t VoltageClass)
446 {
447 MODIFY_REG(SWPMIx->OR, SWPMI_OR_CLASS, VoltageClass);
448 }
449
450 /**
451 * @brief Get SWP Voltage Class
452 * @rmtoll OR CLASS LL_SWPMI_GetVoltageClass
453 * @param SWPMIx SWPMI Instance
454 * @retval Returned value can be one of the following values:
455 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_C
456 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_B
457 */
LL_SWPMI_GetVoltageClass(SWPMI_TypeDef * SWPMIx)458 __STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx)
459 {
460 return (uint32_t)(READ_BIT(SWPMIx->OR, SWPMI_OR_CLASS));
461 }
462
463 /**
464 * @}
465 */
466
467 /** @defgroup SWPMI_LL_EF_FLAG_Management FLAG_Management
468 * @{
469 */
470
471 /**
472 * @brief Check if the last word of the frame under reception has arrived in SWPMI_RDR.
473 * @rmtoll ISR RXBFF LL_SWPMI_IsActiveFlag_RXBF
474 * @param SWPMIx SWPMI Instance
475 * @retval State of bit (1 or 0).
476 */
LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef * SWPMIx)477 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx)
478 {
479 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF)) ? 1UL : 0UL);
480 }
481
482 /**
483 * @brief Check if Frame transmission buffer has been emptied
484 * @rmtoll ISR TXBEF LL_SWPMI_IsActiveFlag_TXBE
485 * @param SWPMIx SWPMI Instance
486 * @retval State of bit (1 or 0).
487 */
LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef * SWPMIx)488 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx)
489 {
490 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF)) ? 1UL : 0UL);
491 }
492
493 /**
494 * @brief Check if CRC error in reception has been detected
495 * @rmtoll ISR RXBERF LL_SWPMI_IsActiveFlag_RXBER
496 * @param SWPMIx SWPMI Instance
497 * @retval State of bit (1 or 0).
498 */
LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef * SWPMIx)499 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx)
500 {
501 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF)) ? 1UL : 0UL);
502 }
503
504 /**
505 * @brief Check if Overrun in reception has been detected
506 * @rmtoll ISR RXOVRF LL_SWPMI_IsActiveFlag_RXOVR
507 * @param SWPMIx SWPMI Instance
508 * @retval State of bit (1 or 0).
509 */
LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef * SWPMIx)510 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
511 {
512 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF)) ? 1UL : 0UL);
513 }
514
515 /**
516 * @brief Check if underrun error in transmission has been detected
517 * @rmtoll ISR TXUNRF LL_SWPMI_IsActiveFlag_TXUNR
518 * @param SWPMIx SWPMI Instance
519 * @retval State of bit (1 or 0).
520 */
LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef * SWPMIx)521 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
522 {
523 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF)) ? 1UL : 0UL);
524 }
525
526 /**
527 * @brief Check if Receive data register not empty (it means that Received data is ready
528 * to be read in the SWPMI_RDR register)
529 * @rmtoll ISR RXNE LL_SWPMI_IsActiveFlag_RXNE
530 * @param SWPMIx SWPMI Instance
531 * @retval State of bit (1 or 0).
532 */
LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef * SWPMIx)533 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx)
534 {
535 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE)) ? 1UL : 0UL);
536 }
537
538 /**
539 * @brief Check if Transmit data register is empty (it means that Data written in transmit
540 * data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again)
541 * @rmtoll ISR TXE LL_SWPMI_IsActiveFlag_TXE
542 * @param SWPMIx SWPMI Instance
543 * @retval State of bit (1 or 0).
544 */
LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef * SWPMIx)545 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx)
546 {
547 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE)) ? 1UL : 0UL);
548 }
549
550 /**
551 * @brief Check if Both transmission and reception are completed and SWP is switched to
552 * the SUSPENDED state
553 * @rmtoll ISR TCF LL_SWPMI_IsActiveFlag_TC
554 * @param SWPMIx SWPMI Instance
555 * @retval State of bit (1 or 0).
556 */
LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef * SWPMIx)557 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx)
558 {
559 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF)) ? 1UL : 0UL);
560 }
561
562 /**
563 * @brief Check if a Resume by slave state has been detected during the SWP bus SUSPENDED
564 * state
565 * @rmtoll ISR SRF LL_SWPMI_IsActiveFlag_SR
566 * @param SWPMIx SWPMI Instance
567 * @retval State of bit (1 or 0).
568 */
LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef * SWPMIx)569 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx)
570 {
571 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF)) ? 1UL : 0UL);
572 }
573
574 /**
575 * @brief Check if SWP bus is in SUSPENDED or DEACTIVATED state
576 * @rmtoll ISR SUSP LL_SWPMI_IsActiveFlag_SUSP
577 * @param SWPMIx SWPMI Instance
578 * @retval State of bit (1 or 0).
579 */
LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef * SWPMIx)580 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx)
581 {
582 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP)) ? 1UL : 0UL);
583 }
584
585 /**
586 * @brief Check if SWP bus is in DEACTIVATED state
587 * @rmtoll ISR DEACTF LL_SWPMI_IsActiveFlag_DEACT
588 * @param SWPMIx SWPMI Instance
589 * @retval State of bit (1 or 0).
590 */
LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef * SWPMIx)591 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx)
592 {
593 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF)) ? 1UL : 0UL);
594 }
595
596 /**
597 * @brief Check if SWPMI transceiver is ready
598 * @rmtoll ISR RDYF LL_SWPMI_IsActiveFlag_RDYF
599 * @param SWPMIx SWPMI Instance
600 * @retval State of bit (1 or 0).
601 */
LL_SWPMI_IsActiveFlag_RDYF(SWPMI_TypeDef * SWPMIx)602 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RDYF(SWPMI_TypeDef *SWPMIx)
603 {
604 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RDYF) == (SWPMI_ISR_RDYF)) ? 1UL : 0UL);
605 }
606
607 /**
608 * @brief Clear receive buffer full flag
609 * @rmtoll ICR CRXBFF LL_SWPMI_ClearFlag_RXBF
610 * @param SWPMIx SWPMI Instance
611 * @retval None
612 */
LL_SWPMI_ClearFlag_RXBF(SWPMI_TypeDef * SWPMIx)613 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBF(SWPMI_TypeDef *SWPMIx)
614 {
615 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBFF);
616 }
617
618 /**
619 * @brief Clear transmit buffer empty flag
620 * @rmtoll ICR CTXBEF LL_SWPMI_ClearFlag_TXBE
621 * @param SWPMIx SWPMI Instance
622 * @retval None
623 */
LL_SWPMI_ClearFlag_TXBE(SWPMI_TypeDef * SWPMIx)624 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXBE(SWPMI_TypeDef *SWPMIx)
625 {
626 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXBEF);
627 }
628
629 /**
630 * @brief Clear receive CRC error flag
631 * @rmtoll ICR CRXBERF LL_SWPMI_ClearFlag_RXBER
632 * @param SWPMIx SWPMI Instance
633 * @retval None
634 */
LL_SWPMI_ClearFlag_RXBER(SWPMI_TypeDef * SWPMIx)635 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBER(SWPMI_TypeDef *SWPMIx)
636 {
637 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBERF);
638 }
639
640 /**
641 * @brief Clear receive overrun error flag
642 * @rmtoll ICR CRXOVRF LL_SWPMI_ClearFlag_RXOVR
643 * @param SWPMIx SWPMI Instance
644 * @retval None
645 */
LL_SWPMI_ClearFlag_RXOVR(SWPMI_TypeDef * SWPMIx)646 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
647 {
648 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXOVRF);
649 }
650
651 /**
652 * @brief Clear transmit underrun error flag
653 * @rmtoll ICR CTXUNRF LL_SWPMI_ClearFlag_TXUNR
654 * @param SWPMIx SWPMI Instance
655 * @retval None
656 */
LL_SWPMI_ClearFlag_TXUNR(SWPMI_TypeDef * SWPMIx)657 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
658 {
659 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXUNRF);
660 }
661
662 /**
663 * @brief Clear transfer complete flag
664 * @rmtoll ICR CTCF LL_SWPMI_ClearFlag_TC
665 * @param SWPMIx SWPMI Instance
666 * @retval None
667 */
LL_SWPMI_ClearFlag_TC(SWPMI_TypeDef * SWPMIx)668 __STATIC_INLINE void LL_SWPMI_ClearFlag_TC(SWPMI_TypeDef *SWPMIx)
669 {
670 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTCF);
671 }
672
673 /**
674 * @brief Clear slave resume flag
675 * @rmtoll ICR CSRF LL_SWPMI_ClearFlag_SR
676 * @param SWPMIx SWPMI Instance
677 * @retval None
678 */
LL_SWPMI_ClearFlag_SR(SWPMI_TypeDef * SWPMIx)679 __STATIC_INLINE void LL_SWPMI_ClearFlag_SR(SWPMI_TypeDef *SWPMIx)
680 {
681 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CSRF);
682 }
683
684 /**
685 * @brief Clear SWPMI transceiver ready flag
686 * @rmtoll ISR CRDYF LL_SWPMI_ClearFlag_RDY
687 * @param SWPMIx SWPMI Instance
688 * @retval None
689 */
LL_SWPMI_ClearFlag_RDY(SWPMI_TypeDef * SWPMIx)690 __STATIC_INLINE void LL_SWPMI_ClearFlag_RDY(SWPMI_TypeDef *SWPMIx)
691 {
692 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRDYF);
693 }
694
695 /**
696 * @}
697 */
698
699 /** @defgroup SWPMI_LL_EF_IT_Management IT_Management
700 * @{
701 */
702
703 /**
704 * @brief Enable SWPMI transceiver ready interrupt
705 * @rmtoll IER RDYIE LL_SWPMI_EnableIT_RDY
706 * @param SWPMIx SWPMI Instance
707 * @retval None
708 */
LL_SWPMI_EnableIT_RDY(SWPMI_TypeDef * SWPMIx)709 __STATIC_INLINE void LL_SWPMI_EnableIT_RDY(SWPMI_TypeDef *SWPMIx)
710 {
711 SET_BIT(SWPMIx->IER, SWPMI_IER_RDYIE);
712 }
713
714 /**
715 * @brief Enable Slave resume interrupt
716 * @rmtoll IER SRIE LL_SWPMI_EnableIT_SR
717 * @param SWPMIx SWPMI Instance
718 * @retval None
719 */
LL_SWPMI_EnableIT_SR(SWPMI_TypeDef * SWPMIx)720 __STATIC_INLINE void LL_SWPMI_EnableIT_SR(SWPMI_TypeDef *SWPMIx)
721 {
722 SET_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
723 }
724
725 /**
726 * @brief Enable Transmit complete interrupt
727 * @rmtoll IER TCIE LL_SWPMI_EnableIT_TC
728 * @param SWPMIx SWPMI Instance
729 * @retval None
730 */
LL_SWPMI_EnableIT_TC(SWPMI_TypeDef * SWPMIx)731 __STATIC_INLINE void LL_SWPMI_EnableIT_TC(SWPMI_TypeDef *SWPMIx)
732 {
733 SET_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
734 }
735
736 /**
737 * @brief Enable Transmit interrupt
738 * @rmtoll IER TIE LL_SWPMI_EnableIT_TX
739 * @param SWPMIx SWPMI Instance
740 * @retval None
741 */
LL_SWPMI_EnableIT_TX(SWPMI_TypeDef * SWPMIx)742 __STATIC_INLINE void LL_SWPMI_EnableIT_TX(SWPMI_TypeDef *SWPMIx)
743 {
744 SET_BIT(SWPMIx->IER, SWPMI_IER_TIE);
745 }
746
747 /**
748 * @brief Enable Receive interrupt
749 * @rmtoll IER RIE LL_SWPMI_EnableIT_RX
750 * @param SWPMIx SWPMI Instance
751 * @retval None
752 */
LL_SWPMI_EnableIT_RX(SWPMI_TypeDef * SWPMIx)753 __STATIC_INLINE void LL_SWPMI_EnableIT_RX(SWPMI_TypeDef *SWPMIx)
754 {
755 SET_BIT(SWPMIx->IER, SWPMI_IER_RIE);
756 }
757
758 /**
759 * @brief Enable Transmit underrun error interrupt
760 * @rmtoll IER TXUNRIE LL_SWPMI_EnableIT_TXUNR
761 * @param SWPMIx SWPMI Instance
762 * @retval None
763 */
LL_SWPMI_EnableIT_TXUNR(SWPMI_TypeDef * SWPMIx)764 __STATIC_INLINE void LL_SWPMI_EnableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
765 {
766 SET_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
767 }
768
769 /**
770 * @brief Enable Receive overrun error interrupt
771 * @rmtoll IER RXOVRIE LL_SWPMI_EnableIT_RXOVR
772 * @param SWPMIx SWPMI Instance
773 * @retval None
774 */
LL_SWPMI_EnableIT_RXOVR(SWPMI_TypeDef * SWPMIx)775 __STATIC_INLINE void LL_SWPMI_EnableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
776 {
777 SET_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
778 }
779
780 /**
781 * @brief Enable Receive CRC error interrupt
782 * @rmtoll IER RXBERIE LL_SWPMI_EnableIT_RXBER
783 * @param SWPMIx SWPMI Instance
784 * @retval None
785 */
LL_SWPMI_EnableIT_RXBER(SWPMI_TypeDef * SWPMIx)786 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBER(SWPMI_TypeDef *SWPMIx)
787 {
788 SET_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
789 }
790
791 /**
792 * @brief Enable Transmit buffer empty interrupt
793 * @rmtoll IER TXBEIE LL_SWPMI_EnableIT_TXBE
794 * @param SWPMIx SWPMI Instance
795 * @retval None
796 */
LL_SWPMI_EnableIT_TXBE(SWPMI_TypeDef * SWPMIx)797 __STATIC_INLINE void LL_SWPMI_EnableIT_TXBE(SWPMI_TypeDef *SWPMIx)
798 {
799 SET_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
800 }
801
802 /**
803 * @brief Enable Receive buffer full interrupt
804 * @rmtoll IER RXBFIE LL_SWPMI_EnableIT_RXBF
805 * @param SWPMIx SWPMI Instance
806 * @retval None
807 */
LL_SWPMI_EnableIT_RXBF(SWPMI_TypeDef * SWPMIx)808 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBF(SWPMI_TypeDef *SWPMIx)
809 {
810 SET_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
811 }
812
813 /**
814 * @brief Disable SWPMI transceiver ready interrupt
815 * @rmtoll IER RDYIE LL_SWPMI_DisableIT_RDY
816 * @param SWPMIx SWPMI Instance
817 * @retval None
818 */
LL_SWPMI_DisableIT_RDY(SWPMI_TypeDef * SWPMIx)819 __STATIC_INLINE void LL_SWPMI_DisableIT_RDY(SWPMI_TypeDef *SWPMIx)
820 {
821 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RDYIE);
822 }
823
824 /**
825 * @brief Disable Slave resume interrupt
826 * @rmtoll IER SRIE LL_SWPMI_DisableIT_SR
827 * @param SWPMIx SWPMI Instance
828 * @retval None
829 */
LL_SWPMI_DisableIT_SR(SWPMI_TypeDef * SWPMIx)830 __STATIC_INLINE void LL_SWPMI_DisableIT_SR(SWPMI_TypeDef *SWPMIx)
831 {
832 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
833 }
834
835 /**
836 * @brief Disable Transmit complete interrupt
837 * @rmtoll IER TCIE LL_SWPMI_DisableIT_TC
838 * @param SWPMIx SWPMI Instance
839 * @retval None
840 */
LL_SWPMI_DisableIT_TC(SWPMI_TypeDef * SWPMIx)841 __STATIC_INLINE void LL_SWPMI_DisableIT_TC(SWPMI_TypeDef *SWPMIx)
842 {
843 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
844 }
845
846 /**
847 * @brief Disable Transmit interrupt
848 * @rmtoll IER TIE LL_SWPMI_DisableIT_TX
849 * @param SWPMIx SWPMI Instance
850 * @retval None
851 */
LL_SWPMI_DisableIT_TX(SWPMI_TypeDef * SWPMIx)852 __STATIC_INLINE void LL_SWPMI_DisableIT_TX(SWPMI_TypeDef *SWPMIx)
853 {
854 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TIE);
855 }
856
857 /**
858 * @brief Disable Receive interrupt
859 * @rmtoll IER RIE LL_SWPMI_DisableIT_RX
860 * @param SWPMIx SWPMI Instance
861 * @retval None
862 */
LL_SWPMI_DisableIT_RX(SWPMI_TypeDef * SWPMIx)863 __STATIC_INLINE void LL_SWPMI_DisableIT_RX(SWPMI_TypeDef *SWPMIx)
864 {
865 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RIE);
866 }
867
868 /**
869 * @brief Disable Transmit underrun error interrupt
870 * @rmtoll IER TXUNRIE LL_SWPMI_DisableIT_TXUNR
871 * @param SWPMIx SWPMI Instance
872 * @retval None
873 */
LL_SWPMI_DisableIT_TXUNR(SWPMI_TypeDef * SWPMIx)874 __STATIC_INLINE void LL_SWPMI_DisableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
875 {
876 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
877 }
878
879 /**
880 * @brief Disable Receive overrun error interrupt
881 * @rmtoll IER RXOVRIE LL_SWPMI_DisableIT_RXOVR
882 * @param SWPMIx SWPMI Instance
883 * @retval None
884 */
LL_SWPMI_DisableIT_RXOVR(SWPMI_TypeDef * SWPMIx)885 __STATIC_INLINE void LL_SWPMI_DisableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
886 {
887 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
888 }
889
890 /**
891 * @brief Disable Receive CRC error interrupt
892 * @rmtoll IER RXBERIE LL_SWPMI_DisableIT_RXBER
893 * @param SWPMIx SWPMI Instance
894 * @retval None
895 */
LL_SWPMI_DisableIT_RXBER(SWPMI_TypeDef * SWPMIx)896 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBER(SWPMI_TypeDef *SWPMIx)
897 {
898 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
899 }
900
901 /**
902 * @brief Disable Transmit buffer empty interrupt
903 * @rmtoll IER TXBEIE LL_SWPMI_DisableIT_TXBE
904 * @param SWPMIx SWPMI Instance
905 * @retval None
906 */
LL_SWPMI_DisableIT_TXBE(SWPMI_TypeDef * SWPMIx)907 __STATIC_INLINE void LL_SWPMI_DisableIT_TXBE(SWPMI_TypeDef *SWPMIx)
908 {
909 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
910 }
911
912 /**
913 * @brief Disable Receive buffer full interrupt
914 * @rmtoll IER RXBFIE LL_SWPMI_DisableIT_RXBF
915 * @param SWPMIx SWPMI Instance
916 * @retval None
917 */
LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef * SWPMIx)918 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx)
919 {
920 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
921 }
922
923 /**
924 * @brief Check if SWPMI transceiver ready interrupt is enabled
925 * @rmtoll IER RDYIE LL_SWPMI_IsEnabledIT_RDY
926 * @param SWPMIx SWPMI Instance
927 * @retval State of bit (1 or 0).
928 */
LL_SWPMI_IsEnabledIT_RDY(SWPMI_TypeDef * SWPMIx)929 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY(SWPMI_TypeDef *SWPMIx)
930 {
931 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RDYIE) == (SWPMI_IER_RDYIE)) ? 1UL : 0UL);
932 }
933
934 /**
935 * @brief Check if Slave resume interrupt is enabled
936 * @rmtoll IER SRIE LL_SWPMI_IsEnabledIT_SR
937 * @param SWPMIx SWPMI Instance
938 * @retval State of bit (1 or 0).
939 */
LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef * SWPMIx)940 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx)
941 {
942 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE)) ? 1UL : 0UL);
943 }
944
945 /**
946 * @brief Check if Transmit complete interrupt is enabled
947 * @rmtoll IER TCIE LL_SWPMI_IsEnabledIT_TC
948 * @param SWPMIx SWPMI Instance
949 * @retval State of bit (1 or 0).
950 */
LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef * SWPMIx)951 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx)
952 {
953 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE)) ? 1UL : 0UL);
954 }
955
956 /**
957 * @brief Check if Transmit interrupt is enabled
958 * @rmtoll IER TIE LL_SWPMI_IsEnabledIT_TX
959 * @param SWPMIx SWPMI Instance
960 * @retval State of bit (1 or 0).
961 */
LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef * SWPMIx)962 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx)
963 {
964 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE)) ? 1UL : 0UL);
965 }
966
967 /**
968 * @brief Check if Receive interrupt is enabled
969 * @rmtoll IER RIE LL_SWPMI_IsEnabledIT_RX
970 * @param SWPMIx SWPMI Instance
971 * @retval State of bit (1 or 0).
972 */
LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef * SWPMIx)973 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx)
974 {
975 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE)) ? 1UL : 0UL);
976 }
977
978 /**
979 * @brief Check if Transmit underrun error interrupt is enabled
980 * @rmtoll IER TXUNRIE LL_SWPMI_IsEnabledIT_TXUNR
981 * @param SWPMIx SWPMI Instance
982 * @retval State of bit (1 or 0).
983 */
LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef * SWPMIx)984 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx)
985 {
986 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE)) ? 1UL : 0UL);
987 }
988
989 /**
990 * @brief Check if Receive overrun error interrupt is enabled
991 * @rmtoll IER RXOVRIE LL_SWPMI_IsEnabledIT_RXOVR
992 * @param SWPMIx SWPMI Instance
993 * @retval State of bit (1 or 0).
994 */
LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef * SWPMIx)995 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx)
996 {
997 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE)) ? 1UL : 0UL);
998 }
999
1000 /**
1001 * @brief Check if Receive CRC error interrupt is enabled
1002 * @rmtoll IER RXBERIE LL_SWPMI_IsEnabledIT_RXBER
1003 * @param SWPMIx SWPMI Instance
1004 * @retval State of bit (1 or 0).
1005 */
LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef * SWPMIx)1006 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx)
1007 {
1008 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE)) ? 1UL : 0UL);
1009 }
1010
1011 /**
1012 * @brief Check if Transmit buffer empty interrupt is enabled
1013 * @rmtoll IER TXBEIE LL_SWPMI_IsEnabledIT_TXBE
1014 * @param SWPMIx SWPMI Instance
1015 * @retval State of bit (1 or 0).
1016 */
LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef * SWPMIx)1017 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx)
1018 {
1019 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE)) ? 1UL : 0UL);
1020 }
1021
1022 /**
1023 * @brief Check if Receive buffer full interrupt is enabled
1024 * @rmtoll IER RXBFIE LL_SWPMI_IsEnabledIT_RXBF
1025 * @param SWPMIx SWPMI Instance
1026 * @retval State of bit (1 or 0).
1027 */
LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef * SWPMIx)1028 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef *SWPMIx)
1029 {
1030 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE)) ? 1UL : 0UL);
1031 }
1032
1033 /**
1034 * @}
1035 */
1036
1037 /** @defgroup SWPMI_LL_EF_DMA_Management DMA_Management
1038 * @{
1039 */
1040
1041 /**
1042 * @brief Enable DMA mode for reception
1043 * @rmtoll CR RXDMA LL_SWPMI_EnableDMAReq_RX
1044 * @param SWPMIx SWPMI Instance
1045 * @retval None
1046 */
LL_SWPMI_EnableDMAReq_RX(SWPMI_TypeDef * SWPMIx)1047 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
1048 {
1049 SET_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
1050 }
1051
1052 /**
1053 * @brief Disable DMA mode for reception
1054 * @rmtoll CR RXDMA LL_SWPMI_DisableDMAReq_RX
1055 * @param SWPMIx SWPMI Instance
1056 * @retval None
1057 */
LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef * SWPMIx)1058 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
1059 {
1060 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
1061 }
1062
1063 /**
1064 * @brief Check if DMA mode for reception is enabled
1065 * @rmtoll CR RXDMA LL_SWPMI_IsEnabledDMAReq_RX
1066 * @param SWPMIx SWPMI Instance
1067 * @retval State of bit (1 or 0).
1068 */
LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef * SWPMIx)1069 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef *SWPMIx)
1070 {
1071 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA)) ? 1UL : 0UL);
1072 }
1073
1074 /**
1075 * @brief Enable DMA mode for transmission
1076 * @rmtoll CR TXDMA LL_SWPMI_EnableDMAReq_TX
1077 * @param SWPMIx SWPMI Instance
1078 * @retval None
1079 */
LL_SWPMI_EnableDMAReq_TX(SWPMI_TypeDef * SWPMIx)1080 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
1081 {
1082 SET_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
1083 }
1084
1085 /**
1086 * @brief Disable DMA mode for transmission
1087 * @rmtoll CR TXDMA LL_SWPMI_DisableDMAReq_TX
1088 * @param SWPMIx SWPMI Instance
1089 * @retval None
1090 */
LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef * SWPMIx)1091 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
1092 {
1093 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
1094 }
1095
1096 /**
1097 * @brief Check if DMA mode for transmission is enabled
1098 * @rmtoll CR TXDMA LL_SWPMI_IsEnabledDMAReq_TX
1099 * @param SWPMIx SWPMI Instance
1100 * @retval State of bit (1 or 0).
1101 */
LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef * SWPMIx)1102 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx)
1103 {
1104 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA)) ? 1UL : 0UL);
1105 }
1106
1107 /**
1108 * @brief Get the data register address used for DMA transfer
1109 * @rmtoll TDR TD LL_SWPMI_DMA_GetRegAddr\n
1110 * RDR RD LL_SWPMI_DMA_GetRegAddr
1111 * @param SWPMIx SWPMI Instance
1112 * @param Direction This parameter can be one of the following values:
1113 * @arg @ref LL_SWPMI_DMA_REG_DATA_TRANSMIT
1114 * @arg @ref LL_SWPMI_DMA_REG_DATA_RECEIVE
1115 * @retval Address of data register
1116 */
LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef * SWPMIx,uint32_t Direction)1117 __STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t Direction)
1118 {
1119 uint32_t data_reg_addr;
1120
1121 if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT)
1122 {
1123 /* return address of TDR register */
1124 data_reg_addr = (uint32_t)&(SWPMIx->TDR);
1125 }
1126 else
1127 {
1128 /* return address of RDR register */
1129 data_reg_addr = (uint32_t)&(SWPMIx->RDR);
1130 }
1131
1132 return data_reg_addr;
1133 }
1134
1135 /**
1136 * @}
1137 */
1138
1139 /** @defgroup SWPMI_LL_EF_Data_Management Data_Management
1140 * @{
1141 */
1142
1143 /**
1144 * @brief Retrieve number of data bytes present in payload of received frame
1145 * @rmtoll RFL RFL LL_SWPMI_GetReceiveFrameLength
1146 * @param SWPMIx SWPMI Instance
1147 * @retval Value between Min_Data=0x00 and Max_Data=0x1F
1148 */
LL_SWPMI_GetReceiveFrameLength(SWPMI_TypeDef * SWPMIx)1149 __STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(SWPMI_TypeDef *SWPMIx)
1150 {
1151 return (uint32_t)(READ_BIT(SWPMIx->RFL, SWPMI_RFL_RFL));
1152 }
1153
1154 /**
1155 * @brief Transmit Data Register
1156 * @rmtoll TDR TD LL_SWPMI_TransmitData32
1157 * @param SWPMIx SWPMI Instance
1158 * @param TxData Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1159 * @retval None
1160 */
LL_SWPMI_TransmitData32(SWPMI_TypeDef * SWPMIx,uint32_t TxData)1161 __STATIC_INLINE void LL_SWPMI_TransmitData32(SWPMI_TypeDef *SWPMIx, uint32_t TxData)
1162 {
1163 WRITE_REG(SWPMIx->TDR, TxData);
1164 }
1165
1166 /**
1167 * @brief Receive Data Register
1168 * @rmtoll RDR RD LL_SWPMI_ReceiveData32
1169 * @param SWPMIx SWPMI Instance
1170 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1171 */
LL_SWPMI_ReceiveData32(SWPMI_TypeDef * SWPMIx)1172 __STATIC_INLINE uint32_t LL_SWPMI_ReceiveData32(SWPMI_TypeDef *SWPMIx)
1173 {
1174 return (uint32_t)(READ_BIT(SWPMIx->RDR, SWPMI_RDR_RD));
1175 }
1176
1177 /**
1178 * @brief Enable SWP Transceiver Bypass
1179 * @note The external interface for SWPMI is SWPMI_IO
1180 * (SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are not available on GPIOs)
1181 * @rmtoll OR TBYP LL_SWPMI_EnableTXBypass
1182 * @param SWPMIx SWPMI Instance
1183 * @retval None
1184 */
LL_SWPMI_EnableTXBypass(SWPMI_TypeDef * SWPMIx)1185 __STATIC_INLINE void LL_SWPMI_EnableTXBypass(SWPMI_TypeDef *SWPMIx)
1186 {
1187 CLEAR_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
1188 }
1189
1190 /**
1191 * @brief Disable SWP Transceiver Bypass
1192 * @note SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate
1193 * function on GPIOs. This configuration is selected to connect an external transceiver
1194 * @note In SWPMI_IO bypass mode, SWPEN bit in SWPMI_CR register must be kept cleared
1195 * @rmtoll OR TBYP LL_SWPMI_DisableTXBypass
1196 * @param SWPMIx SWPMI Instance
1197 * @retval None
1198 */
LL_SWPMI_DisableTXBypass(SWPMI_TypeDef * SWPMIx)1199 __STATIC_INLINE void LL_SWPMI_DisableTXBypass(SWPMI_TypeDef *SWPMIx)
1200 {
1201 SET_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
1202 }
1203
1204 /**
1205 * @}
1206 */
1207
1208 #if defined(USE_FULL_LL_DRIVER)
1209 /** @defgroup SWPMI_LL_EF_Init Initialization and de-initialization functions
1210 * @{
1211 */
1212
1213 ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx);
1214 ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
1215 void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
1216
1217 /**
1218 * @}
1219 */
1220 #endif /*USE_FULL_LL_DRIVER*/
1221
1222 /**
1223 * @}
1224 */
1225
1226 /**
1227 * @}
1228 */
1229
1230
1231 /**
1232 * @}
1233 */
1234
1235 #ifdef __cplusplus
1236 }
1237 #endif
1238
1239 #endif /* STM32H7xx_LL_SWPMI_H */
1240
