1 /**
2   ******************************************************************************
3   * @file    stm32h7xx_ll_rng.h
4   * @author  MCD Application Team
5   * @brief   Header file of RNG LL module.
6   ******************************************************************************
7   * @attention
8   *
9   * Copyright (c) 2017 STMicroelectronics.
10   * All rights reserved.
11   *
12   * This software is licensed under terms that can be found in the LICENSE file
13   * in the root directory of this software component.
14   * If no LICENSE file comes with this software, it is provided AS-IS.
15   *
16   ******************************************************************************
17   */
18 
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7xx_LL_RNG_H
21 #define STM32H7xx_LL_RNG_H
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7xx.h"
29 
30 /** @addtogroup STM32H7xx_LL_Driver
31   * @{
32   */
33 
34 #if defined (RNG)
35 
36 /** @defgroup RNG_LL RNG
37   * @{
38   */
39 
40 /* Private types -------------------------------------------------------------*/
41 /* Private defines -----------------------------------------------------------*/
42 /** @defgroup RNG_LL_Private_Defines RNG Private Defines
43   * @{
44   */
45 /*  Health test control register information to use in CCM algorithm */
46 #define LL_RNG_HTCFG   0x17590ABCU /*!< Magic number */
47 /**
48   * @}
49   */
50 /* Private variables ---------------------------------------------------------*/
51 /* Private constants ---------------------------------------------------------*/
52 /* Private macros ------------------------------------------------------------*/
53 
54 /* Exported types ------------------------------------------------------------*/
55 #if defined(USE_FULL_LL_DRIVER)
56 /** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures
57   * @{
58   */
59 
60 
61 /**
62   * @brief LL RNG Init Structure Definition
63   */
64 typedef struct
65 {
66   uint32_t         ClockErrorDetection; /*!< Clock error detection.
67                                       This parameter can be one value of @ref RNG_LL_CED.
68                                       This parameter can be modified using unitary
69                                       functions @ref LL_RNG_EnableClkErrorDetect(). */
70 } LL_RNG_InitTypeDef;
71 
72 /**
73   * @}
74   */
75 #endif /* USE_FULL_LL_DRIVER */
76 /* Exported constants --------------------------------------------------------*/
77 /** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
78   * @{
79   */
80 
81 /** @defgroup RNG_LL_CED Clock Error Detection
82   * @{
83   */
84 #define LL_RNG_CED_ENABLE         0x00000000U              /*!< Clock error detection enabled  */
85 #define LL_RNG_CED_DISABLE        RNG_CR_CED               /*!< Clock error detection disabled */
86 /**
87   * @}
88   */
89 
90 #if defined(RNG_CR_CONDRST)
91 /** @defgroup RNG_LL_Clock_Divider_Factor  Value used to configure an internal
92   *            programmable divider acting on the incoming RNG clock
93   * @{
94   */
95 #define LL_RNG_CLKDIV_BY_1       (0x00000000UL)                                                           /*!< No clock division                             */
96 #define LL_RNG_CLKDIV_BY_2       (RNG_CR_CLKDIV_0)                                                        /*!< 2 RNG clock cycles per internal RNG clock     */
97 #define LL_RNG_CLKDIV_BY_4       (RNG_CR_CLKDIV_1)                                                        /*!< 4 RNG clock cycles per internal RNG clock     */
98 #define LL_RNG_CLKDIV_BY_8       (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)                                      /*!< 8 RNG clock cycles per internal RNG clock     */
99 #define LL_RNG_CLKDIV_BY_16      (RNG_CR_CLKDIV_2)                                                        /*!< 16 RNG clock cycles per internal RNG clock    */
100 #define LL_RNG_CLKDIV_BY_32      (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)                                      /*!< 32 RNG clock cycles per internal RNG clock    */
101 #define LL_RNG_CLKDIV_BY_64      (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)                                      /*!< 64 RNG clock cycles per internal RNG clock    */
102 #define LL_RNG_CLKDIV_BY_128     (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)                    /*!< 128 RNG clock cycles per internal RNG clock   */
103 #define LL_RNG_CLKDIV_BY_256     (RNG_CR_CLKDIV_3)                                                        /*!< 256 RNG clock cycles per internal RNG clock   */
104 #define LL_RNG_CLKDIV_BY_512     (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)                                      /*!< 512 RNG clock cycles per internal RNG clock   */
105 #define LL_RNG_CLKDIV_BY_1024    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)                                      /*!< 1024 RNG clock cycles per internal RNG clock  */
106 #define LL_RNG_CLKDIV_BY_2048    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)                    /*!< 2048 RNG clock cycles per internal RNG clock  */
107 #define LL_RNG_CLKDIV_BY_4096    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)                                      /*!< 4096 RNG clock cycles per internal RNG clock  */
108 #define LL_RNG_CLKDIV_BY_8192    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)                    /*!< 8192 RNG clock cycles per internal RNG clock  */
109 #define LL_RNG_CLKDIV_BY_16384   (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)                    /*!< 16384 RNG clock cycles per internal RNG clock */
110 #define LL_RNG_CLKDIV_BY_32768   (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)  /*!< 32768 RNG clock cycles per internal RNG clock */
111 /**
112   * @}
113   */
114 
115 /** @defgroup RNG_LL_NIST_Compliance  NIST Compliance configuration
116   * @{
117   */
118 #define LL_RNG_NIST_COMPLIANT     (0x00000000UL) /*!< Default NIST compliant configuration*/
119 #define LL_RNG_CUSTOM_NIST        (RNG_CR_NISTC) /*!< Custom NIST configuration */
120 
121 /**
122   * @}
123   */
124 
125 #endif /* RNG_CR_CONDRST */
126 /** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
127   * @brief    Flags defines which can be used with LL_RNG_ReadReg function
128   * @{
129   */
130 #define LL_RNG_SR_DRDY RNG_SR_DRDY    /*!< Register contains valid random data */
131 #define LL_RNG_SR_CECS RNG_SR_CECS    /*!< Clock error current status */
132 #define LL_RNG_SR_SECS RNG_SR_SECS    /*!< Seed error current status */
133 #define LL_RNG_SR_CEIS RNG_SR_CEIS    /*!< Clock error interrupt status */
134 #define LL_RNG_SR_SEIS RNG_SR_SEIS    /*!< Seed error interrupt status */
135 /**
136   * @}
137   */
138 
139 /** @defgroup RNG_LL_EC_IT IT Defines
140   * @brief    IT defines which can be used with LL_RNG_ReadReg and  LL_RNG_WriteReg macros
141   * @{
142   */
143 #define LL_RNG_CR_IE   RNG_CR_IE      /*!< RNG Interrupt enable */
144 /**
145   * @}
146   */
147 
148 /**
149   * @}
150   */
151 
152 /* Exported macro ------------------------------------------------------------*/
153 /** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
154   * @{
155   */
156 
157 /** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
158   * @{
159   */
160 
161 /**
162   * @brief  Write a value in RNG register
163   * @param  __INSTANCE__ RNG Instance
164   * @param  __REG__ Register to be written
165   * @param  __VALUE__ Value to be written in the register
166   * @retval None
167   */
168 #define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
169 
170 /**
171   * @brief  Read a value in RNG register
172   * @param  __INSTANCE__ RNG Instance
173   * @param  __REG__ Register to be read
174   * @retval Register value
175   */
176 #define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
177 /**
178   * @}
179   */
180 
181 /**
182   * @}
183   */
184 
185 
186 /* Exported functions --------------------------------------------------------*/
187 /** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
188   * @{
189   */
190 /** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
191   * @{
192   */
193 
194 /**
195   * @brief  Enable Random Number Generation
196   * @rmtoll CR           RNGEN         LL_RNG_Enable
197   * @param  RNGx RNG Instance
198   * @retval None
199   */
LL_RNG_Enable(RNG_TypeDef * RNGx)200 __STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
201 {
202   SET_BIT(RNGx->CR, RNG_CR_RNGEN);
203 }
204 
205 /**
206   * @brief  Disable Random Number Generation
207   * @rmtoll CR           RNGEN         LL_RNG_Disable
208   * @param  RNGx RNG Instance
209   * @retval None
210   */
LL_RNG_Disable(RNG_TypeDef * RNGx)211 __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
212 {
213   CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
214 }
215 
216 /**
217   * @brief  Check if Random Number Generator is enabled
218   * @rmtoll CR           RNGEN         LL_RNG_IsEnabled
219   * @param  RNGx RNG Instance
220   * @retval State of bit (1 or 0).
221   */
LL_RNG_IsEnabled(RNG_TypeDef * RNGx)222 __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
223 {
224   return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
225 }
226 
227 /**
228   * @brief  Enable Clock Error Detection
229   * @rmtoll CR           CED           LL_RNG_EnableClkErrorDetect
230   * @param  RNGx RNG Instance
231   * @retval None
232   */
LL_RNG_EnableClkErrorDetect(RNG_TypeDef * RNGx)233 __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
234 {
235   CLEAR_BIT(RNGx->CR, RNG_CR_CED);
236 }
237 
238 /**
239   * @brief  Disable RNG Clock Error Detection
240   * @rmtoll CR           CED         LL_RNG_DisableClkErrorDetect
241   * @param  RNGx RNG Instance
242   * @retval None
243   */
LL_RNG_DisableClkErrorDetect(RNG_TypeDef * RNGx)244 __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
245 {
246   SET_BIT(RNGx->CR, RNG_CR_CED);
247 }
248 
249 /**
250   * @brief  Check if RNG Clock Error Detection is enabled
251   * @rmtoll CR           CED         LL_RNG_IsEnabledClkErrorDetect
252   * @param  RNGx RNG Instance
253   * @retval State of bit (1 or 0).
254   */
LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef * RNGx)255 __STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx)
256 {
257   return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
258 }
259 
260 #if defined(RNG_CR_CONDRST)
261 /**
262   * @brief  Set RNG Conditioning Soft Reset bit
263   * @rmtoll CR           CONDRST          LL_RNG_EnableCondReset
264   * @param  RNGx RNG Instance
265   * @retval None
266   */
LL_RNG_EnableCondReset(RNG_TypeDef * RNGx)267 __STATIC_INLINE void LL_RNG_EnableCondReset(RNG_TypeDef *RNGx)
268 {
269   SET_BIT(RNGx->CR, RNG_CR_CONDRST);
270 }
271 
272 /**
273   * @brief  Reset RNG  Conditioning Soft Reset bit
274   * @rmtoll CR           CONDRST         LL_RNG_DisableCondReset
275   * @param  RNGx RNG Instance
276   * @retval None
277   */
LL_RNG_DisableCondReset(RNG_TypeDef * RNGx)278 __STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx)
279 {
280   CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
281 }
282 
283 /**
284   * @brief  Check if RNG Conditioning Soft Reset bit is set
285   * @rmtoll CR           CONDRST         LL_RNG_IsEnabledCondReset
286   * @param  RNGx RNG Instance
287   * @retval State of bit (1 or 0).
288   */
LL_RNG_IsEnabledCondReset(RNG_TypeDef * RNGx)289 __STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(RNG_TypeDef *RNGx)
290 {
291   return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL);
292 }
293 
294 /**
295   * @brief  Enable RNG Config Lock
296   * @rmtoll CR           CONFIGLOCK          LL_RNG_ConfigLock
297   * @param  RNGx RNG Instance
298   * @retval None
299   */
LL_RNG_ConfigLock(RNG_TypeDef * RNGx)300 __STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx)
301 {
302   SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK);
303 }
304 
305 /**
306   * @brief  Check if RNG Config Lock is enabled
307   * @rmtoll CR           CONFIGLOCK         LL_RNG_IsConfigLocked
308   * @param  RNGx RNG Instance
309   * @retval State of bit (1 or 0).
310   */
LL_RNG_IsConfigLocked(RNG_TypeDef * RNGx)311 __STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(RNG_TypeDef *RNGx)
312 {
313   return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL);
314 }
315 
316 /**
317   * @brief  Enable NIST Compliance
318   * @rmtoll CR           NISTC         LL_RNG_EnableNistCompliance
319   * @param  RNGx RNG Instance
320   * @retval None
321   */
LL_RNG_EnableNistCompliance(RNG_TypeDef * RNGx)322 __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
323 {
324   CLEAR_BIT(RNGx->CR, RNG_CR_NISTC);
325 }
326 
327 /**
328   * @brief  Disable NIST Compliance
329   * @rmtoll CR           NISTC         LL_RNG_DisableNistCompliance
330   * @param  RNGx RNG Instance
331   * @retval None
332   */
LL_RNG_DisableNistCompliance(RNG_TypeDef * RNGx)333 __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
334 {
335   SET_BIT(RNGx->CR, RNG_CR_NISTC);
336 }
337 
338 /**
339   * @brief  Check if NIST Compliance is enabled
340   * @rmtoll CR           NISTC         LL_RNG_IsEnabledNistCompliance
341   * @param  RNGx RNG Instance
342   * @retval State of bit (1 or 0).
343   */
LL_RNG_IsEnabledNistCompliance(RNG_TypeDef * RNGx)344 __STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(RNG_TypeDef *RNGx)
345 {
346   return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL);
347 }
348 
349 /**
350   * @brief  Set RNG  Config1 Configuration field value
351   * @rmtoll CR           RNG_CONFIG1         LL_RNG_SetConfig1
352   * @param  RNGx RNG Instance
353   * @param  Config1 Value between 0 and 0x3F
354   * @retval None
355   */
LL_RNG_SetConfig1(RNG_TypeDef * RNGx,uint32_t Config1)356 __STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
357 {
358   MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1, Config1 << RNG_CR_RNG_CONFIG1_Pos);
359 }
360 
361 /**
362   * @brief  Get RNG  Config1 Configuration field value
363   * @rmtoll CR           RNG_CONFIG1         LL_RNG_GetConfig1
364   * @param  RNGx RNG Instance
365   * @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F
366   */
LL_RNG_GetConfig1(RNG_TypeDef * RNGx)367 __STATIC_INLINE uint32_t LL_RNG_GetConfig1(RNG_TypeDef *RNGx)
368 {
369   return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos);
370 }
371 
372 /**
373   * @brief  Set RNG  Config2 Configuration field value
374   * @rmtoll CR           RNG_CONFIG2         LL_RNG_SetConfig2
375   * @param  RNGx RNG Instance
376   * @param  Config2 Value between 0 and 0x7
377   * @retval None
378   */
LL_RNG_SetConfig2(RNG_TypeDef * RNGx,uint32_t Config2)379 __STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
380 {
381   MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2, Config2 << RNG_CR_RNG_CONFIG2_Pos);
382 }
383 
384 /**
385   * @brief  Get RNG  Config2 Configuration field value
386   * @rmtoll CR           RNG_CONFIG2         LL_RNG_GetConfig2
387   * @param  RNGx RNG Instance
388   * @retval Returned Value expressed on 3 bits : Value between 0 and 0x7
389   */
LL_RNG_GetConfig2(RNG_TypeDef * RNGx)390 __STATIC_INLINE uint32_t LL_RNG_GetConfig2(RNG_TypeDef *RNGx)
391 {
392   return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
393 }
394 
395 /**
396   * @brief  Set RNG  Config3 Configuration field value
397   * @rmtoll CR           RNG_CONFIG3         LL_RNG_SetConfig3
398   * @param  RNGx RNG Instance
399   * @param  Config3 Value between 0 and 0xF
400   * @retval None
401   */
LL_RNG_SetConfig3(RNG_TypeDef * RNGx,uint32_t Config3)402 __STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
403 {
404   MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3, Config3 << RNG_CR_RNG_CONFIG3_Pos);
405 }
406 
407 /**
408   * @brief  Get RNG  Config3 Configuration field value
409   * @rmtoll CR           RNG_CONFIG3         LL_RNG_GetConfig3
410   * @param  RNGx RNG Instance
411   * @retval Returned Value expressed on 4 bits : Value between 0 and 0xF
412   */
LL_RNG_GetConfig3(RNG_TypeDef * RNGx)413 __STATIC_INLINE uint32_t LL_RNG_GetConfig3(RNG_TypeDef *RNGx)
414 {
415   return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
416 }
417 
418 /**
419   * @brief  Set RNG  Clock divider factor
420   * @rmtoll CR           CLKDIV         LL_RNG_SetClockDivider
421   * @param  RNGx RNG Instance
422   * @param  Divider can be one of the following values:
423   *         @arg @ref LL_RNG_CLKDIV_BY_1
424   *         @arg @ref LL_RNG_CLKDIV_BY_2
425   *         @arg @ref LL_RNG_CLKDIV_BY_4
426   *         @arg @ref LL_RNG_CLKDIV_BY_8
427   *         @arg @ref LL_RNG_CLKDIV_BY_16
428   *         @arg @ref LL_RNG_CLKDIV_BY_32
429   *         @arg @ref LL_RNG_CLKDIV_BY_64
430   *         @arg @ref LL_RNG_CLKDIV_BY_128
431   *         @arg @ref LL_RNG_CLKDIV_BY_256
432   *         @arg @ref LL_RNG_CLKDIV_BY_512
433   *         @arg @ref LL_RNG_CLKDIV_BY_1024
434   *         @arg @ref LL_RNG_CLKDIV_BY_2048
435   *         @arg @ref LL_RNG_CLKDIV_BY_4096
436   *         @arg @ref LL_RNG_CLKDIV_BY_8192
437   *         @arg @ref LL_RNG_CLKDIV_BY_16384
438   *         @arg @ref LL_RNG_CLKDIV_BY_32768
439   * @retval None
440   */
LL_RNG_SetClockDivider(RNG_TypeDef * RNGx,uint32_t Divider)441 __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
442 {
443   MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV, Divider << RNG_CR_CLKDIV_Pos);
444 }
445 
446 /**
447   * @brief  Get RNG  Clock divider factor
448   * @rmtoll CR           CLKDIV         LL_RNG_GetClockDivider
449   * @param  RNGx RNG Instance
450   * @retval Returned value can be one of the following values:
451   *         @arg @ref LL_RNG_CLKDIV_BY_1
452   *         @arg @ref LL_RNG_CLKDIV_BY_2
453   *         @arg @ref LL_RNG_CLKDIV_BY_4
454   *         @arg @ref LL_RNG_CLKDIV_BY_8
455   *         @arg @ref LL_RNG_CLKDIV_BY_16
456   *         @arg @ref LL_RNG_CLKDIV_BY_32
457   *         @arg @ref LL_RNG_CLKDIV_BY_64
458   *         @arg @ref LL_RNG_CLKDIV_BY_128
459   *         @arg @ref LL_RNG_CLKDIV_BY_256
460   *         @arg @ref LL_RNG_CLKDIV_BY_512
461   *         @arg @ref LL_RNG_CLKDIV_BY_1024
462   *         @arg @ref LL_RNG_CLKDIV_BY_2048
463   *         @arg @ref LL_RNG_CLKDIV_BY_4096
464   *         @arg @ref LL_RNG_CLKDIV_BY_8192
465   *         @arg @ref LL_RNG_CLKDIV_BY_16384
466   *         @arg @ref LL_RNG_CLKDIV_BY_32768
467   */
LL_RNG_GetClockDivider(RNG_TypeDef * RNGx)468 __STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx)
469 {
470   return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV);
471 }
472 #endif /* RNG_CR_CONDRST */
473 /**
474   * @}
475   */
476 
477 /** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
478   * @{
479   */
480 
481 /**
482   * @brief  Indicate if the RNG Data ready Flag is set or not
483   * @rmtoll SR           DRDY          LL_RNG_IsActiveFlag_DRDY
484   * @param  RNGx RNG Instance
485   * @retval State of bit (1 or 0).
486   */
LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef * RNGx)487 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
488 {
489   return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
490 }
491 
492 /**
493   * @brief  Indicate if the Clock Error Current Status Flag is set or not
494   * @rmtoll SR           CECS          LL_RNG_IsActiveFlag_CECS
495   * @param  RNGx RNG Instance
496   * @retval State of bit (1 or 0).
497   */
LL_RNG_IsActiveFlag_CECS(RNG_TypeDef * RNGx)498 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
499 {
500   return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
501 }
502 
503 /**
504   * @brief  Indicate if the Seed Error Current Status Flag is set or not
505   * @rmtoll SR           SECS          LL_RNG_IsActiveFlag_SECS
506   * @param  RNGx RNG Instance
507   * @retval State of bit (1 or 0).
508   */
LL_RNG_IsActiveFlag_SECS(RNG_TypeDef * RNGx)509 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
510 {
511   return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
512 }
513 
514 /**
515   * @brief  Indicate if the Clock Error Interrupt Status Flag is set or not
516   * @rmtoll SR           CEIS          LL_RNG_IsActiveFlag_CEIS
517   * @param  RNGx RNG Instance
518   * @retval State of bit (1 or 0).
519   */
LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef * RNGx)520 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
521 {
522   return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
523 }
524 
525 /**
526   * @brief  Indicate if the Seed Error Interrupt Status Flag is set or not
527   * @rmtoll SR           SEIS          LL_RNG_IsActiveFlag_SEIS
528   * @param  RNGx RNG Instance
529   * @retval State of bit (1 or 0).
530   */
LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef * RNGx)531 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
532 {
533   return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
534 }
535 
536 /**
537   * @brief  Clear Clock Error interrupt Status (CEIS) Flag
538   * @rmtoll SR           CEIS          LL_RNG_ClearFlag_CEIS
539   * @param  RNGx RNG Instance
540   * @retval None
541   */
LL_RNG_ClearFlag_CEIS(RNG_TypeDef * RNGx)542 __STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
543 {
544   WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
545 }
546 
547 /**
548   * @brief  Clear Seed Error interrupt Status (SEIS) Flag
549   * @rmtoll SR           SEIS          LL_RNG_ClearFlag_SEIS
550   * @param  RNGx RNG Instance
551   * @retval None
552   */
LL_RNG_ClearFlag_SEIS(RNG_TypeDef * RNGx)553 __STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
554 {
555   WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
556 }
557 
558 /**
559   * @}
560   */
561 
562 /** @defgroup RNG_LL_EF_IT_Management IT Management
563   * @{
564   */
565 
566 /**
567   * @brief  Enable Random Number Generator Interrupt
568   *         (applies for either Seed error, Clock Error or Data ready interrupts)
569   * @rmtoll CR           IE            LL_RNG_EnableIT
570   * @param  RNGx RNG Instance
571   * @retval None
572   */
LL_RNG_EnableIT(RNG_TypeDef * RNGx)573 __STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
574 {
575   SET_BIT(RNGx->CR, RNG_CR_IE);
576 }
577 
578 /**
579   * @brief  Disable Random Number Generator Interrupt
580   *         (applies for either Seed error, Clock Error or Data ready interrupts)
581   * @rmtoll CR           IE            LL_RNG_DisableIT
582   * @param  RNGx RNG Instance
583   * @retval None
584   */
LL_RNG_DisableIT(RNG_TypeDef * RNGx)585 __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
586 {
587   CLEAR_BIT(RNGx->CR, RNG_CR_IE);
588 }
589 
590 /**
591   * @brief  Check if Random Number Generator Interrupt is enabled
592   *         (applies for either Seed error, Clock Error or Data ready interrupts)
593   * @rmtoll CR           IE            LL_RNG_IsEnabledIT
594   * @param  RNGx RNG Instance
595   * @retval State of bit (1 or 0).
596   */
LL_RNG_IsEnabledIT(RNG_TypeDef * RNGx)597 __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
598 {
599   return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
600 }
601 
602 /**
603   * @}
604   */
605 
606 /** @defgroup RNG_LL_EF_Data_Management Data Management
607   * @{
608   */
609 
610 /**
611   * @brief  Return32-bit Random Number value
612   * @rmtoll DR           RNDATA        LL_RNG_ReadRandData32
613   * @param  RNGx RNG Instance
614   * @retval Generated 32-bit random value
615   */
LL_RNG_ReadRandData32(RNG_TypeDef * RNGx)616 __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
617 {
618   return (uint32_t)(READ_REG(RNGx->DR));
619 }
620 
621 /**
622   * @}
623   */
624 
625 #if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
626 /** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control
627   * @{
628   */
629 
630 /**
631   * @brief  Set RNG Health Test Control
632   * @rmtoll HTCR       HTCFG       LL_RNG_SetHealthConfig
633   * @param  RNGx RNG Instance
634   * @param  HTCFG can be values of 32 bits
635   * @retval None
636   */
LL_RNG_SetHealthConfig(RNG_TypeDef * RNGx,uint32_t HTCFG)637 __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG)
638 {
639   /*!< magic number must be written immediately before to RNG_HTCRG */
640   WRITE_REG(RNGx->HTCR, LL_RNG_HTCFG);
641 
642   WRITE_REG(RNGx->HTCR, HTCFG);
643 }
644 
645 /**
646   * @brief  Get RNG Health Test Control
647   * @rmtoll HTCR         HTCFG        LL_RNG_GetHealthConfig
648   * @param  RNGx RNG Instance
649   * @retval Return 32-bit RNG Health Test configuration
650   */
LL_RNG_GetHealthConfig(RNG_TypeDef * RNGx)651 __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx)
652 {
653   /*!< magic number must be written immediately before reading RNG_HTCRG */
654   WRITE_REG(RNGx->HTCR, LL_RNG_HTCFG);
655 
656   return (uint32_t)READ_REG(RNGx->HTCR);
657 }
658 
659 /**
660   * @}
661   */
662 #endif  /* RNG_VER_3_2, RNG_VER_3_1 or RNG_VER_3_0 */
663 #if defined(USE_FULL_LL_DRIVER)
664 /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
665   * @{
666   */
667 ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
668 void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
669 ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
670 
671 /**
672   * @}
673   */
674 #endif /* USE_FULL_LL_DRIVER */
675 
676 /**
677   * @}
678   */
679 
680 /**
681   * @}
682   */
683 
684 #endif /* RNG */
685 
686 /**
687   * @}
688   */
689 
690 #ifdef __cplusplus
691 }
692 #endif
693 
694 #endif /* __STM32H7xx_LL_RNG_H */
695 
696