1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7xx_LL_LPTIM_H
21 #define STM32H7xx_LL_LPTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7xx.h"
29
30 /** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5)
35
36 /** @defgroup LPTIM_LL LPTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44
45 /* Private macros ------------------------------------------------------------*/
46 #if defined(USE_FULL_LL_DRIVER)
47 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
48 * @{
49 */
50 /**
51 * @}
52 */
53 #endif /*USE_FULL_LL_DRIVER*/
54
55 /* Exported types ------------------------------------------------------------*/
56 #if defined(USE_FULL_LL_DRIVER)
57 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
58 * @{
59 */
60
61 /**
62 * @brief LPTIM Init structure definition
63 */
64 typedef struct
65 {
66 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
67 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
68
69 This feature can be modified afterwards using unitary
70 function @ref LL_LPTIM_SetClockSource().*/
71
72 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
73 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
74
75 This feature can be modified afterwards using using unitary
76 function @ref LL_LPTIM_SetPrescaler().*/
77
78 uint32_t Waveform; /*!< Specifies the waveform shape.
79 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
80
81 This feature can be modified afterwards using unitary
82 function @ref LL_LPTIM_ConfigOutput().*/
83
84 uint32_t Polarity; /*!< Specifies waveform polarity.
85 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
86
87 This feature can be modified afterwards using unitary
88 function @ref LL_LPTIM_ConfigOutput().*/
89 } LL_LPTIM_InitTypeDef;
90
91 /**
92 * @}
93 */
94 #endif /* USE_FULL_LL_DRIVER */
95
96 /* Exported constants --------------------------------------------------------*/
97 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
98 * @{
99 */
100
101 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
102 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
103 * @{
104 */
105 #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */
106 #define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
107 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
108 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
109 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
110 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
111 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
112 /**
113 * @}
114 */
115
116 /** @defgroup LPTIM_LL_EC_IT IT Defines
117 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
118 * @{
119 */
120 #define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */
121 #define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */
122 #define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */
123 #define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */
124 #define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */
125 #define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */
126 #define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */
127 /**
128 * @}
129 */
130
131 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
132 * @{
133 */
134 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
135 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
136 /**
137 * @}
138 */
139
140 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
141 * @{
142 */
143 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
144 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
145 /**
146 * @}
147 */
148
149 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
150 * @{
151 */
152 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
153 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
154 /**
155 * @}
156 */
157
158 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
159 * @{
160 */
161 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
162 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
163 /**
164 * @}
165 */
166
167 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
168 * @{
169 */
170 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
171 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
172 /**
173 * @}
174 */
175
176 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
177 * @{
178 */
179 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
180 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
181 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
182 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
183 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
184 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
185 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
186 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
187 /**
188 * @}
189 */
190
191 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
192 * @{
193 */
194 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
195 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
196 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
197 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
198 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
199 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
200 #define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
201 #define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /*!<External input trigger is connected to COMP2 output*/
202 #define LL_LPTIM_TRIG_SOURCE_LPTIM2 0x00000000U /*!<External input trigger is connected to LPTIM2 output*/
203 #define LL_LPTIM_TRIG_SOURCE_LPTIM3 LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to LPTIM3 output*/
204 #define LL_LPTIM_TRIG_SOURCE_LPTIM4 LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to LPTIM4 output*/
205 #define LL_LPTIM_TRIG_SOURCE_LPTIM5 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to LPTIM5 output*/
206 #define LL_LPTIM_TRIG_SOURCE_SAI1_FS_A LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to SAI1 FS A output*/
207 #define LL_LPTIM_TRIG_SOURCE_SAI1_FS_B (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI1 FS B output*/
208 #define LL_LPTIM_TRIG_SOURCE_SAI2_FS_A LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to SAI2 FS A output*/
209 #define LL_LPTIM_TRIG_SOURCE_SAI2_FS_B (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI2 FS B output*/
210 #define LL_LPTIM_TRIG_SOURCE_SAI4_FS_A (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI4 FS A output*/
211 #define LL_LPTIM_TRIG_SOURCE_SAI4_FS_B LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to SAI4 FS B output*/
212 #define LL_LPTIM_TRIG_SOURCE_DFSDM2_BRK (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to DFSDM2_BRK[0] */
213 /**
214 * @}
215 */
216
217 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
218 * @{
219 */
220 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
221 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
222 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
223 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
224 /**
225 * @}
226 */
227
228 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
229 * @{
230 */
231 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
232 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
233 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
234 /**
235 * @}
236 */
237
238 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
239 * @{
240 */
241 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
242 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
243 /**
244 * @}
245 */
246
247 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
248 * @{
249 */
250 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
251 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
252 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
253 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
254 /**
255 * @}
256 */
257
258 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
259 * @{
260 */
261 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
262 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
263 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
264 /**
265 * @}
266 */
267
268 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
269 * @{
270 */
271 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
272 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
273 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
274 /**
275 * @}
276 */
277
278 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
279 * @{
280 */
281 #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U /*!< For LPTIM1 and LPTIM2 */
282 #define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM1 and LPTIM2 */
283 #define LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_CFGR2_IN1SEL_1 /*!< For LPTIM2 */
284 #define LL_LPTIM_INPUT1_SRC_COMP1_COMP2 (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0) /*!< For LPTIM2 */
285 #define LL_LPTIM_INPUT1_SRC_SAI4_FS_A LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM3 */
286 #define LL_LPTIM_INPUT1_SRC_SAI4_FS_B LPTIM_CFGR2_IN1SEL_1 /*!< For LPTIM3 */
287 /**
288 * @}
289 */
290
291 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
292 * @{
293 */
294 #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U /*!< For LPTIM1 */
295 #define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_CFGR2_IN2SEL_0 /*!< For LPTIM1 */
296 /**
297 * @}
298 */
299
300 /**
301 * @}
302 */
303
304 /* Exported macro ------------------------------------------------------------*/
305 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
306 * @{
307 */
308
309 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
310 * @{
311 */
312
313 /**
314 * @brief Write a value in LPTIM register
315 * @param __INSTANCE__ LPTIM Instance
316 * @param __REG__ Register to be written
317 * @param __VALUE__ Value to be written in the register
318 * @retval None
319 */
320 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
321
322 /**
323 * @brief Read a value in LPTIM register
324 * @param __INSTANCE__ LPTIM Instance
325 * @param __REG__ Register to be read
326 * @retval Register value
327 */
328 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
329 /**
330 * @}
331 */
332
333 /**
334 * @}
335 */
336
337 /* Exported functions --------------------------------------------------------*/
338 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
339 * @{
340 */
341
342 /** Legacy definitions for compatibility purpose
343 @cond 0
344 */
345 #define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM
346 #define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1
347 #define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2
348 #define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O
349 #define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O
350 #define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM
351 /**
352 @endcond
353 */
354
355 #if defined(USE_FULL_LL_DRIVER)
356 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
357 * @{
358 */
359
360 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
361 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
362 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
363 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
364 /**
365 * @}
366 */
367 #endif /* USE_FULL_LL_DRIVER */
368
369 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
370 * @{
371 */
372
373 /**
374 * @brief Enable the LPTIM instance
375 * @note After setting the ENABLE bit, a delay of two counter clock is needed
376 * before the LPTIM instance is actually enabled.
377 * @rmtoll CR ENABLE LL_LPTIM_Enable
378 * @param LPTIMx Low-Power Timer instance
379 * @retval None
380 */
LL_LPTIM_Enable(LPTIM_TypeDef * LPTIMx)381 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
382 {
383 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
384 }
385
386 /**
387 * @brief Indicates whether the LPTIM instance is enabled.
388 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
389 * @param LPTIMx Low-Power Timer instance
390 * @retval State of bit (1 or 0).
391 */
LL_LPTIM_IsEnabled(const LPTIM_TypeDef * LPTIMx)392 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx)
393 {
394 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
395 }
396
397 /**
398 * @brief Starts the LPTIM counter in the desired mode.
399 * @note LPTIM instance must be enabled before starting the counter.
400 * @note It is possible to change on the fly from One Shot mode to
401 * Continuous mode.
402 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
403 * CR SNGSTRT LL_LPTIM_StartCounter
404 * @param LPTIMx Low-Power Timer instance
405 * @param OperatingMode This parameter can be one of the following values:
406 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
407 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
408 * @retval None
409 */
LL_LPTIM_StartCounter(LPTIM_TypeDef * LPTIMx,uint32_t OperatingMode)410 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
411 {
412 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
413 }
414
415 /**
416 * @brief Enable reset after read.
417 * @note After calling this function any read access to LPTIM_CNT
418 * register will asynchronously reset the LPTIM_CNT register content.
419 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
420 * @param LPTIMx Low-Power Timer instance
421 * @retval None
422 */
LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef * LPTIMx)423 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
424 {
425 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
426 }
427
428 /**
429 * @brief Disable reset after read.
430 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
431 * @param LPTIMx Low-Power Timer instance
432 * @retval None
433 */
LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef * LPTIMx)434 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
435 {
436 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
437 }
438
439 /**
440 * @brief Indicate whether the reset after read feature is enabled.
441 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
442 * @param LPTIMx Low-Power Timer instance
443 * @retval State of bit (1 or 0).
444 */
LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef * LPTIMx)445 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx)
446 {
447 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
448 }
449
450 /**
451 * @brief Reset of the LPTIM_CNT counter register (synchronous).
452 * @note Due to the synchronous nature of this reset, it only takes
453 * place after a synchronization delay of 3 LPTIM core clock cycles
454 * (LPTIM core clock may be different from APB clock).
455 * @note COUNTRST is automatically cleared by hardware
456 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
457 * @param LPTIMx Low-Power Timer instance
458 * @retval None
459 */
LL_LPTIM_ResetCounter(LPTIM_TypeDef * LPTIMx)460 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
461 {
462 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
463 }
464
465 /**
466 * @brief Set the LPTIM registers update mode (enable/disable register preload)
467 * @note This function must be called when the LPTIM instance is disabled.
468 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
469 * @param LPTIMx Low-Power Timer instance
470 * @param UpdateMode This parameter can be one of the following values:
471 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
472 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
473 * @retval None
474 */
LL_LPTIM_SetUpdateMode(LPTIM_TypeDef * LPTIMx,uint32_t UpdateMode)475 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
476 {
477 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
478 }
479
480 /**
481 * @brief Get the LPTIM registers update mode
482 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
483 * @param LPTIMx Low-Power Timer instance
484 * @retval Returned value can be one of the following values:
485 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
486 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
487 */
LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef * LPTIMx)488 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx)
489 {
490 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
491 }
492
493 /**
494 * @brief Set the auto reload value
495 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
496 * @note After a write to the LPTIMx_ARR register a new write operation to the
497 * same register can only be performed when the previous write operation
498 * is completed. Any successive write before the ARROK flag is set, will
499 * lead to unpredictable results.
500 * @note autoreload value be strictly greater than the compare value.
501 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
502 * @param LPTIMx Low-Power Timer instance
503 * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
504 * @retval None
505 */
LL_LPTIM_SetAutoReload(LPTIM_TypeDef * LPTIMx,uint32_t AutoReload)506 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
507 {
508 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
509 }
510
511 /**
512 * @brief Get actual auto reload value
513 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
514 * @param LPTIMx Low-Power Timer instance
515 * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
516 */
LL_LPTIM_GetAutoReload(const LPTIM_TypeDef * LPTIMx)517 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx)
518 {
519 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
520 }
521
522 /**
523 * @brief Set the compare value
524 * @note After a write to the LPTIMx_CMP register a new write operation to the
525 * same register can only be performed when the previous write operation
526 * is completed. Any successive write before the CMPOK flag is set, will
527 * lead to unpredictable results.
528 * @rmtoll CMP CMP LL_LPTIM_SetCompare
529 * @param LPTIMx Low-Power Timer instance
530 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
531 * @retval None
532 */
LL_LPTIM_SetCompare(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)533 __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
534 {
535 MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
536 }
537
538 /**
539 * @brief Get actual compare value
540 * @rmtoll CMP CMP LL_LPTIM_GetCompare
541 * @param LPTIMx Low-Power Timer instance
542 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
543 */
LL_LPTIM_GetCompare(const LPTIM_TypeDef * LPTIMx)544 __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(const LPTIM_TypeDef *LPTIMx)
545 {
546 return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
547 }
548
549 /**
550 * @brief Get actual counter value
551 * @note When the LPTIM instance is running with an asynchronous clock, reading
552 * the LPTIMx_CNT register may return unreliable values. So in this case
553 * it is necessary to perform two consecutive read accesses and verify
554 * that the two returned values are identical.
555 * @rmtoll CNT CNT LL_LPTIM_GetCounter
556 * @param LPTIMx Low-Power Timer instance
557 * @retval Counter value
558 */
LL_LPTIM_GetCounter(const LPTIM_TypeDef * LPTIMx)559 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx)
560 {
561 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
562 }
563
564 /**
565 * @brief Set the counter mode (selection of the LPTIM counter clock source).
566 * @note The counter mode can be set only when the LPTIM instance is disabled.
567 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
568 * @param LPTIMx Low-Power Timer instance
569 * @param CounterMode This parameter can be one of the following values:
570 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
571 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
572 * @retval None
573 */
LL_LPTIM_SetCounterMode(LPTIM_TypeDef * LPTIMx,uint32_t CounterMode)574 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
575 {
576 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
577 }
578
579 /**
580 * @brief Get the counter mode
581 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
582 * @param LPTIMx Low-Power Timer instance
583 * @retval Returned value can be one of the following values:
584 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
585 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
586 */
LL_LPTIM_GetCounterMode(const LPTIM_TypeDef * LPTIMx)587 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx)
588 {
589 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
590 }
591
592 /**
593 * @brief Configure the LPTIM instance output (LPTIMx_OUT)
594 * @note This function must be called when the LPTIM instance is disabled.
595 * @note Regarding the LPTIM output polarity the change takes effect
596 * immediately, so the output default value will change immediately after
597 * the polarity is re-configured, even before the timer is enabled.
598 * @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n
599 * CFGR WAVPOL LL_LPTIM_ConfigOutput
600 * @param LPTIMx Low-Power Timer instance
601 * @param Waveform This parameter can be one of the following values:
602 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
603 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
604 * @param Polarity This parameter can be one of the following values:
605 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
606 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
607 * @retval None
608 */
LL_LPTIM_ConfigOutput(LPTIM_TypeDef * LPTIMx,uint32_t Waveform,uint32_t Polarity)609 __STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
610 {
611 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
612 }
613
614 /**
615 * @brief Set waveform shape
616 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
617 * @param LPTIMx Low-Power Timer instance
618 * @param Waveform This parameter can be one of the following values:
619 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
620 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
621 * @retval None
622 */
LL_LPTIM_SetWaveform(LPTIM_TypeDef * LPTIMx,uint32_t Waveform)623 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
624 {
625 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
626 }
627
628 /**
629 * @brief Get actual waveform shape
630 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
631 * @param LPTIMx Low-Power Timer instance
632 * @retval Returned value can be one of the following values:
633 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
634 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
635 */
LL_LPTIM_GetWaveform(const LPTIM_TypeDef * LPTIMx)636 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx)
637 {
638 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
639 }
640
641 /**
642 * @brief Set output polarity
643 * @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity
644 * @param LPTIMx Low-Power Timer instance
645 * @param Polarity This parameter can be one of the following values:
646 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
647 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
648 * @retval None
649 */
LL_LPTIM_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Polarity)650 __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
651 {
652 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
653 }
654
655 /**
656 * @brief Get actual output polarity
657 * @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity
658 * @param LPTIMx Low-Power Timer instance
659 * @retval Returned value can be one of the following values:
660 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
661 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
662 */
LL_LPTIM_GetPolarity(const LPTIM_TypeDef * LPTIMx)663 __STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(const LPTIM_TypeDef *LPTIMx)
664 {
665 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
666 }
667
668 /**
669 * @brief Set actual prescaler division ratio.
670 * @note This function must be called when the LPTIM instance is disabled.
671 * @note When the LPTIM is configured to be clocked by an internal clock source
672 * and the LPTIM counter is configured to be updated by active edges
673 * detected on the LPTIM external Input1, the internal clock provided to
674 * the LPTIM must be not be prescaled.
675 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
676 * @param LPTIMx Low-Power Timer instance
677 * @param Prescaler This parameter can be one of the following values:
678 * @arg @ref LL_LPTIM_PRESCALER_DIV1
679 * @arg @ref LL_LPTIM_PRESCALER_DIV2
680 * @arg @ref LL_LPTIM_PRESCALER_DIV4
681 * @arg @ref LL_LPTIM_PRESCALER_DIV8
682 * @arg @ref LL_LPTIM_PRESCALER_DIV16
683 * @arg @ref LL_LPTIM_PRESCALER_DIV32
684 * @arg @ref LL_LPTIM_PRESCALER_DIV64
685 * @arg @ref LL_LPTIM_PRESCALER_DIV128
686 * @retval None
687 */
LL_LPTIM_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Prescaler)688 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
689 {
690 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
691 }
692
693 /**
694 * @brief Get actual prescaler division ratio.
695 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
696 * @param LPTIMx Low-Power Timer instance
697 * @retval Returned value can be one of the following values:
698 * @arg @ref LL_LPTIM_PRESCALER_DIV1
699 * @arg @ref LL_LPTIM_PRESCALER_DIV2
700 * @arg @ref LL_LPTIM_PRESCALER_DIV4
701 * @arg @ref LL_LPTIM_PRESCALER_DIV8
702 * @arg @ref LL_LPTIM_PRESCALER_DIV16
703 * @arg @ref LL_LPTIM_PRESCALER_DIV32
704 * @arg @ref LL_LPTIM_PRESCALER_DIV64
705 * @arg @ref LL_LPTIM_PRESCALER_DIV128
706 */
LL_LPTIM_GetPrescaler(const LPTIM_TypeDef * LPTIMx)707 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx)
708 {
709 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
710 }
711
712 /**
713 * @brief Set LPTIM input 1 source (default GPIO).
714 * @rmtoll CFGR2 IN1SEL LL_LPTIM_SetInput1Src
715 * @param LPTIMx Low-Power Timer instance
716 * @param Src This parameter can be one of the following values:
717 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
718 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
719 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP2
720 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1_COMP2
721 * @arg @ref LL_LPTIM_INPUT1_SRC_SAI4_FS_A
722 * @arg @ref LL_LPTIM_INPUT1_SRC_SAI4_FS_B
723 * @retval None
724 */
LL_LPTIM_SetInput1Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)725 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
726 {
727 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src);
728 }
729
730 /**
731 * @brief Set LPTIM input 2 source (default GPIO).
732 * @rmtoll CFGR2 IN2SEL LL_LPTIM_SetInput2Src
733 * @param LPTIMx Low-Power Timer instance
734 * @param Src This parameter can be one of the following values:
735 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
736 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
737 * @retval None
738 */
LL_LPTIM_SetInput2Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)739 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
740 {
741 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src);
742 }
743
744 /**
745 * @}
746 */
747
748 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
749 * @{
750 */
751
752 /**
753 * @brief Enable the timeout function
754 * @note This function must be called when the LPTIM instance is disabled.
755 * @note The first trigger event will start the timer, any successive trigger
756 * event will reset the counter and the timer will restart.
757 * @note The timeout value corresponds to the compare value; if no trigger
758 * occurs within the expected time frame, the MCU is waked-up by the
759 * compare match event.
760 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
761 * @param LPTIMx Low-Power Timer instance
762 * @retval None
763 */
LL_LPTIM_EnableTimeout(LPTIM_TypeDef * LPTIMx)764 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
765 {
766 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
767 }
768
769 /**
770 * @brief Disable the timeout function
771 * @note This function must be called when the LPTIM instance is disabled.
772 * @note A trigger event arriving when the timer is already started will be
773 * ignored.
774 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
775 * @param LPTIMx Low-Power Timer instance
776 * @retval None
777 */
LL_LPTIM_DisableTimeout(LPTIM_TypeDef * LPTIMx)778 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
779 {
780 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
781 }
782
783 /**
784 * @brief Indicate whether the timeout function is enabled.
785 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
786 * @param LPTIMx Low-Power Timer instance
787 * @retval State of bit (1 or 0).
788 */
LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef * LPTIMx)789 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx)
790 {
791 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
792 }
793
794 /**
795 * @brief Start the LPTIM counter
796 * @note This function must be called when the LPTIM instance is disabled.
797 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
798 * @param LPTIMx Low-Power Timer instance
799 * @retval None
800 */
LL_LPTIM_TrigSw(LPTIM_TypeDef * LPTIMx)801 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
802 {
803 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
804 }
805
806 /**
807 * @brief Configure the external trigger used as a trigger event for the LPTIM.
808 * @note This function must be called when the LPTIM instance is disabled.
809 * @note An internal clock source must be present when a digital filter is
810 * required for the trigger.
811 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
812 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
813 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
814 * @param LPTIMx Low-Power Timer instance
815 * @param Source This parameter can be one of the following values:
816 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
817 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
818 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
819 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
820 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
821 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
822 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
823 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
824 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM2 (*)
825 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM3 (*)
826 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM4 (*)
827 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM5 (*)
828 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_A (*)
829 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_B (*)
830 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_A (*)
831 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_B (*)
832 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4_FS_A (*)
833 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4_FS_B (*)
834 * @arg @ref LL_LPTIM_TRIG_SOURCE_DFSDM2_BRK (*)
835 *
836 * (*) Value not defined in all devices. \n
837 *
838 * @param Filter This parameter can be one of the following values:
839 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
840 * @arg @ref LL_LPTIM_TRIG_FILTER_2
841 * @arg @ref LL_LPTIM_TRIG_FILTER_4
842 * @arg @ref LL_LPTIM_TRIG_FILTER_8
843 * @param Polarity This parameter can be one of the following values:
844 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
845 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
846 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
847 * @retval None
848 */
LL_LPTIM_ConfigTrigger(LPTIM_TypeDef * LPTIMx,uint32_t Source,uint32_t Filter,uint32_t Polarity)849 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
850 {
851 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
852 }
853
854 /**
855 * @brief Get actual external trigger source.
856 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
857 * @param LPTIMx Low-Power Timer instance
858 * @retval Returned value can be one of the following values:
859 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
860 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
861 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
862 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
863 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
864 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
865 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
866 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
867 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM2 (*)
868 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM3 (*)
869 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM4 (*)
870 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM5 (*)
871 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_A (*)
872 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_B (*)
873 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_A (*)
874 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_B (*)
875 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4_FS_A (*)
876 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4_FS_B (*)
877 * @arg @ref LL_LPTIM_TRIG_SOURCE_DFSDM2_BRK (*)
878 *
879 * (*) Value not defined in all devices. \n
880 *
881 */
LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef * LPTIMx)882 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx)
883 {
884 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
885 }
886
887 /**
888 * @brief Get actual external trigger filter.
889 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
890 * @param LPTIMx Low-Power Timer instance
891 * @retval Returned value can be one of the following values:
892 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
893 * @arg @ref LL_LPTIM_TRIG_FILTER_2
894 * @arg @ref LL_LPTIM_TRIG_FILTER_4
895 * @arg @ref LL_LPTIM_TRIG_FILTER_8
896 */
LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef * LPTIMx)897 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx)
898 {
899 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
900 }
901
902 /**
903 * @brief Get actual external trigger polarity.
904 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
905 * @param LPTIMx Low-Power Timer instance
906 * @retval Returned value can be one of the following values:
907 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
908 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
909 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
910 */
LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef * LPTIMx)911 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx)
912 {
913 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
914 }
915
916 /**
917 * @}
918 */
919
920 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
921 * @{
922 */
923
924 /**
925 * @brief Set the source of the clock used by the LPTIM instance.
926 * @note This function must be called when the LPTIM instance is disabled.
927 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
928 * @param LPTIMx Low-Power Timer instance
929 * @param ClockSource This parameter can be one of the following values:
930 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
931 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
932 * @retval None
933 */
LL_LPTIM_SetClockSource(LPTIM_TypeDef * LPTIMx,uint32_t ClockSource)934 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
935 {
936 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
937 }
938
939 /**
940 * @brief Get actual LPTIM instance clock source.
941 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
942 * @param LPTIMx Low-Power Timer instance
943 * @retval Returned value can be one of the following values:
944 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
945 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
946 */
LL_LPTIM_GetClockSource(const LPTIM_TypeDef * LPTIMx)947 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx)
948 {
949 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
950 }
951
952 /**
953 * @brief Configure the active edge or edges used by the counter when
954 the LPTIM is clocked by an external clock source.
955 * @note This function must be called when the LPTIM instance is disabled.
956 * @note When both external clock signal edges are considered active ones,
957 * the LPTIM must also be clocked by an internal clock source with a
958 * frequency equal to at least four times the external clock frequency.
959 * @note An internal clock source must be present when a digital filter is
960 * required for external clock.
961 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
962 * CFGR CKPOL LL_LPTIM_ConfigClock
963 * @param LPTIMx Low-Power Timer instance
964 * @param ClockFilter This parameter can be one of the following values:
965 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
966 * @arg @ref LL_LPTIM_CLK_FILTER_2
967 * @arg @ref LL_LPTIM_CLK_FILTER_4
968 * @arg @ref LL_LPTIM_CLK_FILTER_8
969 * @param ClockPolarity This parameter can be one of the following values:
970 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
971 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
972 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
973 * @retval None
974 */
LL_LPTIM_ConfigClock(LPTIM_TypeDef * LPTIMx,uint32_t ClockFilter,uint32_t ClockPolarity)975 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
976 {
977 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
978 }
979
980 /**
981 * @brief Get actual clock polarity
982 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
983 * @param LPTIMx Low-Power Timer instance
984 * @retval Returned value can be one of the following values:
985 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
986 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
987 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
988 */
LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef * LPTIMx)989 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx)
990 {
991 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
992 }
993
994 /**
995 * @brief Get actual clock digital filter
996 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
997 * @param LPTIMx Low-Power Timer instance
998 * @retval Returned value can be one of the following values:
999 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
1000 * @arg @ref LL_LPTIM_CLK_FILTER_2
1001 * @arg @ref LL_LPTIM_CLK_FILTER_4
1002 * @arg @ref LL_LPTIM_CLK_FILTER_8
1003 */
LL_LPTIM_GetClockFilter(const LPTIM_TypeDef * LPTIMx)1004 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx)
1005 {
1006 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
1007 }
1008
1009 /**
1010 * @}
1011 */
1012
1013 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
1014 * @{
1015 */
1016
1017 /**
1018 * @brief Configure the encoder mode.
1019 * @note This function must be called when the LPTIM instance is disabled.
1020 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
1021 * @param LPTIMx Low-Power Timer instance
1022 * @param EncoderMode This parameter can be one of the following values:
1023 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1024 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1025 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1026 * @retval None
1027 */
LL_LPTIM_SetEncoderMode(LPTIM_TypeDef * LPTIMx,uint32_t EncoderMode)1028 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
1029 {
1030 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
1031 }
1032
1033 /**
1034 * @brief Get actual encoder mode.
1035 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
1036 * @param LPTIMx Low-Power Timer instance
1037 * @retval Returned value can be one of the following values:
1038 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1039 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1040 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1041 */
LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef * LPTIMx)1042 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx)
1043 {
1044 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1045 }
1046
1047 /**
1048 * @brief Enable the encoder mode
1049 * @note This function must be called when the LPTIM instance is disabled.
1050 * @note In this mode the LPTIM instance must be clocked by an internal clock
1051 * source. Also, the prescaler division ratio must be equal to 1.
1052 * @note LPTIM instance must be configured in continuous mode prior enabling
1053 * the encoder mode.
1054 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
1055 * @param LPTIMx Low-Power Timer instance
1056 * @retval None
1057 */
LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef * LPTIMx)1058 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
1059 {
1060 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1061 }
1062
1063 /**
1064 * @brief Disable the encoder mode
1065 * @note This function must be called when the LPTIM instance is disabled.
1066 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
1067 * @param LPTIMx Low-Power Timer instance
1068 * @retval None
1069 */
LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef * LPTIMx)1070 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
1071 {
1072 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1073 }
1074
1075 /**
1076 * @brief Indicates whether the LPTIM operates in encoder mode.
1077 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
1078 * @param LPTIMx Low-Power Timer instance
1079 * @retval State of bit (1 or 0).
1080 */
LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef * LPTIMx)1081 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx)
1082 {
1083 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
1084 }
1085
1086 /**
1087 * @}
1088 */
1089
1090 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
1091 * @{
1092 */
1093
1094
1095 /**
1096 * @brief Clear the compare match flag (CMPMCF)
1097 * @rmtoll ICR CMPMCF LL_LPTIM_ClearFlag_CMPM
1098 * @param LPTIMx Low-Power Timer instance
1099 * @retval None
1100 */
LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef * LPTIMx)1101 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef *LPTIMx)
1102 {
1103 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
1104 }
1105
1106 /**
1107 * @brief Inform application whether a compare match interrupt has occurred.
1108 * @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
1109 * @param LPTIMx Low-Power Timer instance
1110 * @retval State of bit (1 or 0).
1111 */
LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef * LPTIMx)1112 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef *LPTIMx)
1113 {
1114 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
1115 }
1116
1117 /**
1118 * @brief Clear the autoreload match flag (ARRMCF)
1119 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM
1120 * @param LPTIMx Low-Power Timer instance
1121 * @retval None
1122 */
LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef * LPTIMx)1123 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx)
1124 {
1125 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
1126 }
1127
1128 /**
1129 * @brief Inform application whether a autoreload match interrupt has occurred.
1130 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
1131 * @param LPTIMx Low-Power Timer instance
1132 * @retval State of bit (1 or 0).
1133 */
LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef * LPTIMx)1134 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx)
1135 {
1136 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
1137 }
1138
1139 /**
1140 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1141 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1142 * @param LPTIMx Low-Power Timer instance
1143 * @retval None
1144 */
LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1145 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1146 {
1147 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1148 }
1149
1150 /**
1151 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1152 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1153 * @param LPTIMx Low-Power Timer instance
1154 * @retval State of bit (1 or 0).
1155 */
LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef * LPTIMx)1156 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
1157 {
1158 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
1159 }
1160
1161 /**
1162 * @brief Clear the compare register update interrupt flag (CMPOKCF).
1163 * @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
1164 * @param LPTIMx Low-Power Timer instance
1165 * @retval None
1166 */
LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef * LPTIMx)1167 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1168 {
1169 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
1170 }
1171
1172 /**
1173 * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully
1174 completed. If so, a new one can be initiated.
1175 * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
1176 * @param LPTIMx Low-Power Timer instance
1177 * @retval State of bit (1 or 0).
1178 */
LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef * LPTIMx)1179 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef *LPTIMx)
1180 {
1181 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
1182 }
1183
1184 /**
1185 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1186 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1187 * @param LPTIMx Low-Power Timer instance
1188 * @retval None
1189 */
LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef * LPTIMx)1190 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1191 {
1192 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1193 }
1194
1195 /**
1196 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
1197 completed. If so, a new one can be initiated.
1198 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1199 * @param LPTIMx Low-Power Timer instance
1200 * @retval State of bit (1 or 0).
1201 */
LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef * LPTIMx)1202 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx)
1203 {
1204 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
1205 }
1206
1207 /**
1208 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1209 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1210 * @param LPTIMx Low-Power Timer instance
1211 * @retval None
1212 */
LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef * LPTIMx)1213 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1214 {
1215 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1216 }
1217
1218 /**
1219 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
1220 operates in encoder mode).
1221 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1222 * @param LPTIMx Low-Power Timer instance
1223 * @retval State of bit (1 or 0).
1224 */
LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef * LPTIMx)1225 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx)
1226 {
1227 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
1228 }
1229
1230 /**
1231 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1232 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1233 * @param LPTIMx Low-Power Timer instance
1234 * @retval None
1235 */
LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef * LPTIMx)1236 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1237 {
1238 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1239 }
1240
1241 /**
1242 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
1243 operates in encoder mode).
1244 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1245 * @param LPTIMx Low-Power Timer instance
1246 * @retval State of bit (1 or 0).
1247 */
LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef * LPTIMx)1248 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx)
1249 {
1250 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
1251 }
1252
1253 /**
1254 * @}
1255 */
1256
1257 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1258 * @{
1259 */
1260
1261 /**
1262 * @brief Enable compare match interrupt (CMPMIE).
1263 * @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM
1264 * @param LPTIMx Low-Power Timer instance
1265 * @retval None
1266 */
LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef * LPTIMx)1267 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1268 {
1269 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1270 }
1271
1272 /**
1273 * @brief Disable compare match interrupt (CMPMIE).
1274 * @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM
1275 * @param LPTIMx Low-Power Timer instance
1276 * @retval None
1277 */
LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef * LPTIMx)1278 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1279 {
1280 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1281 }
1282
1283 /**
1284 * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
1285 * @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
1286 * @param LPTIMx Low-Power Timer instance
1287 * @retval State of bit (1 or 0).
1288 */
LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef * LPTIMx)1289 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef *LPTIMx)
1290 {
1291 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
1292 }
1293
1294 /**
1295 * @brief Enable autoreload match interrupt (ARRMIE).
1296 * @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM
1297 * @param LPTIMx Low-Power Timer instance
1298 * @retval None
1299 */
LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef * LPTIMx)1300 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1301 {
1302 SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1303 }
1304
1305 /**
1306 * @brief Disable autoreload match interrupt (ARRMIE).
1307 * @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM
1308 * @param LPTIMx Low-Power Timer instance
1309 * @retval None
1310 */
LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef * LPTIMx)1311 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1312 {
1313 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1314 }
1315
1316 /**
1317 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
1318 * @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
1319 * @param LPTIMx Low-Power Timer instance
1320 * @retval State of bit (1 or 0).
1321 */
LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef * LPTIMx)1322 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx)
1323 {
1324 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
1325 }
1326
1327 /**
1328 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
1329 * @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
1330 * @param LPTIMx Low-Power Timer instance
1331 * @retval None
1332 */
LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1333 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1334 {
1335 SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1336 }
1337
1338 /**
1339 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
1340 * @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
1341 * @param LPTIMx Low-Power Timer instance
1342 * @retval None
1343 */
LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1344 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1345 {
1346 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1347 }
1348
1349 /**
1350 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
1351 * @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
1352 * @param LPTIMx Low-Power Timer instance
1353 * @retval State of bit (1 or 0).
1354 */
LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef * LPTIMx)1355 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
1356 {
1357 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
1358 }
1359
1360 /**
1361 * @brief Enable compare register write completed interrupt (CMPOKIE).
1362 * @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
1363 * @param LPTIMx Low-Power Timer instance
1364 * @retval None
1365 */
LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef * LPTIMx)1366 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1367 {
1368 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1369 }
1370
1371 /**
1372 * @brief Disable compare register write completed interrupt (CMPOKIE).
1373 * @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
1374 * @param LPTIMx Low-Power Timer instance
1375 * @retval None
1376 */
LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef * LPTIMx)1377 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1378 {
1379 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1380 }
1381
1382 /**
1383 * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
1384 * @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
1385 * @param LPTIMx Low-Power Timer instance
1386 * @retval State of bit (1 or 0).
1387 */
LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef * LPTIMx)1388 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef *LPTIMx)
1389 {
1390 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
1391 }
1392
1393 /**
1394 * @brief Enable autoreload register write completed interrupt (ARROKIE).
1395 * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
1396 * @param LPTIMx Low-Power Timer instance
1397 * @retval None
1398 */
LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef * LPTIMx)1399 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1400 {
1401 SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1402 }
1403
1404 /**
1405 * @brief Disable autoreload register write completed interrupt (ARROKIE).
1406 * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
1407 * @param LPTIMx Low-Power Timer instance
1408 * @retval None
1409 */
LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef * LPTIMx)1410 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1411 {
1412 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1413 }
1414
1415 /**
1416 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
1417 * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
1418 * @param LPTIMx Low-Power Timer instance
1419 * @retval State of bit(1 or 0).
1420 */
LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef * LPTIMx)1421 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx)
1422 {
1423 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
1424 }
1425
1426 /**
1427 * @brief Enable direction change to up interrupt (UPIE).
1428 * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
1429 * @param LPTIMx Low-Power Timer instance
1430 * @retval None
1431 */
LL_LPTIM_EnableIT_UP(LPTIM_TypeDef * LPTIMx)1432 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
1433 {
1434 SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1435 }
1436
1437 /**
1438 * @brief Disable direction change to up interrupt (UPIE).
1439 * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
1440 * @param LPTIMx Low-Power Timer instance
1441 * @retval None
1442 */
LL_LPTIM_DisableIT_UP(LPTIM_TypeDef * LPTIMx)1443 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
1444 {
1445 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1446 }
1447
1448 /**
1449 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
1450 * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
1451 * @param LPTIMx Low-Power Timer instance
1452 * @retval State of bit(1 or 0).
1453 */
LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef * LPTIMx)1454 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx)
1455 {
1456 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
1457 }
1458
1459 /**
1460 * @brief Enable direction change to down interrupt (DOWNIE).
1461 * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
1462 * @param LPTIMx Low-Power Timer instance
1463 * @retval None
1464 */
LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef * LPTIMx)1465 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1466 {
1467 SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1468 }
1469
1470 /**
1471 * @brief Disable direction change to down interrupt (DOWNIE).
1472 * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
1473 * @param LPTIMx Low-Power Timer instance
1474 * @retval None
1475 */
LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef * LPTIMx)1476 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1477 {
1478 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1479 }
1480
1481 /**
1482 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
1483 * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
1484 * @param LPTIMx Low-Power Timer instance
1485 * @retval State of bit(1 or 0).
1486 */
LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef * LPTIMx)1487 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx)
1488 {
1489 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
1490 }
1491
1492 /**
1493 * @}
1494 */
1495
1496 /**
1497 * @}
1498 */
1499
1500 /**
1501 * @}
1502 */
1503
1504 #endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 || LPTIM5 */
1505
1506 /**
1507 * @}
1508 */
1509
1510 #ifdef __cplusplus
1511 }
1512 #endif
1513
1514 #endif /* STM32H7xx_LL_LPTIM_H */
1515
