1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_dma2d.h
4 * @author MCD Application Team
5 * @brief Header file of DMA2D LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7xx_LL_DMA2D_H
21 #define STM32H7xx_LL_DMA2D_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7xx.h"
29
30 /** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DMA2D)
35
36 /** @defgroup DMA2D_LL DMA2D
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 #if defined(USE_FULL_LL_DRIVER)
45 /** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros
46 * @{
47 */
48
49 /**
50 * @}
51 */
52 #endif /*USE_FULL_LL_DRIVER*/
53
54 /* Exported types ------------------------------------------------------------*/
55 #if defined(USE_FULL_LL_DRIVER)
56 /** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures
57 * @{
58 */
59
60 /**
61 * @brief LL DMA2D Init Structure Definition
62 */
63 typedef struct
64 {
65 uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
66 - This parameter can be one value of @ref DMA2D_LL_EC_MODE.
67
68 This parameter can be modified afterwards,
69 using unitary function @ref LL_DMA2D_SetMode(). */
70
71 uint32_t ColorMode; /*!< Specifies the color format of the output image.
72 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
73
74 This parameter can be modified afterwards using,
75 unitary function @ref LL_DMA2D_SetOutputColorMode(). */
76
77 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
78 - This parameter must be a number between:
79 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
80 - This parameter must be a number between:
81 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
82 - This parameter must be a number between:
83 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
84 - This parameter must be a number between:
85 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
86 - This parameter must be a number between:
87 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
88
89 This parameter can be modified afterwards,
90 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
91 function @ref LL_DMA2D_ConfigOutputColor(). */
92
93 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
94 - This parameter must be a number between:
95 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
96 - This parameter must be a number between:
97 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
98 - This parameter must be a number between:
99 Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
100 - This parameter must be a number between:
101 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
102 - This parameter must be a number between:
103 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
104
105 This parameter can be modified afterwards
106 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
107 function @ref LL_DMA2D_ConfigOutputColor(). */
108
109 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
110 - This parameter must be a number between:
111 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
112 - This parameter must be a number between:
113 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
114 - This parameter must be a number between:
115 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
116 - This parameter must be a number between:
117 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
118 - This parameter must be a number between:
119 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
120
121 This parameter can be modified afterwards
122 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
123 function @ref LL_DMA2D_ConfigOutputColor(). */
124
125 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
126 - This parameter must be a number between:
127 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
128 - This parameter must be a number between:
129 Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
130 - This parameter must be a number between:
131 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
132 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
133
134 This parameter can be modified afterwards using,
135 unitary function @ref LL_DMA2D_SetOutputColor() or configuration
136 function @ref LL_DMA2D_ConfigOutputColor(). */
137
138 uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
139 - This parameter must be a number between:
140 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
141
142 This parameter can be modified afterwards,
143 using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
144
145 uint32_t OutputSwapMode; /*!< Specifies the output swap mode color format of the output image.
146 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE.
147
148 This parameter can be modified afterwards,
149 using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */
150
151 uint32_t LineOffsetMode; /*!< Specifies the output line offset mode.
152 - This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE.
153
154 This parameter can be modified afterwards,
155 using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */
156
157 uint32_t LineOffset; /*!< Specifies the output line offset value.
158 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
159
160 This parameter can be modified afterwards,
161 using unitary function @ref LL_DMA2D_SetLineOffset(). */
162
163 uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
164 - This parameter must be a number between:
165 Min_Data = 0x0000 and Max_Data = 0xFFFF.
166
167 This parameter can be modified afterwards,
168 using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
169
170 uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred.
171 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
172
173 This parameter can be modified afterwards using,
174 unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
175
176 uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode.
177 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
178
179 This parameter can be modified afterwards,
180 using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
181
182 uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode.
183 - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP.
184
185 This parameter can be modified afterwards,
186 using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
187
188 } LL_DMA2D_InitTypeDef;
189
190 /**
191 * @brief LL DMA2D Layer Configuration Structure Definition
192 */
193 typedef struct
194 {
195 uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
196 - This parameter must be a number between:
197 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
198
199 This parameter can be modified afterwards using unitary functions
200 - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
201 - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
202
203 uint32_t LineOffset; /*!< Specifies the foreground or background line offset value.
204 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
205
206 This parameter can be modified afterwards using unitary functions
207 - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,
208 - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */
209
210 uint32_t ColorMode; /*!< Specifies the foreground or background color mode.
211 - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.
212
213 This parameter can be modified afterwards using unitary functions
214 - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,
215 - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */
216
217 uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode.
218 - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.
219
220 This parameter can be modified afterwards using unitary functions
221 - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
222 - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */
223
224 uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size.
225 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
226
227 This parameter can be modified afterwards using unitary functions
228 - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
229 - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */
230
231 uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode.
232 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.
233
234 This parameter can be modified afterwards using unitary functions
235 - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
236 - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */
237
238 uint32_t Alpha; /*!< Specifies the foreground or background Alpha value.
239 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
240
241 This parameter can be modified afterwards using unitary functions
242 - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,
243 - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */
244
245 uint32_t Blue; /*!< Specifies the foreground or background Blue color value.
246 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
247
248 This parameter can be modified afterwards using unitary functions
249 - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,
250 - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */
251
252 uint32_t Green; /*!< Specifies the foreground or background Green color value.
253 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
254
255 This parameter can be modified afterwards using unitary functions
256 - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,
257 - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */
258
259 uint32_t Red; /*!< Specifies the foreground or background Red color value.
260 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
261
262 This parameter can be modified afterwards using unitary functions
263 - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,
264 - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
265
266 uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
267 - This parameter must be a number between:
268 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
269
270 This parameter can be modified afterwards using unitary functions
271 - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
272 - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
273
274 uint32_t AlphaInversionMode; /*!< Specifies the foreground or background alpha inversion mode.
275 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
276
277 This parameter can be modified afterwards using unitary functions
278 - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer,
279 - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */
280
281 uint32_t RBSwapMode; /*!< Specifies the foreground or background Red Blue swap mode.
282 This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP .
283
284 This parameter can be modified afterwards using unitary functions
285 - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer,
286 - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */
287
288 uint32_t ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode
289 This parameter is applicable for foreground layer only.
290 This parameter can be one value of @ref DMA2D_LL_CHROMA_SUB_SAMPLING
291
292 This parameter can be modified afterwards using unitary functions
293 - @ref LL_DMA2D_FGND_SetChrSubSampling() for foreground layer. */
294
295 } LL_DMA2D_LayerCfgTypeDef;
296
297 /**
298 * @brief LL DMA2D Output Color Structure Definition
299 */
300 typedef struct
301 {
302 uint32_t ColorMode; /*!< Specifies the color format of the output image.
303 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
304
305 This parameter can be modified afterwards using
306 unitary function @ref LL_DMA2D_SetOutputColorMode(). */
307
308 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
309 - This parameter must be a number between:
310 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
311 - This parameter must be a number between:
312 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
313 - This parameter must be a number between:
314 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
315 - This parameter must be a number between:
316 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
317 - This parameter must be a number between:
318 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
319
320 This parameter can be modified afterwards using,
321 unitary function @ref LL_DMA2D_SetOutputColor() or configuration
322 function @ref LL_DMA2D_ConfigOutputColor(). */
323
324 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
325 - This parameter must be a number between:
326 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
327 - This parameter must be a number between
328 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
329 - This parameter must be a number between:
330 Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
331 - This parameter must be a number between:
332 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
333 - This parameter must be a number between:
334 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
335
336 This parameter can be modified afterwards,
337 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
338 function @ref LL_DMA2D_ConfigOutputColor(). */
339
340 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
341 - This parameter must be a number between:
342 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
343 - This parameter must be a number between:
344 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
345 - This parameter must be a number between:
346 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
347 - This parameter must be a number between:
348 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
349 - This parameter must be a number between:
350 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
351
352 This parameter can be modified afterwards,
353 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
354 function @ref LL_DMA2D_ConfigOutputColor(). */
355
356 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
357 - This parameter must be a number between:
358 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
359 - This parameter must be a number between:
360 Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
361 - This parameter must be a number between:
362 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
363 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
364
365 This parameter can be modified afterwards,
366 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
367 function @ref LL_DMA2D_ConfigOutputColor(). */
368
369 } LL_DMA2D_ColorTypeDef;
370
371 /**
372 * @}
373 */
374 #endif /* USE_FULL_LL_DRIVER */
375
376 /* Exported constants --------------------------------------------------------*/
377 /** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants
378 * @{
379 */
380
381 /** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines
382 * @brief Flags defines which can be used with LL_DMA2D_ReadReg function
383 * @{
384 */
385 #define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
386 #define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
387 #define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
388 #define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
389 #define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
390 #define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
391 /**
392 * @}
393 */
394
395 /** @defgroup DMA2D_LL_EC_IT IT Defines
396 * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions
397 * @{
398 */
399 #define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
400 #define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
401 #define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
402 #define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
403 #define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
404 #define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
405 /**
406 * @}
407 */
408
409 /** @defgroup DMA2D_LL_EC_MODE Mode
410 * @{
411 */
412 #define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
413 #define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
414 #define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
415 #define LL_DMA2D_MODE_R2M (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1) /*!< DMA2D register to memory transfer mode */
416 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color foreground */
417 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2) /*!< DMA2D memory to memory with blending transfer mode and fixed color background */
418 /**
419 * @}
420 */
421
422 /** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode
423 * @{
424 */
425 #define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
426 #define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */
427 #define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */
428 #define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */
429 #define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */
430 /**
431 * @}
432 */
433
434 /** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode
435 * @{
436 */
437 #define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
438 #define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */
439 #define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */
440 #define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */
441 #define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */
442 #define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */
443 #define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */
444 #define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */
445 #define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */
446 #define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */
447 #define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */
448 #define LL_DMA2D_INPUT_MODE_YCBCR (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< YCbCr */
449 /**
450 * @}
451 */
452
453 /** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode
454 * @{
455 */
456 #define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
457 #define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by
458 programmed alpha value */
459 #define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by
460 programmed alpha value with,
461 original alpha channel value */
462 /**
463 * @}
464 */
465
466 /** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode
467 * @{
468 */
469 #define LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U /*!< Regular order */
470 #define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB /*!< Bytes swapped two by two */
471 /**
472 * @}
473 */
474
475 /** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap
476 * @{
477 */
478 #define LL_DMA2D_RB_MODE_REGULAR 0x00000000U /*!< RGB or ARGB */
479 #define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS /*!< BGR or ABGR */
480 /**
481 * @}
482 */
483
484 /** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion
485 * @{
486 */
487 #define LL_DMA2D_ALPHA_REGULAR 0x00000000U /*!< Regular alpha */
488 #define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI /*!< Inverted alpha */
489 /**
490 * @}
491 */
492
493
494 /** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode
495 * @{
496 */
497 #define LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U /*!< Line offsets are expressed in pixels */
498 #define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM /*!< Line offsets are expressed in bytes */
499 /**
500 * @}
501 */
502
503 /** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
504 * @{
505 */
506 #define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
507 #define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */
508 /**
509 * @}
510 */
511
512 /** @defgroup DMA2D_LL_CHROMA_SUB_SAMPLING Chroma Sub Sampling
513 * @{
514 */
515 #define LL_DMA2D_CSS_444 0x00000000U /*!< No chroma sub-sampling 4:4:4 */
516 #define LL_DMA2D_CSS_422 DMA2D_FGPFCCR_CSS_0 /*!< chroma sub-sampling 4:2:2 */
517 #define LL_DMA2D_CSS_420 DMA2D_FGPFCCR_CSS_1 /*!< chroma sub-sampling 4:2:0 */
518 /**
519 * @}
520 */
521
522 /**
523 * @}
524 */
525
526 /* Exported macro ------------------------------------------------------------*/
527 /** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros
528 * @{
529 */
530
531 /** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros
532 * @{
533 */
534
535 /**
536 * @brief Write a value in DMA2D register.
537 * @param __INSTANCE__ DMA2D Instance
538 * @param __REG__ Register to be written
539 * @param __VALUE__ Value to be written in the register
540 * @retval None
541 */
542 #define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
543
544 /**
545 * @brief Read a value in DMA2D register.
546 * @param __INSTANCE__ DMA2D Instance
547 * @param __REG__ Register to be read
548 * @retval Register value
549 */
550 #define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
551 /**
552 * @}
553 */
554
555 /**
556 * @}
557 */
558
559 /* Exported functions --------------------------------------------------------*/
560 /** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions
561 * @{
562 */
563
564 /** @defgroup DMA2D_LL_EF_Configuration Configuration Functions
565 * @{
566 */
567
568 /**
569 * @brief Start a DMA2D transfer.
570 * @rmtoll CR START LL_DMA2D_Start
571 * @param DMA2Dx DMA2D Instance
572 * @retval None
573 */
LL_DMA2D_Start(DMA2D_TypeDef * DMA2Dx)574 __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
575 {
576 SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
577 }
578
579 /**
580 * @brief Indicate if a DMA2D transfer is ongoing.
581 * @rmtoll CR START LL_DMA2D_IsTransferOngoing
582 * @param DMA2Dx DMA2D Instance
583 * @retval State of bit (1 or 0).
584 */
LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef * DMA2Dx)585 __STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
586 {
587 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
588 }
589
590 /**
591 * @brief Suspend DMA2D transfer.
592 * @note This API can be used to suspend automatic foreground or background CLUT loading.
593 * @rmtoll CR SUSP LL_DMA2D_Suspend
594 * @param DMA2Dx DMA2D Instance
595 * @retval None
596 */
LL_DMA2D_Suspend(DMA2D_TypeDef * DMA2Dx)597 __STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
598 {
599 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
600 }
601
602 /**
603 * @brief Resume DMA2D transfer.
604 * @note This API can be used to resume automatic foreground or background CLUT loading.
605 * @rmtoll CR SUSP LL_DMA2D_Resume
606 * @param DMA2Dx DMA2D Instance
607 * @retval None
608 */
LL_DMA2D_Resume(DMA2D_TypeDef * DMA2Dx)609 __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
610 {
611 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
612 }
613
614 /**
615 * @brief Indicate if DMA2D transfer is suspended.
616 * @note This API can be used to indicate whether or not automatic foreground or
617 * background CLUT loading is suspended.
618 * @rmtoll CR SUSP LL_DMA2D_IsSuspended
619 * @param DMA2Dx DMA2D Instance
620 * @retval State of bit (1 or 0).
621 */
LL_DMA2D_IsSuspended(DMA2D_TypeDef * DMA2Dx)622 __STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
623 {
624 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
625 }
626
627 /**
628 * @brief Abort DMA2D transfer.
629 * @note This API can be used to abort automatic foreground or background CLUT loading.
630 * @rmtoll CR ABORT LL_DMA2D_Abort
631 * @param DMA2Dx DMA2D Instance
632 * @retval None
633 */
LL_DMA2D_Abort(DMA2D_TypeDef * DMA2Dx)634 __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
635 {
636 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
637 }
638
639 /**
640 * @brief Indicate if DMA2D transfer is aborted.
641 * @note This API can be used to indicate whether or not automatic foreground or
642 * background CLUT loading is aborted.
643 * @rmtoll CR ABORT LL_DMA2D_IsAborted
644 * @param DMA2Dx DMA2D Instance
645 * @retval State of bit (1 or 0).
646 */
LL_DMA2D_IsAborted(DMA2D_TypeDef * DMA2Dx)647 __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
648 {
649 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
650 }
651
652 /**
653 * @brief Set DMA2D mode.
654 * @rmtoll CR MODE LL_DMA2D_SetMode
655 * @param DMA2Dx DMA2D Instance
656 * @param Mode This parameter can be one of the following values:
657 * @arg @ref LL_DMA2D_MODE_M2M
658 * @arg @ref LL_DMA2D_MODE_M2M_PFC
659 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
660 * @arg @ref LL_DMA2D_MODE_R2M
661 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG
662 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG
663 * @retval None
664 */
LL_DMA2D_SetMode(DMA2D_TypeDef * DMA2Dx,uint32_t Mode)665 __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
666 {
667 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
668 }
669
670 /**
671 * @brief Return DMA2D mode
672 * @rmtoll CR MODE LL_DMA2D_GetMode
673 * @param DMA2Dx DMA2D Instance
674 * @retval Returned value can be one of the following values:
675 * @arg @ref LL_DMA2D_MODE_M2M
676 * @arg @ref LL_DMA2D_MODE_M2M_PFC
677 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
678 * @arg @ref LL_DMA2D_MODE_R2M
679 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG
680 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG
681 */
LL_DMA2D_GetMode(DMA2D_TypeDef * DMA2Dx)682 __STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)
683 {
684 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
685 }
686
687 /**
688 * @brief Set DMA2D output color mode.
689 * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode
690 * @param DMA2Dx DMA2D Instance
691 * @param ColorMode This parameter can be one of the following values:
692 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
693 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
694 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
695 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
696 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
697 * @retval None
698 */
LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)699 __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
700 {
701 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
702 }
703
704 /**
705 * @brief Return DMA2D output color mode.
706 * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode
707 * @param DMA2Dx DMA2D Instance
708 * @retval Returned value can be one of the following values:
709 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
710 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
711 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
712 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
713 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
714 */
LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef * DMA2Dx)715 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
716 {
717 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
718 }
719
720 /**
721 * @brief Set DMA2D output Red Blue swap mode.
722 * @rmtoll OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode
723 * @param DMA2Dx DMA2D Instance
724 * @param RBSwapMode This parameter can be one of the following values:
725 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
726 * @arg @ref LL_DMA2D_RB_MODE_SWAP
727 * @retval None
728 */
LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t RBSwapMode)729 __STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
730 {
731 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode);
732 }
733
734 /**
735 * @brief Return DMA2D output Red Blue swap mode.
736 * @rmtoll OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode
737 * @param DMA2Dx DMA2D Instance
738 * @retval Returned value can be one of the following values:
739 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
740 * @arg @ref LL_DMA2D_RB_MODE_SWAP
741 */
LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef * DMA2Dx)742 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx)
743 {
744 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS));
745 }
746
747 /**
748 * @brief Set DMA2D output alpha inversion mode.
749 * @rmtoll OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode
750 * @param DMA2Dx DMA2D Instance
751 * @param AlphaInversionMode This parameter can be one of the following values:
752 * @arg @ref LL_DMA2D_ALPHA_REGULAR
753 * @arg @ref LL_DMA2D_ALPHA_INVERTED
754 * @retval None
755 */
LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef * DMA2Dx,uint32_t AlphaInversionMode)756 __STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
757 {
758 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode);
759 }
760
761 /**
762 * @brief Return DMA2D output alpha inversion mode.
763 * @rmtoll OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode
764 * @param DMA2Dx DMA2D Instance
765 * @retval Returned value can be one of the following values:
766 * @arg @ref LL_DMA2D_ALPHA_REGULAR
767 * @arg @ref LL_DMA2D_ALPHA_INVERTED
768 */
LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef * DMA2Dx)769 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
770 {
771 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI));
772 }
773
774
775 /**
776 * @brief Set DMA2D output swap mode.
777 * @rmtoll OPFCCR SB LL_DMA2D_SetOutputSwapMode
778 * @param DMA2Dx DMA2D Instance
779 * @param OutputSwapMode This parameter can be one of the following values:
780 * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
781 * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
782 * @retval None
783 */
LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t OutputSwapMode)784 __STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode)
785 {
786 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode);
787 }
788
789 /**
790 * @brief Return DMA2D output swap mode.
791 * @rmtoll OPFCCR SB LL_DMA2D_GetOutputSwapMode
792 * @param DMA2Dx DMA2D Instance
793 * @retval Returned value can be one of the following values:
794 * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
795 * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
796 */
LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef * DMA2Dx)797 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx)
798 {
799 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB));
800 }
801
802 /**
803 * @brief Set DMA2D line offset mode.
804 * @rmtoll CR LOM LL_DMA2D_SetLineOffsetMode
805 * @param DMA2Dx DMA2D Instance
806 * @param LineOffsetMode This parameter can be one of the following values:
807 * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
808 * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
809 * @retval None
810 */
LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffsetMode)811 __STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode)
812 {
813 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode);
814 }
815
816 /**
817 * @brief Return DMA2D line offset mode.
818 * @rmtoll CR LOM LL_DMA2D_GetLineOffsetMode
819 * @param DMA2Dx DMA2D Instance
820 * @retval Returned value can be one of the following values:
821 * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
822 * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
823 */
LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef * DMA2Dx)824 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx)
825 {
826 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM));
827 }
828
829 /**
830 * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
831 * @rmtoll OOR LO LL_DMA2D_SetLineOffset
832 * @param DMA2Dx DMA2D Instance
833 * @param LineOffset Value between Min_Data=0 and Max_Data=0xFFFF
834 * @retval None
835 */
LL_DMA2D_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)836 __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
837 {
838 MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
839 }
840
841 /**
842 * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
843 * @rmtoll OOR LO LL_DMA2D_GetLineOffset
844 * @param DMA2Dx DMA2D Instance
845 * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF
846 */
LL_DMA2D_GetLineOffset(DMA2D_TypeDef * DMA2Dx)847 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
848 {
849 return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
850 }
851
852 /**
853 * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
854 * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines
855 * @param DMA2Dx DMA2D Instance
856 * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
857 * @retval None
858 */
LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef * DMA2Dx,uint32_t NbrOfPixelsPerLines)859 __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
860 {
861 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
862 }
863
864 /**
865 * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
866 * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines
867 * @param DMA2Dx DMA2D Instance
868 * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
869 */
LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef * DMA2Dx)870 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)
871 {
872 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
873 }
874
875 /**
876 * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
877 * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines
878 * @param DMA2Dx DMA2D Instance
879 * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
880 * @retval None
881 */
LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef * DMA2Dx,uint32_t NbrOfLines)882 __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
883 {
884 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
885 }
886
887 /**
888 * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
889 * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines
890 * @param DMA2Dx DMA2D Instance
891 * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
892 */
LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef * DMA2Dx)893 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)
894 {
895 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
896 }
897
898 /**
899 * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
900 * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr
901 * @param DMA2Dx DMA2D Instance
902 * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
903 * @retval None
904 */
LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t OutputMemoryAddress)905 __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
906 {
907 LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
908 }
909
910 /**
911 * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
912 * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr
913 * @param DMA2Dx DMA2D Instance
914 * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
915 */
LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef * DMA2Dx)916 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
917 {
918 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
919 }
920
921 /**
922 * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits).
923 * @note Output color format depends on output color mode, ARGB8888, RGB888,
924 * RGB565, ARGB1555 or ARGB4444.
925 * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting
926 * with respect to color mode is not done by the user code.
927 * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n
928 * OCOLR GREEN LL_DMA2D_SetOutputColor\n
929 * OCOLR RED LL_DMA2D_SetOutputColor\n
930 * OCOLR ALPHA LL_DMA2D_SetOutputColor
931 * @param DMA2Dx DMA2D Instance
932 * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF
933 * @retval None
934 */
LL_DMA2D_SetOutputColor(DMA2D_TypeDef * DMA2Dx,uint32_t OutputColor)935 __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
936 {
937 MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \
938 OutputColor);
939 }
940
941 /**
942 * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits).
943 * @note Alpha channel and red, green, blue color values must be retrieved from the returned
944 * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444)
945 * as set by @ref LL_DMA2D_SetOutputColorMode.
946 * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n
947 * OCOLR GREEN LL_DMA2D_GetOutputColor\n
948 * OCOLR RED LL_DMA2D_GetOutputColor\n
949 * OCOLR ALPHA LL_DMA2D_GetOutputColor
950 * @param DMA2Dx DMA2D Instance
951 * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
952 */
LL_DMA2D_GetOutputColor(DMA2D_TypeDef * DMA2Dx)953 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)
954 {
955 return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
956 (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
957 }
958
959 /**
960 * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
961 * @rmtoll LWR LW LL_DMA2D_SetLineWatermark
962 * @param DMA2Dx DMA2D Instance
963 * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF
964 * @retval None
965 */
LL_DMA2D_SetLineWatermark(DMA2D_TypeDef * DMA2Dx,uint32_t LineWatermark)966 __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
967 {
968 MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
969 }
970
971 /**
972 * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
973 * @rmtoll LWR LW LL_DMA2D_GetLineWatermark
974 * @param DMA2Dx DMA2D Instance
975 * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
976 */
LL_DMA2D_GetLineWatermark(DMA2D_TypeDef * DMA2Dx)977 __STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)
978 {
979 return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
980 }
981
982 /**
983 * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
984 * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime
985 * @param DMA2Dx DMA2D Instance
986 * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF
987 * @retval None
988 */
LL_DMA2D_SetDeadTime(DMA2D_TypeDef * DMA2Dx,uint32_t DeadTime)989 __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
990 {
991 MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
992 }
993
994 /**
995 * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
996 * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime
997 * @param DMA2Dx DMA2D Instance
998 * @retval Dead time value between Min_Data=0 and Max_Data=0xFF
999 */
LL_DMA2D_GetDeadTime(DMA2D_TypeDef * DMA2Dx)1000 __STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)
1001 {
1002 return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
1003 }
1004
1005 /**
1006 * @brief Enable DMA2D dead time functionality.
1007 * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime
1008 * @param DMA2Dx DMA2D Instance
1009 * @retval None
1010 */
LL_DMA2D_EnableDeadTime(DMA2D_TypeDef * DMA2Dx)1011 __STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
1012 {
1013 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
1014 }
1015
1016 /**
1017 * @brief Disable DMA2D dead time functionality.
1018 * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime
1019 * @param DMA2Dx DMA2D Instance
1020 * @retval None
1021 */
LL_DMA2D_DisableDeadTime(DMA2D_TypeDef * DMA2Dx)1022 __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
1023 {
1024 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
1025 }
1026
1027 /**
1028 * @brief Indicate if DMA2D dead time functionality is enabled.
1029 * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime
1030 * @param DMA2Dx DMA2D Instance
1031 * @retval State of bit (1 or 0).
1032 */
LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef * DMA2Dx)1033 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
1034 {
1035 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
1036 }
1037
1038 /** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
1039 * @{
1040 */
1041
1042 /**
1043 * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
1044 * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr
1045 * @param DMA2Dx DMA2D Instance
1046 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1047 * @retval None
1048 */
LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t MemoryAddress)1049 __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1050 {
1051 LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
1052 }
1053
1054 /**
1055 * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
1056 * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr
1057 * @param DMA2Dx DMA2D Instance
1058 * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1059 */
LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef * DMA2Dx)1060 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
1061 {
1062 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
1063 }
1064
1065 /**
1066 * @brief Enable DMA2D foreground CLUT loading.
1067 * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad
1068 * @param DMA2Dx DMA2D Instance
1069 * @retval None
1070 */
LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef * DMA2Dx)1071 __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1072 {
1073 SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
1074 }
1075
1076 /**
1077 * @brief Indicate if DMA2D foreground CLUT loading is enabled.
1078 * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad
1079 * @param DMA2Dx DMA2D Instance
1080 * @retval State of bit (1 or 0).
1081 */
LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef * DMA2Dx)1082 __STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1083 {
1084 return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
1085 }
1086
1087 /**
1088 * @brief Set DMA2D foreground color mode.
1089 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode
1090 * @param DMA2Dx DMA2D Instance
1091 * @param ColorMode This parameter can be one of the following values:
1092 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1093 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1094 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1095 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1096 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1097 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1098 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1099 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1100 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1101 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1102 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1103 * @retval None
1104 */
LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)1105 __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1106 {
1107 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
1108 }
1109
1110 /**
1111 * @brief Return DMA2D foreground color mode.
1112 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode
1113 * @param DMA2Dx DMA2D Instance
1114 * @retval Returned value can be one of the following values:
1115 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1116 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1117 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1118 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1119 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1120 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1121 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1122 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1123 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1124 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1125 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1126 */
LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef * DMA2Dx)1127 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
1128 {
1129 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
1130 }
1131
1132 /**
1133 * @brief Set DMA2D foreground alpha mode.
1134 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode
1135 * @param DMA2Dx DMA2D Instance
1136 * @param AphaMode This parameter can be one of the following values:
1137 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1138 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1139 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1140 * @retval None
1141 */
LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef * DMA2Dx,uint32_t AphaMode)1142 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1143 {
1144 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
1145 }
1146
1147 /**
1148 * @brief Return DMA2D foreground alpha mode.
1149 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode
1150 * @param DMA2Dx DMA2D Instance
1151 * @retval Returned value can be one of the following values:
1152 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1153 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1154 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1155 */
LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef * DMA2Dx)1156 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
1157 {
1158 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
1159 }
1160
1161 /**
1162 * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
1163 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha
1164 * @param DMA2Dx DMA2D Instance
1165 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1166 * @retval None
1167 */
LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef * DMA2Dx,uint32_t Alpha)1168 __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1169 {
1170 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
1171 }
1172
1173 /**
1174 * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
1175 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha
1176 * @param DMA2Dx DMA2D Instance
1177 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1178 */
LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef * DMA2Dx)1179 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
1180 {
1181 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
1182 }
1183
1184 /**
1185 * @brief Set DMA2D foreground Red Blue swap mode.
1186 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode
1187 * @param DMA2Dx DMA2D Instance
1188 * @param RBSwapMode This parameter can be one of the following values:
1189 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1190 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1191 * @retval None
1192 */
LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t RBSwapMode)1193 __STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1194 {
1195 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode);
1196 }
1197
1198 /**
1199 * @brief Return DMA2D foreground Red Blue swap mode.
1200 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode
1201 * @param DMA2Dx DMA2D Instance
1202 * @retval Returned value can be one of the following values:
1203 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1204 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1205 */
LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef * DMA2Dx)1206 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
1207 {
1208 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS));
1209 }
1210
1211 /**
1212 * @brief Set DMA2D foreground alpha inversion mode.
1213 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode
1214 * @param DMA2Dx DMA2D Instance
1215 * @param AlphaInversionMode This parameter can be one of the following values:
1216 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1217 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1218 * @retval None
1219 */
LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef * DMA2Dx,uint32_t AlphaInversionMode)1220 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1221 {
1222 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode);
1223 }
1224
1225 /**
1226 * @brief Return DMA2D foreground alpha inversion mode.
1227 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode
1228 * @param DMA2Dx DMA2D Instance
1229 * @retval Returned value can be one of the following values:
1230 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1231 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1232 */
LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef * DMA2Dx)1233 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
1234 {
1235 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI));
1236 }
1237
1238 /**
1239 * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1240 * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset
1241 * @param DMA2Dx DMA2D Instance
1242 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1243 * @retval None
1244 */
LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)1245 __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1246 {
1247 MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
1248 }
1249
1250 /**
1251 * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1252 * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset
1253 * @param DMA2Dx DMA2D Instance
1254 * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
1255 */
LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef * DMA2Dx)1256 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1257 {
1258 return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
1259 }
1260
1261 /**
1262 * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
1263 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor
1264 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor
1265 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor
1266 * @param DMA2Dx DMA2D Instance
1267 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1268 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1269 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1270 * @retval None
1271 */
LL_DMA2D_FGND_SetColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red,uint32_t Green,uint32_t Blue)1272 __STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1273 {
1274 MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
1275 ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
1276 }
1277
1278 /**
1279 * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1280 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor
1281 * @param DMA2Dx DMA2D Instance
1282 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1283 * @retval None
1284 */
LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red)1285 __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1286 {
1287 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
1288 }
1289
1290 /**
1291 * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1292 * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor
1293 * @param DMA2Dx DMA2D Instance
1294 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1295 */
LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef * DMA2Dx)1296 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1297 {
1298 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
1299 }
1300
1301 /**
1302 * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1303 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor
1304 * @param DMA2Dx DMA2D Instance
1305 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1306 * @retval None
1307 */
LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef * DMA2Dx,uint32_t Green)1308 __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1309 {
1310 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
1311 }
1312
1313 /**
1314 * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1315 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor
1316 * @param DMA2Dx DMA2D Instance
1317 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1318 */
LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef * DMA2Dx)1319 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1320 {
1321 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
1322 }
1323
1324 /**
1325 * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1326 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor
1327 * @param DMA2Dx DMA2D Instance
1328 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1329 * @retval None
1330 */
LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef * DMA2Dx,uint32_t Blue)1331 __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1332 {
1333 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
1334 }
1335
1336 /**
1337 * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1338 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor
1339 * @param DMA2Dx DMA2D Instance
1340 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1341 */
LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef * DMA2Dx)1342 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1343 {
1344 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
1345 }
1346
1347 /**
1348 * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1349 * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr
1350 * @param DMA2Dx DMA2D Instance
1351 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1352 * @retval None
1353 */
LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTMemoryAddress)1354 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1355 {
1356 LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
1357 }
1358
1359 /**
1360 * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1361 * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr
1362 * @param DMA2Dx DMA2D Instance
1363 * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1364 */
LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx)1365 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1366 {
1367 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
1368 }
1369
1370 /**
1371 * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1372 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize
1373 * @param DMA2Dx DMA2D Instance
1374 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1375 * @retval None
1376 */
LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTSize)1377 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1378 {
1379 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
1380 }
1381
1382 /**
1383 * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1384 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize
1385 * @param DMA2Dx DMA2D Instance
1386 * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
1387 */
LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef * DMA2Dx)1388 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1389 {
1390 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
1391 }
1392
1393 /**
1394 * @brief Set DMA2D foreground CLUT color mode.
1395 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode
1396 * @param DMA2Dx DMA2D Instance
1397 * @param CLUTColorMode This parameter can be one of the following values:
1398 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1399 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1400 * @retval None
1401 */
LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTColorMode)1402 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1403 {
1404 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
1405 }
1406
1407 /**
1408 * @brief Return DMA2D foreground CLUT color mode.
1409 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode
1410 * @param DMA2Dx DMA2D Instance
1411 * @retval Returned value can be one of the following values:
1412 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1413 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1414 */
LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef * DMA2Dx)1415 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1416 {
1417 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
1418 }
1419
1420 /**
1421 * @brief Set DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode).
1422 * @rmtoll FGPFCCR CSS LL_DMA2D_FGND_SetChrSubSampling
1423 * @param DMA2Dx DMA2D Instance
1424 * @param ChromaSubSampling This parameter can be one of the following values:
1425 * @arg @ref LL_DMA2D_CSS_444
1426 * @arg @ref LL_DMA2D_CSS_422
1427 * @arg @ref LL_DMA2D_CSS_420
1428 * @retval None
1429 */
LL_DMA2D_FGND_SetChrSubSampling(DMA2D_TypeDef * DMA2Dx,uint32_t ChromaSubSampling)1430 __STATIC_INLINE void LL_DMA2D_FGND_SetChrSubSampling(DMA2D_TypeDef *DMA2Dx, uint32_t ChromaSubSampling)
1431 {
1432 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS, ChromaSubSampling);
1433 }
1434
1435 /**
1436 * @brief Return DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode).
1437 * @rmtoll FGPFCCR CSS LL_DMA2D_FGND_GetChrSubSampling
1438 * @param DMA2Dx DMA2D Instance
1439 * @retval Returned value can be one of the following values:
1440 * @arg @ref LL_DMA2D_CSS_444
1441 * @arg @ref LL_DMA2D_CSS_422
1442 * @arg @ref LL_DMA2D_CSS_420
1443 */
LL_DMA2D_FGND_GetChrSubSampling(DMA2D_TypeDef * DMA2Dx)1444 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(DMA2D_TypeDef *DMA2Dx)
1445 {
1446 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS));
1447 }
1448 /**
1449 * @}
1450 */
1451
1452 /** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions
1453 * @{
1454 */
1455
1456 /**
1457 * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1458 * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr
1459 * @param DMA2Dx DMA2D Instance
1460 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1461 * @retval None
1462 */
LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t MemoryAddress)1463 __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1464 {
1465 LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
1466 }
1467
1468 /**
1469 * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1470 * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr
1471 * @param DMA2Dx DMA2D Instance
1472 * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1473 */
LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef * DMA2Dx)1474 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
1475 {
1476 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
1477 }
1478
1479 /**
1480 * @brief Enable DMA2D background CLUT loading.
1481 * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad
1482 * @param DMA2Dx DMA2D Instance
1483 * @retval None
1484 */
LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef * DMA2Dx)1485 __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1486 {
1487 SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
1488 }
1489
1490 /**
1491 * @brief Indicate if DMA2D background CLUT loading is enabled.
1492 * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad
1493 * @param DMA2Dx DMA2D Instance
1494 * @retval State of bit (1 or 0).
1495 */
LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef * DMA2Dx)1496 __STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1497 {
1498 return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
1499 }
1500
1501 /**
1502 * @brief Set DMA2D background color mode.
1503 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode
1504 * @param DMA2Dx DMA2D Instance
1505 * @param ColorMode This parameter can be one of the following values:
1506 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1507 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1508 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1509 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1510 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1511 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1512 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1513 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1514 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1515 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1516 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1517 * @retval None
1518 */
LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)1519 __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1520 {
1521 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
1522 }
1523
1524 /**
1525 * @brief Return DMA2D background color mode.
1526 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode
1527 * @param DMA2Dx DMA2D Instance
1528 * @retval Returned value can be one of the following values:
1529 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1530 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1531 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1532 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1533 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1534 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1535 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1536 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1537 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1538 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1539 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1540 */
LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef * DMA2Dx)1541 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
1542 {
1543 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
1544 }
1545
1546 /**
1547 * @brief Set DMA2D background alpha mode.
1548 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode
1549 * @param DMA2Dx DMA2D Instance
1550 * @param AphaMode This parameter can be one of the following values:
1551 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1552 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1553 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1554 * @retval None
1555 */
LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef * DMA2Dx,uint32_t AphaMode)1556 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1557 {
1558 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
1559 }
1560
1561 /**
1562 * @brief Return DMA2D background alpha mode.
1563 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode
1564 * @param DMA2Dx DMA2D Instance
1565 * @retval Returned value can be one of the following values:
1566 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1567 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1568 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1569 */
LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef * DMA2Dx)1570 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
1571 {
1572 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
1573 }
1574
1575 /**
1576 * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1577 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha
1578 * @param DMA2Dx DMA2D Instance
1579 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1580 * @retval None
1581 */
LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef * DMA2Dx,uint32_t Alpha)1582 __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1583 {
1584 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
1585 }
1586
1587 /**
1588 * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1589 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha
1590 * @param DMA2Dx DMA2D Instance
1591 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1592 */
LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef * DMA2Dx)1593 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
1594 {
1595 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
1596 }
1597
1598 /**
1599 * @brief Set DMA2D background Red Blue swap mode.
1600 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode
1601 * @param DMA2Dx DMA2D Instance
1602 * @param RBSwapMode This parameter can be one of the following values:
1603 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1604 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1605 * @retval None
1606 */
LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t RBSwapMode)1607 __STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1608 {
1609 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode);
1610 }
1611
1612 /**
1613 * @brief Return DMA2D background Red Blue swap mode.
1614 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode
1615 * @param DMA2Dx DMA2D Instance
1616 * @retval Returned value can be one of the following values:
1617 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1618 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1619 */
LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef * DMA2Dx)1620 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
1621 {
1622 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS));
1623 }
1624
1625 /**
1626 * @brief Set DMA2D background alpha inversion mode.
1627 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode
1628 * @param DMA2Dx DMA2D Instance
1629 * @param AlphaInversionMode This parameter can be one of the following values:
1630 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1631 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1632 * @retval None
1633 */
LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef * DMA2Dx,uint32_t AlphaInversionMode)1634 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1635 {
1636 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode);
1637 }
1638
1639 /**
1640 * @brief Return DMA2D background alpha inversion mode.
1641 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode
1642 * @param DMA2Dx DMA2D Instance
1643 * @retval Returned value can be one of the following values:
1644 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1645 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1646 */
LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef * DMA2Dx)1647 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
1648 {
1649 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI));
1650 }
1651
1652 /**
1653 * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1654 * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset
1655 * @param DMA2Dx DMA2D Instance
1656 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1657 * @retval None
1658 */
LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)1659 __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1660 {
1661 MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
1662 }
1663
1664 /**
1665 * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1666 * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset
1667 * @param DMA2Dx DMA2D Instance
1668 * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
1669 */
LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef * DMA2Dx)1670 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1671 {
1672 return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
1673 }
1674
1675 /**
1676 * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
1677 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor
1678 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor
1679 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor
1680 * @param DMA2Dx DMA2D Instance
1681 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1682 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1683 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1684 * @retval None
1685 */
LL_DMA2D_BGND_SetColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red,uint32_t Green,uint32_t Blue)1686 __STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1687 {
1688 MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
1689 ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
1690 }
1691
1692 /**
1693 * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1694 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor
1695 * @param DMA2Dx DMA2D Instance
1696 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1697 * @retval None
1698 */
LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red)1699 __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1700 {
1701 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
1702 }
1703
1704 /**
1705 * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1706 * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor
1707 * @param DMA2Dx DMA2D Instance
1708 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1709 */
LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef * DMA2Dx)1710 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1711 {
1712 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
1713 }
1714
1715 /**
1716 * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1717 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor
1718 * @param DMA2Dx DMA2D Instance
1719 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1720 * @retval None
1721 */
LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef * DMA2Dx,uint32_t Green)1722 __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1723 {
1724 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
1725 }
1726
1727 /**
1728 * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1729 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor
1730 * @param DMA2Dx DMA2D Instance
1731 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1732 */
LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef * DMA2Dx)1733 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1734 {
1735 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
1736 }
1737
1738 /**
1739 * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1740 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor
1741 * @param DMA2Dx DMA2D Instance
1742 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1743 * @retval None
1744 */
LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef * DMA2Dx,uint32_t Blue)1745 __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1746 {
1747 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
1748 }
1749
1750 /**
1751 * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1752 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor
1753 * @param DMA2Dx DMA2D Instance
1754 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1755 */
LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef * DMA2Dx)1756 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1757 {
1758 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
1759 }
1760
1761 /**
1762 * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1763 * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr
1764 * @param DMA2Dx DMA2D Instance
1765 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1766 * @retval None
1767 */
LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTMemoryAddress)1768 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1769 {
1770 LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
1771 }
1772
1773 /**
1774 * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1775 * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr
1776 * @param DMA2Dx DMA2D Instance
1777 * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1778 */
LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx)1779 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1780 {
1781 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
1782 }
1783
1784 /**
1785 * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1786 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize
1787 * @param DMA2Dx DMA2D Instance
1788 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1789 * @retval None
1790 */
LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTSize)1791 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1792 {
1793 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
1794 }
1795
1796 /**
1797 * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1798 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize
1799 * @param DMA2Dx DMA2D Instance
1800 * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
1801 */
LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef * DMA2Dx)1802 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1803 {
1804 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
1805 }
1806
1807 /**
1808 * @brief Set DMA2D background CLUT color mode.
1809 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode
1810 * @param DMA2Dx DMA2D Instance
1811 * @param CLUTColorMode This parameter can be one of the following values:
1812 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1813 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1814 * @retval None
1815 */
LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTColorMode)1816 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1817 {
1818 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
1819 }
1820
1821 /**
1822 * @brief Return DMA2D background CLUT color mode.
1823 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode
1824 * @param DMA2Dx DMA2D Instance
1825 * @retval Returned value can be one of the following values:
1826 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1827 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1828 */
LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef * DMA2Dx)1829 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1830 {
1831 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
1832 }
1833
1834 /**
1835 * @}
1836 */
1837
1838 /**
1839 * @}
1840 */
1841
1842
1843 /** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management
1844 * @{
1845 */
1846
1847 /**
1848 * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not
1849 * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE
1850 * @param DMA2Dx DMA2D Instance
1851 * @retval State of bit (1 or 0).
1852 */
LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef * DMA2Dx)1853 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
1854 {
1855 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
1856 }
1857
1858 /**
1859 * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not
1860 * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC
1861 * @param DMA2Dx DMA2D Instance
1862 * @retval State of bit (1 or 0).
1863 */
LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef * DMA2Dx)1864 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1865 {
1866 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
1867 }
1868
1869 /**
1870 * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not
1871 * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE
1872 * @param DMA2Dx DMA2D Instance
1873 * @retval State of bit (1 or 0).
1874 */
LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef * DMA2Dx)1875 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1876 {
1877 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
1878 }
1879
1880 /**
1881 * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not
1882 * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW
1883 * @param DMA2Dx DMA2D Instance
1884 * @retval State of bit (1 or 0).
1885 */
LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef * DMA2Dx)1886 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
1887 {
1888 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
1889 }
1890
1891 /**
1892 * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not
1893 * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC
1894 * @param DMA2Dx DMA2D Instance
1895 * @retval State of bit (1 or 0).
1896 */
LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef * DMA2Dx)1897 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
1898 {
1899 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
1900 }
1901
1902 /**
1903 * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not
1904 * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE
1905 * @param DMA2Dx DMA2D Instance
1906 * @retval State of bit (1 or 0).
1907 */
LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef * DMA2Dx)1908 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
1909 {
1910 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
1911 }
1912
1913 /**
1914 * @brief Clear DMA2D Configuration Error Interrupt Flag
1915 * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE
1916 * @param DMA2Dx DMA2D Instance
1917 * @retval None
1918 */
LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef * DMA2Dx)1919 __STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
1920 {
1921 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
1922 }
1923
1924 /**
1925 * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag
1926 * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC
1927 * @param DMA2Dx DMA2D Instance
1928 * @retval None
1929 */
LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef * DMA2Dx)1930 __STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1931 {
1932 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
1933 }
1934
1935 /**
1936 * @brief Clear DMA2D CLUT Access Error Interrupt Flag
1937 * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE
1938 * @param DMA2Dx DMA2D Instance
1939 * @retval None
1940 */
LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef * DMA2Dx)1941 __STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1942 {
1943 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
1944 }
1945
1946 /**
1947 * @brief Clear DMA2D Transfer Watermark Interrupt Flag
1948 * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW
1949 * @param DMA2Dx DMA2D Instance
1950 * @retval None
1951 */
LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef * DMA2Dx)1952 __STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
1953 {
1954 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
1955 }
1956
1957 /**
1958 * @brief Clear DMA2D Transfer Complete Interrupt Flag
1959 * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC
1960 * @param DMA2Dx DMA2D Instance
1961 * @retval None
1962 */
LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef * DMA2Dx)1963 __STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
1964 {
1965 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
1966 }
1967
1968 /**
1969 * @brief Clear DMA2D Transfer Error Interrupt Flag
1970 * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE
1971 * @param DMA2Dx DMA2D Instance
1972 * @retval None
1973 */
LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef * DMA2Dx)1974 __STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
1975 {
1976 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
1977 }
1978
1979 /**
1980 * @}
1981 */
1982
1983 /** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management
1984 * @{
1985 */
1986
1987 /**
1988 * @brief Enable Configuration Error Interrupt
1989 * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE
1990 * @param DMA2Dx DMA2D Instance
1991 * @retval None
1992 */
LL_DMA2D_EnableIT_CE(DMA2D_TypeDef * DMA2Dx)1993 __STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
1994 {
1995 SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
1996 }
1997
1998 /**
1999 * @brief Enable CLUT Transfer Complete Interrupt
2000 * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC
2001 * @param DMA2Dx DMA2D Instance
2002 * @retval None
2003 */
LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef * DMA2Dx)2004 __STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
2005 {
2006 SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
2007 }
2008
2009 /**
2010 * @brief Enable CLUT Access Error Interrupt
2011 * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE
2012 * @param DMA2Dx DMA2D Instance
2013 * @retval None
2014 */
LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef * DMA2Dx)2015 __STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
2016 {
2017 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
2018 }
2019
2020 /**
2021 * @brief Enable Transfer Watermark Interrupt
2022 * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW
2023 * @param DMA2Dx DMA2D Instance
2024 * @retval None
2025 */
LL_DMA2D_EnableIT_TW(DMA2D_TypeDef * DMA2Dx)2026 __STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
2027 {
2028 SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
2029 }
2030
2031 /**
2032 * @brief Enable Transfer Complete Interrupt
2033 * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC
2034 * @param DMA2Dx DMA2D Instance
2035 * @retval None
2036 */
LL_DMA2D_EnableIT_TC(DMA2D_TypeDef * DMA2Dx)2037 __STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
2038 {
2039 SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
2040 }
2041
2042 /**
2043 * @brief Enable Transfer Error Interrupt
2044 * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE
2045 * @param DMA2Dx DMA2D Instance
2046 * @retval None
2047 */
LL_DMA2D_EnableIT_TE(DMA2D_TypeDef * DMA2Dx)2048 __STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
2049 {
2050 SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
2051 }
2052
2053 /**
2054 * @brief Disable Configuration Error Interrupt
2055 * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE
2056 * @param DMA2Dx DMA2D Instance
2057 * @retval None
2058 */
LL_DMA2D_DisableIT_CE(DMA2D_TypeDef * DMA2Dx)2059 __STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
2060 {
2061 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
2062 }
2063
2064 /**
2065 * @brief Disable CLUT Transfer Complete Interrupt
2066 * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC
2067 * @param DMA2Dx DMA2D Instance
2068 * @retval None
2069 */
LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef * DMA2Dx)2070 __STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
2071 {
2072 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
2073 }
2074
2075 /**
2076 * @brief Disable CLUT Access Error Interrupt
2077 * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE
2078 * @param DMA2Dx DMA2D Instance
2079 * @retval None
2080 */
LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef * DMA2Dx)2081 __STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
2082 {
2083 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
2084 }
2085
2086 /**
2087 * @brief Disable Transfer Watermark Interrupt
2088 * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW
2089 * @param DMA2Dx DMA2D Instance
2090 * @retval None
2091 */
LL_DMA2D_DisableIT_TW(DMA2D_TypeDef * DMA2Dx)2092 __STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
2093 {
2094 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
2095 }
2096
2097 /**
2098 * @brief Disable Transfer Complete Interrupt
2099 * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC
2100 * @param DMA2Dx DMA2D Instance
2101 * @retval None
2102 */
LL_DMA2D_DisableIT_TC(DMA2D_TypeDef * DMA2Dx)2103 __STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
2104 {
2105 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
2106 }
2107
2108 /**
2109 * @brief Disable Transfer Error Interrupt
2110 * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE
2111 * @param DMA2Dx DMA2D Instance
2112 * @retval None
2113 */
LL_DMA2D_DisableIT_TE(DMA2D_TypeDef * DMA2Dx)2114 __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
2115 {
2116 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
2117 }
2118
2119 /**
2120 * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
2121 * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE
2122 * @param DMA2Dx DMA2D Instance
2123 * @retval State of bit (1 or 0).
2124 */
LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef * DMA2Dx)2125 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
2126 {
2127 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
2128 }
2129
2130 /**
2131 * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
2132 * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC
2133 * @param DMA2Dx DMA2D Instance
2134 * @retval State of bit (1 or 0).
2135 */
LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef * DMA2Dx)2136 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
2137 {
2138 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
2139 }
2140
2141 /**
2142 * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
2143 * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE
2144 * @param DMA2Dx DMA2D Instance
2145 * @retval State of bit (1 or 0).
2146 */
LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef * DMA2Dx)2147 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
2148 {
2149 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
2150 }
2151
2152 /**
2153 * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
2154 * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW
2155 * @param DMA2Dx DMA2D Instance
2156 * @retval State of bit (1 or 0).
2157 */
LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef * DMA2Dx)2158 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
2159 {
2160 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
2161 }
2162
2163 /**
2164 * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
2165 * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC
2166 * @param DMA2Dx DMA2D Instance
2167 * @retval State of bit (1 or 0).
2168 */
LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef * DMA2Dx)2169 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
2170 {
2171 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
2172 }
2173
2174 /**
2175 * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
2176 * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE
2177 * @param DMA2Dx DMA2D Instance
2178 * @retval State of bit (1 or 0).
2179 */
LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef * DMA2Dx)2180 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
2181 {
2182 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
2183 }
2184
2185
2186
2187 /**
2188 * @}
2189 */
2190
2191 #if defined(USE_FULL_LL_DRIVER)
2192 /** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
2193 * @{
2194 */
2195
2196 ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx);
2197 ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2198 void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2199 void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
2200 void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
2201 void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
2202 uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2203 uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2204 uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2205 uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2206 void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
2207
2208 /**
2209 * @}
2210 */
2211 #endif /* USE_FULL_LL_DRIVER */
2212
2213 /**
2214 * @}
2215 */
2216
2217 /**
2218 * @}
2219 */
2220
2221 #endif /* defined (DMA2D) */
2222
2223 /**
2224 * @}
2225 */
2226
2227 #ifdef __cplusplus
2228 }
2229 #endif
2230
2231 #endif /* STM32H7xx_LL_DMA2D_H */
2232
