1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7xx_LL_DMA_H
21 #define STM32H7xx_LL_DMA_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7xx.h"
29 #include "stm32h7xx_ll_dmamux.h"
30
31 /** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMA1) || defined (DMA2)
36
37 /** @defgroup DMA_LL DMA
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
44 * @{
45 */
46 /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
47 static const uint8_t LL_DMA_STR_OFFSET_TAB[] =
48 {
49 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
55 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
56 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
57 };
58
59
60 /**
61 * @}
62 */
63
64 /* Private macros ------------------------------------------------------------*/
65 /** @defgroup DMA_LL_Private_Macros DMA LL Private Macros
66 * @{
67 */
68 /**
69 * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel
70 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
71 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
72 * @param __DMA_INSTANCE__ DMAx
73 * @retval Channel_Offset (LL_DMAMUX_CHANNEL_8 or 0).
74 */
75 #define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \
76 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL)
77 /**
78 * @}
79 */
80
81 /* Exported types ------------------------------------------------------------*/
82 #if defined(USE_FULL_LL_DRIVER)
83 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
84 * @{
85 */
86 typedef struct
87 {
88 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
89 or as Source base address in case of memory to memory transfer direction.
90
91 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
92
93 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
94 or as Destination base address in case of memory to memory transfer direction.
95
96 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
97
98 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
99 from memory to memory or from peripheral to memory.
100 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
101
102 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
103
104 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
105 This parameter can be a value of @ref DMA_LL_EC_MODE
106 @note The circular buffer mode cannot be used if the memory to memory
107 data transfer direction is configured on the selected Stream
108
109 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
110
111 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
112 is incremented or not.
113 This parameter can be a value of @ref DMA_LL_EC_PERIPH
114
115 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
116
117 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
118 is incremented or not.
119 This parameter can be a value of @ref DMA_LL_EC_MEMORY
120
121 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
122
123 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
124 in case of memory to memory transfer direction.
125 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
126
127 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
128
129 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
130 in case of memory to memory transfer direction.
131 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
132
133 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
134
135 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
136 The data unit is equal to the source buffer configuration set in PeripheralSize
137 or MemorySize parameters depending in the transfer direction.
138 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
139
140 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
141
142 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
143 This parameter can be a value of @ref DMAMUX1_Request_selection
144
145 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
146
147 uint32_t Priority; /*!< Specifies the channel priority level.
148 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
149
150 This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
151
152 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
153 This parameter can be a value of @ref DMA_LL_FIFOMODE
154 @note The Direct mode (FIFO mode disabled) cannot be used if the
155 memory-to-memory data transfer is configured on the selected stream
156
157 This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
158
159 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
160 This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
161
162 This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
163
164 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
165 It specifies the amount of data to be transferred in a single non interruptible
166 transaction.
167 This parameter can be a value of @ref DMA_LL_EC_MBURST
168 @note The burst mode is possible only if the address Increment mode is enabled.
169
170 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
171
172 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
173 It specifies the amount of data to be transferred in a single non interruptible
174 transaction.
175 This parameter can be a value of @ref DMA_LL_EC_PBURST
176 @note The burst mode is possible only if the address Increment mode is enabled.
177
178 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
179
180 } LL_DMA_InitTypeDef;
181 /**
182 * @}
183 */
184 #endif /*USE_FULL_LL_DRIVER*/
185 /* Exported constants --------------------------------------------------------*/
186 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
187 * @{
188 */
189
190 /** @defgroup DMA_LL_EC_STREAM STREAM
191 * @{
192 */
193 #define LL_DMA_STREAM_0 0x00000000U
194 #define LL_DMA_STREAM_1 0x00000001U
195 #define LL_DMA_STREAM_2 0x00000002U
196 #define LL_DMA_STREAM_3 0x00000003U
197 #define LL_DMA_STREAM_4 0x00000004U
198 #define LL_DMA_STREAM_5 0x00000005U
199 #define LL_DMA_STREAM_6 0x00000006U
200 #define LL_DMA_STREAM_7 0x00000007U
201 #define LL_DMA_STREAM_ALL 0xFFFF0000U
202 /**
203 * @}
204 */
205
206
207 /** @defgroup DMA_LL_EC_DIRECTION DIRECTION
208 * @{
209 */
210 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
211 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */
212 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */
213 /**
214 * @}
215 */
216
217 /** @defgroup DMA_LL_EC_MODE MODE
218 * @{
219 */
220 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
221 #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */
222 #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */
223 /**
224 * @}
225 */
226
227 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
228 * @{
229 */
230 #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */
231 #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */
232 /**
233 * @}
234 */
235
236 /** @defgroup DMA_LL_EC_PERIPH PERIPH
237 * @{
238 */
239 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
240 #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */
241 /**
242 * @}
243 */
244
245 /** @defgroup DMA_LL_EC_MEMORY MEMORY
246 * @{
247 */
248 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
249 #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */
250 /**
251 * @}
252 */
253
254 /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
255 * @{
256 */
257 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
258 #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
259 #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */
260 /**
261 * @}
262 */
263
264 /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
265 * @{
266 */
267 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
268 #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
269 #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */
270 /**
271 * @}
272 */
273
274 /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
275 * @{
276 */
277 #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */
278 #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
279 /**
280 * @}
281 */
282
283 /** @defgroup DMA_LL_EC_PRIORITY PRIORITY
284 * @{
285 */
286 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
287 #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */
288 #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */
289 #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */
290 /**
291 * @}
292 */
293
294
295 /** @defgroup DMA_LL_EC_MBURST MBURST
296 * @{
297 */
298 #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */
299 #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */
300 #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */
301 #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
302 /**
303 * @}
304 */
305
306 /** @defgroup DMA_LL_EC_PBURST PBURST
307 * @{
308 */
309 #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */
310 #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */
311 #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */
312 #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
313 /**
314 * @}
315 */
316
317 /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
318 * @{
319 */
320 #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */
321 #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */
322 /**
323 * @}
324 */
325
326 /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
327 * @{
328 */
329 #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */
330 #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */
331 #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */
332 #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */
333 #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */
334 #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */
335 /**
336 * @}
337 */
338
339 /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
340 * @{
341 */
342 #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */
343 #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */
344 #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */
345 #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */
346 /**
347 * @}
348 */
349
350 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
351 * @{
352 */
353 #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
354 #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
355 /**
356 * @}
357 */
358
359 /**
360 * @}
361 */
362
363 /* Exported macro ------------------------------------------------------------*/
364 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
365 * @{
366 */
367
368 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
369 * @{
370 */
371 /**
372 * @brief Write a value in DMA register
373 * @param __INSTANCE__ DMA Instance
374 * @param __REG__ Register to be written
375 * @param __VALUE__ Value to be written in the register
376 * @retval None
377 */
378 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
379
380 /**
381 * @brief Read a value in DMA register
382 * @param __INSTANCE__ DMA Instance
383 * @param __REG__ Register to be read
384 * @retval Register value
385 */
386 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
387 /**
388 * @}
389 */
390
391 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
392 * @{
393 */
394 /**
395 * @brief Convert DMAx_Streamy into DMAx
396 * @param __STREAM_INSTANCE__ DMAx_Streamy
397 * @retval DMAx
398 */
399 #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
400 (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
401
402 /**
403 * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
404 * @param __STREAM_INSTANCE__ DMAx_Streamy
405 * @retval LL_DMA_STREAM_y
406 */
407 #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
408 (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
409 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
410 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
411 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
412 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
413 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
414 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
415 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
416 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
417 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
418 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
419 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
420 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
421 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
422 LL_DMA_STREAM_7)
423
424 /**
425 * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
426 * @param __DMA_INSTANCE__ DMAx
427 * @param __STREAM__ LL_DMA_STREAM_y
428 * @retval DMAx_Streamy
429 */
430 #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
431 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
432 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
433 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
434 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
435 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
436 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
437 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
438 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
439 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
440 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
441 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
442 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
443 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
444 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
445 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
446 DMA2_Stream7)
447
448 /**
449 * @}
450 */
451
452 /**
453 * @}
454 */
455
456
457 /* Exported functions --------------------------------------------------------*/
458 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
459 * @{
460 */
461
462 /** @defgroup DMA_LL_EF_Configuration Configuration
463 * @{
464 */
465 /**
466 * @brief Enable DMA stream.
467 * @rmtoll CR EN LL_DMA_EnableStream
468 * @param DMAx DMAx Instance
469 * @param Stream This parameter can be one of the following values:
470 * @arg @ref LL_DMA_STREAM_0
471 * @arg @ref LL_DMA_STREAM_1
472 * @arg @ref LL_DMA_STREAM_2
473 * @arg @ref LL_DMA_STREAM_3
474 * @arg @ref LL_DMA_STREAM_4
475 * @arg @ref LL_DMA_STREAM_5
476 * @arg @ref LL_DMA_STREAM_6
477 * @arg @ref LL_DMA_STREAM_7
478 * @retval None
479 */
LL_DMA_EnableStream(DMA_TypeDef * DMAx,uint32_t Stream)480 __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
481 {
482 uint32_t dma_base_addr = (uint32_t)DMAx;
483
484 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
485 }
486
487 /**
488 * @brief Disable DMA stream.
489 * @rmtoll CR EN LL_DMA_DisableStream
490 * @param DMAx DMAx Instance
491 * @param Stream This parameter can be one of the following values:
492 * @arg @ref LL_DMA_STREAM_0
493 * @arg @ref LL_DMA_STREAM_1
494 * @arg @ref LL_DMA_STREAM_2
495 * @arg @ref LL_DMA_STREAM_3
496 * @arg @ref LL_DMA_STREAM_4
497 * @arg @ref LL_DMA_STREAM_5
498 * @arg @ref LL_DMA_STREAM_6
499 * @arg @ref LL_DMA_STREAM_7
500 * @retval None
501 */
LL_DMA_DisableStream(DMA_TypeDef * DMAx,uint32_t Stream)502 __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
503 {
504 uint32_t dma_base_addr = (uint32_t)DMAx;
505
506 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
507 }
508
509 /**
510 * @brief Check if DMA stream is enabled or disabled.
511 * @rmtoll CR EN LL_DMA_IsEnabledStream
512 * @param DMAx DMAx Instance
513 * @param Stream This parameter can be one of the following values:
514 * @arg @ref LL_DMA_STREAM_0
515 * @arg @ref LL_DMA_STREAM_1
516 * @arg @ref LL_DMA_STREAM_2
517 * @arg @ref LL_DMA_STREAM_3
518 * @arg @ref LL_DMA_STREAM_4
519 * @arg @ref LL_DMA_STREAM_5
520 * @arg @ref LL_DMA_STREAM_6
521 * @arg @ref LL_DMA_STREAM_7
522 * @retval State of bit (1 or 0).
523 */
LL_DMA_IsEnabledStream(DMA_TypeDef * DMAx,uint32_t Stream)524 __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
525 {
526 uint32_t dma_base_addr = (uint32_t)DMAx;
527
528 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL : 0UL);
529 }
530
531 /**
532 * @brief Configure all parameters linked to DMA transfer.
533 * @rmtoll CR DIR LL_DMA_ConfigTransfer\n
534 * CR CIRC LL_DMA_ConfigTransfer\n
535 * CR PINC LL_DMA_ConfigTransfer\n
536 * CR MINC LL_DMA_ConfigTransfer\n
537 * CR PSIZE LL_DMA_ConfigTransfer\n
538 * CR MSIZE LL_DMA_ConfigTransfer\n
539 * CR PL LL_DMA_ConfigTransfer\n
540 * CR PFCTRL LL_DMA_ConfigTransfer
541 * @param DMAx DMAx Instance
542 * @param Stream This parameter can be one of the following values:
543 * @arg @ref LL_DMA_STREAM_0
544 * @arg @ref LL_DMA_STREAM_1
545 * @arg @ref LL_DMA_STREAM_2
546 * @arg @ref LL_DMA_STREAM_3
547 * @arg @ref LL_DMA_STREAM_4
548 * @arg @ref LL_DMA_STREAM_5
549 * @arg @ref LL_DMA_STREAM_6
550 * @arg @ref LL_DMA_STREAM_7
551 * @param Configuration This parameter must be a combination of all the following values:
552 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
553 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
554 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
555 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
556 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
557 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
558 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
559 *@retval None
560 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Configuration)561 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
562 {
563 uint32_t dma_base_addr = (uint32_t)DMAx;
564
565 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR,
566 DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
567 Configuration);
568 }
569
570 /**
571 * @brief Set Data transfer direction (read from peripheral or from memory).
572 * @rmtoll CR DIR LL_DMA_SetDataTransferDirection
573 * @param DMAx DMAx Instance
574 * @param Stream This parameter can be one of the following values:
575 * @arg @ref LL_DMA_STREAM_0
576 * @arg @ref LL_DMA_STREAM_1
577 * @arg @ref LL_DMA_STREAM_2
578 * @arg @ref LL_DMA_STREAM_3
579 * @arg @ref LL_DMA_STREAM_4
580 * @arg @ref LL_DMA_STREAM_5
581 * @arg @ref LL_DMA_STREAM_6
582 * @arg @ref LL_DMA_STREAM_7
583 * @param Direction This parameter can be one of the following values:
584 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
585 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
586 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
587 * @retval None
588 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Direction)589 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
590 {
591 uint32_t dma_base_addr = (uint32_t)DMAx;
592
593 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR, Direction);
594 }
595
596 /**
597 * @brief Get Data transfer direction (read from peripheral or from memory).
598 * @rmtoll CR DIR LL_DMA_GetDataTransferDirection
599 * @param DMAx DMAx Instance
600 * @param Stream This parameter can be one of the following values:
601 * @arg @ref LL_DMA_STREAM_0
602 * @arg @ref LL_DMA_STREAM_1
603 * @arg @ref LL_DMA_STREAM_2
604 * @arg @ref LL_DMA_STREAM_3
605 * @arg @ref LL_DMA_STREAM_4
606 * @arg @ref LL_DMA_STREAM_5
607 * @arg @ref LL_DMA_STREAM_6
608 * @arg @ref LL_DMA_STREAM_7
609 * @retval Returned value can be one of the following values:
610 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
611 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
612 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
613 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Stream)614 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
615 {
616 uint32_t dma_base_addr = (uint32_t)DMAx;
617
618 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR));
619 }
620
621 /**
622 * @brief Set DMA mode normal, circular or peripheral flow control.
623 * @rmtoll CR CIRC LL_DMA_SetMode\n
624 * CR PFCTRL LL_DMA_SetMode
625 * @param DMAx DMAx Instance
626 * @param Stream This parameter can be one of the following values:
627 * @arg @ref LL_DMA_STREAM_0
628 * @arg @ref LL_DMA_STREAM_1
629 * @arg @ref LL_DMA_STREAM_2
630 * @arg @ref LL_DMA_STREAM_3
631 * @arg @ref LL_DMA_STREAM_4
632 * @arg @ref LL_DMA_STREAM_5
633 * @arg @ref LL_DMA_STREAM_6
634 * @arg @ref LL_DMA_STREAM_7
635 * @param Mode This parameter can be one of the following values:
636 * @arg @ref LL_DMA_MODE_NORMAL
637 * @arg @ref LL_DMA_MODE_CIRCULAR
638 * @arg @ref LL_DMA_MODE_PFCTRL
639 * @retval None
640 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Mode)641 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
642 {
643 uint32_t dma_base_addr = (uint32_t)DMAx;
644
645 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
646 }
647
648 /**
649 * @brief Get DMA mode normal, circular or peripheral flow control.
650 * @rmtoll CR CIRC LL_DMA_GetMode\n
651 * CR PFCTRL LL_DMA_GetMode
652 * @param DMAx DMAx Instance
653 * @param Stream This parameter can be one of the following values:
654 * @arg @ref LL_DMA_STREAM_0
655 * @arg @ref LL_DMA_STREAM_1
656 * @arg @ref LL_DMA_STREAM_2
657 * @arg @ref LL_DMA_STREAM_3
658 * @arg @ref LL_DMA_STREAM_4
659 * @arg @ref LL_DMA_STREAM_5
660 * @arg @ref LL_DMA_STREAM_6
661 * @arg @ref LL_DMA_STREAM_7
662 * @retval Returned value can be one of the following values:
663 * @arg @ref LL_DMA_MODE_NORMAL
664 * @arg @ref LL_DMA_MODE_CIRCULAR
665 * @arg @ref LL_DMA_MODE_PFCTRL
666 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Stream)667 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
668 {
669 uint32_t dma_base_addr = (uint32_t)DMAx;
670
671 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
672 }
673
674 /**
675 * @brief Set Peripheral increment mode.
676 * @rmtoll CR PINC LL_DMA_SetPeriphIncMode
677 * @param DMAx DMAx Instance
678 * @param Stream This parameter can be one of the following values:
679 * @arg @ref LL_DMA_STREAM_0
680 * @arg @ref LL_DMA_STREAM_1
681 * @arg @ref LL_DMA_STREAM_2
682 * @arg @ref LL_DMA_STREAM_3
683 * @arg @ref LL_DMA_STREAM_4
684 * @arg @ref LL_DMA_STREAM_5
685 * @arg @ref LL_DMA_STREAM_6
686 * @arg @ref LL_DMA_STREAM_7
687 * @param IncrementMode This parameter can be one of the following values:
688 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
689 * @arg @ref LL_DMA_PERIPH_INCREMENT
690 * @retval None
691 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t IncrementMode)692 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
693 {
694 uint32_t dma_base_addr = (uint32_t)DMAx;
695
696 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC, IncrementMode);
697 }
698
699 /**
700 * @brief Get Peripheral increment mode.
701 * @rmtoll CR PINC LL_DMA_GetPeriphIncMode
702 * @param DMAx DMAx Instance
703 * @param Stream This parameter can be one of the following values:
704 * @arg @ref LL_DMA_STREAM_0
705 * @arg @ref LL_DMA_STREAM_1
706 * @arg @ref LL_DMA_STREAM_2
707 * @arg @ref LL_DMA_STREAM_3
708 * @arg @ref LL_DMA_STREAM_4
709 * @arg @ref LL_DMA_STREAM_5
710 * @arg @ref LL_DMA_STREAM_6
711 * @arg @ref LL_DMA_STREAM_7
712 * @retval Returned value can be one of the following values:
713 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
714 * @arg @ref LL_DMA_PERIPH_INCREMENT
715 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Stream)716 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
717 {
718 uint32_t dma_base_addr = (uint32_t)DMAx;
719
720 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC));
721 }
722
723 /**
724 * @brief Set Memory increment mode.
725 * @rmtoll CR MINC LL_DMA_SetMemoryIncMode
726 * @param DMAx DMAx Instance
727 * @param Stream This parameter can be one of the following values:
728 * @arg @ref LL_DMA_STREAM_0
729 * @arg @ref LL_DMA_STREAM_1
730 * @arg @ref LL_DMA_STREAM_2
731 * @arg @ref LL_DMA_STREAM_3
732 * @arg @ref LL_DMA_STREAM_4
733 * @arg @ref LL_DMA_STREAM_5
734 * @arg @ref LL_DMA_STREAM_6
735 * @arg @ref LL_DMA_STREAM_7
736 * @param IncrementMode This parameter can be one of the following values:
737 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
738 * @arg @ref LL_DMA_MEMORY_INCREMENT
739 * @retval None
740 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t IncrementMode)741 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
742 {
743 uint32_t dma_base_addr = (uint32_t)DMAx;
744
745 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC, IncrementMode);
746 }
747
748 /**
749 * @brief Get Memory increment mode.
750 * @rmtoll CR MINC LL_DMA_GetMemoryIncMode
751 * @param DMAx DMAx Instance
752 * @param Stream This parameter can be one of the following values:
753 * @arg @ref LL_DMA_STREAM_0
754 * @arg @ref LL_DMA_STREAM_1
755 * @arg @ref LL_DMA_STREAM_2
756 * @arg @ref LL_DMA_STREAM_3
757 * @arg @ref LL_DMA_STREAM_4
758 * @arg @ref LL_DMA_STREAM_5
759 * @arg @ref LL_DMA_STREAM_6
760 * @arg @ref LL_DMA_STREAM_7
761 * @retval Returned value can be one of the following values:
762 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
763 * @arg @ref LL_DMA_MEMORY_INCREMENT
764 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Stream)765 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
766 {
767 uint32_t dma_base_addr = (uint32_t)DMAx;
768
769 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC));
770 }
771
772 /**
773 * @brief Set Peripheral size.
774 * @rmtoll CR PSIZE LL_DMA_SetPeriphSize
775 * @param DMAx DMAx Instance
776 * @param Stream This parameter can be one of the following values:
777 * @arg @ref LL_DMA_STREAM_0
778 * @arg @ref LL_DMA_STREAM_1
779 * @arg @ref LL_DMA_STREAM_2
780 * @arg @ref LL_DMA_STREAM_3
781 * @arg @ref LL_DMA_STREAM_4
782 * @arg @ref LL_DMA_STREAM_5
783 * @arg @ref LL_DMA_STREAM_6
784 * @arg @ref LL_DMA_STREAM_7
785 * @param Size This parameter can be one of the following values:
786 * @arg @ref LL_DMA_PDATAALIGN_BYTE
787 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
788 * @arg @ref LL_DMA_PDATAALIGN_WORD
789 * @retval None
790 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Size)791 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
792 {
793 uint32_t dma_base_addr = (uint32_t)DMAx;
794
795 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE, Size);
796 }
797
798 /**
799 * @brief Get Peripheral size.
800 * @rmtoll CR PSIZE LL_DMA_GetPeriphSize
801 * @param DMAx DMAx Instance
802 * @param Stream This parameter can be one of the following values:
803 * @arg @ref LL_DMA_STREAM_0
804 * @arg @ref LL_DMA_STREAM_1
805 * @arg @ref LL_DMA_STREAM_2
806 * @arg @ref LL_DMA_STREAM_3
807 * @arg @ref LL_DMA_STREAM_4
808 * @arg @ref LL_DMA_STREAM_5
809 * @arg @ref LL_DMA_STREAM_6
810 * @arg @ref LL_DMA_STREAM_7
811 * @retval Returned value can be one of the following values:
812 * @arg @ref LL_DMA_PDATAALIGN_BYTE
813 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
814 * @arg @ref LL_DMA_PDATAALIGN_WORD
815 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Stream)816 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
817 {
818 uint32_t dma_base_addr = (uint32_t)DMAx;
819
820 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE));
821 }
822
823 /**
824 * @brief Set Memory size.
825 * @rmtoll CR MSIZE LL_DMA_SetMemorySize
826 * @param DMAx DMAx Instance
827 * @param Stream This parameter can be one of the following values:
828 * @arg @ref LL_DMA_STREAM_0
829 * @arg @ref LL_DMA_STREAM_1
830 * @arg @ref LL_DMA_STREAM_2
831 * @arg @ref LL_DMA_STREAM_3
832 * @arg @ref LL_DMA_STREAM_4
833 * @arg @ref LL_DMA_STREAM_5
834 * @arg @ref LL_DMA_STREAM_6
835 * @arg @ref LL_DMA_STREAM_7
836 * @param Size This parameter can be one of the following values:
837 * @arg @ref LL_DMA_MDATAALIGN_BYTE
838 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
839 * @arg @ref LL_DMA_MDATAALIGN_WORD
840 * @retval None
841 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Size)842 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
843 {
844 uint32_t dma_base_addr = (uint32_t)DMAx;
845
846 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE, Size);
847 }
848
849 /**
850 * @brief Get Memory size.
851 * @rmtoll CR MSIZE LL_DMA_GetMemorySize
852 * @param DMAx DMAx Instance
853 * @param Stream This parameter can be one of the following values:
854 * @arg @ref LL_DMA_STREAM_0
855 * @arg @ref LL_DMA_STREAM_1
856 * @arg @ref LL_DMA_STREAM_2
857 * @arg @ref LL_DMA_STREAM_3
858 * @arg @ref LL_DMA_STREAM_4
859 * @arg @ref LL_DMA_STREAM_5
860 * @arg @ref LL_DMA_STREAM_6
861 * @arg @ref LL_DMA_STREAM_7
862 * @retval Returned value can be one of the following values:
863 * @arg @ref LL_DMA_MDATAALIGN_BYTE
864 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
865 * @arg @ref LL_DMA_MDATAALIGN_WORD
866 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Stream)867 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
868 {
869 uint32_t dma_base_addr = (uint32_t)DMAx;
870
871 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE));
872 }
873
874 /**
875 * @brief Set Peripheral increment offset size.
876 * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
877 * @param DMAx DMAx Instance
878 * @param Stream This parameter can be one of the following values:
879 * @arg @ref LL_DMA_STREAM_0
880 * @arg @ref LL_DMA_STREAM_1
881 * @arg @ref LL_DMA_STREAM_2
882 * @arg @ref LL_DMA_STREAM_3
883 * @arg @ref LL_DMA_STREAM_4
884 * @arg @ref LL_DMA_STREAM_5
885 * @arg @ref LL_DMA_STREAM_6
886 * @arg @ref LL_DMA_STREAM_7
887 * @param OffsetSize This parameter can be one of the following values:
888 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
889 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
890 * @retval None
891 */
LL_DMA_SetIncOffsetSize(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t OffsetSize)892 __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
893 {
894 uint32_t dma_base_addr = (uint32_t)DMAx;
895
896 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS, OffsetSize);
897 }
898
899 /**
900 * @brief Get Peripheral increment offset size.
901 * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
902 * @param DMAx DMAx Instance
903 * @param Stream This parameter can be one of the following values:
904 * @arg @ref LL_DMA_STREAM_0
905 * @arg @ref LL_DMA_STREAM_1
906 * @arg @ref LL_DMA_STREAM_2
907 * @arg @ref LL_DMA_STREAM_3
908 * @arg @ref LL_DMA_STREAM_4
909 * @arg @ref LL_DMA_STREAM_5
910 * @arg @ref LL_DMA_STREAM_6
911 * @arg @ref LL_DMA_STREAM_7
912 * @retval Returned value can be one of the following values:
913 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
914 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
915 */
LL_DMA_GetIncOffsetSize(DMA_TypeDef * DMAx,uint32_t Stream)916 __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
917 {
918 uint32_t dma_base_addr = (uint32_t)DMAx;
919
920 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS));
921 }
922
923 /**
924 * @brief Set Stream priority level.
925 * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
926 * @param DMAx DMAx Instance
927 * @param Stream This parameter can be one of the following values:
928 * @arg @ref LL_DMA_STREAM_0
929 * @arg @ref LL_DMA_STREAM_1
930 * @arg @ref LL_DMA_STREAM_2
931 * @arg @ref LL_DMA_STREAM_3
932 * @arg @ref LL_DMA_STREAM_4
933 * @arg @ref LL_DMA_STREAM_5
934 * @arg @ref LL_DMA_STREAM_6
935 * @arg @ref LL_DMA_STREAM_7
936 * @param Priority This parameter can be one of the following values:
937 * @arg @ref LL_DMA_PRIORITY_LOW
938 * @arg @ref LL_DMA_PRIORITY_MEDIUM
939 * @arg @ref LL_DMA_PRIORITY_HIGH
940 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
941 * @retval None
942 */
LL_DMA_SetStreamPriorityLevel(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Priority)943 __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
944 {
945 uint32_t dma_base_addr = (uint32_t)DMAx;
946
947 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL, Priority);
948 }
949
950 /**
951 * @brief Get Stream priority level.
952 * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
953 * @param DMAx DMAx Instance
954 * @param Stream This parameter can be one of the following values:
955 * @arg @ref LL_DMA_STREAM_0
956 * @arg @ref LL_DMA_STREAM_1
957 * @arg @ref LL_DMA_STREAM_2
958 * @arg @ref LL_DMA_STREAM_3
959 * @arg @ref LL_DMA_STREAM_4
960 * @arg @ref LL_DMA_STREAM_5
961 * @arg @ref LL_DMA_STREAM_6
962 * @arg @ref LL_DMA_STREAM_7
963 * @retval Returned value can be one of the following values:
964 * @arg @ref LL_DMA_PRIORITY_LOW
965 * @arg @ref LL_DMA_PRIORITY_MEDIUM
966 * @arg @ref LL_DMA_PRIORITY_HIGH
967 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
968 */
LL_DMA_GetStreamPriorityLevel(DMA_TypeDef * DMAx,uint32_t Stream)969 __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
970 {
971 uint32_t dma_base_addr = (uint32_t)DMAx;
972
973 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL));
974 }
975
976 /**
977 * @brief Enable DMA stream bufferable transfer.
978 * @rmtoll CR TRBUFF LL_DMA_EnableBufferableTransfer
979 * @param DMAx DMAx Instance
980 * @param Stream This parameter can be one of the following values:
981 * @arg @ref LL_DMA_STREAM_0
982 * @arg @ref LL_DMA_STREAM_1
983 * @arg @ref LL_DMA_STREAM_2
984 * @arg @ref LL_DMA_STREAM_3
985 * @arg @ref LL_DMA_STREAM_4
986 * @arg @ref LL_DMA_STREAM_5
987 * @arg @ref LL_DMA_STREAM_6
988 * @arg @ref LL_DMA_STREAM_7
989 * @retval None
990 */
LL_DMA_EnableBufferableTransfer(DMA_TypeDef * DMAx,uint32_t Stream)991 __STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream)
992 {
993 uint32_t dma_base_addr = (uint32_t)DMAx;
994
995 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);
996 }
997
998 /**
999 * @brief Disable DMA stream bufferable transfer.
1000 * @rmtoll CR TRBUFF LL_DMA_DisableBufferableTransfer
1001 * @param DMAx DMAx Instance
1002 * @param Stream This parameter can be one of the following values:
1003 * @arg @ref LL_DMA_STREAM_0
1004 * @arg @ref LL_DMA_STREAM_1
1005 * @arg @ref LL_DMA_STREAM_2
1006 * @arg @ref LL_DMA_STREAM_3
1007 * @arg @ref LL_DMA_STREAM_4
1008 * @arg @ref LL_DMA_STREAM_5
1009 * @arg @ref LL_DMA_STREAM_6
1010 * @arg @ref LL_DMA_STREAM_7
1011 * @retval None
1012 */
LL_DMA_DisableBufferableTransfer(DMA_TypeDef * DMAx,uint32_t Stream)1013 __STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream)
1014 {
1015 uint32_t dma_base_addr = (uint32_t)DMAx;
1016
1017 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);
1018 }
1019
1020 /**
1021 * @brief Set Number of data to transfer.
1022 * @rmtoll NDTR NDT LL_DMA_SetDataLength
1023 * @note This action has no effect if
1024 * stream is enabled.
1025 * @param DMAx DMAx Instance
1026 * @param Stream This parameter can be one of the following values:
1027 * @arg @ref LL_DMA_STREAM_0
1028 * @arg @ref LL_DMA_STREAM_1
1029 * @arg @ref LL_DMA_STREAM_2
1030 * @arg @ref LL_DMA_STREAM_3
1031 * @arg @ref LL_DMA_STREAM_4
1032 * @arg @ref LL_DMA_STREAM_5
1033 * @arg @ref LL_DMA_STREAM_6
1034 * @arg @ref LL_DMA_STREAM_7
1035 * @param NbData Between 0 to 0xFFFFFFFF
1036 * @retval None
1037 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t NbData)1038 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData)
1039 {
1040 uint32_t dma_base_addr = (uint32_t)DMAx;
1041
1042 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT, NbData);
1043 }
1044
1045 /**
1046 * @brief Get Number of data to transfer.
1047 * @rmtoll NDTR NDT LL_DMA_GetDataLength
1048 * @note Once the stream is enabled, the return value indicate the
1049 * remaining bytes to be transmitted.
1050 * @param DMAx DMAx Instance
1051 * @param Stream This parameter can be one of the following values:
1052 * @arg @ref LL_DMA_STREAM_0
1053 * @arg @ref LL_DMA_STREAM_1
1054 * @arg @ref LL_DMA_STREAM_2
1055 * @arg @ref LL_DMA_STREAM_3
1056 * @arg @ref LL_DMA_STREAM_4
1057 * @arg @ref LL_DMA_STREAM_5
1058 * @arg @ref LL_DMA_STREAM_6
1059 * @arg @ref LL_DMA_STREAM_7
1060 * @retval Between 0 to 0xFFFFFFFF
1061 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Stream)1062 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream)
1063 {
1064 uint32_t dma_base_addr = (uint32_t)DMAx;
1065
1066 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT));
1067 }
1068 /**
1069 * @brief Set DMA request for DMA Streams on DMAMUX Channel x.
1070 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
1071 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
1072 * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
1073 * @param DMAx DMAx Instance
1074 * @param Stream This parameter can be one of the following values:
1075 * @arg @ref LL_DMA_STREAM_0
1076 * @arg @ref LL_DMA_STREAM_1
1077 * @arg @ref LL_DMA_STREAM_2
1078 * @arg @ref LL_DMA_STREAM_3
1079 * @arg @ref LL_DMA_STREAM_4
1080 * @arg @ref LL_DMA_STREAM_5
1081 * @arg @ref LL_DMA_STREAM_6
1082 * @arg @ref LL_DMA_STREAM_7
1083 * @param Request This parameter can be one of the following values:
1084 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM
1085 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0
1086 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1
1087 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2
1088 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3
1089 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4
1090 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5
1091 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6
1092 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7
1093 * @arg @ref LL_DMAMUX1_REQ_ADC1
1094 * @arg @ref LL_DMAMUX1_REQ_ADC2
1095 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
1096 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
1097 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
1098 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
1099 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP
1100 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
1101 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM
1102 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
1103 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
1104 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
1105 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
1106 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP
1107 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
1108 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
1109 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
1110 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
1111 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP
1112 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
1113 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
1114 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
1115 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
1116 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP
1117 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX
1118 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX
1119 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX
1120 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX
1121 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX
1122 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX
1123 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX
1124 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX
1125 * @arg @ref LL_DMAMUX1_REQ_USART1_RX
1126 * @arg @ref LL_DMAMUX1_REQ_USART1_TX
1127 * @arg @ref LL_DMAMUX1_REQ_USART2_RX
1128 * @arg @ref LL_DMAMUX1_REQ_USART2_TX
1129 * @arg @ref LL_DMAMUX1_REQ_USART3_RX
1130 * @arg @ref LL_DMAMUX1_REQ_USART3_TX
1131 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
1132 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
1133 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
1134 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
1135 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP
1136 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
1137 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM
1138 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
1139 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
1140 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
1141 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
1142 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP
1143 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
1144 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX
1145 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX
1146 * @arg @ref LL_DMAMUX1_REQ_UART4_RX
1147 * @arg @ref LL_DMAMUX1_REQ_UART4_TX
1148 * @arg @ref LL_DMAMUX1_REQ_UART5_RX
1149 * @arg @ref LL_DMAMUX1_REQ_UART5_TX
1150 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
1151 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
1152 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP
1153 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP
1154 * @arg @ref LL_DMAMUX1_REQ_USART6_RX
1155 * @arg @ref LL_DMAMUX1_REQ_USART6_TX
1156 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX
1157 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX
1158 * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
1159 * @arg @ref LL_DMAMUX1_REQ_CRYP_IN
1160 * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
1161 * @arg @ref LL_DMAMUX1_REQ_HASH_IN
1162 * @arg @ref LL_DMAMUX1_REQ_UART7_RX
1163 * @arg @ref LL_DMAMUX1_REQ_UART7_TX
1164 * @arg @ref LL_DMAMUX1_REQ_UART8_RX
1165 * @arg @ref LL_DMAMUX1_REQ_UART8_TX
1166 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX
1167 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX
1168 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX
1169 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX
1170 * @arg @ref LL_DMAMUX1_REQ_SAI1_A
1171 * @arg @ref LL_DMAMUX1_REQ_SAI1_B
1172 * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
1173 * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
1174 * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
1175 * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
1176 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
1177 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
1178 * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
1179 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
1180 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
1181 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
1182 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
1183 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
1184 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
1185 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
1186 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
1187 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
1188 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
1189 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP
1190 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
1191 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM
1192 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
1193 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP
1194 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
1195 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP
1196 * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
1197 * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
1198 * @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
1199 * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
1200 * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
1201 * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
1202 * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
1203 * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*)
1204 * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
1205 * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
1206 * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
1207 * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*)
1208 * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*)
1209 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*)
1210 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*)
1211 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*)
1212 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*)
1213 * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*)
1214 * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*)
1215 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*)
1216 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*)
1217 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*)
1218 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*)
1219 * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*)
1220 * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*)
1221 *
1222 * @note (*) Availability depends on devices.
1223 * @retval None
1224 */
LL_DMA_SetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Request)1225 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Request)
1226 {
1227 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
1228 }
1229
1230 /**
1231 * @brief Get DMA request for DMA Channels on DMAMUX Channel x.
1232 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
1233 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
1234 * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
1235 * @param DMAx DMAx Instance
1236 * @param Stream This parameter can be one of the following values:
1237 * @arg @ref LL_DMA_STREAM_0
1238 * @arg @ref LL_DMA_STREAM_1
1239 * @arg @ref LL_DMA_STREAM_2
1240 * @arg @ref LL_DMA_STREAM_3
1241 * @arg @ref LL_DMA_STREAM_4
1242 * @arg @ref LL_DMA_STREAM_5
1243 * @arg @ref LL_DMA_STREAM_6
1244 * @arg @ref LL_DMA_STREAM_7
1245 * @retval Returned value can be one of the following values:
1246 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM
1247 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0
1248 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1
1249 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2
1250 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3
1251 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4
1252 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5
1253 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6
1254 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7
1255 * @arg @ref LL_DMAMUX1_REQ_ADC1
1256 * @arg @ref LL_DMAMUX1_REQ_ADC2
1257 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
1258 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
1259 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
1260 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
1261 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP
1262 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
1263 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM
1264 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
1265 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
1266 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
1267 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
1268 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP
1269 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
1270 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
1271 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
1272 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
1273 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP
1274 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
1275 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
1276 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
1277 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
1278 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP
1279 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX
1280 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX
1281 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX
1282 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX
1283 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX
1284 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX
1285 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX
1286 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX
1287 * @arg @ref LL_DMAMUX1_REQ_USART1_RX
1288 * @arg @ref LL_DMAMUX1_REQ_USART1_TX
1289 * @arg @ref LL_DMAMUX1_REQ_USART2_RX
1290 * @arg @ref LL_DMAMUX1_REQ_USART2_TX
1291 * @arg @ref LL_DMAMUX1_REQ_USART3_RX
1292 * @arg @ref LL_DMAMUX1_REQ_USART3_TX
1293 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
1294 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
1295 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
1296 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
1297 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP
1298 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
1299 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM
1300 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
1301 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
1302 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
1303 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
1304 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP
1305 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
1306 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX
1307 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX
1308 * @arg @ref LL_DMAMUX1_REQ_UART4_RX
1309 * @arg @ref LL_DMAMUX1_REQ_UART4_TX
1310 * @arg @ref LL_DMAMUX1_REQ_UART5_RX
1311 * @arg @ref LL_DMAMUX1_REQ_UART5_TX
1312 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
1313 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
1314 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP
1315 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP
1316 * @arg @ref LL_DMAMUX1_REQ_USART6_RX
1317 * @arg @ref LL_DMAMUX1_REQ_USART6_TX
1318 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX
1319 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX
1320 * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
1321 * @arg @ref LL_DMAMUX1_REQ_CRYP_IN
1322 * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
1323 * @arg @ref LL_DMAMUX1_REQ_HASH_IN
1324 * @arg @ref LL_DMAMUX1_REQ_UART7_RX
1325 * @arg @ref LL_DMAMUX1_REQ_UART7_TX
1326 * @arg @ref LL_DMAMUX1_REQ_UART8_RX
1327 * @arg @ref LL_DMAMUX1_REQ_UART8_TX
1328 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX
1329 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX
1330 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX
1331 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX
1332 * @arg @ref LL_DMAMUX1_REQ_SAI1_A
1333 * @arg @ref LL_DMAMUX1_REQ_SAI1_B
1334 * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
1335 * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
1336 * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
1337 * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
1338 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
1339 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
1340 * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
1341 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
1342 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
1343 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
1344 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
1345 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
1346 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
1347 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
1348 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
1349 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
1350 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
1351 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP
1352 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
1353 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM
1354 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
1355 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP
1356 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
1357 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP
1358 * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
1359 * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
1360 * @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
1361 * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
1362 * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
1363 * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
1364 * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
1365 * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*)
1366 * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
1367 * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
1368 * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
1369 * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*)
1370 * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*)
1371 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*)
1372 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*)
1373 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*)
1374 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*)
1375 * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*)
1376 * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*)
1377 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*)
1378 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*)
1379 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*)
1380 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*)
1381 * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*)
1382 * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*)
1383 *
1384 * @note (*) Availability depends on devices.
1385 */
LL_DMA_GetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Stream)1386 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream)
1387 {
1388 return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
1389 }
1390
1391 /**
1392 * @brief Set Memory burst transfer configuration.
1393 * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
1394 * @param DMAx DMAx Instance
1395 * @param Stream This parameter can be one of the following values:
1396 * @arg @ref LL_DMA_STREAM_0
1397 * @arg @ref LL_DMA_STREAM_1
1398 * @arg @ref LL_DMA_STREAM_2
1399 * @arg @ref LL_DMA_STREAM_3
1400 * @arg @ref LL_DMA_STREAM_4
1401 * @arg @ref LL_DMA_STREAM_5
1402 * @arg @ref LL_DMA_STREAM_6
1403 * @arg @ref LL_DMA_STREAM_7
1404 * @param Mburst This parameter can be one of the following values:
1405 * @arg @ref LL_DMA_MBURST_SINGLE
1406 * @arg @ref LL_DMA_MBURST_INC4
1407 * @arg @ref LL_DMA_MBURST_INC8
1408 * @arg @ref LL_DMA_MBURST_INC16
1409 * @retval None
1410 */
LL_DMA_SetMemoryBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Mburst)1411 __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
1412 {
1413 uint32_t dma_base_addr = (uint32_t)DMAx;
1414
1415 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST, Mburst);
1416 }
1417
1418 /**
1419 * @brief Get Memory burst transfer configuration.
1420 * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
1421 * @param DMAx DMAx Instance
1422 * @param Stream This parameter can be one of the following values:
1423 * @arg @ref LL_DMA_STREAM_0
1424 * @arg @ref LL_DMA_STREAM_1
1425 * @arg @ref LL_DMA_STREAM_2
1426 * @arg @ref LL_DMA_STREAM_3
1427 * @arg @ref LL_DMA_STREAM_4
1428 * @arg @ref LL_DMA_STREAM_5
1429 * @arg @ref LL_DMA_STREAM_6
1430 * @arg @ref LL_DMA_STREAM_7
1431 * @retval Returned value can be one of the following values:
1432 * @arg @ref LL_DMA_MBURST_SINGLE
1433 * @arg @ref LL_DMA_MBURST_INC4
1434 * @arg @ref LL_DMA_MBURST_INC8
1435 * @arg @ref LL_DMA_MBURST_INC16
1436 */
LL_DMA_GetMemoryBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream)1437 __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
1438 {
1439 uint32_t dma_base_addr = (uint32_t)DMAx;
1440
1441 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST));
1442 }
1443
1444 /**
1445 * @brief Set Peripheral burst transfer configuration.
1446 * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
1447 * @param DMAx DMAx Instance
1448 * @param Stream This parameter can be one of the following values:
1449 * @arg @ref LL_DMA_STREAM_0
1450 * @arg @ref LL_DMA_STREAM_1
1451 * @arg @ref LL_DMA_STREAM_2
1452 * @arg @ref LL_DMA_STREAM_3
1453 * @arg @ref LL_DMA_STREAM_4
1454 * @arg @ref LL_DMA_STREAM_5
1455 * @arg @ref LL_DMA_STREAM_6
1456 * @arg @ref LL_DMA_STREAM_7
1457 * @param Pburst This parameter can be one of the following values:
1458 * @arg @ref LL_DMA_PBURST_SINGLE
1459 * @arg @ref LL_DMA_PBURST_INC4
1460 * @arg @ref LL_DMA_PBURST_INC8
1461 * @arg @ref LL_DMA_PBURST_INC16
1462 * @retval None
1463 */
LL_DMA_SetPeriphBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Pburst)1464 __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
1465 {
1466 uint32_t dma_base_addr = (uint32_t)DMAx;
1467
1468 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST, Pburst);
1469 }
1470
1471 /**
1472 * @brief Get Peripheral burst transfer configuration.
1473 * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
1474 * @param DMAx DMAx Instance
1475 * @param Stream This parameter can be one of the following values:
1476 * @arg @ref LL_DMA_STREAM_0
1477 * @arg @ref LL_DMA_STREAM_1
1478 * @arg @ref LL_DMA_STREAM_2
1479 * @arg @ref LL_DMA_STREAM_3
1480 * @arg @ref LL_DMA_STREAM_4
1481 * @arg @ref LL_DMA_STREAM_5
1482 * @arg @ref LL_DMA_STREAM_6
1483 * @arg @ref LL_DMA_STREAM_7
1484 * @retval Returned value can be one of the following values:
1485 * @arg @ref LL_DMA_PBURST_SINGLE
1486 * @arg @ref LL_DMA_PBURST_INC4
1487 * @arg @ref LL_DMA_PBURST_INC8
1488 * @arg @ref LL_DMA_PBURST_INC16
1489 */
LL_DMA_GetPeriphBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream)1490 __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
1491 {
1492 uint32_t dma_base_addr = (uint32_t)DMAx;
1493
1494 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST));
1495 }
1496
1497 /**
1498 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1499 * @rmtoll CR CT LL_DMA_SetCurrentTargetMem
1500 * @param DMAx DMAx Instance
1501 * @param Stream This parameter can be one of the following values:
1502 * @arg @ref LL_DMA_STREAM_0
1503 * @arg @ref LL_DMA_STREAM_1
1504 * @arg @ref LL_DMA_STREAM_2
1505 * @arg @ref LL_DMA_STREAM_3
1506 * @arg @ref LL_DMA_STREAM_4
1507 * @arg @ref LL_DMA_STREAM_5
1508 * @arg @ref LL_DMA_STREAM_6
1509 * @arg @ref LL_DMA_STREAM_7
1510 * @param CurrentMemory This parameter can be one of the following values:
1511 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1512 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1513 * @retval None
1514 */
LL_DMA_SetCurrentTargetMem(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t CurrentMemory)1515 __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
1516 {
1517 uint32_t dma_base_addr = (uint32_t)DMAx;
1518
1519 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT, CurrentMemory);
1520 }
1521
1522 /**
1523 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1524 * @rmtoll CR CT LL_DMA_GetCurrentTargetMem
1525 * @param DMAx DMAx Instance
1526 * @param Stream This parameter can be one of the following values:
1527 * @arg @ref LL_DMA_STREAM_0
1528 * @arg @ref LL_DMA_STREAM_1
1529 * @arg @ref LL_DMA_STREAM_2
1530 * @arg @ref LL_DMA_STREAM_3
1531 * @arg @ref LL_DMA_STREAM_4
1532 * @arg @ref LL_DMA_STREAM_5
1533 * @arg @ref LL_DMA_STREAM_6
1534 * @arg @ref LL_DMA_STREAM_7
1535 * @retval Returned value can be one of the following values:
1536 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1537 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1538 */
LL_DMA_GetCurrentTargetMem(DMA_TypeDef * DMAx,uint32_t Stream)1539 __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
1540 {
1541 uint32_t dma_base_addr = (uint32_t)DMAx;
1542
1543 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT));
1544 }
1545
1546 /**
1547 * @brief Enable the double buffer mode.
1548 * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
1549 * @param DMAx DMAx Instance
1550 * @param Stream This parameter can be one of the following values:
1551 * @arg @ref LL_DMA_STREAM_0
1552 * @arg @ref LL_DMA_STREAM_1
1553 * @arg @ref LL_DMA_STREAM_2
1554 * @arg @ref LL_DMA_STREAM_3
1555 * @arg @ref LL_DMA_STREAM_4
1556 * @arg @ref LL_DMA_STREAM_5
1557 * @arg @ref LL_DMA_STREAM_6
1558 * @arg @ref LL_DMA_STREAM_7
1559 * @retval None
1560 */
LL_DMA_EnableDoubleBufferMode(DMA_TypeDef * DMAx,uint32_t Stream)1561 __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
1562 {
1563 uint32_t dma_base_addr = (uint32_t)DMAx;
1564
1565 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
1566 }
1567
1568 /**
1569 * @brief Disable the double buffer mode.
1570 * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
1571 * @param DMAx DMAx Instance
1572 * @param Stream This parameter can be one of the following values:
1573 * @arg @ref LL_DMA_STREAM_0
1574 * @arg @ref LL_DMA_STREAM_1
1575 * @arg @ref LL_DMA_STREAM_2
1576 * @arg @ref LL_DMA_STREAM_3
1577 * @arg @ref LL_DMA_STREAM_4
1578 * @arg @ref LL_DMA_STREAM_5
1579 * @arg @ref LL_DMA_STREAM_6
1580 * @arg @ref LL_DMA_STREAM_7
1581 * @retval None
1582 */
LL_DMA_DisableDoubleBufferMode(DMA_TypeDef * DMAx,uint32_t Stream)1583 __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
1584 {
1585 uint32_t dma_base_addr = (uint32_t)DMAx;
1586
1587 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
1588 }
1589
1590 /**
1591 * @brief Get FIFO status.
1592 * @rmtoll FCR FS LL_DMA_GetFIFOStatus
1593 * @param DMAx DMAx Instance
1594 * @param Stream This parameter can be one of the following values:
1595 * @arg @ref LL_DMA_STREAM_0
1596 * @arg @ref LL_DMA_STREAM_1
1597 * @arg @ref LL_DMA_STREAM_2
1598 * @arg @ref LL_DMA_STREAM_3
1599 * @arg @ref LL_DMA_STREAM_4
1600 * @arg @ref LL_DMA_STREAM_5
1601 * @arg @ref LL_DMA_STREAM_6
1602 * @arg @ref LL_DMA_STREAM_7
1603 * @retval Returned value can be one of the following values:
1604 * @arg @ref LL_DMA_FIFOSTATUS_0_25
1605 * @arg @ref LL_DMA_FIFOSTATUS_25_50
1606 * @arg @ref LL_DMA_FIFOSTATUS_50_75
1607 * @arg @ref LL_DMA_FIFOSTATUS_75_100
1608 * @arg @ref LL_DMA_FIFOSTATUS_EMPTY
1609 * @arg @ref LL_DMA_FIFOSTATUS_FULL
1610 */
LL_DMA_GetFIFOStatus(DMA_TypeDef * DMAx,uint32_t Stream)1611 __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
1612 {
1613 uint32_t dma_base_addr = (uint32_t)DMAx;
1614
1615 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FS));
1616 }
1617
1618 /**
1619 * @brief Disable Fifo mode.
1620 * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
1621 * @param DMAx DMAx Instance
1622 * @param Stream This parameter can be one of the following values:
1623 * @arg @ref LL_DMA_STREAM_0
1624 * @arg @ref LL_DMA_STREAM_1
1625 * @arg @ref LL_DMA_STREAM_2
1626 * @arg @ref LL_DMA_STREAM_3
1627 * @arg @ref LL_DMA_STREAM_4
1628 * @arg @ref LL_DMA_STREAM_5
1629 * @arg @ref LL_DMA_STREAM_6
1630 * @arg @ref LL_DMA_STREAM_7
1631 * @retval None
1632 */
LL_DMA_DisableFifoMode(DMA_TypeDef * DMAx,uint32_t Stream)1633 __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
1634 {
1635 uint32_t dma_base_addr = (uint32_t)DMAx;
1636
1637 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
1638 }
1639
1640 /**
1641 * @brief Enable Fifo mode.
1642 * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
1643 * @param DMAx DMAx Instance
1644 * @param Stream This parameter can be one of the following values:
1645 * @arg @ref LL_DMA_STREAM_0
1646 * @arg @ref LL_DMA_STREAM_1
1647 * @arg @ref LL_DMA_STREAM_2
1648 * @arg @ref LL_DMA_STREAM_3
1649 * @arg @ref LL_DMA_STREAM_4
1650 * @arg @ref LL_DMA_STREAM_5
1651 * @arg @ref LL_DMA_STREAM_6
1652 * @arg @ref LL_DMA_STREAM_7
1653 * @retval None
1654 */
LL_DMA_EnableFifoMode(DMA_TypeDef * DMAx,uint32_t Stream)1655 __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
1656 {
1657 uint32_t dma_base_addr = (uint32_t)DMAx;
1658
1659 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
1660 }
1661
1662 /**
1663 * @brief Select FIFO threshold.
1664 * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
1665 * @param DMAx DMAx Instance
1666 * @param Stream This parameter can be one of the following values:
1667 * @arg @ref LL_DMA_STREAM_0
1668 * @arg @ref LL_DMA_STREAM_1
1669 * @arg @ref LL_DMA_STREAM_2
1670 * @arg @ref LL_DMA_STREAM_3
1671 * @arg @ref LL_DMA_STREAM_4
1672 * @arg @ref LL_DMA_STREAM_5
1673 * @arg @ref LL_DMA_STREAM_6
1674 * @arg @ref LL_DMA_STREAM_7
1675 * @param Threshold This parameter can be one of the following values:
1676 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1677 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1678 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1679 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1680 * @retval None
1681 */
LL_DMA_SetFIFOThreshold(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Threshold)1682 __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
1683 {
1684 uint32_t dma_base_addr = (uint32_t)DMAx;
1685
1686 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH, Threshold);
1687 }
1688
1689 /**
1690 * @brief Get FIFO threshold.
1691 * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
1692 * @param DMAx DMAx Instance
1693 * @param Stream This parameter can be one of the following values:
1694 * @arg @ref LL_DMA_STREAM_0
1695 * @arg @ref LL_DMA_STREAM_1
1696 * @arg @ref LL_DMA_STREAM_2
1697 * @arg @ref LL_DMA_STREAM_3
1698 * @arg @ref LL_DMA_STREAM_4
1699 * @arg @ref LL_DMA_STREAM_5
1700 * @arg @ref LL_DMA_STREAM_6
1701 * @arg @ref LL_DMA_STREAM_7
1702 * @retval Returned value can be one of the following values:
1703 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1704 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1705 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1706 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1707 */
LL_DMA_GetFIFOThreshold(DMA_TypeDef * DMAx,uint32_t Stream)1708 __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
1709 {
1710 uint32_t dma_base_addr = (uint32_t)DMAx;
1711
1712 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH));
1713 }
1714
1715 /**
1716 * @brief Configure the FIFO .
1717 * @rmtoll FCR FTH LL_DMA_ConfigFifo\n
1718 * FCR DMDIS LL_DMA_ConfigFifo
1719 * @param DMAx DMAx Instance
1720 * @param Stream This parameter can be one of the following values:
1721 * @arg @ref LL_DMA_STREAM_0
1722 * @arg @ref LL_DMA_STREAM_1
1723 * @arg @ref LL_DMA_STREAM_2
1724 * @arg @ref LL_DMA_STREAM_3
1725 * @arg @ref LL_DMA_STREAM_4
1726 * @arg @ref LL_DMA_STREAM_5
1727 * @arg @ref LL_DMA_STREAM_6
1728 * @arg @ref LL_DMA_STREAM_7
1729 * @param FifoMode This parameter can be one of the following values:
1730 * @arg @ref LL_DMA_FIFOMODE_ENABLE
1731 * @arg @ref LL_DMA_FIFOMODE_DISABLE
1732 * @param FifoThreshold This parameter can be one of the following values:
1733 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1734 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1735 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1736 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1737 * @retval None
1738 */
LL_DMA_ConfigFifo(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t FifoMode,uint32_t FifoThreshold)1739 __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
1740 {
1741 uint32_t dma_base_addr = (uint32_t)DMAx;
1742
1743 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH | DMA_SxFCR_DMDIS, FifoMode | FifoThreshold);
1744 }
1745
1746 /**
1747 * @brief Configure the Source and Destination addresses.
1748 * @note This API must not be called when the DMA stream is enabled.
1749 * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
1750 * PAR PA LL_DMA_ConfigAddresses
1751 * @param DMAx DMAx Instance
1752 * @param Stream This parameter can be one of the following values:
1753 * @arg @ref LL_DMA_STREAM_0
1754 * @arg @ref LL_DMA_STREAM_1
1755 * @arg @ref LL_DMA_STREAM_2
1756 * @arg @ref LL_DMA_STREAM_3
1757 * @arg @ref LL_DMA_STREAM_4
1758 * @arg @ref LL_DMA_STREAM_5
1759 * @arg @ref LL_DMA_STREAM_6
1760 * @arg @ref LL_DMA_STREAM_7
1761 * @param SrcAddress Between 0 to 0xFFFFFFFF
1762 * @param DstAddress Between 0 to 0xFFFFFFFF
1763 * @param Direction This parameter can be one of the following values:
1764 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1765 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1766 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1767 * @retval None
1768 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)1769 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
1770 {
1771 uint32_t dma_base_addr = (uint32_t)DMAx;
1772
1773 /* Direction Memory to Periph */
1774 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
1775 {
1776 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, SrcAddress);
1777 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, DstAddress);
1778 }
1779 /* Direction Periph to Memory and Memory to Memory */
1780 else
1781 {
1782 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, SrcAddress);
1783 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, DstAddress);
1784 }
1785 }
1786
1787 /**
1788 * @brief Set the Memory address.
1789 * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
1790 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1791 * @note This API must not be called when the DMA stream is enabled.
1792 * @param DMAx DMAx Instance
1793 * @param Stream This parameter can be one of the following values:
1794 * @arg @ref LL_DMA_STREAM_0
1795 * @arg @ref LL_DMA_STREAM_1
1796 * @arg @ref LL_DMA_STREAM_2
1797 * @arg @ref LL_DMA_STREAM_3
1798 * @arg @ref LL_DMA_STREAM_4
1799 * @arg @ref LL_DMA_STREAM_5
1800 * @arg @ref LL_DMA_STREAM_6
1801 * @arg @ref LL_DMA_STREAM_7
1802 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1803 * @retval None
1804 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t MemoryAddress)1805 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
1806 {
1807 uint32_t dma_base_addr = (uint32_t)DMAx;
1808
1809 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
1810 }
1811
1812 /**
1813 * @brief Set the Peripheral address.
1814 * @rmtoll PAR PA LL_DMA_SetPeriphAddress
1815 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1816 * @note This API must not be called when the DMA stream is enabled.
1817 * @param DMAx DMAx Instance
1818 * @param Stream This parameter can be one of the following values:
1819 * @arg @ref LL_DMA_STREAM_0
1820 * @arg @ref LL_DMA_STREAM_1
1821 * @arg @ref LL_DMA_STREAM_2
1822 * @arg @ref LL_DMA_STREAM_3
1823 * @arg @ref LL_DMA_STREAM_4
1824 * @arg @ref LL_DMA_STREAM_5
1825 * @arg @ref LL_DMA_STREAM_6
1826 * @arg @ref LL_DMA_STREAM_7
1827 * @param PeriphAddress Between 0 to 0xFFFFFFFF
1828 * @retval None
1829 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t PeriphAddress)1830 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress)
1831 {
1832 uint32_t dma_base_addr = (uint32_t)DMAx;
1833
1834 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddress);
1835 }
1836
1837 /**
1838 * @brief Get the Memory address.
1839 * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
1840 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1841 * @param DMAx DMAx Instance
1842 * @param Stream This parameter can be one of the following values:
1843 * @arg @ref LL_DMA_STREAM_0
1844 * @arg @ref LL_DMA_STREAM_1
1845 * @arg @ref LL_DMA_STREAM_2
1846 * @arg @ref LL_DMA_STREAM_3
1847 * @arg @ref LL_DMA_STREAM_4
1848 * @arg @ref LL_DMA_STREAM_5
1849 * @arg @ref LL_DMA_STREAM_6
1850 * @arg @ref LL_DMA_STREAM_7
1851 * @retval Between 0 to 0xFFFFFFFF
1852 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Stream)1853 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream)
1854 {
1855 uint32_t dma_base_addr = (uint32_t)DMAx;
1856
1857 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
1858 }
1859
1860 /**
1861 * @brief Get the Peripheral address.
1862 * @rmtoll PAR PA LL_DMA_GetPeriphAddress
1863 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1864 * @param DMAx DMAx Instance
1865 * @param Stream This parameter can be one of the following values:
1866 * @arg @ref LL_DMA_STREAM_0
1867 * @arg @ref LL_DMA_STREAM_1
1868 * @arg @ref LL_DMA_STREAM_2
1869 * @arg @ref LL_DMA_STREAM_3
1870 * @arg @ref LL_DMA_STREAM_4
1871 * @arg @ref LL_DMA_STREAM_5
1872 * @arg @ref LL_DMA_STREAM_6
1873 * @arg @ref LL_DMA_STREAM_7
1874 * @retval Between 0 to 0xFFFFFFFF
1875 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Stream)1876 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream)
1877 {
1878 uint32_t dma_base_addr = (uint32_t)DMAx;
1879
1880 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
1881 }
1882
1883 /**
1884 * @brief Set the Memory to Memory Source address.
1885 * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
1886 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1887 * @note This API must not be called when the DMA stream is enabled.
1888 * @param DMAx DMAx Instance
1889 * @param Stream This parameter can be one of the following values:
1890 * @arg @ref LL_DMA_STREAM_0
1891 * @arg @ref LL_DMA_STREAM_1
1892 * @arg @ref LL_DMA_STREAM_2
1893 * @arg @ref LL_DMA_STREAM_3
1894 * @arg @ref LL_DMA_STREAM_4
1895 * @arg @ref LL_DMA_STREAM_5
1896 * @arg @ref LL_DMA_STREAM_6
1897 * @arg @ref LL_DMA_STREAM_7
1898 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1899 * @retval None
1900 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t MemoryAddress)1901 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
1902 {
1903 uint32_t dma_base_addr = (uint32_t)DMAx;
1904
1905 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddress);
1906 }
1907
1908 /**
1909 * @brief Set the Memory to Memory Destination address.
1910 * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
1911 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1912 * @note This API must not be called when the DMA stream is enabled.
1913 * @param DMAx DMAx Instance
1914 * @param Stream This parameter can be one of the following values:
1915 * @arg @ref LL_DMA_STREAM_0
1916 * @arg @ref LL_DMA_STREAM_1
1917 * @arg @ref LL_DMA_STREAM_2
1918 * @arg @ref LL_DMA_STREAM_3
1919 * @arg @ref LL_DMA_STREAM_4
1920 * @arg @ref LL_DMA_STREAM_5
1921 * @arg @ref LL_DMA_STREAM_6
1922 * @arg @ref LL_DMA_STREAM_7
1923 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1924 * @retval None
1925 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t MemoryAddress)1926 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
1927 {
1928 uint32_t dma_base_addr = (uint32_t)DMAx;
1929
1930 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
1931 }
1932
1933 /**
1934 * @brief Get the Memory to Memory Source address.
1935 * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
1936 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1937 * @param DMAx DMAx Instance
1938 * @param Stream This parameter can be one of the following values:
1939 * @arg @ref LL_DMA_STREAM_0
1940 * @arg @ref LL_DMA_STREAM_1
1941 * @arg @ref LL_DMA_STREAM_2
1942 * @arg @ref LL_DMA_STREAM_3
1943 * @arg @ref LL_DMA_STREAM_4
1944 * @arg @ref LL_DMA_STREAM_5
1945 * @arg @ref LL_DMA_STREAM_6
1946 * @arg @ref LL_DMA_STREAM_7
1947 * @retval Between 0 to 0xFFFFFFFF
1948 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Stream)1949 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream)
1950 {
1951 uint32_t dma_base_addr = (uint32_t)DMAx;
1952
1953 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
1954 }
1955
1956 /**
1957 * @brief Get the Memory to Memory Destination address.
1958 * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
1959 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1960 * @param DMAx DMAx Instance
1961 * @param Stream This parameter can be one of the following values:
1962 * @arg @ref LL_DMA_STREAM_0
1963 * @arg @ref LL_DMA_STREAM_1
1964 * @arg @ref LL_DMA_STREAM_2
1965 * @arg @ref LL_DMA_STREAM_3
1966 * @arg @ref LL_DMA_STREAM_4
1967 * @arg @ref LL_DMA_STREAM_5
1968 * @arg @ref LL_DMA_STREAM_6
1969 * @arg @ref LL_DMA_STREAM_7
1970 * @retval Between 0 to 0xFFFFFFFF
1971 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Stream)1972 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream)
1973 {
1974 uint32_t dma_base_addr = (uint32_t)DMAx;
1975
1976 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
1977 }
1978
1979 /**
1980 * @brief Set Memory 1 address (used in case of Double buffer mode).
1981 * @rmtoll M1AR M1A LL_DMA_SetMemory1Address
1982 * @param DMAx DMAx Instance
1983 * @param Stream This parameter can be one of the following values:
1984 * @arg @ref LL_DMA_STREAM_0
1985 * @arg @ref LL_DMA_STREAM_1
1986 * @arg @ref LL_DMA_STREAM_2
1987 * @arg @ref LL_DMA_STREAM_3
1988 * @arg @ref LL_DMA_STREAM_4
1989 * @arg @ref LL_DMA_STREAM_5
1990 * @arg @ref LL_DMA_STREAM_6
1991 * @arg @ref LL_DMA_STREAM_7
1992 * @param Address Between 0 to 0xFFFFFFFF
1993 * @retval None
1994 */
LL_DMA_SetMemory1Address(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Address)1995 __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
1996 {
1997 uint32_t dma_base_addr = (uint32_t)DMAx;
1998
1999 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR, DMA_SxM1AR_M1A, Address);
2000 }
2001
2002 /**
2003 * @brief Get Memory 1 address (used in case of Double buffer mode).
2004 * @rmtoll M1AR M1A LL_DMA_GetMemory1Address
2005 * @param DMAx DMAx Instance
2006 * @param Stream This parameter can be one of the following values:
2007 * @arg @ref LL_DMA_STREAM_0
2008 * @arg @ref LL_DMA_STREAM_1
2009 * @arg @ref LL_DMA_STREAM_2
2010 * @arg @ref LL_DMA_STREAM_3
2011 * @arg @ref LL_DMA_STREAM_4
2012 * @arg @ref LL_DMA_STREAM_5
2013 * @arg @ref LL_DMA_STREAM_6
2014 * @arg @ref LL_DMA_STREAM_7
2015 * @retval Between 0 to 0xFFFFFFFF
2016 */
LL_DMA_GetMemory1Address(DMA_TypeDef * DMAx,uint32_t Stream)2017 __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
2018 {
2019 uint32_t dma_base_addr = (uint32_t)DMAx;
2020
2021 return (((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR);
2022 }
2023
2024 /**
2025 * @}
2026 */
2027
2028 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
2029 * @{
2030 */
2031
2032 /**
2033 * @brief Get Stream 0 half transfer flag.
2034 * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
2035 * @param DMAx DMAx Instance
2036 * @retval State of bit (1 or 0).
2037 */
LL_DMA_IsActiveFlag_HT0(DMA_TypeDef * DMAx)2038 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
2039 {
2040 return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL);
2041 }
2042
2043 /**
2044 * @brief Get Stream 1 half transfer flag.
2045 * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
2046 * @param DMAx DMAx Instance
2047 * @retval State of bit (1 or 0).
2048 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)2049 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
2050 {
2051 return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL);
2052 }
2053
2054 /**
2055 * @brief Get Stream 2 half transfer flag.
2056 * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
2057 * @param DMAx DMAx Instance
2058 * @retval State of bit (1 or 0).
2059 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)2060 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
2061 {
2062 return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL);
2063 }
2064
2065 /**
2066 * @brief Get Stream 3 half transfer flag.
2067 * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
2068 * @param DMAx DMAx Instance
2069 * @retval State of bit (1 or 0).
2070 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)2071 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
2072 {
2073 return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL);
2074 }
2075
2076 /**
2077 * @brief Get Stream 4 half transfer flag.
2078 * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
2079 * @param DMAx DMAx Instance
2080 * @retval State of bit (1 or 0).
2081 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)2082 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
2083 {
2084 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL);
2085 }
2086
2087 /**
2088 * @brief Get Stream 5 half transfer flag.
2089 * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
2090 * @param DMAx DMAx Instance
2091 * @retval State of bit (1 or 0).
2092 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)2093 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
2094 {
2095 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL);
2096 }
2097
2098 /**
2099 * @brief Get Stream 6 half transfer flag.
2100 * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
2101 * @param DMAx DMAx Instance
2102 * @retval State of bit (1 or 0).
2103 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)2104 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
2105 {
2106 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL);
2107 }
2108
2109 /**
2110 * @brief Get Stream 7 half transfer flag.
2111 * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
2112 * @param DMAx DMAx Instance
2113 * @retval State of bit (1 or 0).
2114 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)2115 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
2116 {
2117 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL);
2118 }
2119
2120 /**
2121 * @brief Get Stream 0 transfer complete flag.
2122 * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
2123 * @param DMAx DMAx Instance
2124 * @retval State of bit (1 or 0).
2125 */
LL_DMA_IsActiveFlag_TC0(DMA_TypeDef * DMAx)2126 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
2127 {
2128 return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL);
2129 }
2130
2131 /**
2132 * @brief Get Stream 1 transfer complete flag.
2133 * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
2134 * @param DMAx DMAx Instance
2135 * @retval State of bit (1 or 0).
2136 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)2137 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
2138 {
2139 return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL);
2140 }
2141
2142 /**
2143 * @brief Get Stream 2 transfer complete flag.
2144 * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
2145 * @param DMAx DMAx Instance
2146 * @retval State of bit (1 or 0).
2147 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)2148 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
2149 {
2150 return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL);
2151 }
2152
2153 /**
2154 * @brief Get Stream 3 transfer complete flag.
2155 * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
2156 * @param DMAx DMAx Instance
2157 * @retval State of bit (1 or 0).
2158 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)2159 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
2160 {
2161 return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL);
2162 }
2163
2164 /**
2165 * @brief Get Stream 4 transfer complete flag.
2166 * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
2167 * @param DMAx DMAx Instance
2168 * @retval State of bit (1 or 0).
2169 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)2170 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
2171 {
2172 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL);
2173 }
2174
2175 /**
2176 * @brief Get Stream 5 transfer complete flag.
2177 * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
2178 * @param DMAx DMAx Instance
2179 * @retval State of bit (1 or 0).
2180 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)2181 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
2182 {
2183 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL);
2184 }
2185
2186 /**
2187 * @brief Get Stream 6 transfer complete flag.
2188 * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
2189 * @param DMAx DMAx Instance
2190 * @retval State of bit (1 or 0).
2191 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)2192 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
2193 {
2194 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL);
2195 }
2196
2197 /**
2198 * @brief Get Stream 7 transfer complete flag.
2199 * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
2200 * @param DMAx DMAx Instance
2201 * @retval State of bit (1 or 0).
2202 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)2203 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
2204 {
2205 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL);
2206 }
2207
2208 /**
2209 * @brief Get Stream 0 transfer error flag.
2210 * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
2211 * @param DMAx DMAx Instance
2212 * @retval State of bit (1 or 0).
2213 */
LL_DMA_IsActiveFlag_TE0(DMA_TypeDef * DMAx)2214 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
2215 {
2216 return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL);
2217 }
2218
2219 /**
2220 * @brief Get Stream 1 transfer error flag.
2221 * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
2222 * @param DMAx DMAx Instance
2223 * @retval State of bit (1 or 0).
2224 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)2225 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
2226 {
2227 return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL);
2228 }
2229
2230 /**
2231 * @brief Get Stream 2 transfer error flag.
2232 * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
2233 * @param DMAx DMAx Instance
2234 * @retval State of bit (1 or 0).
2235 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)2236 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
2237 {
2238 return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL);
2239 }
2240
2241 /**
2242 * @brief Get Stream 3 transfer error flag.
2243 * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
2244 * @param DMAx DMAx Instance
2245 * @retval State of bit (1 or 0).
2246 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)2247 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
2248 {
2249 return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL);
2250 }
2251
2252 /**
2253 * @brief Get Stream 4 transfer error flag.
2254 * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
2255 * @param DMAx DMAx Instance
2256 * @retval State of bit (1 or 0).
2257 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)2258 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
2259 {
2260 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL);
2261 }
2262
2263 /**
2264 * @brief Get Stream 5 transfer error flag.
2265 * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
2266 * @param DMAx DMAx Instance
2267 * @retval State of bit (1 or 0).
2268 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)2269 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
2270 {
2271 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL);
2272 }
2273
2274 /**
2275 * @brief Get Stream 6 transfer error flag.
2276 * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
2277 * @param DMAx DMAx Instance
2278 * @retval State of bit (1 or 0).
2279 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)2280 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
2281 {
2282 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL);
2283 }
2284
2285 /**
2286 * @brief Get Stream 7 transfer error flag.
2287 * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
2288 * @param DMAx DMAx Instance
2289 * @retval State of bit (1 or 0).
2290 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)2291 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
2292 {
2293 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL);
2294 }
2295
2296 /**
2297 * @brief Get Stream 0 direct mode error flag.
2298 * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
2299 * @param DMAx DMAx Instance
2300 * @retval State of bit (1 or 0).
2301 */
LL_DMA_IsActiveFlag_DME0(DMA_TypeDef * DMAx)2302 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
2303 {
2304 return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL);
2305 }
2306
2307 /**
2308 * @brief Get Stream 1 direct mode error flag.
2309 * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
2310 * @param DMAx DMAx Instance
2311 * @retval State of bit (1 or 0).
2312 */
LL_DMA_IsActiveFlag_DME1(DMA_TypeDef * DMAx)2313 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
2314 {
2315 return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL);
2316 }
2317
2318 /**
2319 * @brief Get Stream 2 direct mode error flag.
2320 * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
2321 * @param DMAx DMAx Instance
2322 * @retval State of bit (1 or 0).
2323 */
LL_DMA_IsActiveFlag_DME2(DMA_TypeDef * DMAx)2324 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
2325 {
2326 return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL);
2327 }
2328
2329 /**
2330 * @brief Get Stream 3 direct mode error flag.
2331 * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
2332 * @param DMAx DMAx Instance
2333 * @retval State of bit (1 or 0).
2334 */
LL_DMA_IsActiveFlag_DME3(DMA_TypeDef * DMAx)2335 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
2336 {
2337 return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL);
2338 }
2339
2340 /**
2341 * @brief Get Stream 4 direct mode error flag.
2342 * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
2343 * @param DMAx DMAx Instance
2344 * @retval State of bit (1 or 0).
2345 */
LL_DMA_IsActiveFlag_DME4(DMA_TypeDef * DMAx)2346 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
2347 {
2348 return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL);
2349 }
2350
2351 /**
2352 * @brief Get Stream 5 direct mode error flag.
2353 * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
2354 * @param DMAx DMAx Instance
2355 * @retval State of bit (1 or 0).
2356 */
LL_DMA_IsActiveFlag_DME5(DMA_TypeDef * DMAx)2357 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
2358 {
2359 return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL);
2360 }
2361
2362 /**
2363 * @brief Get Stream 6 direct mode error flag.
2364 * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
2365 * @param DMAx DMAx Instance
2366 * @retval State of bit (1 or 0).
2367 */
LL_DMA_IsActiveFlag_DME6(DMA_TypeDef * DMAx)2368 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
2369 {
2370 return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL);
2371 }
2372
2373 /**
2374 * @brief Get Stream 7 direct mode error flag.
2375 * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
2376 * @param DMAx DMAx Instance
2377 * @retval State of bit (1 or 0).
2378 */
LL_DMA_IsActiveFlag_DME7(DMA_TypeDef * DMAx)2379 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
2380 {
2381 return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL);
2382 }
2383
2384 /**
2385 * @brief Get Stream 0 FIFO error flag.
2386 * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
2387 * @param DMAx DMAx Instance
2388 * @retval State of bit (1 or 0).
2389 */
LL_DMA_IsActiveFlag_FE0(DMA_TypeDef * DMAx)2390 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
2391 {
2392 return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL);
2393 }
2394
2395 /**
2396 * @brief Get Stream 1 FIFO error flag.
2397 * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
2398 * @param DMAx DMAx Instance
2399 * @retval State of bit (1 or 0).
2400 */
LL_DMA_IsActiveFlag_FE1(DMA_TypeDef * DMAx)2401 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
2402 {
2403 return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL);
2404 }
2405
2406 /**
2407 * @brief Get Stream 2 FIFO error flag.
2408 * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
2409 * @param DMAx DMAx Instance
2410 * @retval State of bit (1 or 0).
2411 */
LL_DMA_IsActiveFlag_FE2(DMA_TypeDef * DMAx)2412 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
2413 {
2414 return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL);
2415 }
2416
2417 /**
2418 * @brief Get Stream 3 FIFO error flag.
2419 * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
2420 * @param DMAx DMAx Instance
2421 * @retval State of bit (1 or 0).
2422 */
LL_DMA_IsActiveFlag_FE3(DMA_TypeDef * DMAx)2423 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
2424 {
2425 return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL);
2426 }
2427
2428 /**
2429 * @brief Get Stream 4 FIFO error flag.
2430 * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
2431 * @param DMAx DMAx Instance
2432 * @retval State of bit (1 or 0).
2433 */
LL_DMA_IsActiveFlag_FE4(DMA_TypeDef * DMAx)2434 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
2435 {
2436 return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL);
2437 }
2438
2439 /**
2440 * @brief Get Stream 5 FIFO error flag.
2441 * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
2442 * @param DMAx DMAx Instance
2443 * @retval State of bit (1 or 0).
2444 */
LL_DMA_IsActiveFlag_FE5(DMA_TypeDef * DMAx)2445 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
2446 {
2447 return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL);
2448 }
2449
2450 /**
2451 * @brief Get Stream 6 FIFO error flag.
2452 * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
2453 * @param DMAx DMAx Instance
2454 * @retval State of bit (1 or 0).
2455 */
LL_DMA_IsActiveFlag_FE6(DMA_TypeDef * DMAx)2456 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
2457 {
2458 return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL);
2459 }
2460
2461 /**
2462 * @brief Get Stream 7 FIFO error flag.
2463 * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
2464 * @param DMAx DMAx Instance
2465 * @retval State of bit (1 or 0).
2466 */
LL_DMA_IsActiveFlag_FE7(DMA_TypeDef * DMAx)2467 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
2468 {
2469 return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL);
2470 }
2471
2472 /**
2473 * @brief Clear Stream 0 half transfer flag.
2474 * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
2475 * @param DMAx DMAx Instance
2476 * @retval None
2477 */
LL_DMA_ClearFlag_HT0(DMA_TypeDef * DMAx)2478 __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
2479 {
2480 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF0);
2481 }
2482
2483 /**
2484 * @brief Clear Stream 1 half transfer flag.
2485 * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
2486 * @param DMAx DMAx Instance
2487 * @retval None
2488 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)2489 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
2490 {
2491 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF1);
2492 }
2493
2494 /**
2495 * @brief Clear Stream 2 half transfer flag.
2496 * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
2497 * @param DMAx DMAx Instance
2498 * @retval None
2499 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)2500 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
2501 {
2502 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF2);
2503 }
2504
2505 /**
2506 * @brief Clear Stream 3 half transfer flag.
2507 * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
2508 * @param DMAx DMAx Instance
2509 * @retval None
2510 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)2511 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
2512 {
2513 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF3);
2514 }
2515
2516 /**
2517 * @brief Clear Stream 4 half transfer flag.
2518 * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
2519 * @param DMAx DMAx Instance
2520 * @retval None
2521 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)2522 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
2523 {
2524 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF4);
2525 }
2526
2527 /**
2528 * @brief Clear Stream 5 half transfer flag.
2529 * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
2530 * @param DMAx DMAx Instance
2531 * @retval None
2532 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)2533 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
2534 {
2535 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF5);
2536 }
2537
2538 /**
2539 * @brief Clear Stream 6 half transfer flag.
2540 * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
2541 * @param DMAx DMAx Instance
2542 * @retval None
2543 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)2544 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
2545 {
2546 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF6);
2547 }
2548
2549 /**
2550 * @brief Clear Stream 7 half transfer flag.
2551 * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
2552 * @param DMAx DMAx Instance
2553 * @retval None
2554 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)2555 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
2556 {
2557 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF7);
2558 }
2559
2560 /**
2561 * @brief Clear Stream 0 transfer complete flag.
2562 * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
2563 * @param DMAx DMAx Instance
2564 * @retval None
2565 */
LL_DMA_ClearFlag_TC0(DMA_TypeDef * DMAx)2566 __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
2567 {
2568 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF0);
2569 }
2570
2571 /**
2572 * @brief Clear Stream 1 transfer complete flag.
2573 * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
2574 * @param DMAx DMAx Instance
2575 * @retval None
2576 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)2577 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
2578 {
2579 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF1);
2580 }
2581
2582 /**
2583 * @brief Clear Stream 2 transfer complete flag.
2584 * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
2585 * @param DMAx DMAx Instance
2586 * @retval None
2587 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)2588 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
2589 {
2590 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF2);
2591 }
2592
2593 /**
2594 * @brief Clear Stream 3 transfer complete flag.
2595 * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
2596 * @param DMAx DMAx Instance
2597 * @retval None
2598 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)2599 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
2600 {
2601 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF3);
2602 }
2603
2604 /**
2605 * @brief Clear Stream 4 transfer complete flag.
2606 * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
2607 * @param DMAx DMAx Instance
2608 * @retval None
2609 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)2610 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
2611 {
2612 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF4);
2613 }
2614
2615 /**
2616 * @brief Clear Stream 5 transfer complete flag.
2617 * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
2618 * @param DMAx DMAx Instance
2619 * @retval None
2620 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)2621 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
2622 {
2623 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF5);
2624 }
2625
2626 /**
2627 * @brief Clear Stream 6 transfer complete flag.
2628 * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
2629 * @param DMAx DMAx Instance
2630 * @retval None
2631 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)2632 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
2633 {
2634 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF6);
2635 }
2636
2637 /**
2638 * @brief Clear Stream 7 transfer complete flag.
2639 * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
2640 * @param DMAx DMAx Instance
2641 * @retval None
2642 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)2643 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
2644 {
2645 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF7);
2646 }
2647
2648 /**
2649 * @brief Clear Stream 0 transfer error flag.
2650 * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
2651 * @param DMAx DMAx Instance
2652 * @retval None
2653 */
LL_DMA_ClearFlag_TE0(DMA_TypeDef * DMAx)2654 __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
2655 {
2656 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF0);
2657 }
2658
2659 /**
2660 * @brief Clear Stream 1 transfer error flag.
2661 * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
2662 * @param DMAx DMAx Instance
2663 * @retval None
2664 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)2665 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
2666 {
2667 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF1);
2668 }
2669
2670 /**
2671 * @brief Clear Stream 2 transfer error flag.
2672 * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
2673 * @param DMAx DMAx Instance
2674 * @retval None
2675 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)2676 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
2677 {
2678 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF2);
2679 }
2680
2681 /**
2682 * @brief Clear Stream 3 transfer error flag.
2683 * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
2684 * @param DMAx DMAx Instance
2685 * @retval None
2686 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)2687 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
2688 {
2689 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF3);
2690 }
2691
2692 /**
2693 * @brief Clear Stream 4 transfer error flag.
2694 * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
2695 * @param DMAx DMAx Instance
2696 * @retval None
2697 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)2698 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
2699 {
2700 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF4);
2701 }
2702
2703 /**
2704 * @brief Clear Stream 5 transfer error flag.
2705 * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
2706 * @param DMAx DMAx Instance
2707 * @retval None
2708 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)2709 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
2710 {
2711 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF5);
2712 }
2713
2714 /**
2715 * @brief Clear Stream 6 transfer error flag.
2716 * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
2717 * @param DMAx DMAx Instance
2718 * @retval None
2719 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)2720 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
2721 {
2722 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF6);
2723 }
2724
2725 /**
2726 * @brief Clear Stream 7 transfer error flag.
2727 * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
2728 * @param DMAx DMAx Instance
2729 * @retval None
2730 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)2731 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
2732 {
2733 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF7);
2734 }
2735
2736 /**
2737 * @brief Clear Stream 0 direct mode error flag.
2738 * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
2739 * @param DMAx DMAx Instance
2740 * @retval None
2741 */
LL_DMA_ClearFlag_DME0(DMA_TypeDef * DMAx)2742 __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
2743 {
2744 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF0);
2745 }
2746
2747 /**
2748 * @brief Clear Stream 1 direct mode error flag.
2749 * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
2750 * @param DMAx DMAx Instance
2751 * @retval None
2752 */
LL_DMA_ClearFlag_DME1(DMA_TypeDef * DMAx)2753 __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
2754 {
2755 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF1);
2756 }
2757
2758 /**
2759 * @brief Clear Stream 2 direct mode error flag.
2760 * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
2761 * @param DMAx DMAx Instance
2762 * @retval None
2763 */
LL_DMA_ClearFlag_DME2(DMA_TypeDef * DMAx)2764 __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
2765 {
2766 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF2);
2767 }
2768
2769 /**
2770 * @brief Clear Stream 3 direct mode error flag.
2771 * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
2772 * @param DMAx DMAx Instance
2773 * @retval None
2774 */
LL_DMA_ClearFlag_DME3(DMA_TypeDef * DMAx)2775 __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
2776 {
2777 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF3);
2778 }
2779
2780 /**
2781 * @brief Clear Stream 4 direct mode error flag.
2782 * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
2783 * @param DMAx DMAx Instance
2784 * @retval None
2785 */
LL_DMA_ClearFlag_DME4(DMA_TypeDef * DMAx)2786 __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
2787 {
2788 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF4);
2789 }
2790
2791 /**
2792 * @brief Clear Stream 5 direct mode error flag.
2793 * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
2794 * @param DMAx DMAx Instance
2795 * @retval None
2796 */
LL_DMA_ClearFlag_DME5(DMA_TypeDef * DMAx)2797 __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
2798 {
2799 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF5);
2800 }
2801
2802 /**
2803 * @brief Clear Stream 6 direct mode error flag.
2804 * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
2805 * @param DMAx DMAx Instance
2806 * @retval None
2807 */
LL_DMA_ClearFlag_DME6(DMA_TypeDef * DMAx)2808 __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
2809 {
2810 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF6);
2811 }
2812
2813 /**
2814 * @brief Clear Stream 7 direct mode error flag.
2815 * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
2816 * @param DMAx DMAx Instance
2817 * @retval None
2818 */
LL_DMA_ClearFlag_DME7(DMA_TypeDef * DMAx)2819 __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
2820 {
2821 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF7);
2822 }
2823
2824 /**
2825 * @brief Clear Stream 0 FIFO error flag.
2826 * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
2827 * @param DMAx DMAx Instance
2828 * @retval None
2829 */
LL_DMA_ClearFlag_FE0(DMA_TypeDef * DMAx)2830 __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
2831 {
2832 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF0);
2833 }
2834
2835 /**
2836 * @brief Clear Stream 1 FIFO error flag.
2837 * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
2838 * @param DMAx DMAx Instance
2839 * @retval None
2840 */
LL_DMA_ClearFlag_FE1(DMA_TypeDef * DMAx)2841 __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
2842 {
2843 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF1);
2844 }
2845
2846 /**
2847 * @brief Clear Stream 2 FIFO error flag.
2848 * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
2849 * @param DMAx DMAx Instance
2850 * @retval None
2851 */
LL_DMA_ClearFlag_FE2(DMA_TypeDef * DMAx)2852 __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
2853 {
2854 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF2);
2855 }
2856
2857 /**
2858 * @brief Clear Stream 3 FIFO error flag.
2859 * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
2860 * @param DMAx DMAx Instance
2861 * @retval None
2862 */
LL_DMA_ClearFlag_FE3(DMA_TypeDef * DMAx)2863 __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
2864 {
2865 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF3);
2866 }
2867
2868 /**
2869 * @brief Clear Stream 4 FIFO error flag.
2870 * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
2871 * @param DMAx DMAx Instance
2872 * @retval None
2873 */
LL_DMA_ClearFlag_FE4(DMA_TypeDef * DMAx)2874 __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
2875 {
2876 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF4);
2877 }
2878
2879 /**
2880 * @brief Clear Stream 5 FIFO error flag.
2881 * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
2882 * @param DMAx DMAx Instance
2883 * @retval None
2884 */
LL_DMA_ClearFlag_FE5(DMA_TypeDef * DMAx)2885 __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
2886 {
2887 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF5);
2888 }
2889
2890 /**
2891 * @brief Clear Stream 6 FIFO error flag.
2892 * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
2893 * @param DMAx DMAx Instance
2894 * @retval None
2895 */
LL_DMA_ClearFlag_FE6(DMA_TypeDef * DMAx)2896 __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
2897 {
2898 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF6);
2899 }
2900
2901 /**
2902 * @brief Clear Stream 7 FIFO error flag.
2903 * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
2904 * @param DMAx DMAx Instance
2905 * @retval None
2906 */
LL_DMA_ClearFlag_FE7(DMA_TypeDef * DMAx)2907 __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
2908 {
2909 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF7);
2910 }
2911
2912 /**
2913 * @}
2914 */
2915
2916 /** @defgroup DMA_LL_EF_IT_Management IT_Management
2917 * @{
2918 */
2919
2920 /**
2921 * @brief Enable Half transfer interrupt.
2922 * @rmtoll CR HTIE LL_DMA_EnableIT_HT
2923 * @param DMAx DMAx Instance
2924 * @param Stream This parameter can be one of the following values:
2925 * @arg @ref LL_DMA_STREAM_0
2926 * @arg @ref LL_DMA_STREAM_1
2927 * @arg @ref LL_DMA_STREAM_2
2928 * @arg @ref LL_DMA_STREAM_3
2929 * @arg @ref LL_DMA_STREAM_4
2930 * @arg @ref LL_DMA_STREAM_5
2931 * @arg @ref LL_DMA_STREAM_6
2932 * @arg @ref LL_DMA_STREAM_7
2933 * @retval None
2934 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Stream)2935 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2936 {
2937 uint32_t dma_base_addr = (uint32_t)DMAx;
2938
2939 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
2940 }
2941
2942 /**
2943 * @brief Enable Transfer error interrupt.
2944 * @rmtoll CR TEIE LL_DMA_EnableIT_TE
2945 * @param DMAx DMAx Instance
2946 * @param Stream This parameter can be one of the following values:
2947 * @arg @ref LL_DMA_STREAM_0
2948 * @arg @ref LL_DMA_STREAM_1
2949 * @arg @ref LL_DMA_STREAM_2
2950 * @arg @ref LL_DMA_STREAM_3
2951 * @arg @ref LL_DMA_STREAM_4
2952 * @arg @ref LL_DMA_STREAM_5
2953 * @arg @ref LL_DMA_STREAM_6
2954 * @arg @ref LL_DMA_STREAM_7
2955 * @retval None
2956 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Stream)2957 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2958 {
2959 uint32_t dma_base_addr = (uint32_t)DMAx;
2960
2961 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
2962 }
2963
2964 /**
2965 * @brief Enable Transfer complete interrupt.
2966 * @rmtoll CR TCIE LL_DMA_EnableIT_TC
2967 * @param DMAx DMAx Instance
2968 * @param Stream This parameter can be one of the following values:
2969 * @arg @ref LL_DMA_STREAM_0
2970 * @arg @ref LL_DMA_STREAM_1
2971 * @arg @ref LL_DMA_STREAM_2
2972 * @arg @ref LL_DMA_STREAM_3
2973 * @arg @ref LL_DMA_STREAM_4
2974 * @arg @ref LL_DMA_STREAM_5
2975 * @arg @ref LL_DMA_STREAM_6
2976 * @arg @ref LL_DMA_STREAM_7
2977 * @retval None
2978 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Stream)2979 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2980 {
2981 uint32_t dma_base_addr = (uint32_t)DMAx;
2982
2983 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
2984 }
2985
2986 /**
2987 * @brief Enable Direct mode error interrupt.
2988 * @rmtoll CR DMEIE LL_DMA_EnableIT_DME
2989 * @param DMAx DMAx Instance
2990 * @param Stream This parameter can be one of the following values:
2991 * @arg @ref LL_DMA_STREAM_0
2992 * @arg @ref LL_DMA_STREAM_1
2993 * @arg @ref LL_DMA_STREAM_2
2994 * @arg @ref LL_DMA_STREAM_3
2995 * @arg @ref LL_DMA_STREAM_4
2996 * @arg @ref LL_DMA_STREAM_5
2997 * @arg @ref LL_DMA_STREAM_6
2998 * @arg @ref LL_DMA_STREAM_7
2999 * @retval None
3000 */
LL_DMA_EnableIT_DME(DMA_TypeDef * DMAx,uint32_t Stream)3001 __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
3002 {
3003 uint32_t dma_base_addr = (uint32_t)DMAx;
3004
3005 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
3006 }
3007
3008 /**
3009 * @brief Enable FIFO error interrupt.
3010 * @rmtoll FCR FEIE LL_DMA_EnableIT_FE
3011 * @param DMAx DMAx Instance
3012 * @param Stream This parameter can be one of the following values:
3013 * @arg @ref LL_DMA_STREAM_0
3014 * @arg @ref LL_DMA_STREAM_1
3015 * @arg @ref LL_DMA_STREAM_2
3016 * @arg @ref LL_DMA_STREAM_3
3017 * @arg @ref LL_DMA_STREAM_4
3018 * @arg @ref LL_DMA_STREAM_5
3019 * @arg @ref LL_DMA_STREAM_6
3020 * @arg @ref LL_DMA_STREAM_7
3021 * @retval None
3022 */
LL_DMA_EnableIT_FE(DMA_TypeDef * DMAx,uint32_t Stream)3023 __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
3024 {
3025 uint32_t dma_base_addr = (uint32_t)DMAx;
3026
3027 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
3028 }
3029
3030 /**
3031 * @brief Disable Half transfer interrupt.
3032 * @rmtoll CR HTIE LL_DMA_DisableIT_HT
3033 * @param DMAx DMAx Instance
3034 * @param Stream This parameter can be one of the following values:
3035 * @arg @ref LL_DMA_STREAM_0
3036 * @arg @ref LL_DMA_STREAM_1
3037 * @arg @ref LL_DMA_STREAM_2
3038 * @arg @ref LL_DMA_STREAM_3
3039 * @arg @ref LL_DMA_STREAM_4
3040 * @arg @ref LL_DMA_STREAM_5
3041 * @arg @ref LL_DMA_STREAM_6
3042 * @arg @ref LL_DMA_STREAM_7
3043 * @retval None
3044 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Stream)3045 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
3046 {
3047 uint32_t dma_base_addr = (uint32_t)DMAx;
3048
3049 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
3050 }
3051
3052 /**
3053 * @brief Disable Transfer error interrupt.
3054 * @rmtoll CR TEIE LL_DMA_DisableIT_TE
3055 * @param DMAx DMAx Instance
3056 * @param Stream This parameter can be one of the following values:
3057 * @arg @ref LL_DMA_STREAM_0
3058 * @arg @ref LL_DMA_STREAM_1
3059 * @arg @ref LL_DMA_STREAM_2
3060 * @arg @ref LL_DMA_STREAM_3
3061 * @arg @ref LL_DMA_STREAM_4
3062 * @arg @ref LL_DMA_STREAM_5
3063 * @arg @ref LL_DMA_STREAM_6
3064 * @arg @ref LL_DMA_STREAM_7
3065 * @retval None
3066 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Stream)3067 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
3068 {
3069 uint32_t dma_base_addr = (uint32_t)DMAx;
3070
3071 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
3072 }
3073
3074 /**
3075 * @brief Disable Transfer complete interrupt.
3076 * @rmtoll CR TCIE LL_DMA_DisableIT_TC
3077 * @param DMAx DMAx Instance
3078 * @param Stream This parameter can be one of the following values:
3079 * @arg @ref LL_DMA_STREAM_0
3080 * @arg @ref LL_DMA_STREAM_1
3081 * @arg @ref LL_DMA_STREAM_2
3082 * @arg @ref LL_DMA_STREAM_3
3083 * @arg @ref LL_DMA_STREAM_4
3084 * @arg @ref LL_DMA_STREAM_5
3085 * @arg @ref LL_DMA_STREAM_6
3086 * @arg @ref LL_DMA_STREAM_7
3087 * @retval None
3088 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Stream)3089 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
3090 {
3091 uint32_t dma_base_addr = (uint32_t)DMAx;
3092
3093 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
3094 }
3095
3096 /**
3097 * @brief Disable Direct mode error interrupt.
3098 * @rmtoll CR DMEIE LL_DMA_DisableIT_DME
3099 * @param DMAx DMAx Instance
3100 * @param Stream This parameter can be one of the following values:
3101 * @arg @ref LL_DMA_STREAM_0
3102 * @arg @ref LL_DMA_STREAM_1
3103 * @arg @ref LL_DMA_STREAM_2
3104 * @arg @ref LL_DMA_STREAM_3
3105 * @arg @ref LL_DMA_STREAM_4
3106 * @arg @ref LL_DMA_STREAM_5
3107 * @arg @ref LL_DMA_STREAM_6
3108 * @arg @ref LL_DMA_STREAM_7
3109 * @retval None
3110 */
LL_DMA_DisableIT_DME(DMA_TypeDef * DMAx,uint32_t Stream)3111 __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
3112 {
3113 uint32_t dma_base_addr = (uint32_t)DMAx;
3114
3115 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
3116 }
3117
3118 /**
3119 * @brief Disable FIFO error interrupt.
3120 * @rmtoll FCR FEIE LL_DMA_DisableIT_FE
3121 * @param DMAx DMAx Instance
3122 * @param Stream This parameter can be one of the following values:
3123 * @arg @ref LL_DMA_STREAM_0
3124 * @arg @ref LL_DMA_STREAM_1
3125 * @arg @ref LL_DMA_STREAM_2
3126 * @arg @ref LL_DMA_STREAM_3
3127 * @arg @ref LL_DMA_STREAM_4
3128 * @arg @ref LL_DMA_STREAM_5
3129 * @arg @ref LL_DMA_STREAM_6
3130 * @arg @ref LL_DMA_STREAM_7
3131 * @retval None
3132 */
LL_DMA_DisableIT_FE(DMA_TypeDef * DMAx,uint32_t Stream)3133 __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
3134 {
3135 uint32_t dma_base_addr = (uint32_t)DMAx;
3136
3137 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
3138 }
3139
3140 /**
3141 * @brief Check if Half transfer interrupt is enabled.
3142 * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
3143 * @param DMAx DMAx Instance
3144 * @param Stream This parameter can be one of the following values:
3145 * @arg @ref LL_DMA_STREAM_0
3146 * @arg @ref LL_DMA_STREAM_1
3147 * @arg @ref LL_DMA_STREAM_2
3148 * @arg @ref LL_DMA_STREAM_3
3149 * @arg @ref LL_DMA_STREAM_4
3150 * @arg @ref LL_DMA_STREAM_5
3151 * @arg @ref LL_DMA_STREAM_6
3152 * @arg @ref LL_DMA_STREAM_7
3153 * @retval State of bit (1 or 0).
3154 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Stream)3155 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
3156 {
3157 uint32_t dma_base_addr = (uint32_t)DMAx;
3158
3159 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1UL : 0UL);
3160 }
3161
3162 /**
3163 * @brief Check if Transfer error nterrup is enabled.
3164 * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
3165 * @param DMAx DMAx Instance
3166 * @param Stream This parameter can be one of the following values:
3167 * @arg @ref LL_DMA_STREAM_0
3168 * @arg @ref LL_DMA_STREAM_1
3169 * @arg @ref LL_DMA_STREAM_2
3170 * @arg @ref LL_DMA_STREAM_3
3171 * @arg @ref LL_DMA_STREAM_4
3172 * @arg @ref LL_DMA_STREAM_5
3173 * @arg @ref LL_DMA_STREAM_6
3174 * @arg @ref LL_DMA_STREAM_7
3175 * @retval State of bit (1 or 0).
3176 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Stream)3177 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
3178 {
3179 uint32_t dma_base_addr = (uint32_t)DMAx;
3180
3181 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE) ? 1UL : 0UL);
3182 }
3183
3184 /**
3185 * @brief Check if Transfer complete interrupt is enabled.
3186 * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
3187 * @param DMAx DMAx Instance
3188 * @param Stream This parameter can be one of the following values:
3189 * @arg @ref LL_DMA_STREAM_0
3190 * @arg @ref LL_DMA_STREAM_1
3191 * @arg @ref LL_DMA_STREAM_2
3192 * @arg @ref LL_DMA_STREAM_3
3193 * @arg @ref LL_DMA_STREAM_4
3194 * @arg @ref LL_DMA_STREAM_5
3195 * @arg @ref LL_DMA_STREAM_6
3196 * @arg @ref LL_DMA_STREAM_7
3197 * @retval State of bit (1 or 0).
3198 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Stream)3199 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
3200 {
3201 uint32_t dma_base_addr = (uint32_t)DMAx;
3202
3203 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1UL : 0UL);
3204 }
3205
3206 /**
3207 * @brief Check if Direct mode error interrupt is enabled.
3208 * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
3209 * @param DMAx DMAx Instance
3210 * @param Stream This parameter can be one of the following values:
3211 * @arg @ref LL_DMA_STREAM_0
3212 * @arg @ref LL_DMA_STREAM_1
3213 * @arg @ref LL_DMA_STREAM_2
3214 * @arg @ref LL_DMA_STREAM_3
3215 * @arg @ref LL_DMA_STREAM_4
3216 * @arg @ref LL_DMA_STREAM_5
3217 * @arg @ref LL_DMA_STREAM_6
3218 * @arg @ref LL_DMA_STREAM_7
3219 * @retval State of bit (1 or 0).
3220 */
LL_DMA_IsEnabledIT_DME(DMA_TypeDef * DMAx,uint32_t Stream)3221 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
3222 {
3223 uint32_t dma_base_addr = (uint32_t)DMAx;
3224
3225 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE) ? 1UL : 0UL);
3226 }
3227
3228 /**
3229 * @brief Check if FIFO error interrupt is enabled.
3230 * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
3231 * @param DMAx DMAx Instance
3232 * @param Stream This parameter can be one of the following values:
3233 * @arg @ref LL_DMA_STREAM_0
3234 * @arg @ref LL_DMA_STREAM_1
3235 * @arg @ref LL_DMA_STREAM_2
3236 * @arg @ref LL_DMA_STREAM_3
3237 * @arg @ref LL_DMA_STREAM_4
3238 * @arg @ref LL_DMA_STREAM_5
3239 * @arg @ref LL_DMA_STREAM_6
3240 * @arg @ref LL_DMA_STREAM_7
3241 * @retval State of bit (1 or 0).
3242 */
LL_DMA_IsEnabledIT_FE(DMA_TypeDef * DMAx,uint32_t Stream)3243 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
3244 {
3245 uint32_t dma_base_addr = (uint32_t)DMAx;
3246
3247 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE) ? 1UL : 0UL);
3248 }
3249
3250 /**
3251 * @}
3252 */
3253
3254 #if defined(USE_FULL_LL_DRIVER)
3255 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
3256 * @{
3257 */
3258
3259 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
3260 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
3261 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
3262
3263 /**
3264 * @}
3265 */
3266 #endif /* USE_FULL_LL_DRIVER */
3267
3268 /**
3269 * @}
3270 */
3271
3272 /**
3273 * @}
3274 */
3275
3276 #endif /* DMA1 || DMA2 */
3277
3278 /**
3279 * @}
3280 */
3281
3282 #ifdef __cplusplus
3283 }
3284 #endif
3285
3286 #endif /* __STM32H7xx_LL_DMA_H */
3287
3288
