1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7xx_LL_DAC_H
21 #define STM32H7xx_LL_DAC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7xx.h"
29
30 /** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34 #if defined(DAC1) || defined(DAC2)
35
36 /** @defgroup DAC_LL DAC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
45 * @{
46 */
47
48 /* Internal masks for DAC channels definition */
49 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
50 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
51 /* - channel bits position into register SWTRIG */
52 /* - channel register offset of data holding register DHRx */
53 /* - channel register offset of data output register DORx */
54 /* - channel register offset of sample-and-hold sample time register SHSRx */
55 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
56 CR, MCR, CCR, SHHR, SHRR of channel 1 */
57 #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
58 CR, MCR, CCR, SHHR, SHRR of channel 2 */
59 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
60
61 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
62 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
63 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
64
65 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
66 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
67 DHR12Rx channel 1 (shifted left of 20 bits) */
68 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
69 DHR12Rx channel 1 (shifted left of 24 bits) */
70
71 #define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus
72 DHR12Rx channel 1 (shifted left of 28 bits) */
73 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
74 DHR12Rx channel 1 (shifted left of 20 bits) */
75 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
76 DHR12Rx channel 1 (shifted left of 24 bits) */
77
78 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
79 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
80 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
81 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
82 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
83
84 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
85
86 #define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus
87 DORx channel 2 (shifted left of 5 bits) */
88 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
89
90 #define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
91 #define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus
92 SHSRx channel 2 (shifted left of 6 bits) */
93 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
94
95
96 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
97 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
98 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
99 to position 0 */
100 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
101 to position 0 */
102
103 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx
104 channel 1 or 2 versus DHR12Rx channel 1
105 (shifted left of 28 bits) */
106 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
107 channel 1 or 2 versus DHR12Rx channel 1
108 (shifted left of 20 bits) */
109 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
110 channel 1 or 2 versus DHR12Rx channel 1
111 (shifted left of 24 bits) */
112 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx
113 channel 1 or 2 versus DORx channel 1
114 (shifted left of 5 bits) */
115 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx
116 channel 1 or 2 versus SHSRx channel 1
117 (shifted left of 6 bits) */
118
119 /* DAC registers bits positions */
120 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
121 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
122 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
123
124 /* Miscellaneous data */
125 #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
126 bits (voltage range determined by analog voltage
127 references Vref+ and Vref-, refer to reference manual) */
128
129 /**
130 * @}
131 */
132
133
134 /* Private macros ------------------------------------------------------------*/
135 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
136 * @{
137 */
138
139 /**
140 * @brief Driver macro reserved for internal use: set a pointer to
141 * a register from a register basis from which an offset
142 * is applied.
143 * @param __REG__ Register basis from which the offset is applied.
144 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
145 * @retval Pointer to register address
146 */
147 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
148 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
149
150 /**
151 * @}
152 */
153
154
155 /* Exported types ------------------------------------------------------------*/
156 #if defined(USE_FULL_LL_DRIVER)
157 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
158 * @{
159 */
160
161 /**
162 * @brief Structure definition of some features of DAC instance.
163 */
164 typedef struct
165 {
166 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
167 internal (SW start) or from external peripheral
168 (timer event, external interrupt line).
169 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
170
171 This feature can be modified afterwards using unitary
172 function @ref LL_DAC_SetTriggerSource(). */
173
174 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
175 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
176
177 This feature can be modified afterwards using unitary
178 function @ref LL_DAC_SetWaveAutoGeneration(). */
179
180 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
181 If waveform automatic generation mode is set to noise, this parameter
182 can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
183 If waveform automatic generation mode is set to triangle,
184 this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
185 @note If waveform automatic generation mode is disabled,
186 this parameter is discarded.
187
188 This feature can be modified afterwards using unitary
189 function @ref LL_DAC_SetWaveNoiseLFSR(),
190 @ref LL_DAC_SetWaveTriangleAmplitude()
191 depending on the wave automatic generation selected. */
192
193 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
194 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
195
196 This feature can be modified afterwards using unitary
197 function @ref LL_DAC_SetOutputBuffer(). */
198
199 uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
200 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
201
202 This feature can be modified afterwards using unitary
203 function @ref LL_DAC_SetOutputConnection(). */
204
205 uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC
206 channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
207
208 This feature can be modified afterwards using unitary
209 function @ref LL_DAC_SetOutputMode(). */
210 } LL_DAC_InitTypeDef;
211
212 /**
213 * @}
214 */
215 #endif /* USE_FULL_LL_DRIVER */
216
217 /* Exported constants --------------------------------------------------------*/
218 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
219 * @{
220 */
221
222 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
223 * @brief Flags defines which can be used with LL_DAC_ReadReg function
224 * @{
225 */
226 /* DAC channel 1 flags */
227 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
228 #define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
229 #define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */
230
231 /* DAC channel 2 flags */
232 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
233 #define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
234 #define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */
235
236 /**
237 * @}
238 */
239
240 /** @defgroup DAC_LL_EC_IT DAC interruptions
241 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
242 * @{
243 */
244 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
245
246 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
247
248 /**
249 * @}
250 */
251
252 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
253 * @{
254 */
255 #define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
256 #define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
257 /**
258 * @}
259 */
260
261 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
262 * @{
263 */
264 #define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL /*!< DAC channel in mode normal operation */
265 #define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */
266 /**
267 * @}
268 */
269
270 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
271 * @{
272 */
273 #define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC channel conversion trigger internal (SW start) */
274 #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM1 TRGO. */
275 #define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
276 #define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
277 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
278 #define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
279 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
280 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
281 #define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */
282 #if defined (HRTIM1)
283 #define LL_DAC_TRIG_EXT_HRTIM_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel 1 */
284 #define LL_DAC_TRIG_EXT_HRTIM_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel 2 */
285 #endif
286 #define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. */
287 #define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM2 TRGO. */
288 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
289 #if defined(TIM23)
290 #define LL_DAC_TRIG_EXT_TIM23_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM23 TRGO. */
291 #endif
292 #if defined(TIM24)
293 #define LL_DAC_TRIG_EXT_TIM24_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM24 TRGO. */
294 #endif
295 #if defined (DAC2)
296 #define LL_DAC_TRIG_EXT_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 TRGO. */
297 #endif
298 /**
299 * @}
300 */
301
302 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
303 * @{
304 */
305 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
306 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
307 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
308 /**
309 * @}
310 */
311
312 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
313 * @{
314 */
315 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
316 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
317 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
318 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
319 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
320 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
321 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
322 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
323 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
324 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
325 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
326 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
327 /**
328 * @}
329 */
330
331 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
332 * @{
333 */
334 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
335 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
336 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
337 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
338 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
339 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
340 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
341 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
342 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
343 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
344 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
345 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
346 /**
347 * @}
348 */
349
350 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
351 * @{
352 */
353 #define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL /*!< The selected DAC channel output is on mode normal. */
354 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
355 /**
356 * @}
357 */
358
359 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
360 * @{
361 */
362 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
363 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
364 /**
365 * @}
366 */
367
368 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
369 * @{
370 */
371 #define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL /*!< The selected DAC channel output is connected to external pin */
372 #define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
373 /**
374 * @}
375 */
376
377 /** @defgroup DAC_LL_EC_LEGACY DAC literals legacy naming
378 * @{
379 */
380 #define LL_DAC_TRIGGER_SOFTWARE (LL_DAC_TRIG_SOFTWARE)
381 #define LL_DAC_TRIGGER_TIM2_TRGO (LL_DAC_TRIG_EXT_TIM2_TRGO)
382 #define LL_DAC_TRIGGER_TIM4_TRGO (LL_DAC_TRIG_EXT_TIM4_TRGO)
383 #define LL_DAC_TRIGGER_TIM6_TRGO (LL_DAC_TRIG_EXT_TIM6_TRGO)
384 #define LL_DAC_TRIGGER_TIM7_TRGO (LL_DAC_TRIG_EXT_TIM7_TRGO)
385 #define LL_DAC_TRIGGER_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM8_TRGO)
386 #define LL_DAC_TRIGGER_EXT_IT9 (LL_DAC_TRIG_EXT_EXTI_LINE9)
387
388 #define LL_DAC_WAVEGENERATION_NONE (LL_DAC_WAVE_AUTO_GENERATION_NONE)
389 #define LL_DAC_WAVEGENERATION_NOISE (LL_DAC_WAVE_AUTO_GENERATION_NOISE)
390 #define LL_DAC_WAVEGENERATION_TRIANGLE (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)
391
392 #define LL_DAC_CONNECT_GPIO (LL_DAC_OUTPUT_CONNECT_GPIO)
393 #define LL_DAC_CONNECT_INTERNAL (LL_DAC_OUTPUT_CONNECT_INTERNAL)
394 /**
395 * @}
396 */
397 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
398 * @{
399 */
400 #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
401 #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
402 /**
403 * @}
404 */
405
406 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
407 * @{
408 */
409 /* List of DAC registers intended to be used (most commonly) with */
410 /* DMA transfer. */
411 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
412 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
413 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
414 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
415 /**
416 * @}
417 */
418
419 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
420 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
421 * not timeout values.
422 * For details on delays values, refer to descriptions in source code
423 * above each literal definition.
424 * @{
425 */
426
427 /* Delay for DAC channel voltage settling time from DAC channel startup */
428 /* (transition from disable to enable). */
429 /* Note: DAC channel startup time depends on board application environment: */
430 /* impedance connected to DAC channel output. */
431 /* The delay below is specified under conditions: */
432 /* - voltage maximum transition (lowest to highest value) */
433 /* - until voltage reaches final value +-1LSB */
434 /* - DAC channel output buffer enabled */
435 /* - load impedance of 5kOhm (min), 50pF (max) */
436 /* Literal set to maximum value (refer to device datasheet, */
437 /* parameter "tWAKEUP"). */
438 /* Unit: us */
439 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
440
441 /* Delay for DAC channel voltage settling time. */
442 /* Note: DAC channel startup time depends on board application environment: */
443 /* impedance connected to DAC channel output. */
444 /* The delay below is specified under conditions: */
445 /* - voltage maximum transition (lowest to highest value) */
446 /* - until voltage reaches final value +-1LSB */
447 /* - DAC channel output buffer enabled */
448 /* - load impedance of 5kOhm min, 50pF max */
449 /* Literal set to maximum value (refer to device datasheet, */
450 /* parameter "tSETTLING"). */
451 /* Unit: us */
452 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL /*!< Delay for DAC channel voltage settling time */
453
454 /**
455 * @}
456 */
457
458 /**
459 * @}
460 */
461
462 /* Exported macro ------------------------------------------------------------*/
463 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
464 * @{
465 */
466
467 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
468 * @{
469 */
470
471 /**
472 * @brief Write a value in DAC register
473 * @param __INSTANCE__ DAC Instance
474 * @param __REG__ Register to be written
475 * @param __VALUE__ Value to be written in the register
476 * @retval None
477 */
478 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
479
480 /**
481 * @brief Read a value in DAC register
482 * @param __INSTANCE__ DAC Instance
483 * @param __REG__ Register to be read
484 * @retval Register value
485 */
486 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
487
488 /**
489 * @}
490 */
491
492 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
493 * @{
494 */
495
496 /**
497 * @brief Helper macro to get DAC channel number in decimal format
498 * from literals LL_DAC_CHANNEL_x.
499 * Example:
500 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
501 * will return decimal number "1".
502 * @note The input can be a value from functions where a channel
503 * number is returned.
504 * @param __CHANNEL__ This parameter can be one of the following values:
505 * @arg @ref LL_DAC_CHANNEL_1
506 * @arg @ref LL_DAC_CHANNEL_2
507 * @retval 1...2
508 */
509 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
510 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
511
512 /**
513 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
514 * from number in decimal format.
515 * Example:
516 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
517 * will return a data equivalent to "LL_DAC_CHANNEL_1".
518 * @note If the input parameter does not correspond to a DAC channel,
519 * this macro returns value '0'.
520 * @param __DECIMAL_NB__ 1...2
521 * @retval Returned value can be one of the following values:
522 * @arg @ref LL_DAC_CHANNEL_1
523 * @arg @ref LL_DAC_CHANNEL_2
524 */
525 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
526 (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
527
528 /**
529 * @brief Helper macro to define the DAC conversion data full-scale digital
530 * value corresponding to the selected DAC resolution.
531 * @note DAC conversion data full-scale corresponds to voltage range
532 * determined by analog voltage references Vref+ and Vref-
533 * (refer to reference manual).
534 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
535 * @arg @ref LL_DAC_RESOLUTION_12B
536 * @arg @ref LL_DAC_RESOLUTION_8B
537 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
538 */
539 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
540 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
541
542 /**
543 * @brief Helper macro to calculate the DAC conversion data (unit: digital
544 * value) corresponding to a voltage (unit: mVolt).
545 * @note This helper macro is intended to provide input data in voltage
546 * rather than digital value,
547 * to be used with LL DAC functions such as
548 * @ref LL_DAC_ConvertData12RightAligned().
549 * @note Analog reference voltage (Vref+) must be either known from
550 * user board environment or can be calculated using ADC measurement
551 * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
552 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
553 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
554 * (unit: mVolt).
555 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
556 * @arg @ref LL_DAC_RESOLUTION_12B
557 * @arg @ref LL_DAC_RESOLUTION_8B
558 * @retval DAC conversion data (unit: digital value)
559 */
560 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
561 __DAC_VOLTAGE__,\
562 __DAC_RESOLUTION__) \
563 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
564 / (__VREFANALOG_VOLTAGE__) \
565 )
566
567 /**
568 * @}
569 */
570
571 /**
572 * @}
573 */
574
575
576 /* Exported functions --------------------------------------------------------*/
577 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
578 * @{
579 */
580 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
581 * @{
582 */
583
584 /**
585 * @brief Set the operating mode for the selected DAC channel:
586 * calibration or normal operating mode.
587 * @rmtoll CR CEN1 LL_DAC_SetMode\n
588 * CR CEN2 LL_DAC_SetMode
589 * @param DACx DAC instance
590 * @param DAC_Channel This parameter can be one of the following values:
591 * @arg @ref LL_DAC_CHANNEL_1
592 * @arg @ref LL_DAC_CHANNEL_2
593 * @param ChannelMode This parameter can be one of the following values:
594 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
595 * @arg @ref LL_DAC_MODE_CALIBRATION
596 * @retval None
597 */
LL_DAC_SetMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t ChannelMode)598 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
599 {
600 MODIFY_REG(DACx->CR,
601 DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
602 ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
603 }
604
605 /**
606 * @brief Get the operating mode for the selected DAC channel:
607 * calibration or normal operating mode.
608 * @rmtoll CR CEN1 LL_DAC_GetMode\n
609 * CR CEN2 LL_DAC_GetMode
610 * @param DACx DAC instance
611 * @param DAC_Channel This parameter can be one of the following values:
612 * @arg @ref LL_DAC_CHANNEL_1
613 * @arg @ref LL_DAC_CHANNEL_2
614 * @retval Returned value can be one of the following values:
615 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
616 * @arg @ref LL_DAC_MODE_CALIBRATION
617 */
LL_DAC_GetMode(DAC_TypeDef * DACx,uint32_t DAC_Channel)618 __STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
619 {
620 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
621 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
622 );
623 }
624
625 /**
626 * @brief Set the offset trimming value for the selected DAC channel.
627 * Trimming has an impact when output buffer is enabled
628 * and is intended to replace factory calibration default values.
629 * @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n
630 * CCR OTRIM2 LL_DAC_SetTrimmingValue
631 * @param DACx DAC instance
632 * @param DAC_Channel This parameter can be one of the following values:
633 * @arg @ref LL_DAC_CHANNEL_1
634 * @arg @ref LL_DAC_CHANNEL_2
635 * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
636 * @retval None
637 */
LL_DAC_SetTrimmingValue(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TrimmingValue)638 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
639 {
640 MODIFY_REG(DACx->CCR,
641 DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
642 TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
643 }
644
645 /**
646 * @brief Get the offset trimming value for the selected DAC channel.
647 * Trimming has an impact when output buffer is enabled
648 * and is intended to replace factory calibration default values.
649 * @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n
650 * CCR OTRIM2 LL_DAC_GetTrimmingValue
651 * @param DACx DAC instance
652 * @param DAC_Channel This parameter can be one of the following values:
653 * @arg @ref LL_DAC_CHANNEL_1
654 * @arg @ref LL_DAC_CHANNEL_2
655 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
656 */
LL_DAC_GetTrimmingValue(DAC_TypeDef * DACx,uint32_t DAC_Channel)657 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
658 {
659 return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
660 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
661 );
662 }
663
664 /**
665 * @brief Set the conversion trigger source for the selected DAC channel.
666 * @note For conversion trigger source to be effective, DAC trigger
667 * must be enabled using function @ref LL_DAC_EnableTrigger().
668 * @note To set conversion trigger source, DAC channel must be disabled.
669 * Otherwise, the setting is discarded.
670 * @note Availability of parameters of trigger sources from timer
671 * depends on timers availability on the selected device.
672 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
673 * CR TSEL2 LL_DAC_SetTriggerSource
674 * @param DACx DAC instance
675 * @param DAC_Channel This parameter can be one of the following values:
676 * @arg @ref LL_DAC_CHANNEL_1
677 * @arg @ref LL_DAC_CHANNEL_2
678 * @param TriggerSource This parameter can be one of the following values:
679 * @arg @ref LL_DAC_TRIG_SOFTWARE
680 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
681 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
682 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
683 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
684 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
685 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
686 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
687 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
688 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (1)
689 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (1)
690 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
691 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
692 * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT (2)
693 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
694 * @arg @ref LL_DAC_TRIG_EXT_TIM23_TRGO (3)
695 * @arg @ref LL_DAC_TRIG_EXT_TIM24_TRGO (4)
696 *
697 * (1) On this STM32 series, parameter not available on all devices.
698 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
699 * (2) On this STM32 series, parameter only available on DAC2.
700 * (3) On this STM32 series, parameter not available on all devices.
701 * Only available if TIM23 feature is supported (refer to device datasheet for supported features list)
702 * (4) On this STM32 series, parameter not available on all devices.
703 * Only available if TIM24 feature is supported (refer to device datasheet for supported features list)
704 * @retval None
705 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)706 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
707 {
708 MODIFY_REG(DACx->CR,
709 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
710 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
711 }
712
713 /**
714 * @brief Get the conversion trigger source for the selected DAC channel.
715 * @note For conversion trigger source to be effective, DAC trigger
716 * must be enabled using function @ref LL_DAC_EnableTrigger().
717 * @note Availability of parameters of trigger sources from timer
718 * depends on timers availability on the selected device.
719 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
720 * CR TSEL2 LL_DAC_GetTriggerSource
721 * @param DACx DAC instance
722 * @param DAC_Channel This parameter can be one of the following values:
723 * @arg @ref LL_DAC_CHANNEL_1
724 * @arg @ref LL_DAC_CHANNEL_2
725 * @retval Returned value can be one of the following values:
726 * @arg @ref LL_DAC_TRIG_SOFTWARE
727 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
728 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
729 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
730 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
731 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
732 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
733 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
734 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
735 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (1)
736 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (1)
737 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
738 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
739 * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT (2)
740 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
741 * @arg @ref LL_DAC_TRIG_EXT_TIM23_TRGO (3)
742 * @arg @ref LL_DAC_TRIG_EXT_TIM24_TRGO (4)
743 *
744 * (1) On this STM32 series, parameter not available on all devices.
745 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
746 * (2) On this STM32 series, parameter only available on DAC2.
747 * (3) On this STM32 series, parameter not available on all devices.
748 * Only available if TIM23 feature is supported (refer to device datasheet for supported features list)
749 * (4) On this STM32 series, parameter not available on all devices.
750 * Only available if TIM24 feature is supported (refer to device datasheet for supported features list)
751 */
LL_DAC_GetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel)752 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
753 {
754 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
755 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
756 );
757 }
758
759 /**
760 * @brief Set the waveform automatic generation mode
761 * for the selected DAC channel.
762 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
763 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
764 * @param DACx DAC instance
765 * @param DAC_Channel This parameter can be one of the following values:
766 * @arg @ref LL_DAC_CHANNEL_1
767 * @arg @ref LL_DAC_CHANNEL_2
768 * @param WaveAutoGeneration This parameter can be one of the following values:
769 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
770 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
771 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
772 * @retval None
773 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)774 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
775 {
776 MODIFY_REG(DACx->CR,
777 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
778 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
779 }
780
781 /**
782 * @brief Get the waveform automatic generation mode
783 * for the selected DAC channel.
784 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
785 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
786 * @param DACx DAC instance
787 * @param DAC_Channel This parameter can be one of the following values:
788 * @arg @ref LL_DAC_CHANNEL_1
789 * @arg @ref LL_DAC_CHANNEL_2
790 * @retval Returned value can be one of the following values:
791 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
792 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
793 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
794 */
LL_DAC_GetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel)795 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
796 {
797 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
798 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
799 );
800 }
801
802 /**
803 * @brief Set the noise waveform generation for the selected DAC channel:
804 * Noise mode and parameters LFSR (linear feedback shift register).
805 * @note For wave generation to be effective, DAC channel
806 * wave generation mode must be enabled using
807 * function @ref LL_DAC_SetWaveAutoGeneration().
808 * @note This setting can be set when the selected DAC channel is disabled
809 * (otherwise, the setting operation is ignored).
810 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
811 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
812 * @param DACx DAC instance
813 * @param DAC_Channel This parameter can be one of the following values:
814 * @arg @ref LL_DAC_CHANNEL_1
815 * @arg @ref LL_DAC_CHANNEL_2
816 * @param NoiseLFSRMask This parameter can be one of the following values:
817 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
818 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
819 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
820 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
821 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
822 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
823 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
824 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
825 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
826 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
827 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
828 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
829 * @retval None
830 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)831 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
832 {
833 MODIFY_REG(DACx->CR,
834 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
835 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
836 }
837
838 /**
839 * @brief Get the noise waveform generation for the selected DAC channel:
840 * Noise mode and parameters LFSR (linear feedback shift register).
841 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
842 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
843 * @param DACx DAC instance
844 * @param DAC_Channel This parameter can be one of the following values:
845 * @arg @ref LL_DAC_CHANNEL_1
846 * @arg @ref LL_DAC_CHANNEL_2
847 * @retval Returned value can be one of the following values:
848 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
849 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
850 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
851 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
852 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
853 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
854 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
855 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
856 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
857 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
858 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
859 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
860 */
LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel)861 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
862 {
863 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
864 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
865 );
866 }
867
868 /**
869 * @brief Set the triangle waveform generation for the selected DAC channel:
870 * triangle mode and amplitude.
871 * @note For wave generation to be effective, DAC channel
872 * wave generation mode must be enabled using
873 * function @ref LL_DAC_SetWaveAutoGeneration().
874 * @note This setting can be set when the selected DAC channel is disabled
875 * (otherwise, the setting operation is ignored).
876 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
877 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
878 * @param DACx DAC instance
879 * @param DAC_Channel This parameter can be one of the following values:
880 * @arg @ref LL_DAC_CHANNEL_1
881 * @arg @ref LL_DAC_CHANNEL_2
882 * @param TriangleAmplitude This parameter can be one of the following values:
883 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
884 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
885 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
886 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
887 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
888 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
889 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
890 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
891 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
892 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
893 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
894 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
895 * @retval None
896 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)897 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
898 uint32_t TriangleAmplitude)
899 {
900 MODIFY_REG(DACx->CR,
901 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
902 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
903 }
904
905 /**
906 * @brief Get the triangle waveform generation for the selected DAC channel:
907 * triangle mode and amplitude.
908 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
909 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
910 * @param DACx DAC instance
911 * @param DAC_Channel This parameter can be one of the following values:
912 * @arg @ref LL_DAC_CHANNEL_1
913 * @arg @ref LL_DAC_CHANNEL_2
914 * @retval Returned value can be one of the following values:
915 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
916 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
917 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
918 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
919 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
920 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
921 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
922 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
923 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
924 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
925 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
926 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
927 */
LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel)928 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
929 {
930 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
931 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
932 );
933 }
934
935 /**
936 * @brief Set the output for the selected DAC channel.
937 * @note This function set several features:
938 * - mode normal or sample-and-hold
939 * - buffer
940 * - connection to GPIO or internal path.
941 * These features can also be set individually using
942 * dedicated functions:
943 * - @ref LL_DAC_SetOutputBuffer()
944 * - @ref LL_DAC_SetOutputMode()
945 * - @ref LL_DAC_SetOutputConnection()
946 * @note On this STM32 series, output connection depends on output mode
947 * (normal or sample and hold) and output buffer state.
948 * - if output connection is set to internal path and output buffer
949 * is enabled (whatever output mode):
950 * output connection is also connected to GPIO pin
951 * (both connections to GPIO pin and internal path).
952 * - if output connection is set to GPIO pin, output buffer
953 * is disabled, output mode set to sample and hold:
954 * output connection is also connected to internal path
955 * (both connections to GPIO pin and internal path).
956 * @note Mode sample-and-hold requires an external capacitor
957 * to be connected between DAC channel output and ground.
958 * Capacitor value depends on load on DAC channel output and
959 * sample-and-hold timings configured.
960 * As indication, capacitor typical value is 100nF
961 * (refer to device datasheet, parameter "CSH").
962 * @rmtoll CR MODE1 LL_DAC_ConfigOutput\n
963 * CR MODE2 LL_DAC_ConfigOutput
964 * @param DACx DAC instance
965 * @param DAC_Channel This parameter can be one of the following values:
966 * @arg @ref LL_DAC_CHANNEL_1
967 * @arg @ref LL_DAC_CHANNEL_2
968 * @param OutputMode This parameter can be one of the following values:
969 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
970 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
971 * @param OutputBuffer This parameter can be one of the following values:
972 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
973 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
974 * @param OutputConnection This parameter can be one of the following values:
975 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
976 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
977 * @retval None
978 */
LL_DAC_ConfigOutput(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode,uint32_t OutputBuffer,uint32_t OutputConnection)979 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
980 uint32_t OutputBuffer, uint32_t OutputConnection)
981 {
982 MODIFY_REG(DACx->MCR,
983 (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
984 (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
985 }
986
987 /**
988 * @brief Set the output mode normal or sample-and-hold
989 * for the selected DAC channel.
990 * @note Mode sample-and-hold requires an external capacitor
991 * to be connected between DAC channel output and ground.
992 * Capacitor value depends on load on DAC channel output and
993 * sample-and-hold timings configured.
994 * As indication, capacitor typical value is 100nF
995 * (refer to device datasheet, parameter "CSH").
996 * @rmtoll CR MODE1 LL_DAC_SetOutputMode\n
997 * CR MODE2 LL_DAC_SetOutputMode
998 * @param DACx DAC instance
999 * @param DAC_Channel This parameter can be one of the following values:
1000 * @arg @ref LL_DAC_CHANNEL_1
1001 * @arg @ref LL_DAC_CHANNEL_2
1002 * @param OutputMode This parameter can be one of the following values:
1003 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1004 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1005 * @retval None
1006 */
LL_DAC_SetOutputMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode)1007 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
1008 {
1009 MODIFY_REG(DACx->MCR,
1010 (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1011 OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1012 }
1013
1014 /**
1015 * @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
1016 * @rmtoll CR MODE1 LL_DAC_GetOutputMode\n
1017 * CR MODE2 LL_DAC_GetOutputMode
1018 * @param DACx DAC instance
1019 * @param DAC_Channel This parameter can be one of the following values:
1020 * @arg @ref LL_DAC_CHANNEL_1
1021 * @arg @ref LL_DAC_CHANNEL_2
1022 * @retval Returned value can be one of the following values:
1023 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1024 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1025 */
LL_DAC_GetOutputMode(DAC_TypeDef * DACx,uint32_t DAC_Channel)1026 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1027 {
1028 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1029 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1030 );
1031 }
1032
1033 /**
1034 * @brief Set the output buffer for the selected DAC channel.
1035 * @note On this STM32 series, when buffer is enabled, its offset can be
1036 * trimmed: factory calibration default values can be
1037 * replaced by user trimming values, using function
1038 * @ref LL_DAC_SetTrimmingValue().
1039 * @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n
1040 * CR MODE2 LL_DAC_SetOutputBuffer
1041 * @param DACx DAC instance
1042 * @param DAC_Channel This parameter can be one of the following values:
1043 * @arg @ref LL_DAC_CHANNEL_1
1044 * @arg @ref LL_DAC_CHANNEL_2
1045 * @param OutputBuffer This parameter can be one of the following values:
1046 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1047 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1048 * @retval None
1049 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)1050 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
1051 {
1052 MODIFY_REG(DACx->MCR,
1053 (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1054 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1055 }
1056
1057 /**
1058 * @brief Get the output buffer state for the selected DAC channel.
1059 * @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n
1060 * CR MODE2 LL_DAC_GetOutputBuffer
1061 * @param DACx DAC instance
1062 * @param DAC_Channel This parameter can be one of the following values:
1063 * @arg @ref LL_DAC_CHANNEL_1
1064 * @arg @ref LL_DAC_CHANNEL_2
1065 * @retval Returned value can be one of the following values:
1066 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1067 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1068 */
LL_DAC_GetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel)1069 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1070 {
1071 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1072 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1073 );
1074 }
1075
1076 /**
1077 * @brief Set the output connection for the selected DAC channel.
1078 * @note On this STM32 series, output connection depends on output mode (normal or
1079 * sample and hold) and output buffer state.
1080 * - if output connection is set to internal path and output buffer
1081 * is enabled (whatever output mode):
1082 * output connection is also connected to GPIO pin
1083 * (both connections to GPIO pin and internal path).
1084 * - if output connection is set to GPIO pin, output buffer
1085 * is disabled, output mode set to sample and hold:
1086 * output connection is also connected to internal path
1087 * (both connections to GPIO pin and internal path).
1088 * @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n
1089 * CR MODE2 LL_DAC_SetOutputConnection
1090 * @param DACx DAC instance
1091 * @param DAC_Channel This parameter can be one of the following values:
1092 * @arg @ref LL_DAC_CHANNEL_1
1093 * @arg @ref LL_DAC_CHANNEL_2
1094 * @param OutputConnection This parameter can be one of the following values:
1095 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1096 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1097 * @retval None
1098 */
LL_DAC_SetOutputConnection(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputConnection)1099 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
1100 {
1101 MODIFY_REG(DACx->MCR,
1102 (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1103 OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1104 }
1105
1106 /**
1107 * @brief Get the output connection for the selected DAC channel.
1108 * @note On this STM32 series, output connection depends on output mode (normal or
1109 * sample and hold) and output buffer state.
1110 * - if output connection is set to internal path and output buffer
1111 * is enabled (whatever output mode):
1112 * output connection is also connected to GPIO pin
1113 * (both connections to GPIO pin and internal path).
1114 * - if output connection is set to GPIO pin, output buffer
1115 * is disabled, output mode set to sample and hold:
1116 * output connection is also connected to internal path
1117 * (both connections to GPIO pin and internal path).
1118 * @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n
1119 * CR MODE2 LL_DAC_GetOutputConnection
1120 * @param DACx DAC instance
1121 * @param DAC_Channel This parameter can be one of the following values:
1122 * @arg @ref LL_DAC_CHANNEL_1
1123 * @arg @ref LL_DAC_CHANNEL_2
1124 * @retval Returned value can be one of the following values:
1125 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1126 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1127 */
LL_DAC_GetOutputConnection(DAC_TypeDef * DACx,uint32_t DAC_Channel)1128 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1129 {
1130 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1131 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1132 );
1133 }
1134
1135 /**
1136 * @brief Set the sample-and-hold timing for the selected DAC channel:
1137 * sample time
1138 * @note Sample time must be set when DAC channel is disabled
1139 * or during DAC operation when DAC channel flag BWSTx is reset,
1140 * otherwise the setting is ignored.
1141 * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
1142 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n
1143 * SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
1144 * @param DACx DAC instance
1145 * @param DAC_Channel This parameter can be one of the following values:
1146 * @arg @ref LL_DAC_CHANNEL_1
1147 * @arg @ref LL_DAC_CHANNEL_2
1148 * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
1149 * @retval None
1150 */
LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t SampleTime)1151 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
1152 {
1153 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1154 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1155
1156 MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
1157 }
1158
1159 /**
1160 * @brief Get the sample-and-hold timing for the selected DAC channel:
1161 * sample time
1162 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n
1163 * SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
1164 * @param DACx DAC instance
1165 * @param DAC_Channel This parameter can be one of the following values:
1166 * @arg @ref LL_DAC_CHANNEL_1
1167 * @arg @ref LL_DAC_CHANNEL_2
1168 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1169 */
LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef * DACx,uint32_t DAC_Channel)1170 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1171 {
1172 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1173 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1174
1175 return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
1176 }
1177
1178 /**
1179 * @brief Set the sample-and-hold timing for the selected DAC channel:
1180 * hold time
1181 * @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n
1182 * SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
1183 * @param DACx DAC instance
1184 * @param DAC_Channel This parameter can be one of the following values:
1185 * @arg @ref LL_DAC_CHANNEL_1
1186 * @arg @ref LL_DAC_CHANNEL_2
1187 * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
1188 * @retval None
1189 */
LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t HoldTime)1190 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
1191 {
1192 MODIFY_REG(DACx->SHHR,
1193 DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1194 HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1195 }
1196
1197 /**
1198 * @brief Get the sample-and-hold timing for the selected DAC channel:
1199 * hold time
1200 * @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n
1201 * SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
1202 * @param DACx DAC instance
1203 * @param DAC_Channel This parameter can be one of the following values:
1204 * @arg @ref LL_DAC_CHANNEL_1
1205 * @arg @ref LL_DAC_CHANNEL_2
1206 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1207 */
LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef * DACx,uint32_t DAC_Channel)1208 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1209 {
1210 return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1211 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1212 );
1213 }
1214
1215 /**
1216 * @brief Set the sample-and-hold timing for the selected DAC channel:
1217 * refresh time
1218 * @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n
1219 * SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
1220 * @param DACx DAC instance
1221 * @param DAC_Channel This parameter can be one of the following values:
1222 * @arg @ref LL_DAC_CHANNEL_1
1223 * @arg @ref LL_DAC_CHANNEL_2
1224 * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
1225 * @retval None
1226 */
LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t RefreshTime)1227 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
1228 {
1229 MODIFY_REG(DACx->SHRR,
1230 DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1231 RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1232 }
1233
1234 /**
1235 * @brief Get the sample-and-hold timing for the selected DAC channel:
1236 * refresh time
1237 * @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n
1238 * SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
1239 * @param DACx DAC instance
1240 * @param DAC_Channel This parameter can be one of the following values:
1241 * @arg @ref LL_DAC_CHANNEL_1
1242 * @arg @ref LL_DAC_CHANNEL_2
1243 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1244 */
LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef * DACx,uint32_t DAC_Channel)1245 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1246 {
1247 return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1248 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1249 );
1250 }
1251
1252 /**
1253 * @}
1254 */
1255
1256 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
1257 * @{
1258 */
1259
1260 /**
1261 * @brief Enable DAC DMA transfer request of the selected channel.
1262 * @note To configure DMA source address (peripheral address),
1263 * use function @ref LL_DAC_DMA_GetRegAddr().
1264 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
1265 * CR DMAEN2 LL_DAC_EnableDMAReq
1266 * @param DACx DAC instance
1267 * @param DAC_Channel This parameter can be one of the following values:
1268 * @arg @ref LL_DAC_CHANNEL_1
1269 * @arg @ref LL_DAC_CHANNEL_2
1270 * @retval None
1271 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1272 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1273 {
1274 SET_BIT(DACx->CR,
1275 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1276 }
1277
1278 /**
1279 * @brief Disable DAC DMA transfer request of the selected channel.
1280 * @note To configure DMA source address (peripheral address),
1281 * use function @ref LL_DAC_DMA_GetRegAddr().
1282 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
1283 * CR DMAEN2 LL_DAC_DisableDMAReq
1284 * @param DACx DAC instance
1285 * @param DAC_Channel This parameter can be one of the following values:
1286 * @arg @ref LL_DAC_CHANNEL_1
1287 * @arg @ref LL_DAC_CHANNEL_2
1288 * @retval None
1289 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1290 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1291 {
1292 CLEAR_BIT(DACx->CR,
1293 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1294 }
1295
1296 /**
1297 * @brief Get DAC DMA transfer request state of the selected channel.
1298 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
1299 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
1300 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
1301 * @param DACx DAC instance
1302 * @param DAC_Channel This parameter can be one of the following values:
1303 * @arg @ref LL_DAC_CHANNEL_1
1304 * @arg @ref LL_DAC_CHANNEL_2
1305 * @retval State of bit (1 or 0).
1306 */
LL_DAC_IsDMAReqEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1307 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1308 {
1309 return ((READ_BIT(DACx->CR,
1310 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1311 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1312 }
1313
1314 /**
1315 * @brief Function to help to configure DMA transfer to DAC: retrieve the
1316 * DAC register address from DAC instance and a list of DAC registers
1317 * intended to be used (most commonly) with DMA transfer.
1318 * @note These DAC registers are data holding registers:
1319 * when DAC conversion is requested, DAC generates a DMA transfer
1320 * request to have data available in DAC data holding registers.
1321 * @note This macro is intended to be used with LL DMA driver, refer to
1322 * function "LL_DMA_ConfigAddresses()".
1323 * Example:
1324 * LL_DMA_ConfigAddresses(DMA1,
1325 * LL_DMA_CHANNEL_1,
1326 * (uint32_t)&< array or variable >,
1327 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
1328 * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
1329 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
1330 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1331 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1332 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1333 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1334 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1335 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
1336 * @param DACx DAC instance
1337 * @param DAC_Channel This parameter can be one of the following values:
1338 * @arg @ref LL_DAC_CHANNEL_1
1339 * @arg @ref LL_DAC_CHANNEL_2
1340 * @param Register This parameter can be one of the following values:
1341 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
1342 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
1343 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
1344 * @retval DAC register address
1345 */
LL_DAC_DMA_GetRegAddr(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)1346 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
1347 {
1348 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
1349 /* DAC channel selected. */
1350 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
1351 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
1352 }
1353 /**
1354 * @}
1355 */
1356
1357 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
1358 * @{
1359 */
1360
1361 /**
1362 * @brief Enable DAC selected channel.
1363 * @rmtoll CR EN1 LL_DAC_Enable\n
1364 * CR EN2 LL_DAC_Enable
1365 * @note After enable from off state, DAC channel requires a delay
1366 * for output voltage to reach accuracy +/- 1 LSB.
1367 * Refer to device datasheet, parameter "tWAKEUP".
1368 * @param DACx DAC instance
1369 * @param DAC_Channel This parameter can be one of the following values:
1370 * @arg @ref LL_DAC_CHANNEL_1
1371 * @arg @ref LL_DAC_CHANNEL_2
1372 * @retval None
1373 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1374 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1375 {
1376 SET_BIT(DACx->CR,
1377 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1378 }
1379
1380 /**
1381 * @brief Disable DAC selected channel.
1382 * @rmtoll CR EN1 LL_DAC_Disable\n
1383 * CR EN2 LL_DAC_Disable
1384 * @param DACx DAC instance
1385 * @param DAC_Channel This parameter can be one of the following values:
1386 * @arg @ref LL_DAC_CHANNEL_1
1387 * @arg @ref LL_DAC_CHANNEL_2
1388 * @retval None
1389 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1390 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1391 {
1392 CLEAR_BIT(DACx->CR,
1393 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1394 }
1395
1396 /**
1397 * @brief Get DAC enable state of the selected channel.
1398 * (0: DAC channel is disabled, 1: DAC channel is enabled)
1399 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
1400 * CR EN2 LL_DAC_IsEnabled
1401 * @param DACx DAC instance
1402 * @param DAC_Channel This parameter can be one of the following values:
1403 * @arg @ref LL_DAC_CHANNEL_1
1404 * @arg @ref LL_DAC_CHANNEL_2
1405 * @retval State of bit (1 or 0).
1406 */
LL_DAC_IsEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1407 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1408 {
1409 return ((READ_BIT(DACx->CR,
1410 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1411 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1412 }
1413
1414 /**
1415 * @brief Enable DAC trigger of the selected channel.
1416 * @note - If DAC trigger is disabled, DAC conversion is performed
1417 * automatically once the data holding register is updated,
1418 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1419 * @ref LL_DAC_ConvertData12RightAligned(), ...
1420 * - If DAC trigger is enabled, DAC conversion is performed
1421 * only when a hardware of software trigger event is occurring.
1422 * Select trigger source using
1423 * function @ref LL_DAC_SetTriggerSource().
1424 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1425 * CR TEN2 LL_DAC_EnableTrigger
1426 * @param DACx DAC instance
1427 * @param DAC_Channel This parameter can be one of the following values:
1428 * @arg @ref LL_DAC_CHANNEL_1
1429 * @arg @ref LL_DAC_CHANNEL_2
1430 * @retval None
1431 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1432 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1433 {
1434 SET_BIT(DACx->CR,
1435 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1436 }
1437
1438 /**
1439 * @brief Disable DAC trigger of the selected channel.
1440 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1441 * CR TEN2 LL_DAC_DisableTrigger
1442 * @param DACx DAC instance
1443 * @param DAC_Channel This parameter can be one of the following values:
1444 * @arg @ref LL_DAC_CHANNEL_1
1445 * @arg @ref LL_DAC_CHANNEL_2
1446 * @retval None
1447 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1448 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1449 {
1450 CLEAR_BIT(DACx->CR,
1451 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1452 }
1453
1454 /**
1455 * @brief Get DAC trigger state of the selected channel.
1456 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1457 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1458 * CR TEN2 LL_DAC_IsTriggerEnabled
1459 * @param DACx DAC instance
1460 * @param DAC_Channel This parameter can be one of the following values:
1461 * @arg @ref LL_DAC_CHANNEL_1
1462 * @arg @ref LL_DAC_CHANNEL_2
1463 * @retval State of bit (1 or 0).
1464 */
LL_DAC_IsTriggerEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1465 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1466 {
1467 return ((READ_BIT(DACx->CR,
1468 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1469 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1470 }
1471
1472 /**
1473 * @brief Trig DAC conversion by software for the selected DAC channel.
1474 * @note Preliminarily, DAC trigger must be set to software trigger
1475 * using function
1476 * @ref LL_DAC_Init()
1477 * @ref LL_DAC_SetTriggerSource()
1478 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1479 * and DAC trigger must be enabled using
1480 * function @ref LL_DAC_EnableTrigger().
1481 * @note For devices featuring DAC with 2 channels: this function
1482 * can perform a SW start of both DAC channels simultaneously.
1483 * Two channels can be selected as parameter.
1484 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1485 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1486 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1487 * @param DACx DAC instance
1488 * @param DAC_Channel This parameter can a combination of the following values:
1489 * @arg @ref LL_DAC_CHANNEL_1
1490 * @arg @ref LL_DAC_CHANNEL_2
1491 * @retval None
1492 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1493 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1494 {
1495 SET_BIT(DACx->SWTRIGR,
1496 (DAC_Channel & DAC_SWTR_CHX_MASK));
1497 }
1498
1499 /**
1500 * @brief Set the data to be loaded in the data holding register
1501 * in format 12 bits left alignment (LSB aligned on bit 0),
1502 * for the selected DAC channel.
1503 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1504 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1505 * @param DACx DAC instance
1506 * @param DAC_Channel This parameter can be one of the following values:
1507 * @arg @ref LL_DAC_CHANNEL_1
1508 * @arg @ref LL_DAC_CHANNEL_2
1509 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1510 * @retval None
1511 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1512 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1513 {
1514 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
1515 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1516
1517 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
1518 }
1519
1520 /**
1521 * @brief Set the data to be loaded in the data holding register
1522 * in format 12 bits left alignment (MSB aligned on bit 15),
1523 * for the selected DAC channel.
1524 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1525 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1526 * @param DACx DAC instance
1527 * @param DAC_Channel This parameter can be one of the following values:
1528 * @arg @ref LL_DAC_CHANNEL_1
1529 * @arg @ref LL_DAC_CHANNEL_2
1530 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1531 * @retval None
1532 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1533 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1534 {
1535 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
1536 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1537
1538 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
1539 }
1540
1541 /**
1542 * @brief Set the data to be loaded in the data holding register
1543 * in format 8 bits left alignment (LSB aligned on bit 0),
1544 * for the selected DAC channel.
1545 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1546 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1547 * @param DACx DAC instance
1548 * @param DAC_Channel This parameter can be one of the following values:
1549 * @arg @ref LL_DAC_CHANNEL_1
1550 * @arg @ref LL_DAC_CHANNEL_2
1551 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1552 * @retval None
1553 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1554 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1555 {
1556 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
1557 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1558
1559 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
1560 }
1561
1562
1563 /**
1564 * @brief Set the data to be loaded in the data holding register
1565 * in format 12 bits left alignment (LSB aligned on bit 0),
1566 * for both DAC channels.
1567 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1568 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1569 * @param DACx DAC instance
1570 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1571 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1572 * @retval None
1573 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1574 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1575 uint32_t DataChannel2)
1576 {
1577 MODIFY_REG(DACx->DHR12RD,
1578 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1579 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1580 }
1581
1582 /**
1583 * @brief Set the data to be loaded in the data holding register
1584 * in format 12 bits left alignment (MSB aligned on bit 15),
1585 * for both DAC channels.
1586 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1587 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1588 * @param DACx DAC instance
1589 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1590 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1591 * @retval None
1592 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1593 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1594 uint32_t DataChannel2)
1595 {
1596 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1597 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1598 /* the 4 LSB must be taken into account for the shift value. */
1599 MODIFY_REG(DACx->DHR12LD,
1600 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1601 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1602 }
1603
1604 /**
1605 * @brief Set the data to be loaded in the data holding register
1606 * in format 8 bits left alignment (LSB aligned on bit 0),
1607 * for both DAC channels.
1608 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1609 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1610 * @param DACx DAC instance
1611 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1612 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1613 * @retval None
1614 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1615 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1616 uint32_t DataChannel2)
1617 {
1618 MODIFY_REG(DACx->DHR8RD,
1619 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1620 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1621 }
1622
1623
1624 /**
1625 * @brief Retrieve output data currently generated for the selected DAC channel.
1626 * @note Whatever alignment and resolution settings
1627 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1628 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1629 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1630 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1631 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1632 * @param DACx DAC instance
1633 * @param DAC_Channel This parameter can be one of the following values:
1634 * @arg @ref LL_DAC_CHANNEL_1
1635 * @arg @ref LL_DAC_CHANNEL_2
1636 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1637 */
LL_DAC_RetrieveOutputData(DAC_TypeDef * DACx,uint32_t DAC_Channel)1638 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1639 {
1640 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
1641 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1642
1643 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1644 }
1645
1646 /**
1647 * @}
1648 */
1649
1650 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1651 * @{
1652 */
1653
1654 /**
1655 * @brief Get DAC calibration offset flag for DAC channel 1
1656 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
1657 * @param DACx DAC instance
1658 * @retval State of bit (1 or 0).
1659 */
LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef * DACx)1660 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
1661 {
1662 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
1663 }
1664
1665
1666 /**
1667 * @brief Get DAC calibration offset flag for DAC channel 2
1668 * @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
1669 * @param DACx DAC instance
1670 * @retval State of bit (1 or 0).
1671 */
LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef * DACx)1672 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
1673 {
1674 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
1675 }
1676
1677
1678 /**
1679 * @brief Get DAC busy writing sample time flag for DAC channel 1
1680 * @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
1681 * @param DACx DAC instance
1682 * @retval State of bit (1 or 0).
1683 */
LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef * DACx)1684 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
1685 {
1686 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
1687 }
1688
1689 /**
1690 * @brief Get DAC busy writing sample time flag for DAC channel 2
1691 * @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
1692 * @param DACx DAC instance
1693 * @retval State of bit (1 or 0).
1694 */
LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef * DACx)1695 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
1696 {
1697 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
1698 }
1699
1700
1701 /**
1702 * @brief Get DAC underrun flag for DAC channel 1
1703 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1704 * @param DACx DAC instance
1705 * @retval State of bit (1 or 0).
1706 */
LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef * DACx)1707 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1708 {
1709 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1710 }
1711
1712
1713 /**
1714 * @brief Get DAC underrun flag for DAC channel 2
1715 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1716 * @param DACx DAC instance
1717 * @retval State of bit (1 or 0).
1718 */
LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef * DACx)1719 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1720 {
1721 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
1722 }
1723
1724
1725 /**
1726 * @brief Clear DAC underrun flag for DAC channel 1
1727 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1728 * @param DACx DAC instance
1729 * @retval None
1730 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1731 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1732 {
1733 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1734 }
1735
1736
1737 /**
1738 * @brief Clear DAC underrun flag for DAC channel 2
1739 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1740 * @param DACx DAC instance
1741 * @retval None
1742 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)1743 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1744 {
1745 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1746 }
1747
1748
1749 /**
1750 * @}
1751 */
1752
1753 /** @defgroup DAC_LL_EF_IT_Management IT management
1754 * @{
1755 */
1756
1757 /**
1758 * @brief Enable DMA underrun interrupt for DAC channel 1
1759 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1760 * @param DACx DAC instance
1761 * @retval None
1762 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1763 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1764 {
1765 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1766 }
1767
1768
1769 /**
1770 * @brief Enable DMA underrun interrupt for DAC channel 2
1771 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1772 * @param DACx DAC instance
1773 * @retval None
1774 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)1775 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1776 {
1777 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1778 }
1779
1780
1781 /**
1782 * @brief Disable DMA underrun interrupt for DAC channel 1
1783 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1784 * @param DACx DAC instance
1785 * @retval None
1786 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1787 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1788 {
1789 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1790 }
1791
1792
1793 /**
1794 * @brief Disable DMA underrun interrupt for DAC channel 2
1795 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1796 * @param DACx DAC instance
1797 * @retval None
1798 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)1799 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1800 {
1801 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1802 }
1803
1804
1805 /**
1806 * @brief Get DMA underrun interrupt for DAC channel 1
1807 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1808 * @param DACx DAC instance
1809 * @retval State of bit (1 or 0).
1810 */
LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef * DACx)1811 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1812 {
1813 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1814 }
1815
1816
1817 /**
1818 * @brief Get DMA underrun interrupt for DAC channel 2
1819 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1820 * @param DACx DAC instance
1821 * @retval State of bit (1 or 0).
1822 */
LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef * DACx)1823 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1824 {
1825 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
1826 }
1827
1828
1829 /**
1830 * @}
1831 */
1832
1833 #if defined(USE_FULL_LL_DRIVER)
1834 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1835 * @{
1836 */
1837
1838 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
1839 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
1840 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
1841
1842 /**
1843 * @}
1844 */
1845 #endif /* USE_FULL_LL_DRIVER */
1846
1847 /**
1848 * @}
1849 */
1850
1851 /**
1852 * @}
1853 */
1854
1855 #endif /* DAC1 || DAC2 */
1856
1857 /**
1858 * @}
1859 */
1860
1861 #ifdef __cplusplus
1862 }
1863 #endif
1864
1865 #endif /* STM32H7xx_LL_DAC_H */
1866
1867
