1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL CORTEX driver contains a set of generic APIs that can be
12 used by user:
13 (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
14 functions
15 (+) Low power mode configuration (SCB register of Cortex-MCU)
16 (+) MPU API to configure and enable regions
17 (+) API to access to MCU info (CPUID register)
18 (+) API to enable fault handler (SHCSR accesses)
19
20 @endverbatim
21 ******************************************************************************
22 * @attention
23 *
24 * Copyright (c) 2017 STMicroelectronics.
25 * All rights reserved.
26 *
27 * This software is licensed under terms that can be found in the LICENSE file in
28 * the root directory of this software component.
29 * If no LICENSE file comes with this software, it is provided AS-IS.
30 *
31 ******************************************************************************
32 */
33
34 /* Define to prevent recursive inclusion -------------------------------------*/
35 #ifndef STM32H7xx_LL_CORTEX_H
36 #define STM32H7xx_LL_CORTEX_H
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 /* Includes ------------------------------------------------------------------*/
43 #include "stm32h7xx.h"
44
45 /** @addtogroup STM32H7xx_LL_Driver
46 * @{
47 */
48
49 /** @defgroup CORTEX_LL CORTEX
50 * @{
51 */
52
53 /* Private types -------------------------------------------------------------*/
54 /* Private variables ---------------------------------------------------------*/
55
56 /* Private constants ---------------------------------------------------------*/
57
58 /* Private macros ------------------------------------------------------------*/
59
60 /* Exported types ------------------------------------------------------------*/
61 /* Exported constants --------------------------------------------------------*/
62 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
63 * @{
64 */
65
66 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
67 * @{
68 */
69 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000UL /*!< AHB clock divided by 8 selected as SysTick clock source.*/
70 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
71 /**
72 * @}
73 */
74
75 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
76 * @{
77 */
78 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
79 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
80 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
81 /**
82 * @}
83 */
84
85 #if __MPU_PRESENT
86
87 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
88 * @{
89 */
90 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000UL /*!< Disable NMI and privileged SW access */
91 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
92 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
93 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
94 /**
95 * @}
96 */
97
98 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
99 * @{
100 */
101 #define LL_MPU_REGION_NUMBER0 0x00UL /*!< REGION Number 0 */
102 #define LL_MPU_REGION_NUMBER1 0x01UL /*!< REGION Number 1 */
103 #define LL_MPU_REGION_NUMBER2 0x02UL /*!< REGION Number 2 */
104 #define LL_MPU_REGION_NUMBER3 0x03UL /*!< REGION Number 3 */
105 #define LL_MPU_REGION_NUMBER4 0x04UL /*!< REGION Number 4 */
106 #define LL_MPU_REGION_NUMBER5 0x05UL /*!< REGION Number 5 */
107 #define LL_MPU_REGION_NUMBER6 0x06UL /*!< REGION Number 6 */
108 #define LL_MPU_REGION_NUMBER7 0x07UL /*!< REGION Number 7 */
109 #if !defined(CORE_CM4)
110 #define LL_MPU_REGION_NUMBER8 0x08UL /*!< REGION Number 8 */
111 #define LL_MPU_REGION_NUMBER9 0x09UL /*!< REGION Number 9 */
112 #define LL_MPU_REGION_NUMBER10 0x0AUL /*!< REGION Number 10 */
113 #define LL_MPU_REGION_NUMBER11 0x0BUL /*!< REGION Number 11 */
114 #define LL_MPU_REGION_NUMBER12 0x0CUL /*!< REGION Number 12 */
115 #define LL_MPU_REGION_NUMBER13 0x0DUL /*!< REGION Number 13 */
116 #define LL_MPU_REGION_NUMBER14 0x0EUL /*!< REGION Number 14 */
117 #define LL_MPU_REGION_NUMBER15 0x0FUL /*!< REGION Number 15 */
118 #endif /* !defined(CORE_CM4) */
119 /**
120 * @}
121 */
122
123 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
124 * @{
125 */
126 #define LL_MPU_REGION_SIZE_32B (0x04UL << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
127 #define LL_MPU_REGION_SIZE_64B (0x05UL << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
128 #define LL_MPU_REGION_SIZE_128B (0x06UL << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
129 #define LL_MPU_REGION_SIZE_256B (0x07UL << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
130 #define LL_MPU_REGION_SIZE_512B (0x08UL << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
131 #define LL_MPU_REGION_SIZE_1KB (0x09UL << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
132 #define LL_MPU_REGION_SIZE_2KB (0x0AUL << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
133 #define LL_MPU_REGION_SIZE_4KB (0x0BUL << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
134 #define LL_MPU_REGION_SIZE_8KB (0x0CUL << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
135 #define LL_MPU_REGION_SIZE_16KB (0x0DUL << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
136 #define LL_MPU_REGION_SIZE_32KB (0x0EUL << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
137 #define LL_MPU_REGION_SIZE_64KB (0x0FUL << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
138 #define LL_MPU_REGION_SIZE_128KB (0x10UL << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
139 #define LL_MPU_REGION_SIZE_256KB (0x11UL << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
140 #define LL_MPU_REGION_SIZE_512KB (0x12UL << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
141 #define LL_MPU_REGION_SIZE_1MB (0x13UL << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
142 #define LL_MPU_REGION_SIZE_2MB (0x14UL << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
143 #define LL_MPU_REGION_SIZE_4MB (0x15UL << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
144 #define LL_MPU_REGION_SIZE_8MB (0x16UL << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
145 #define LL_MPU_REGION_SIZE_16MB (0x17UL << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
146 #define LL_MPU_REGION_SIZE_32MB (0x18UL << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
147 #define LL_MPU_REGION_SIZE_64MB (0x19UL << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
148 #define LL_MPU_REGION_SIZE_128MB (0x1AUL << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
149 #define LL_MPU_REGION_SIZE_256MB (0x1BUL << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
150 #define LL_MPU_REGION_SIZE_512MB (0x1CUL << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
151 #define LL_MPU_REGION_SIZE_1GB (0x1DUL << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
152 #define LL_MPU_REGION_SIZE_2GB (0x1EUL << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
153 #define LL_MPU_REGION_SIZE_4GB (0x1FUL << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
154 /**
155 * @}
156 */
157
158 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
159 * @{
160 */
161 #define LL_MPU_REGION_NO_ACCESS (0x00UL << MPU_RASR_AP_Pos) /*!< No access*/
162 #define LL_MPU_REGION_PRIV_RW (0x01UL << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
163 #define LL_MPU_REGION_PRIV_RW_URO (0x02UL << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
164 #define LL_MPU_REGION_FULL_ACCESS (0x03UL << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
165 #define LL_MPU_REGION_PRIV_RO (0x05UL << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
166 #define LL_MPU_REGION_PRIV_RO_URO (0x06UL << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
167 /**
168 * @}
169 */
170
171 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
172 * @{
173 */
174 #define LL_MPU_TEX_LEVEL0 (0x00UL << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
175 #define LL_MPU_TEX_LEVEL1 (0x01UL << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
176 #define LL_MPU_TEX_LEVEL2 (0x02UL << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
177
178 /* Legacy Define */
179 #define LL_MPU_TEX_LEVEL4 (0x04UL << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
180 /**
181 * @}
182 */
183
184 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
185 * @{
186 */
187 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00UL /*!< Instruction fetches enabled */
188 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
189 /**
190 * @}
191 */
192
193 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
194 * @{
195 */
196 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
197 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00UL /*!< Not Shareable memory attribute */
198 /**
199 * @}
200 */
201
202 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
203 * @{
204 */
205 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
206 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00UL /*!< Not Cacheable memory attribute */
207 /**
208 * @}
209 */
210
211 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
212 * @{
213 */
214 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
215 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00UL /*!< Not Bufferable memory attribute */
216 /**
217 * @}
218 */
219 #endif /* __MPU_PRESENT */
220 /**
221 * @}
222 */
223
224 /* Exported macro ------------------------------------------------------------*/
225
226 /* Exported functions --------------------------------------------------------*/
227 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
228 * @{
229 */
230
231 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
232 * @{
233 */
234
235 /**
236 * @brief This function checks if the Systick counter flag is active or not.
237 * @note It can be used in timeout function on application side.
238 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
239 * @retval State of bit (1 or 0).
240 */
LL_SYSTICK_IsActiveCounterFlag(void)241 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
242 {
243 return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
244 }
245
246 /**
247 * @brief Configures the SysTick clock source
248 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
249 * @param Source This parameter can be one of the following values:
250 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
251 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
252 * @retval None
253 */
LL_SYSTICK_SetClkSource(uint32_t Source)254 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
255 {
256 MODIFY_REG(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK, Source);
257 }
258
259 /**
260 * @brief Get the SysTick clock source
261 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
262 * @retval Returned value can be one of the following values:
263 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
264 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
265 */
LL_SYSTICK_GetClkSource(void)266 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
267 {
268 return (uint32_t)(READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK));
269 }
270
271 /**
272 * @brief Enable SysTick exception request
273 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
274 * @retval None
275 */
LL_SYSTICK_EnableIT(void)276 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
277 {
278 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
279 }
280
281 /**
282 * @brief Disable SysTick exception request
283 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
284 * @retval None
285 */
LL_SYSTICK_DisableIT(void)286 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
287 {
288 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
289 }
290
291 /**
292 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
293 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
294 * @retval State of bit (1 or 0).
295 */
LL_SYSTICK_IsEnabledIT(void)296 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
297 {
298 return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
299 }
300
301 /**
302 * @}
303 */
304
305 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
306 * @{
307 */
308
309 /**
310 * @brief Processor uses sleep as its low power mode
311 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
312 * @retval None
313 */
LL_LPM_EnableSleep(void)314 __STATIC_INLINE void LL_LPM_EnableSleep(void)
315 {
316 /* Clear SLEEPDEEP bit of Cortex System Control Register */
317 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
318 }
319
320 /**
321 * @brief Processor uses deep sleep as its low power mode
322 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
323 * @retval None
324 */
LL_LPM_EnableDeepSleep(void)325 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
326 {
327 /* Set SLEEPDEEP bit of Cortex System Control Register */
328 SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
329 }
330
331 /**
332 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
333 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
334 * empty main application.
335 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
336 * @retval None
337 */
LL_LPM_EnableSleepOnExit(void)338 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
339 {
340 /* Set SLEEPONEXIT bit of Cortex System Control Register */
341 SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
342 }
343
344 /**
345 * @brief Do not sleep when returning to Thread mode.
346 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
347 * @retval None
348 */
LL_LPM_DisableSleepOnExit(void)349 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
350 {
351 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
352 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
353 }
354
355 /**
356 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
357 * processor.
358 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
359 * @retval None
360 */
LL_LPM_EnableEventOnPend(void)361 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
362 {
363 /* Set SEVEONPEND bit of Cortex System Control Register */
364 SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
365 }
366
367 /**
368 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
369 * excluded
370 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
371 * @retval None
372 */
LL_LPM_DisableEventOnPend(void)373 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
374 {
375 /* Clear SEVEONPEND bit of Cortex System Control Register */
376 CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
377 }
378
379 /**
380 * @}
381 */
382
383 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
384 * @{
385 */
386
387 /**
388 * @brief Enable a fault in System handler control register (SHCSR)
389 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
390 * @param Fault This parameter can be a combination of the following values:
391 * @arg @ref LL_HANDLER_FAULT_USG
392 * @arg @ref LL_HANDLER_FAULT_BUS
393 * @arg @ref LL_HANDLER_FAULT_MEM
394 * @retval None
395 */
LL_HANDLER_EnableFault(uint32_t Fault)396 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
397 {
398 /* Enable the system handler fault */
399 SET_BIT(SCB->SHCSR, Fault);
400 }
401
402 /**
403 * @brief Disable a fault in System handler control register (SHCSR)
404 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
405 * @param Fault This parameter can be a combination of the following values:
406 * @arg @ref LL_HANDLER_FAULT_USG
407 * @arg @ref LL_HANDLER_FAULT_BUS
408 * @arg @ref LL_HANDLER_FAULT_MEM
409 * @retval None
410 */
LL_HANDLER_DisableFault(uint32_t Fault)411 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
412 {
413 /* Disable the system handler fault */
414 CLEAR_BIT(SCB->SHCSR, Fault);
415 }
416
417 /**
418 * @}
419 */
420
421 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
422 * @{
423 */
424
425 /**
426 * @brief Get Implementer code
427 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
428 * @retval Value should be equal to 0x41 for ARM
429 */
LL_CPUID_GetImplementer(void)430 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
431 {
432 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
433 }
434
435 /**
436 * @brief Get Variant number (The r value in the rnpn product revision identifier)
437 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
438 * @retval Value between 0 and 255 (0x0: revision 0)
439 */
LL_CPUID_GetVariant(void)440 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
441 {
442 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
443 }
444
445 /**
446 * @brief Get Constant number
447 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
448 * @retval Value should be equal to 0xF for Cortex-M7 and Cortex-M4 devices
449 */
LL_CPUID_GetConstant(void)450 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
451 {
452 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
453 }
454
455 /**
456 * @brief Get Part number
457 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
458 * @retval Value should be equal to 0xC27 for Cortex-M7 and equal to 0xC24 for Cortex-M4
459 */
LL_CPUID_GetParNo(void)460 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
461 {
462 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
463 }
464
465 /**
466 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
467 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
468 * @retval Value between 0 and 255 (0x1: patch 1)
469 */
LL_CPUID_GetRevision(void)470 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
471 {
472 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
473 }
474
475 /**
476 * @}
477 */
478
479 #if __MPU_PRESENT
480 /** @defgroup CORTEX_LL_EF_MPU MPU
481 * @{
482 */
483
484 /**
485 * @brief Enable MPU with input options
486 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
487 * @param Options This parameter can be one of the following values:
488 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
489 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
490 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
491 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
492 * @retval None
493 */
LL_MPU_Enable(uint32_t Options)494 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
495 {
496 /* Enable the MPU*/
497 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
498 /* Ensure MPU settings take effects */
499 __DSB();
500 /* Sequence instruction fetches using update settings */
501 __ISB();
502 }
503
504 /**
505 * @brief Disable MPU
506 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
507 * @retval None
508 */
LL_MPU_Disable(void)509 __STATIC_INLINE void LL_MPU_Disable(void)
510 {
511 /* Make sure outstanding transfers are done */
512 __DMB();
513 /* Disable MPU*/
514 WRITE_REG(MPU->CTRL, 0U);
515 }
516
517 /**
518 * @brief Check if MPU is enabled or not
519 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
520 * @retval State of bit (1 or 0).
521 */
LL_MPU_IsEnabled(void)522 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
523 {
524 return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
525 }
526
527 /**
528 * @brief Enable a MPU region
529 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
530 * @param Region This parameter can be one of the following values:
531 * @arg @ref LL_MPU_REGION_NUMBER0
532 * @arg @ref LL_MPU_REGION_NUMBER1
533 * @arg @ref LL_MPU_REGION_NUMBER2
534 * @arg @ref LL_MPU_REGION_NUMBER3
535 * @arg @ref LL_MPU_REGION_NUMBER4
536 * @arg @ref LL_MPU_REGION_NUMBER5
537 * @arg @ref LL_MPU_REGION_NUMBER6
538 * @arg @ref LL_MPU_REGION_NUMBER7
539 * @arg @ref LL_MPU_REGION_NUMBER8
540 * @arg @ref LL_MPU_REGION_NUMBER9
541 * @arg @ref LL_MPU_REGION_NUMBER10
542 * @arg @ref LL_MPU_REGION_NUMBER11
543 * @arg @ref LL_MPU_REGION_NUMBER12
544 * @arg @ref LL_MPU_REGION_NUMBER13
545 * @arg @ref LL_MPU_REGION_NUMBER14
546 * @arg @ref LL_MPU_REGION_NUMBER15
547 * @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
548 * @retval None
549 */
LL_MPU_EnableRegion(uint32_t Region)550 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
551 {
552 /* Set Region number */
553 WRITE_REG(MPU->RNR, Region);
554 /* Enable the MPU region */
555 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
556 }
557
558 /**
559 * @brief Configure and enable a region
560 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
561 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
562 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
563 * MPU_RASR XN LL_MPU_ConfigRegion\n
564 * MPU_RASR AP LL_MPU_ConfigRegion\n
565 * MPU_RASR S LL_MPU_ConfigRegion\n
566 * MPU_RASR C LL_MPU_ConfigRegion\n
567 * MPU_RASR B LL_MPU_ConfigRegion\n
568 * MPU_RASR SIZE LL_MPU_ConfigRegion
569 * @param Region This parameter can be one of the following values:
570 * @arg @ref LL_MPU_REGION_NUMBER0
571 * @arg @ref LL_MPU_REGION_NUMBER1
572 * @arg @ref LL_MPU_REGION_NUMBER2
573 * @arg @ref LL_MPU_REGION_NUMBER3
574 * @arg @ref LL_MPU_REGION_NUMBER4
575 * @arg @ref LL_MPU_REGION_NUMBER5
576 * @arg @ref LL_MPU_REGION_NUMBER6
577 * @arg @ref LL_MPU_REGION_NUMBER7
578 * @arg @ref LL_MPU_REGION_NUMBER8
579 * @arg @ref LL_MPU_REGION_NUMBER9
580 * @arg @ref LL_MPU_REGION_NUMBER10
581 * @arg @ref LL_MPU_REGION_NUMBER11
582 * @arg @ref LL_MPU_REGION_NUMBER12
583 * @arg @ref LL_MPU_REGION_NUMBER13
584 * @arg @ref LL_MPU_REGION_NUMBER14
585 * @arg @ref LL_MPU_REGION_NUMBER15
586 * @param Address Value of region base address
587 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
588 * @param Attributes This parameter can be a combination of the following values:
589 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
590 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
591 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
592 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
593 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
594 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
595 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
596 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
597 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2
598 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
599 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
600 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
601 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
602 * @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
603 * @retval None
604 */
LL_MPU_ConfigRegion(uint32_t Region,uint32_t SubRegionDisable,uint32_t Address,uint32_t Attributes)605 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
606 {
607 /* Set Region number */
608 WRITE_REG(MPU->RNR, Region);
609 /* Set base address */
610 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
611 /* Configure MPU */
612 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
613 }
614
615 /**
616 * @brief Disable a region
617 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
618 * MPU_RASR ENABLE LL_MPU_DisableRegion
619 * @param Region This parameter can be one of the following values:
620 * @arg @ref LL_MPU_REGION_NUMBER0
621 * @arg @ref LL_MPU_REGION_NUMBER1
622 * @arg @ref LL_MPU_REGION_NUMBER2
623 * @arg @ref LL_MPU_REGION_NUMBER3
624 * @arg @ref LL_MPU_REGION_NUMBER4
625 * @arg @ref LL_MPU_REGION_NUMBER5
626 * @arg @ref LL_MPU_REGION_NUMBER6
627 * @arg @ref LL_MPU_REGION_NUMBER7
628 * @arg @ref LL_MPU_REGION_NUMBER8
629 * @arg @ref LL_MPU_REGION_NUMBER9
630 * @arg @ref LL_MPU_REGION_NUMBER10
631 * @arg @ref LL_MPU_REGION_NUMBER11
632 * @arg @ref LL_MPU_REGION_NUMBER12
633 * @arg @ref LL_MPU_REGION_NUMBER13
634 * @arg @ref LL_MPU_REGION_NUMBER14
635 * @arg @ref LL_MPU_REGION_NUMBER15
636 * @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
637 * @retval None
638 */
LL_MPU_DisableRegion(uint32_t Region)639 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
640 {
641 /* Set Region number */
642 WRITE_REG(MPU->RNR, Region);
643 /* Disable the MPU region */
644 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
645 }
646
647 /**
648 * @}
649 */
650
651 #endif /* __MPU_PRESENT */
652 /**
653 * @}
654 */
655
656 /**
657 * @}
658 */
659
660 /**
661 * @}
662 */
663
664 #ifdef __cplusplus
665 }
666 #endif
667
668 #endif /* STM32H7xx_LL_CORTEX_H */
669
670
