1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_bdma.h
4 * @author MCD Application Team
5 * @brief Header file of BDMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7xx_LL_BDMA_H
21 #define STM32H7xx_LL_BDMA_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7xx.h"
29 #include "stm32h7xx_ll_dmamux.h"
30
31 /** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (BDMA) || defined (BDMA1) || defined (BDMA2)
36
37 /** @defgroup BDMA_LL BDMA
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup BDMA_LL_Private_Variables BDMA Private Variables
44 * @{
45 */
46 /* Array used to get the BDMA channel register offset versus channel index LL_BDMA_CHANNEL_x */
47 static const uint8_t LL_BDMA_CH_OFFSET_TAB[] =
48 {
49 (uint8_t)(BDMA_Channel0_BASE - BDMA_BASE),
50 (uint8_t)(BDMA_Channel1_BASE - BDMA_BASE),
51 (uint8_t)(BDMA_Channel2_BASE - BDMA_BASE),
52 (uint8_t)(BDMA_Channel3_BASE - BDMA_BASE),
53 (uint8_t)(BDMA_Channel4_BASE - BDMA_BASE),
54 (uint8_t)(BDMA_Channel5_BASE - BDMA_BASE),
55 (uint8_t)(BDMA_Channel6_BASE - BDMA_BASE),
56 (uint8_t)(BDMA_Channel7_BASE - BDMA_BASE)
57 };
58 /**
59 * @}
60 */
61
62 /* Private constants ---------------------------------------------------------*/
63 /* Private macros ------------------------------------------------------------*/
64 /** @defgroup BDMA_LL_Private_Macros BDMA Private Macros
65 * @{
66 */
67 #if !defined(UNUSED)
68 #define UNUSED(x) ((void)(x))
69 #endif
70 /**
71 * @}
72 */
73 /* Exported types ------------------------------------------------------------*/
74 #if defined(USE_FULL_LL_DRIVER)
75 /** @defgroup BDMA_LL_ES_INIT BDMA Exported Init structure
76 * @{
77 */
78 typedef struct
79 {
80 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for BDMA transfer
81 or as Source base address in case of memory to memory transfer direction.
82
83 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
84
85 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
86 or as Destination base address in case of memory to memory transfer direction.
87
88 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
89
90 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
91 from memory to memory or from peripheral to memory.
92 This parameter can be a value of @ref BDMA_LL_EC_DIRECTION
93
94 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataTransferDirection(). */
95
96 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
97 This parameter can be a value of @ref BDMA_LL_EC_MODE
98 @note: The circular buffer mode cannot be used if the memory to memory
99 data transfer direction is configured on the selected Channel
100
101 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMode(). */
102
103 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
104 is incremented or not.
105 This parameter can be a value of @ref BDMA_LL_EC_PERIPH
106
107 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphIncMode(). */
108
109 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
110 is incremented or not.
111 This parameter can be a value of @ref BDMA_LL_EC_MEMORY
112
113 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemoryIncMode(). */
114
115 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
116 in case of memory to memory transfer direction.
117 This parameter can be a value of @ref BDMA_LL_EC_PDATAALIGN
118
119 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphSize(). */
120
121 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
122 in case of memory to memory transfer direction.
123 This parameter can be a value of @ref BDMA_LL_EC_MDATAALIGN
124
125 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemorySize(). */
126
127 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
128 The data unit is equal to the source buffer configuration set in PeripheralSize
129 or MemorySize parameters depending in the transfer direction.
130 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
131
132 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataLength(). */
133
134 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
135 This parameter can be a value of @ref DMAMUX2_Request_selection
136
137 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphRequest(). */
138
139 uint32_t Priority; /*!< Specifies the channel priority level.
140 This parameter can be a value of @ref BDMA_LL_EC_PRIORITY
141
142 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetChannelPriorityLevel(). */
143
144 } LL_BDMA_InitTypeDef;
145 /**
146 * @}
147 */
148 #endif /* USE_FULL_LL_DRIVER */
149
150 /* Exported constants --------------------------------------------------------*/
151 /** @defgroup BDMA_LL_Exported_Constants BDMA Exported Constants
152 * @{
153 */
154 /** @defgroup BDMA_LL_EC_CLEAR_FLAG Clear Flags Defines
155 * @brief Flags defines which can be used with LL_BDMA_WriteReg function
156 * @{
157 */
158 #define LL_BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1 /*!< Channel 1 global flag */
159 #define LL_BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
160 #define LL_BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
161 #define LL_BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
162 #define LL_BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2 /*!< Channel 2 global flag */
163 #define LL_BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
164 #define LL_BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
165 #define LL_BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
166 #define LL_BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3 /*!< Channel 3 global flag */
167 #define LL_BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
168 #define LL_BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
169 #define LL_BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
170 #define LL_BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4 /*!< Channel 4 global flag */
171 #define LL_BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
172 #define LL_BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
173 #define LL_BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
174 #define LL_BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5 /*!< Channel 5 global flag */
175 #define LL_BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
176 #define LL_BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
177 #define LL_BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
178 #define LL_BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6 /*!< Channel 6 global flag */
179 #define LL_BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
180 #define LL_BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
181 #define LL_BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
182 #define LL_BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7 /*!< Channel 7 global flag */
183 #define LL_BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
184 #define LL_BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
185 #define LL_BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
186 /**
187 * @}
188 */
189
190 /** @defgroup BDMA_LL_EC_GET_FLAG Get Flags Defines
191 * @brief Flags defines which can be used with LL_BDMA_ReadReg function
192 * @{
193 */
194 #define LL_BDMA_ISR_GIF0 BDMA_ISR_GIF0 /*!< Channel 1 global flag */
195 #define LL_BDMA_ISR_TCIF0 BDMA_ISR_TCIF0 /*!< Channel 1 transfer complete flag */
196 #define LL_BDMA_ISR_HTIF0 BDMA_ISR_HTIF0 /*!< Channel 1 half transfer flag */
197 #define LL_BDMA_ISR_TEIF0 BDMA_ISR_TEIF0 /*!< Channel 1 transfer error flag */
198 #define LL_BDMA_ISR_GIF1 BDMA_ISR_GIF1 /*!< Channel 1 global flag */
199 #define LL_BDMA_ISR_TCIF1 BDMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
200 #define LL_BDMA_ISR_HTIF1 BDMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
201 #define LL_BDMA_ISR_TEIF1 BDMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
202 #define LL_BDMA_ISR_GIF2 BDMA_ISR_GIF2 /*!< Channel 2 global flag */
203 #define LL_BDMA_ISR_TCIF2 BDMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
204 #define LL_BDMA_ISR_HTIF2 BDMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
205 #define LL_BDMA_ISR_TEIF2 BDMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
206 #define LL_BDMA_ISR_GIF3 BDMA_ISR_GIF3 /*!< Channel 3 global flag */
207 #define LL_BDMA_ISR_TCIF3 BDMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
208 #define LL_BDMA_ISR_HTIF3 BDMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
209 #define LL_BDMA_ISR_TEIF3 BDMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
210 #define LL_BDMA_ISR_GIF4 BDMA_ISR_GIF4 /*!< Channel 4 global flag */
211 #define LL_BDMA_ISR_TCIF4 BDMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
212 #define LL_BDMA_ISR_HTIF4 BDMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
213 #define LL_BDMA_ISR_TEIF4 BDMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
214 #define LL_BDMA_ISR_GIF5 BDMA_ISR_GIF5 /*!< Channel 5 global flag */
215 #define LL_BDMA_ISR_TCIF5 BDMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
216 #define LL_BDMA_ISR_HTIF5 BDMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
217 #define LL_BDMA_ISR_TEIF5 BDMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
218 #define LL_BDMA_ISR_GIF6 BDMA_ISR_GIF6 /*!< Channel 6 global flag */
219 #define LL_BDMA_ISR_TCIF6 BDMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
220 #define LL_BDMA_ISR_HTIF6 BDMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
221 #define LL_BDMA_ISR_TEIF6 BDMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
222 #define LL_BDMA_ISR_GIF7 BDMA_ISR_GIF7 /*!< Channel 7 global flag */
223 #define LL_BDMA_ISR_TCIF7 BDMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
224 #define LL_BDMA_ISR_HTIF7 BDMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
225 #define LL_BDMA_ISR_TEIF7 BDMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
226 /**
227 * @}
228 */
229
230 /** @defgroup BDMA_LL_EC_IT IT Defines
231 * @brief IT defines which can be used with LL_BDMA_ReadReg and LL_BDMA_WriteReg functions
232 * @{
233 */
234 #define LL_BDMA_CCR_TCIE BDMA_CCR_TCIE /*!< Transfer complete interrupt */
235 #define LL_BDMA_CCR_HTIE BDMA_CCR_HTIE /*!< Half Transfer interrupt */
236 #define LL_BDMA_CCR_TEIE BDMA_CCR_TEIE /*!< Transfer error interrupt */
237 /**
238 * @}
239 */
240
241 /** @defgroup BDMA_LL_EC_CHANNEL CHANNEL
242 * @{
243 */
244 #define LL_BDMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */
245 #define LL_BDMA_CHANNEL_1 0x00000001U /*!< BDMA Channel 1 */
246 #define LL_BDMA_CHANNEL_2 0x00000002U /*!< BDMA Channel 2 */
247 #define LL_BDMA_CHANNEL_3 0x00000003U /*!< BDMA Channel 3 */
248 #define LL_BDMA_CHANNEL_4 0x00000004U /*!< BDMA Channel 4 */
249 #define LL_BDMA_CHANNEL_5 0x00000005U /*!< BDMA Channel 5 */
250 #define LL_BDMA_CHANNEL_6 0x00000006U /*!< BDMA Channel 6 */
251 #define LL_BDMA_CHANNEL_7 0x00000007U /*!< BDMA Channel 7 */
252 #if defined(USE_FULL_LL_DRIVER)
253 #define LL_BDMA_CHANNEL_ALL 0xFFFF0000U /*!< BDMA Channel all (used only for function @ref LL_BDMA_DeInit(). */
254 #endif /*USE_FULL_LL_DRIVER*/
255 /**
256 * @}
257 */
258
259 /** @defgroup BDMA_LL_EC_DIRECTION Transfer Direction
260 * @{
261 */
262 #define LL_BDMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
263 #define LL_BDMA_DIRECTION_MEMORY_TO_PERIPH BDMA_CCR_DIR /*!< Memory to peripheral direction */
264 #define LL_BDMA_DIRECTION_MEMORY_TO_MEMORY BDMA_CCR_MEM2MEM /*!< Memory to memory direction */
265 /**
266 * @}
267 */
268
269 /** @defgroup BDMA_LL_EC_MODE Transfer mode
270 * @{
271 */
272 #define LL_BDMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
273 #define LL_BDMA_MODE_CIRCULAR BDMA_CCR_CIRC /*!< Circular Mode */
274 /**
275 * @}
276 */
277
278 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
279 * @{
280 */
281 #define LL_BDMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */
282 #define LL_BDMA_DOUBLEBUFFER_MODE_ENABLE BDMA_CCR_DBM /*!< Enable double buffering mode */
283 /**
284 * @}
285 */
286
287 /** @defgroup BDMA_LL_EC_PERIPH Peripheral increment mode
288 * @{
289 */
290 #define LL_BDMA_PERIPH_INCREMENT BDMA_CCR_PINC /*!< Peripheral increment mode Enable */
291 #define LL_BDMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
292 /**
293 * @}
294 */
295
296 /** @defgroup BDMA_LL_EC_MEMORY Memory increment mode
297 * @{
298 */
299 #define LL_BDMA_MEMORY_INCREMENT BDMA_CCR_MINC /*!< Memory increment mode Enable */
300 #define LL_BDMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
301 /**
302 * @}
303 */
304
305 /** @defgroup BDMA_LL_EC_PDATAALIGN Peripheral data alignment
306 * @{
307 */
308 #define LL_BDMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
309 #define LL_BDMA_PDATAALIGN_HALFWORD BDMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
310 #define LL_BDMA_PDATAALIGN_WORD BDMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
311 /**
312 * @}
313 */
314
315 /** @defgroup BDMA_LL_EC_MDATAALIGN Memory data alignment
316 * @{
317 */
318 #define LL_BDMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
319 #define LL_BDMA_MDATAALIGN_HALFWORD BDMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
320 #define LL_BDMA_MDATAALIGN_WORD BDMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
321 /**
322 * @}
323 */
324
325 /** @defgroup BDMA_LL_EC_PRIORITY Transfer Priority level
326 * @{
327 */
328 #define LL_BDMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
329 #define LL_BDMA_PRIORITY_MEDIUM BDMA_CCR_PL_0 /*!< Priority level : Medium */
330 #define LL_BDMA_PRIORITY_HIGH BDMA_CCR_PL_1 /*!< Priority level : High */
331 #define LL_BDMA_PRIORITY_VERYHIGH BDMA_CCR_PL /*!< Priority level : Very_High */
332 /**
333 * @}
334 */
335
336 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
337 * @{
338 */
339 #define LL_BDMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
340 #define LL_BDMA_CURRENTTARGETMEM1 BDMA_CCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
341 /**
342 * @}
343 */
344
345 /**
346 * @}
347 */
348 /* Exported macro ------------------------------------------------------------*/
349 /** @defgroup BDMA_LL_Exported_Macros BDMA Exported Macros
350 * @{
351 */
352
353 /** @defgroup BDMA_LL_EM_WRITE_READ Common Write and read registers macros
354 * @{
355 */
356 /**
357 * @brief Write a value in BDMA register
358 * @param __INSTANCE__ BDMA Instance
359 * @param __REG__ Register to be written
360 * @param __VALUE__ Value to be written in the register
361 * @retval None
362 */
363 #define LL_BDMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
364
365 /**
366 * @brief Read a value in BDMA register
367 * @param __INSTANCE__ BDMA Instance
368 * @param __REG__ Register to be read
369 * @retval Register value
370 */
371 #define LL_BDMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
372 /**
373 * @}
374 */
375
376 /** @defgroup BDMA_LL_EM_CONVERT_DMAxCHANNELy Convert BDMAxChannely
377 * @{
378 */
379 /**
380 * @brief Convert BDMAx_Channely into BDMAx
381 * @param __CHANNEL_INSTANCE__ BDMAx_Channely
382 * @retval BDMAx
383 */
384 #if defined (BDMA1)
385 #define __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
386 (((uint32_t)(__CHANNEL_INSTANCE__) < LL_BDMA_CHANNEL_0) ? BDMA1 : BDMA)
387 #else
388 #define __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (BDMA)
389 #endif /* BDMA1 */
390
391 /**
392 * @brief Convert BDMAx_Channely into LL_BDMA_CHANNEL_y
393 * @param __CHANNEL_INSTANCE__ BDMAx_Channely
394 * @retval LL_BDMA_CHANNEL_y
395 */
396 #if defined (BDMA1)
397 #define __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
398 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0)) ? LL_BDMA_CHANNEL_0 : \
399 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel0)) ? LL_BDMA_CHANNEL_0 : \
400 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1)) ? LL_BDMA_CHANNEL_1 : \
401 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel1)) ? LL_BDMA_CHANNEL_1 : \
402 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2)) ? LL_BDMA_CHANNEL_2 : \
403 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel2)) ? LL_BDMA_CHANNEL_2 : \
404 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3)) ? LL_BDMA_CHANNEL_3 : \
405 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel3)) ? LL_BDMA_CHANNEL_3 : \
406 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4)) ? LL_BDMA_CHANNEL_4 : \
407 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel4)) ? LL_BDMA_CHANNEL_4 : \
408 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5)) ? LL_BDMA_CHANNEL_5 : \
409 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel5)) ? LL_BDMA_CHANNEL_5 : \
410 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6)) ? LL_BDMA_CHANNEL_6 : \
411 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel6)) ? LL_BDMA_CHANNEL_6 : \
412 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel7)) ? LL_BDMA_CHANNEL_7 : \
413 LL_BDMA_CHANNEL_7)
414 #else
415 #define __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
416 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0)) ? LL_BDMA_CHANNEL_0 : \
417 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1)) ? LL_BDMA_CHANNEL_1 : \
418 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2)) ? LL_BDMA_CHANNEL_2 : \
419 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3)) ? LL_BDMA_CHANNEL_3 : \
420 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4)) ? LL_BDMA_CHANNEL_4 : \
421 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5)) ? LL_BDMA_CHANNEL_5 : \
422 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6)) ? LL_BDMA_CHANNEL_6 : \
423 LL_BDMA_CHANNEL_7)
424 #endif /* BDMA1 */
425
426 /**
427 * @brief Convert BDMA Instance BDMAx and LL_BDMA_CHANNEL_y into BDMAx_Channely
428 * @param __BDMA_INSTANCE__ BDMAx
429 * @param __CHANNEL__ LL_BDMA_CHANNEL_y
430 * @retval BDMAx_Channely
431 */
432 #if defined (BDMA1)
433 #define __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__) \
434 ((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0 : \
435 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA1_Channel0 : \
436 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1 : \
437 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA1_Channel1 : \
438 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2 : \
439 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA1_Channel2 : \
440 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3 : \
441 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA1_Channel3 : \
442 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4 : \
443 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA1_Channel4 : \
444 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5 : \
445 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA1_Channel5 : \
446 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6 : \
447 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA1_Channel6 : \
448 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_7))) ? BDMA_Channel7 : \
449 BDMA1_Channel7)
450 #else
451 #define __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__) \
452 ((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0 : \
453 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1 : \
454 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2 : \
455 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3 : \
456 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4 : \
457 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5 : \
458 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6 : \
459 BDMA_Channel7)
460 #endif /* BDMA1 */
461 /**
462 * @}
463 */
464
465 /**
466 * @}
467 */
468
469 /* Exported functions --------------------------------------------------------*/
470 /** @defgroup BDMA_LL_Exported_Functions BDMA Exported Functions
471 * @{
472 */
473
474 /** @defgroup BDMA_LL_EF_Configuration Configuration
475 * @{
476 */
477 /**
478 * @brief Enable BDMA channel.
479 * @rmtoll CCR EN LL_BDMA_EnableChannel
480 * @param BDMAx BDMA Instance
481 * @param Channel This parameter can be one of the following values:
482 * @arg @ref LL_BDMA_CHANNEL_0
483 * @arg @ref LL_BDMA_CHANNEL_1
484 * @arg @ref LL_BDMA_CHANNEL_2
485 * @arg @ref LL_BDMA_CHANNEL_3
486 * @arg @ref LL_BDMA_CHANNEL_4
487 * @arg @ref LL_BDMA_CHANNEL_5
488 * @arg @ref LL_BDMA_CHANNEL_6
489 * @arg @ref LL_BDMA_CHANNEL_7
490 * @retval None
491 */
LL_BDMA_EnableChannel(BDMA_TypeDef * BDMAx,uint32_t Channel)492 __STATIC_INLINE void LL_BDMA_EnableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)
493 {
494 uint32_t bdma_base_addr = (uint32_t)BDMAx;
495
496 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN);
497 }
498
499 /**
500 * @brief Disable BDMA channel.
501 * @rmtoll CCR EN LL_BDMA_DisableChannel
502 * @param BDMAx BDMA Instance
503 * @param Channel This parameter can be one of the following values:
504 * @arg @ref LL_BDMA_CHANNEL_0
505 * @arg @ref LL_BDMA_CHANNEL_1
506 * @arg @ref LL_BDMA_CHANNEL_2
507 * @arg @ref LL_BDMA_CHANNEL_3
508 * @arg @ref LL_BDMA_CHANNEL_4
509 * @arg @ref LL_BDMA_CHANNEL_5
510 * @arg @ref LL_BDMA_CHANNEL_6
511 * @arg @ref LL_BDMA_CHANNEL_7
512 * @retval None
513 */
LL_BDMA_DisableChannel(BDMA_TypeDef * BDMAx,uint32_t Channel)514 __STATIC_INLINE void LL_BDMA_DisableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)
515 {
516 uint32_t bdma_base_addr = (uint32_t)BDMAx;
517
518 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN);
519 }
520
521 /**
522 * @brief Check if BDMA channel is enabled or disabled.
523 * @rmtoll CCR EN LL_BDMA_IsEnabledChannel
524 * @param BDMAx BDMA Instance
525 * @param Channel This parameter can be one of the following values:
526 * @arg @ref LL_BDMA_CHANNEL_0
527 * @arg @ref LL_BDMA_CHANNEL_1
528 * @arg @ref LL_BDMA_CHANNEL_2
529 * @arg @ref LL_BDMA_CHANNEL_3
530 * @arg @ref LL_BDMA_CHANNEL_4
531 * @arg @ref LL_BDMA_CHANNEL_5
532 * @arg @ref LL_BDMA_CHANNEL_6
533 * @arg @ref LL_BDMA_CHANNEL_7
534 * @retval State of bit (1 or 0).
535 */
LL_BDMA_IsEnabledChannel(BDMA_TypeDef * BDMAx,uint32_t Channel)536 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)
537 {
538 uint32_t bdma_base_addr = (uint32_t)BDMAx;
539
540 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN) == (BDMA_CCR_EN)) ? 1UL : 0UL);
541 }
542
543 /**
544 * @brief Configure all parameters link to BDMA transfer.
545 * @rmtoll CCR DIR LL_BDMA_ConfigTransfer\n
546 * CCR MEM2MEM LL_BDMA_ConfigTransfer\n
547 * CCR CIRC LL_BDMA_ConfigTransfer\n
548 * CCR PINC LL_BDMA_ConfigTransfer\n
549 * CCR MINC LL_BDMA_ConfigTransfer\n
550 * CCR PSIZE LL_BDMA_ConfigTransfer\n
551 * CCR MSIZE LL_BDMA_ConfigTransfer\n
552 * CCR PL LL_BDMA_ConfigTransfer
553 * @param BDMAx BDMA Instance
554 * @param Channel This parameter can be one of the following values:
555 * @arg @ref LL_BDMA_CHANNEL_0
556 * @arg @ref LL_BDMA_CHANNEL_1
557 * @arg @ref LL_BDMA_CHANNEL_2
558 * @arg @ref LL_BDMA_CHANNEL_3
559 * @arg @ref LL_BDMA_CHANNEL_4
560 * @arg @ref LL_BDMA_CHANNEL_5
561 * @arg @ref LL_BDMA_CHANNEL_6
562 * @arg @ref LL_BDMA_CHANNEL_7
563 * @param Configuration This parameter must be a combination of all the following values:
564 * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY
565 * @arg @ref LL_BDMA_MODE_NORMAL or @ref LL_BDMA_MODE_CIRCULAR
566 * @arg @ref LL_BDMA_PERIPH_INCREMENT or @ref LL_BDMA_PERIPH_NOINCREMENT
567 * @arg @ref LL_BDMA_MEMORY_INCREMENT or @ref LL_BDMA_MEMORY_NOINCREMENT
568 * @arg @ref LL_BDMA_PDATAALIGN_BYTE or @ref LL_BDMA_PDATAALIGN_HALFWORD or @ref LL_BDMA_PDATAALIGN_WORD
569 * @arg @ref LL_BDMA_MDATAALIGN_BYTE or @ref LL_BDMA_MDATAALIGN_HALFWORD or @ref LL_BDMA_MDATAALIGN_WORD
570 * @arg @ref LL_BDMA_PRIORITY_LOW or @ref LL_BDMA_PRIORITY_MEDIUM or @ref LL_BDMA_PRIORITY_HIGH or @ref LL_BDMA_PRIORITY_VERYHIGH
571 * @retval None
572 */
LL_BDMA_ConfigTransfer(BDMA_TypeDef * BDMAx,uint32_t Channel,uint32_t Configuration)573 __STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration)
574 {
575 uint32_t bdma_base_addr = (uint32_t)BDMAx;
576
577 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
578 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_CIRC | BDMA_CCR_PINC | BDMA_CCR_MINC | BDMA_CCR_PSIZE | BDMA_CCR_MSIZE | BDMA_CCR_PL,
579 Configuration);
580 }
581
582 /**
583 * @brief Set Data transfer direction (read from peripheral or from memory).
584 * @rmtoll CCR DIR LL_BDMA_SetDataTransferDirection\n
585 * CCR MEM2MEM LL_BDMA_SetDataTransferDirection
586 * @param BDMAx BDMA Instance
587 * @param Channel This parameter can be one of the following values:
588 * @arg @ref LL_BDMA_CHANNEL_0
589 * @arg @ref LL_BDMA_CHANNEL_1
590 * @arg @ref LL_BDMA_CHANNEL_2
591 * @arg @ref LL_BDMA_CHANNEL_3
592 * @arg @ref LL_BDMA_CHANNEL_4
593 * @arg @ref LL_BDMA_CHANNEL_5
594 * @arg @ref LL_BDMA_CHANNEL_6
595 * @arg @ref LL_BDMA_CHANNEL_7
596 * @param Direction This parameter can be one of the following values:
597 * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY
598 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH
599 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY
600 * @retval None
601 */
LL_BDMA_SetDataTransferDirection(BDMA_TypeDef * BDMAx,uint32_t Channel,uint32_t Direction)602 __STATIC_INLINE void LL_BDMA_SetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction)
603 {
604 uint32_t bdma_base_addr = (uint32_t)BDMAx;
605
606 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
607 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM, Direction);
608 }
609
610 /**
611 * @brief Get Data transfer direction (read from peripheral or from memory).
612 * @rmtoll CCR DIR LL_BDMA_GetDataTransferDirection\n
613 * CCR MEM2MEM LL_BDMA_GetDataTransferDirection
614 * @param BDMAx BDMA Instance
615 * @param Channel This parameter can be one of the following values:
616 * @arg @ref LL_BDMA_CHANNEL_0
617 * @arg @ref LL_BDMA_CHANNEL_1
618 * @arg @ref LL_BDMA_CHANNEL_2
619 * @arg @ref LL_BDMA_CHANNEL_3
620 * @arg @ref LL_BDMA_CHANNEL_4
621 * @arg @ref LL_BDMA_CHANNEL_5
622 * @arg @ref LL_BDMA_CHANNEL_6
623 * @arg @ref LL_BDMA_CHANNEL_7
624 * @retval Returned value can be one of the following values:
625 * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY
626 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH
627 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY
628 */
LL_BDMA_GetDataTransferDirection(BDMA_TypeDef * BDMAx,uint32_t Channel)629 __STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel)
630 {
631 uint32_t bdma_base_addr = (uint32_t)BDMAx;
632
633 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
634 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM));
635 }
636
637 /**
638 * @brief Set BDMA mode circular or normal.
639 * @note The circular buffer mode cannot be used if the memory-to-memory
640 * data transfer is configured on the selected Channel.
641 * @rmtoll CCR CIRC LL_BDMA_SetMode
642 * @param BDMAx BDMA Instance
643 * @param Channel This parameter can be one of the following values:
644 * @arg @ref LL_BDMA_CHANNEL_0
645 * @arg @ref LL_BDMA_CHANNEL_1
646 * @arg @ref LL_BDMA_CHANNEL_2
647 * @arg @ref LL_BDMA_CHANNEL_3
648 * @arg @ref LL_BDMA_CHANNEL_4
649 * @arg @ref LL_BDMA_CHANNEL_5
650 * @arg @ref LL_BDMA_CHANNEL_6
651 * @arg @ref LL_BDMA_CHANNEL_7
652 * @param Mode This parameter can be one of the following values:
653 * @arg @ref LL_BDMA_MODE_NORMAL
654 * @arg @ref LL_BDMA_MODE_CIRCULAR
655 * @retval None
656 */
LL_BDMA_SetMode(BDMA_TypeDef * BDMAx,uint32_t Channel,uint32_t Mode)657 __STATIC_INLINE void LL_BDMA_SetMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode)
658 {
659 uint32_t bdma_base_addr = (uint32_t)BDMAx;
660
661 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CIRC,
662 Mode);
663 }
664
665 /**
666 * @brief Get BDMA mode circular or normal.
667 * @rmtoll CCR CIRC LL_BDMA_GetMode
668 * @param BDMAx BDMA Instance
669 * @param Channel This parameter can be one of the following values:
670 * @arg @ref LL_BDMA_CHANNEL_0
671 * @arg @ref LL_BDMA_CHANNEL_1
672 * @arg @ref LL_BDMA_CHANNEL_2
673 * @arg @ref LL_BDMA_CHANNEL_3
674 * @arg @ref LL_BDMA_CHANNEL_4
675 * @arg @ref LL_BDMA_CHANNEL_5
676 * @arg @ref LL_BDMA_CHANNEL_6
677 * @arg @ref LL_BDMA_CHANNEL_7
678 * @retval Returned value can be one of the following values:
679 * @arg @ref LL_BDMA_MODE_NORMAL
680 * @arg @ref LL_BDMA_MODE_CIRCULAR
681 */
LL_BDMA_GetMode(BDMA_TypeDef * BDMAx,uint32_t Channel)682 __STATIC_INLINE uint32_t LL_BDMA_GetMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
683 {
684 uint32_t bdma_base_addr = (uint32_t)BDMAx;
685
686 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
687 BDMA_CCR_CIRC));
688 }
689
690 /**
691 * @brief Set Peripheral increment mode.
692 * @rmtoll CCR PINC LL_BDMA_SetPeriphIncMode
693 * @param BDMAx BDMA Instance
694 * @param Channel This parameter can be one of the following values:
695 * @arg @ref LL_BDMA_CHANNEL_0
696 * @arg @ref LL_BDMA_CHANNEL_1
697 * @arg @ref LL_BDMA_CHANNEL_2
698 * @arg @ref LL_BDMA_CHANNEL_3
699 * @arg @ref LL_BDMA_CHANNEL_4
700 * @arg @ref LL_BDMA_CHANNEL_5
701 * @arg @ref LL_BDMA_CHANNEL_6
702 * @arg @ref LL_BDMA_CHANNEL_7
703 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
704 * @arg @ref LL_BDMA_PERIPH_INCREMENT
705 * @arg @ref LL_BDMA_PERIPH_NOINCREMENT
706 * @retval None
707 */
LL_BDMA_SetPeriphIncMode(BDMA_TypeDef * BDMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcIncMode)708 __STATIC_INLINE void LL_BDMA_SetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
709 {
710 uint32_t bdma_base_addr = (uint32_t)BDMAx;
711
712 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PINC,
713 PeriphOrM2MSrcIncMode);
714 }
715
716 /**
717 * @brief Get Peripheral increment mode.
718 * @rmtoll CCR PINC LL_BDMA_GetPeriphIncMode
719 * @param BDMAx BDMA Instance
720 * @param Channel This parameter can be one of the following values:
721 * @arg @ref LL_BDMA_CHANNEL_0
722 * @arg @ref LL_BDMA_CHANNEL_1
723 * @arg @ref LL_BDMA_CHANNEL_2
724 * @arg @ref LL_BDMA_CHANNEL_3
725 * @arg @ref LL_BDMA_CHANNEL_4
726 * @arg @ref LL_BDMA_CHANNEL_5
727 * @arg @ref LL_BDMA_CHANNEL_6
728 * @arg @ref LL_BDMA_CHANNEL_7
729 * @retval Returned value can be one of the following values:
730 * @arg @ref LL_BDMA_PERIPH_INCREMENT
731 * @arg @ref LL_BDMA_PERIPH_NOINCREMENT
732 */
LL_BDMA_GetPeriphIncMode(BDMA_TypeDef * BDMAx,uint32_t Channel)733 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
734 {
735 uint32_t bdma_base_addr = (uint32_t)BDMAx;
736
737 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
738 BDMA_CCR_PINC));
739 }
740
741 /**
742 * @brief Set Memory increment mode.
743 * @rmtoll CCR MINC LL_BDMA_SetMemoryIncMode
744 * @param BDMAx BDMA Instance
745 * @param Channel This parameter can be one of the following values:
746 * @arg @ref LL_BDMA_CHANNEL_0
747 * @arg @ref LL_BDMA_CHANNEL_1
748 * @arg @ref LL_BDMA_CHANNEL_2
749 * @arg @ref LL_BDMA_CHANNEL_3
750 * @arg @ref LL_BDMA_CHANNEL_4
751 * @arg @ref LL_BDMA_CHANNEL_5
752 * @arg @ref LL_BDMA_CHANNEL_6
753 * @arg @ref LL_BDMA_CHANNEL_7
754 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
755 * @arg @ref LL_BDMA_MEMORY_INCREMENT
756 * @arg @ref LL_BDMA_MEMORY_NOINCREMENT
757 * @retval None
758 */
LL_BDMA_SetMemoryIncMode(BDMA_TypeDef * BDMAx,uint32_t Channel,uint32_t MemoryOrM2MDstIncMode)759 __STATIC_INLINE void LL_BDMA_SetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
760 {
761 uint32_t bdma_base_addr = (uint32_t)BDMAx;
762
763 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MINC,
764 MemoryOrM2MDstIncMode);
765 }
766
767 /**
768 * @brief Get Memory increment mode.
769 * @rmtoll CCR MINC LL_BDMA_GetMemoryIncMode
770 * @param BDMAx BDMA Instance
771 * @param Channel This parameter can be one of the following values:
772 * @arg @ref LL_BDMA_CHANNEL_0
773 * @arg @ref LL_BDMA_CHANNEL_1
774 * @arg @ref LL_BDMA_CHANNEL_2
775 * @arg @ref LL_BDMA_CHANNEL_3
776 * @arg @ref LL_BDMA_CHANNEL_4
777 * @arg @ref LL_BDMA_CHANNEL_5
778 * @arg @ref LL_BDMA_CHANNEL_6
779 * @arg @ref LL_BDMA_CHANNEL_7
780 * @retval Returned value can be one of the following values:
781 * @arg @ref LL_BDMA_MEMORY_INCREMENT
782 * @arg @ref LL_BDMA_MEMORY_NOINCREMENT
783 */
LL_BDMA_GetMemoryIncMode(BDMA_TypeDef * BDMAx,uint32_t Channel)784 __STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
785 {
786 uint32_t bdma_base_addr = (uint32_t)BDMAx;
787
788 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
789 BDMA_CCR_MINC));
790 }
791
792 /**
793 * @brief Set Peripheral size.
794 * @rmtoll CCR PSIZE LL_BDMA_SetPeriphSize
795 * @param BDMAx BDMA Instance
796 * @param Channel This parameter can be one of the following values:
797 * @arg @ref LL_BDMA_CHANNEL_0
798 * @arg @ref LL_BDMA_CHANNEL_1
799 * @arg @ref LL_BDMA_CHANNEL_2
800 * @arg @ref LL_BDMA_CHANNEL_3
801 * @arg @ref LL_BDMA_CHANNEL_4
802 * @arg @ref LL_BDMA_CHANNEL_5
803 * @arg @ref LL_BDMA_CHANNEL_6
804 * @arg @ref LL_BDMA_CHANNEL_7
805 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
806 * @arg @ref LL_BDMA_PDATAALIGN_BYTE
807 * @arg @ref LL_BDMA_PDATAALIGN_HALFWORD
808 * @arg @ref LL_BDMA_PDATAALIGN_WORD
809 * @retval None
810 */
LL_BDMA_SetPeriphSize(BDMA_TypeDef * BDMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcDataSize)811 __STATIC_INLINE void LL_BDMA_SetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
812 {
813 uint32_t bdma_base_addr = (uint32_t)BDMAx;
814
815 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PSIZE,
816 PeriphOrM2MSrcDataSize);
817 }
818
819 /**
820 * @brief Get Peripheral size.
821 * @rmtoll CCR PSIZE LL_BDMA_GetPeriphSize
822 * @param BDMAx BDMA Instance
823 * @param Channel This parameter can be one of the following values:
824 * @arg @ref LL_BDMA_CHANNEL_0
825 * @arg @ref LL_BDMA_CHANNEL_1
826 * @arg @ref LL_BDMA_CHANNEL_2
827 * @arg @ref LL_BDMA_CHANNEL_3
828 * @arg @ref LL_BDMA_CHANNEL_4
829 * @arg @ref LL_BDMA_CHANNEL_5
830 * @arg @ref LL_BDMA_CHANNEL_6
831 * @arg @ref LL_BDMA_CHANNEL_7
832 * @retval Returned value can be one of the following values:
833 * @arg @ref LL_BDMA_PDATAALIGN_BYTE
834 * @arg @ref LL_BDMA_PDATAALIGN_HALFWORD
835 * @arg @ref LL_BDMA_PDATAALIGN_WORD
836 */
LL_BDMA_GetPeriphSize(BDMA_TypeDef * BDMAx,uint32_t Channel)837 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel)
838 {
839 uint32_t bdma_base_addr = (uint32_t)BDMAx;
840
841 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
842 BDMA_CCR_PSIZE));
843 }
844
845 /**
846 * @brief Set Memory size.
847 * @rmtoll CCR MSIZE LL_BDMA_SetMemorySize
848 * @param BDMAx BDMA Instance
849 * @param Channel This parameter can be one of the following values:
850 * @arg @ref LL_BDMA_CHANNEL_0
851 * @arg @ref LL_BDMA_CHANNEL_1
852 * @arg @ref LL_BDMA_CHANNEL_2
853 * @arg @ref LL_BDMA_CHANNEL_3
854 * @arg @ref LL_BDMA_CHANNEL_4
855 * @arg @ref LL_BDMA_CHANNEL_5
856 * @arg @ref LL_BDMA_CHANNEL_6
857 * @arg @ref LL_BDMA_CHANNEL_7
858 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
859 * @arg @ref LL_BDMA_MDATAALIGN_BYTE
860 * @arg @ref LL_BDMA_MDATAALIGN_HALFWORD
861 * @arg @ref LL_BDMA_MDATAALIGN_WORD
862 * @retval None
863 */
LL_BDMA_SetMemorySize(BDMA_TypeDef * BDMAx,uint32_t Channel,uint32_t MemoryOrM2MDstDataSize)864 __STATIC_INLINE void LL_BDMA_SetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
865 {
866 uint32_t bdma_base_addr = (uint32_t)BDMAx;
867
868 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MSIZE,
869 MemoryOrM2MDstDataSize);
870 }
871
872 /**
873 * @brief Get Memory size.
874 * @rmtoll CCR MSIZE LL_BDMA_GetMemorySize
875 * @param BDMAx BDMA Instance
876 * @param Channel This parameter can be one of the following values:
877 * @arg @ref LL_BDMA_CHANNEL_0
878 * @arg @ref LL_BDMA_CHANNEL_1
879 * @arg @ref LL_BDMA_CHANNEL_2
880 * @arg @ref LL_BDMA_CHANNEL_3
881 * @arg @ref LL_BDMA_CHANNEL_4
882 * @arg @ref LL_BDMA_CHANNEL_5
883 * @arg @ref LL_BDMA_CHANNEL_6
884 * @arg @ref LL_BDMA_CHANNEL_7
885 * @retval Returned value can be one of the following values:
886 * @arg @ref LL_BDMA_MDATAALIGN_BYTE
887 * @arg @ref LL_BDMA_MDATAALIGN_HALFWORD
888 * @arg @ref LL_BDMA_MDATAALIGN_WORD
889 */
LL_BDMA_GetMemorySize(BDMA_TypeDef * BDMAx,uint32_t Channel)890 __STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel)
891 {
892 uint32_t bdma_base_addr = (uint32_t)BDMAx;
893
894 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
895 BDMA_CCR_MSIZE));
896 }
897
898 /**
899 * @brief Set Channel priority level.
900 * @rmtoll CCR PL LL_BDMA_SetChannelPriorityLevel
901 * @param BDMAx BDMA Instance
902 * @param Channel This parameter can be one of the following values:
903 * @arg @ref LL_BDMA_CHANNEL_0
904 * @arg @ref LL_BDMA_CHANNEL_1
905 * @arg @ref LL_BDMA_CHANNEL_2
906 * @arg @ref LL_BDMA_CHANNEL_3
907 * @arg @ref LL_BDMA_CHANNEL_4
908 * @arg @ref LL_BDMA_CHANNEL_5
909 * @arg @ref LL_BDMA_CHANNEL_6
910 * @arg @ref LL_BDMA_CHANNEL_7
911 * @param Priority This parameter can be one of the following values:
912 * @arg @ref LL_BDMA_PRIORITY_LOW
913 * @arg @ref LL_BDMA_PRIORITY_MEDIUM
914 * @arg @ref LL_BDMA_PRIORITY_HIGH
915 * @arg @ref LL_BDMA_PRIORITY_VERYHIGH
916 * @retval None
917 */
LL_BDMA_SetChannelPriorityLevel(BDMA_TypeDef * BDMAx,uint32_t Channel,uint32_t Priority)918 __STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority)
919 {
920 uint32_t bdma_base_addr = (uint32_t)BDMAx;
921
922 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PL,
923 Priority);
924 }
925
926 /**
927 * @brief Get Channel priority level.
928 * @rmtoll CCR PL LL_BDMA_GetChannelPriorityLevel
929 * @param BDMAx BDMA Instance
930 * @param Channel This parameter can be one of the following values:
931 * @arg @ref LL_BDMA_CHANNEL_0
932 * @arg @ref LL_BDMA_CHANNEL_1
933 * @arg @ref LL_BDMA_CHANNEL_2
934 * @arg @ref LL_BDMA_CHANNEL_3
935 * @arg @ref LL_BDMA_CHANNEL_4
936 * @arg @ref LL_BDMA_CHANNEL_5
937 * @arg @ref LL_BDMA_CHANNEL_6
938 * @arg @ref LL_BDMA_CHANNEL_7
939 * @retval Returned value can be one of the following values:
940 * @arg @ref LL_BDMA_PRIORITY_LOW
941 * @arg @ref LL_BDMA_PRIORITY_MEDIUM
942 * @arg @ref LL_BDMA_PRIORITY_HIGH
943 * @arg @ref LL_BDMA_PRIORITY_VERYHIGH
944 */
LL_BDMA_GetChannelPriorityLevel(BDMA_TypeDef * BDMAx,uint32_t Channel)945 __STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel)
946 {
947 uint32_t bdma_base_addr = (uint32_t)BDMAx;
948
949 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
950 BDMA_CCR_PL));
951 }
952
953 /**
954 * @brief Set Number of data to transfer.
955 * @note This action has no effect if
956 * channel is enabled.
957 * @rmtoll CNDTR NDT LL_BDMA_SetDataLength
958 * @param BDMAx BDMA Instance
959 * @param Channel This parameter can be one of the following values:
960 * @arg @ref LL_BDMA_CHANNEL_0
961 * @arg @ref LL_BDMA_CHANNEL_1
962 * @arg @ref LL_BDMA_CHANNEL_2
963 * @arg @ref LL_BDMA_CHANNEL_3
964 * @arg @ref LL_BDMA_CHANNEL_4
965 * @arg @ref LL_BDMA_CHANNEL_5
966 * @arg @ref LL_BDMA_CHANNEL_6
967 * @arg @ref LL_BDMA_CHANNEL_7
968 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
969 * @retval None
970 */
LL_BDMA_SetDataLength(BDMA_TypeDef * BDMAx,uint32_t Channel,uint32_t NbData)971 __STATIC_INLINE void LL_BDMA_SetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData)
972 {
973 uint32_t bdma_base_addr = (uint32_t)BDMAx;
974
975 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR,
976 BDMA_CNDTR_NDT, NbData);
977 }
978
979 /**
980 * @brief Get Number of data to transfer.
981 * @note Once the channel is enabled, the return value indicate the
982 * remaining bytes to be transmitted.
983 * @rmtoll CNDTR NDT LL_BDMA_GetDataLength
984 * @param BDMAx BDMA Instance
985 * @param Channel This parameter can be one of the following values:
986 * @arg @ref LL_BDMA_CHANNEL_0
987 * @arg @ref LL_BDMA_CHANNEL_1
988 * @arg @ref LL_BDMA_CHANNEL_2
989 * @arg @ref LL_BDMA_CHANNEL_3
990 * @arg @ref LL_BDMA_CHANNEL_4
991 * @arg @ref LL_BDMA_CHANNEL_5
992 * @arg @ref LL_BDMA_CHANNEL_6
993 * @arg @ref LL_BDMA_CHANNEL_7
994 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
995 */
LL_BDMA_GetDataLength(BDMA_TypeDef * BDMAx,uint32_t Channel)996 __STATIC_INLINE uint32_t LL_BDMA_GetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel)
997 {
998 uint32_t bdma_base_addr = (uint32_t)BDMAx;
999
1000 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR,
1001 BDMA_CNDTR_NDT));
1002 }
1003
1004 /**
1005 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1006 * @rmtoll CR CT LL_BDMA_SetCurrentTargetMem
1007 * @param BDMAx BDMAx Instance
1008 * @param Channel This parameter can be one of the following values:
1009 * @arg @ref LL_BDMA_CHANNEL_0
1010 * @arg @ref LL_BDMA_CHANNEL_1
1011 * @arg @ref LL_BDMA_CHANNEL_2
1012 * @arg @ref LL_BDMA_CHANNEL_3
1013 * @arg @ref LL_BDMA_CHANNEL_4
1014 * @arg @ref LL_BDMA_CHANNEL_5
1015 * @arg @ref LL_BDMA_CHANNEL_6
1016 * @arg @ref LL_BDMA_CHANNEL_7
1017 * @param CurrentMemory This parameter can be one of the following values:
1018 * @arg @ref LL_BDMA_CURRENTTARGETMEM0
1019 * @arg @ref LL_BDMA_CURRENTTARGETMEM1
1020 * @retval None
1021 */
LL_BDMA_SetCurrentTargetMem(BDMA_TypeDef * BDMAx,uint32_t Channel,uint32_t CurrentMemory)1022 __STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory)
1023 {
1024 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1025
1026 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT, CurrentMemory);
1027 }
1028
1029 /**
1030 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1031 * @rmtoll CR CT LL_BDMA_GetCurrentTargetMem
1032 * @param BDMAx BDMAx Instance
1033 * @param Channel This parameter can be one of the following values:
1034 * @arg @ref LL_BDMA_CHANNEL_0
1035 * @arg @ref LL_BDMA_CHANNEL_1
1036 * @arg @ref LL_BDMA_CHANNEL_2
1037 * @arg @ref LL_BDMA_CHANNEL_3
1038 * @arg @ref LL_BDMA_CHANNEL_4
1039 * @arg @ref LL_BDMA_CHANNEL_5
1040 * @arg @ref LL_BDMA_CHANNEL_6
1041 * @arg @ref LL_BDMA_CHANNEL_7
1042 * @retval Returned value can be one of the following values:
1043 * @arg @ref LL_BDMA_CURRENTTARGETMEM0
1044 * @arg @ref LL_BDMA_CURRENTTARGETMEM1
1045 */
LL_BDMA_GetCurrentTargetMem(BDMA_TypeDef * BDMAx,uint32_t Channel)1046 __STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel)
1047 {
1048 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1049
1050 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT));
1051 }
1052
1053 /**
1054 * @brief Enable the double buffer mode.
1055 * @rmtoll CR DBM LL_BDMA_EnableDoubleBufferMode
1056 * @param BDMAx BDMAx Instance
1057 * @param Channel This parameter can be one of the following values:
1058 * @arg @ref LL_BDMA_CHANNEL_0
1059 * @arg @ref LL_BDMA_CHANNEL_1
1060 * @arg @ref LL_BDMA_CHANNEL_2
1061 * @arg @ref LL_BDMA_CHANNEL_3
1062 * @arg @ref LL_BDMA_CHANNEL_4
1063 * @arg @ref LL_BDMA_CHANNEL_5
1064 * @arg @ref LL_BDMA_CHANNEL_6
1065 * @arg @ref LL_BDMA_CHANNEL_7
1066 * @retval None
1067 */
LL_BDMA_EnableDoubleBufferMode(BDMA_TypeDef * BDMAx,uint32_t Channel)1068 __STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
1069 {
1070 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1071
1072 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM);
1073 }
1074
1075 /**
1076 * @brief Disable the double buffer mode.
1077 * @rmtoll CR DBM LL_BDMA_DisableDoubleBufferMode
1078 * @param BDMAx BDMAx Instance
1079 * @param Channel This parameter can be one of the following values:
1080 * @arg @ref LL_BDMA_CHANNEL_0
1081 * @arg @ref LL_BDMA_CHANNEL_1
1082 * @arg @ref LL_BDMA_CHANNEL_2
1083 * @arg @ref LL_BDMA_CHANNEL_3
1084 * @arg @ref LL_BDMA_CHANNEL_4
1085 * @arg @ref LL_BDMA_CHANNEL_5
1086 * @arg @ref LL_BDMA_CHANNEL_6
1087 * @arg @ref LL_BDMA_CHANNEL_7
1088 * @retval None
1089 */
LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef * BDMAx,uint32_t Channel)1090 __STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
1091 {
1092 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1093
1094 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM);
1095 }
1096
1097 /**
1098 * @brief Configure the Source and Destination addresses.
1099 * @note This API must not be called when the BDMA channel is enabled.
1100 * @note Each IP using BDMA provides an API to get directly the register address (LL_PPP_BDMA_GetRegAddr).
1101 * @rmtoll CPAR PA LL_BDMA_ConfigAddresses\n
1102 * CMAR MA LL_BDMA_ConfigAddresses
1103 * @param BDMAx BDMA Instance
1104 * @param Channel This parameter can be one of the following values:
1105 * @arg @ref LL_BDMA_CHANNEL_0
1106 * @arg @ref LL_BDMA_CHANNEL_1
1107 * @arg @ref LL_BDMA_CHANNEL_2
1108 * @arg @ref LL_BDMA_CHANNEL_3
1109 * @arg @ref LL_BDMA_CHANNEL_4
1110 * @arg @ref LL_BDMA_CHANNEL_5
1111 * @arg @ref LL_BDMA_CHANNEL_6
1112 * @arg @ref LL_BDMA_CHANNEL_7
1113 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1114 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1115 * @param Direction This parameter can be one of the following values:
1116 * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY
1117 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH
1118 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY
1119 * @retval None
1120 */
LL_BDMA_ConfigAddresses(BDMA_TypeDef * BDMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)1121 __STATIC_INLINE void LL_BDMA_ConfigAddresses(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress,
1122 uint32_t DstAddress, uint32_t Direction)
1123 {
1124 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1125
1126 /* Direction Memory to Periph */
1127 if (Direction == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH)
1128 {
1129 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, SrcAddress);
1130 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, DstAddress);
1131 }
1132 /* Direction Periph to Memory and Memory to Memory */
1133 else
1134 {
1135 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, SrcAddress);
1136 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, DstAddress);
1137 }
1138 }
1139
1140 /**
1141 * @brief Set the Memory address.
1142 * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.
1143 * @note This API must not be called when the BDMA channel is enabled.
1144 * @rmtoll CMAR MA LL_BDMA_SetMemoryAddress
1145 * @param BDMAx BDMA Instance
1146 * @param Channel This parameter can be one of the following values:
1147 * @arg @ref LL_BDMA_CHANNEL_0
1148 * @arg @ref LL_BDMA_CHANNEL_1
1149 * @arg @ref LL_BDMA_CHANNEL_2
1150 * @arg @ref LL_BDMA_CHANNEL_3
1151 * @arg @ref LL_BDMA_CHANNEL_4
1152 * @arg @ref LL_BDMA_CHANNEL_5
1153 * @arg @ref LL_BDMA_CHANNEL_6
1154 * @arg @ref LL_BDMA_CHANNEL_7
1155 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1156 * @retval None
1157 */
LL_BDMA_SetMemoryAddress(BDMA_TypeDef * BDMAx,uint32_t Channel,uint32_t MemoryAddress)1158 __STATIC_INLINE void LL_BDMA_SetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
1159 {
1160 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1161
1162 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress);
1163 }
1164
1165 /**
1166 * @brief Set the Peripheral address.
1167 * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.
1168 * @note This API must not be called when the BDMA channel is enabled.
1169 * @rmtoll CPAR PA LL_BDMA_SetPeriphAddress
1170 * @param BDMAx BDMA Instance
1171 * @param Channel This parameter can be one of the following values:
1172 * @arg @ref LL_BDMA_CHANNEL_0
1173 * @arg @ref LL_BDMA_CHANNEL_1
1174 * @arg @ref LL_BDMA_CHANNEL_2
1175 * @arg @ref LL_BDMA_CHANNEL_3
1176 * @arg @ref LL_BDMA_CHANNEL_4
1177 * @arg @ref LL_BDMA_CHANNEL_5
1178 * @arg @ref LL_BDMA_CHANNEL_6
1179 * @arg @ref LL_BDMA_CHANNEL_7
1180 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1181 * @retval None
1182 */
LL_BDMA_SetPeriphAddress(BDMA_TypeDef * BDMAx,uint32_t Channel,uint32_t PeriphAddress)1183 __STATIC_INLINE void LL_BDMA_SetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress)
1184 {
1185 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1186
1187 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, PeriphAddress);
1188 }
1189
1190 /**
1191 * @brief Get Memory address.
1192 * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.
1193 * @rmtoll CMAR MA LL_BDMA_GetMemoryAddress
1194 * @param BDMAx BDMA Instance
1195 * @param Channel This parameter can be one of the following values:
1196 * @arg @ref LL_BDMA_CHANNEL_0
1197 * @arg @ref LL_BDMA_CHANNEL_1
1198 * @arg @ref LL_BDMA_CHANNEL_2
1199 * @arg @ref LL_BDMA_CHANNEL_3
1200 * @arg @ref LL_BDMA_CHANNEL_4
1201 * @arg @ref LL_BDMA_CHANNEL_5
1202 * @arg @ref LL_BDMA_CHANNEL_6
1203 * @arg @ref LL_BDMA_CHANNEL_7
1204 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1205 */
LL_BDMA_GetMemoryAddress(BDMA_TypeDef * BDMAx,uint32_t Channel)1206 __STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
1207 {
1208 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1209
1210 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR));
1211 }
1212
1213 /**
1214 * @brief Get Peripheral address.
1215 * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.
1216 * @rmtoll CPAR PA LL_BDMA_GetPeriphAddress
1217 * @param BDMAx BDMA Instance
1218 * @param Channel This parameter can be one of the following values:
1219 * @arg @ref LL_BDMA_CHANNEL_0
1220 * @arg @ref LL_BDMA_CHANNEL_1
1221 * @arg @ref LL_BDMA_CHANNEL_2
1222 * @arg @ref LL_BDMA_CHANNEL_3
1223 * @arg @ref LL_BDMA_CHANNEL_4
1224 * @arg @ref LL_BDMA_CHANNEL_5
1225 * @arg @ref LL_BDMA_CHANNEL_6
1226 * @arg @ref LL_BDMA_CHANNEL_7
1227 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1228 */
LL_BDMA_GetPeriphAddress(BDMA_TypeDef * BDMAx,uint32_t Channel)1229 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
1230 {
1231 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1232
1233 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR));
1234 }
1235
1236 /**
1237 * @brief Set the Memory to Memory Source address.
1238 * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.
1239 * @note This API must not be called when the BDMA channel is enabled.
1240 * @rmtoll CPAR PA LL_BDMA_SetM2MSrcAddress
1241 * @param BDMAx BDMA Instance
1242 * @param Channel This parameter can be one of the following values:
1243 * @arg @ref LL_BDMA_CHANNEL_0
1244 * @arg @ref LL_BDMA_CHANNEL_1
1245 * @arg @ref LL_BDMA_CHANNEL_2
1246 * @arg @ref LL_BDMA_CHANNEL_3
1247 * @arg @ref LL_BDMA_CHANNEL_4
1248 * @arg @ref LL_BDMA_CHANNEL_5
1249 * @arg @ref LL_BDMA_CHANNEL_6
1250 * @arg @ref LL_BDMA_CHANNEL_7
1251 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1252 * @retval None
1253 */
LL_BDMA_SetM2MSrcAddress(BDMA_TypeDef * BDMAx,uint32_t Channel,uint32_t MemoryAddress)1254 __STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
1255 {
1256 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1257
1258 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, MemoryAddress);
1259 }
1260
1261 /**
1262 * @brief Set the Memory to Memory Destination address.
1263 * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.
1264 * @note This API must not be called when the BDMA channel is enabled.
1265 * @rmtoll CMAR MA LL_BDMA_SetM2MDstAddress
1266 * @param BDMAx BDMA Instance
1267 * @param Channel This parameter can be one of the following values:
1268 * @arg @ref LL_BDMA_CHANNEL_0
1269 * @arg @ref LL_BDMA_CHANNEL_1
1270 * @arg @ref LL_BDMA_CHANNEL_2
1271 * @arg @ref LL_BDMA_CHANNEL_3
1272 * @arg @ref LL_BDMA_CHANNEL_4
1273 * @arg @ref LL_BDMA_CHANNEL_5
1274 * @arg @ref LL_BDMA_CHANNEL_6
1275 * @arg @ref LL_BDMA_CHANNEL_7
1276 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1277 * @retval None
1278 */
LL_BDMA_SetM2MDstAddress(BDMA_TypeDef * BDMAx,uint32_t Channel,uint32_t MemoryAddress)1279 __STATIC_INLINE void LL_BDMA_SetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
1280 {
1281 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1282
1283 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress);
1284 }
1285
1286 /**
1287 * @brief Get the Memory to Memory Source address.
1288 * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.
1289 * @rmtoll CPAR PA LL_BDMA_GetM2MSrcAddress
1290 * @param BDMAx BDMA Instance
1291 * @param Channel This parameter can be one of the following values:
1292 * @arg @ref LL_BDMA_CHANNEL_0
1293 * @arg @ref LL_BDMA_CHANNEL_1
1294 * @arg @ref LL_BDMA_CHANNEL_2
1295 * @arg @ref LL_BDMA_CHANNEL_3
1296 * @arg @ref LL_BDMA_CHANNEL_4
1297 * @arg @ref LL_BDMA_CHANNEL_5
1298 * @arg @ref LL_BDMA_CHANNEL_6
1299 * @arg @ref LL_BDMA_CHANNEL_7
1300 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1301 */
LL_BDMA_GetM2MSrcAddress(BDMA_TypeDef * BDMAx,uint32_t Channel)1302 __STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
1303 {
1304 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1305
1306 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR));
1307 }
1308
1309 /**
1310 * @brief Get the Memory to Memory Destination address.
1311 * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.
1312 * @rmtoll CMAR MA LL_BDMA_GetM2MDstAddress
1313 * @param BDMAx BDMA Instance
1314 * @param Channel This parameter can be one of the following values:
1315 * @arg @ref LL_BDMA_CHANNEL_0
1316 * @arg @ref LL_BDMA_CHANNEL_1
1317 * @arg @ref LL_BDMA_CHANNEL_2
1318 * @arg @ref LL_BDMA_CHANNEL_3
1319 * @arg @ref LL_BDMA_CHANNEL_4
1320 * @arg @ref LL_BDMA_CHANNEL_5
1321 * @arg @ref LL_BDMA_CHANNEL_6
1322 * @arg @ref LL_BDMA_CHANNEL_7
1323 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1324 */
LL_BDMA_GetM2MDstAddress(BDMA_TypeDef * BDMAx,uint32_t Channel)1325 __STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
1326 {
1327 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1328
1329 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR));
1330 }
1331
1332 /**
1333 * @brief Set Memory 1 address (used in case of Double buffer mode).
1334 * @rmtoll M1AR M1A LL_BDMA_SetMemory1Address
1335 * @param BDMAx BDMAx Instance
1336 * @param Channel This parameter can be one of the following values:
1337 * @arg @ref LL_BDMA_CHANNEL_0
1338 * @arg @ref LL_BDMA_CHANNEL_1
1339 * @arg @ref LL_BDMA_CHANNEL_2
1340 * @arg @ref LL_BDMA_CHANNEL_3
1341 * @arg @ref LL_BDMA_CHANNEL_4
1342 * @arg @ref LL_BDMA_CHANNEL_5
1343 * @arg @ref LL_BDMA_CHANNEL_6
1344 * @arg @ref LL_BDMA_CHANNEL_7
1345 * @param Address Between 0 to 0xFFFFFFFF
1346 * @retval None
1347 */
LL_BDMA_SetMemory1Address(BDMA_TypeDef * BDMAx,uint32_t Channel,uint32_t Address)1348 __STATIC_INLINE void LL_BDMA_SetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address)
1349 {
1350 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1351
1352 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR, BDMA_CM1AR_MA, Address);
1353 }
1354
1355 /**
1356 * @brief Get Memory 1 address (used in case of Double buffer mode).
1357 * @rmtoll M1AR M1A LL_BDMA_GetMemory1Address
1358 * @param BDMAx BDMAx Instance
1359 * @param Channel This parameter can be one of the following values:
1360 * @arg @ref LL_BDMA_CHANNEL_0
1361 * @arg @ref LL_BDMA_CHANNEL_1
1362 * @arg @ref LL_BDMA_CHANNEL_2
1363 * @arg @ref LL_BDMA_CHANNEL_3
1364 * @arg @ref LL_BDMA_CHANNEL_4
1365 * @arg @ref LL_BDMA_CHANNEL_5
1366 * @arg @ref LL_BDMA_CHANNEL_6
1367 * @arg @ref LL_BDMA_CHANNEL_7
1368 * @retval Between 0 to 0xFFFFFFFF
1369 */
LL_BDMA_GetMemory1Address(BDMA_TypeDef * BDMAx,uint32_t Channel)1370 __STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel)
1371 {
1372 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1373
1374 return (((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR);
1375 }
1376
1377 /**
1378 * @brief Set BDMA request for BDMA Channels on DMAMUX Channel x.
1379 * @note DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7.
1380 * @rmtoll CxCR DMAREQ_ID LL_BDMA_SetPeriphRequest
1381 * @param BDMAx BDMAx Instance
1382 * @param Channel This parameter can be one of the following values:
1383 * @arg @ref LL_BDMA_CHANNEL_0
1384 * @arg @ref LL_BDMA_CHANNEL_1
1385 * @arg @ref LL_BDMA_CHANNEL_2
1386 * @arg @ref LL_BDMA_CHANNEL_3
1387 * @arg @ref LL_BDMA_CHANNEL_4
1388 * @arg @ref LL_BDMA_CHANNEL_5
1389 * @arg @ref LL_BDMA_CHANNEL_6
1390 * @arg @ref LL_BDMA_CHANNEL_7
1391 * @param Request This parameter can be one of the following values:
1392 * @arg @ref LL_DMAMUX2_REQ_MEM2MEM
1393 * @arg @ref LL_DMAMUX2_REQ_GENERATOR0
1394 * @arg @ref LL_DMAMUX2_REQ_GENERATOR1
1395 * @arg @ref LL_DMAMUX2_REQ_GENERATOR2
1396 * @arg @ref LL_DMAMUX2_REQ_GENERATOR3
1397 * @arg @ref LL_DMAMUX2_REQ_GENERATOR4
1398 * @arg @ref LL_DMAMUX2_REQ_GENERATOR5
1399 * @arg @ref LL_DMAMUX2_REQ_GENERATOR6
1400 * @arg @ref LL_DMAMUX2_REQ_GENERATOR7
1401 * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
1402 * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
1403 * @arg @ref LL_DMAMUX2_REQ_SPI6_RX
1404 * @arg @ref LL_DMAMUX2_REQ_SPI6_TX
1405 * @arg @ref LL_DMAMUX2_REQ_I2C4_RX
1406 * @arg @ref LL_DMAMUX2_REQ_I2C4_TX
1407 * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
1408 * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
1409 * @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
1410 * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
1411 * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
1412 *
1413 * @note (*) Availability depends on devices.
1414 * @retval None
1415 */
LL_BDMA_SetPeriphRequest(BDMA_TypeDef * BDMAx,uint32_t Channel,uint32_t Request)1416 __STATIC_INLINE void LL_BDMA_SetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Request)
1417 {
1418 UNUSED(BDMAx);
1419 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
1420 }
1421
1422 /**
1423 * @brief Get BDMA request for BDMA Channels on DMAMUX Channel x.
1424 * @note DMAMUX channel 0 to 7 are mapped to BDMA channel 0 to 7.
1425 * @rmtoll CxCR DMAREQ_ID LL_BDMA_GetPeriphRequest
1426 * @param BDMAx BDMAx Instance
1427 * @param Channel This parameter can be one of the following values:
1428 * @arg @ref LL_BDMA_CHANNEL_0
1429 * @arg @ref LL_BDMA_CHANNEL_1
1430 * @arg @ref LL_BDMA_CHANNEL_2
1431 * @arg @ref LL_BDMA_CHANNEL_3
1432 * @arg @ref LL_BDMA_CHANNEL_4
1433 * @arg @ref LL_BDMA_CHANNEL_5
1434 * @arg @ref LL_BDMA_CHANNEL_6
1435 * @arg @ref LL_BDMA_CHANNEL_7
1436 * @retval Returned value can be one of the following values:
1437 * @arg @ref LL_DMAMUX2_REQ_MEM2MEM
1438 * @arg @ref LL_DMAMUX2_REQ_GENERATOR0
1439 * @arg @ref LL_DMAMUX2_REQ_GENERATOR1
1440 * @arg @ref LL_DMAMUX2_REQ_GENERATOR2
1441 * @arg @ref LL_DMAMUX2_REQ_GENERATOR3
1442 * @arg @ref LL_DMAMUX2_REQ_GENERATOR4
1443 * @arg @ref LL_DMAMUX2_REQ_GENERATOR5
1444 * @arg @ref LL_DMAMUX2_REQ_GENERATOR6
1445 * @arg @ref LL_DMAMUX2_REQ_GENERATOR7
1446 * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
1447 * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
1448 * @arg @ref LL_DMAMUX2_REQ_SPI6_RX
1449 * @arg @ref LL_DMAMUX2_REQ_SPI6_TX
1450 * @arg @ref LL_DMAMUX2_REQ_I2C4_RX
1451 * @arg @ref LL_DMAMUX2_REQ_I2C4_TX
1452 * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
1453 * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
1454 * @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
1455 * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
1456 * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
1457 *
1458 * @note (*) Availability depends on devices.
1459 */
LL_BDMA_GetPeriphRequest(BDMA_TypeDef * BDMAx,uint32_t Channel)1460 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel)
1461 {
1462 UNUSED(BDMAx);
1463 return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
1464 }
1465
1466 /**
1467 * @}
1468 */
1469
1470
1471 /** @defgroup BDMA_LL_EF_FLAG_Management FLAG_Management
1472 * @{
1473 */
1474 /**
1475 * @brief Get Channel 0 global interrupt flag.
1476 * @rmtoll ISR GIF0 LL_BDMA_IsActiveFlag_GI0
1477 * @param BDMAx BDMA Instance
1478 * @retval State of bit (1 or 0).
1479 */
LL_BDMA_IsActiveFlag_GI0(BDMA_TypeDef * BDMAx)1480 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(BDMA_TypeDef *BDMAx)
1481 {
1482 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF0) == (BDMA_ISR_GIF0)) ? 1UL : 0UL);
1483 }
1484
1485 /**
1486 * @brief Get Channel 1 global interrupt flag.
1487 * @rmtoll ISR GIF1 LL_BDMA_IsActiveFlag_GI1
1488 * @param BDMAx BDMA Instance
1489 * @retval State of bit (1 or 0).
1490 */
LL_BDMA_IsActiveFlag_GI1(BDMA_TypeDef * BDMAx)1491 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(BDMA_TypeDef *BDMAx)
1492 {
1493 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF1) == (BDMA_ISR_GIF1)) ? 1UL : 0UL);
1494 }
1495
1496 /**
1497 * @brief Get Channel 2 global interrupt flag.
1498 * @rmtoll ISR GIF2 LL_BDMA_IsActiveFlag_GI2
1499 * @param BDMAx BDMA Instance
1500 * @retval State of bit (1 or 0).
1501 */
LL_BDMA_IsActiveFlag_GI2(BDMA_TypeDef * BDMAx)1502 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(BDMA_TypeDef *BDMAx)
1503 {
1504 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF2) == (BDMA_ISR_GIF2)) ? 1UL : 0UL);
1505 }
1506
1507 /**
1508 * @brief Get Channel 3 global interrupt flag.
1509 * @rmtoll ISR GIF3 LL_BDMA_IsActiveFlag_GI3
1510 * @param BDMAx BDMA Instance
1511 * @retval State of bit (1 or 0).
1512 */
LL_BDMA_IsActiveFlag_GI3(BDMA_TypeDef * BDMAx)1513 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(BDMA_TypeDef *BDMAx)
1514 {
1515 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF3) == (BDMA_ISR_GIF3)) ? 1UL : 0UL);
1516 }
1517
1518 /**
1519 * @brief Get Channel 4 global interrupt flag.
1520 * @rmtoll ISR GIF4 LL_BDMA_IsActiveFlag_GI4
1521 * @param BDMAx BDMA Instance
1522 * @retval State of bit (1 or 0).
1523 */
LL_BDMA_IsActiveFlag_GI4(BDMA_TypeDef * BDMAx)1524 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(BDMA_TypeDef *BDMAx)
1525 {
1526 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF4) == (BDMA_ISR_GIF4)) ? 1UL : 0UL);
1527 }
1528
1529 /**
1530 * @brief Get Channel 5 global interrupt flag.
1531 * @rmtoll ISR GIF5 LL_BDMA_IsActiveFlag_GI5
1532 * @param BDMAx BDMA Instance
1533 * @retval State of bit (1 or 0).
1534 */
LL_BDMA_IsActiveFlag_GI5(BDMA_TypeDef * BDMAx)1535 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(BDMA_TypeDef *BDMAx)
1536 {
1537 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF5) == (BDMA_ISR_GIF5)) ? 1UL : 0UL);
1538 }
1539
1540 /**
1541 * @brief Get Channel 6 global interrupt flag.
1542 * @rmtoll ISR GIF6 LL_BDMA_IsActiveFlag_GI6
1543 * @param BDMAx BDMA Instance
1544 * @retval State of bit (1 or 0).
1545 */
LL_BDMA_IsActiveFlag_GI6(BDMA_TypeDef * BDMAx)1546 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(BDMA_TypeDef *BDMAx)
1547 {
1548 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF6) == (BDMA_ISR_GIF6)) ? 1UL : 0UL);
1549 }
1550
1551 /**
1552 * @brief Get Channel 7 global interrupt flag.
1553 * @rmtoll ISR GIF7 LL_BDMA_IsActiveFlag_GI7
1554 * @param BDMAx BDMA Instance
1555 * @retval State of bit (1 or 0).
1556 */
LL_BDMA_IsActiveFlag_GI7(BDMA_TypeDef * BDMAx)1557 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(BDMA_TypeDef *BDMAx)
1558 {
1559 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF7) == (BDMA_ISR_GIF7)) ? 1UL : 0UL);
1560 }
1561
1562 /**
1563 * @brief Get Channel 0 transfer complete flag.
1564 * @rmtoll ISR TCIF0 LL_BDMA_IsActiveFlag_TC0
1565 * @param BDMAx BDMA Instance
1566 * @retval State of bit (1 or 0).
1567 */
LL_BDMA_IsActiveFlag_TC0(BDMA_TypeDef * BDMAx)1568 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(BDMA_TypeDef *BDMAx)
1569 {
1570 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF0) == (BDMA_ISR_TCIF0)) ? 1UL : 0UL);
1571 }
1572 /**
1573 * @brief Get Channel 1 transfer complete flag.
1574 * @rmtoll ISR TCIF1 LL_BDMA_IsActiveFlag_TC1
1575 * @param BDMAx BDMA Instance
1576 * @retval State of bit (1 or 0).
1577 */
LL_BDMA_IsActiveFlag_TC1(BDMA_TypeDef * BDMAx)1578 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(BDMA_TypeDef *BDMAx)
1579 {
1580 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF1) == (BDMA_ISR_TCIF1)) ? 1UL : 0UL);
1581 }
1582
1583 /**
1584 * @brief Get Channel 2 transfer complete flag.
1585 * @rmtoll ISR TCIF2 LL_BDMA_IsActiveFlag_TC2
1586 * @param BDMAx BDMA Instance
1587 * @retval State of bit (1 or 0).
1588 */
LL_BDMA_IsActiveFlag_TC2(BDMA_TypeDef * BDMAx)1589 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(BDMA_TypeDef *BDMAx)
1590 {
1591 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF2) == (BDMA_ISR_TCIF2)) ? 1UL : 0UL);
1592 }
1593
1594 /**
1595 * @brief Get Channel 3 transfer complete flag.
1596 * @rmtoll ISR TCIF3 LL_BDMA_IsActiveFlag_TC3
1597 * @param BDMAx BDMA Instance
1598 * @retval State of bit (1 or 0).
1599 */
LL_BDMA_IsActiveFlag_TC3(BDMA_TypeDef * BDMAx)1600 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(BDMA_TypeDef *BDMAx)
1601 {
1602 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF3) == (BDMA_ISR_TCIF3)) ? 1UL : 0UL);
1603 }
1604
1605 /**
1606 * @brief Get Channel 4 transfer complete flag.
1607 * @rmtoll ISR TCIF4 LL_BDMA_IsActiveFlag_TC4
1608 * @param BDMAx BDMA Instance
1609 * @retval State of bit (1 or 0).
1610 */
LL_BDMA_IsActiveFlag_TC4(BDMA_TypeDef * BDMAx)1611 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(BDMA_TypeDef *BDMAx)
1612 {
1613 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF4) == (BDMA_ISR_TCIF4)) ? 1UL : 0UL);
1614 }
1615
1616 /**
1617 * @brief Get Channel 5 transfer complete flag.
1618 * @rmtoll ISR TCIF5 LL_BDMA_IsActiveFlag_TC5
1619 * @param BDMAx BDMA Instance
1620 * @retval State of bit (1 or 0).
1621 */
LL_BDMA_IsActiveFlag_TC5(BDMA_TypeDef * BDMAx)1622 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(BDMA_TypeDef *BDMAx)
1623 {
1624 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF5) == (BDMA_ISR_TCIF5)) ? 1UL : 0UL);
1625 }
1626
1627 /**
1628 * @brief Get Channel 6 transfer complete flag.
1629 * @rmtoll ISR TCIF6 LL_BDMA_IsActiveFlag_TC6
1630 * @param BDMAx BDMA Instance
1631 * @retval State of bit (1 or 0).
1632 */
LL_BDMA_IsActiveFlag_TC6(BDMA_TypeDef * BDMAx)1633 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(BDMA_TypeDef *BDMAx)
1634 {
1635 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF6) == (BDMA_ISR_TCIF6)) ? 1UL : 0UL);
1636 }
1637
1638 /**
1639 * @brief Get Channel 7 transfer complete flag.
1640 * @rmtoll ISR TCIF7 LL_BDMA_IsActiveFlag_TC7
1641 * @param BDMAx BDMA Instance
1642 * @retval State of bit (1 or 0).
1643 */
LL_BDMA_IsActiveFlag_TC7(BDMA_TypeDef * BDMAx)1644 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(BDMA_TypeDef *BDMAx)
1645 {
1646 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF7) == (BDMA_ISR_TCIF7)) ? 1UL : 0UL);
1647 }
1648
1649 /**
1650 * @brief Get Channel 0 half transfer flag.
1651 * @rmtoll ISR HTIF0 LL_BDMA_IsActiveFlag_HT0
1652 * @param BDMAx BDMA Instance
1653 * @retval State of bit (1 or 0).
1654 */
LL_BDMA_IsActiveFlag_HT0(BDMA_TypeDef * BDMAx)1655 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(BDMA_TypeDef *BDMAx)
1656 {
1657 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF0) == (BDMA_ISR_HTIF0)) ? 1UL : 0UL);
1658 }
1659
1660 /**
1661 * @brief Get Channel 1 half transfer flag.
1662 * @rmtoll ISR HTIF1 LL_BDMA_IsActiveFlag_HT1
1663 * @param BDMAx BDMA Instance
1664 * @retval State of bit (1 or 0).
1665 */
LL_BDMA_IsActiveFlag_HT1(BDMA_TypeDef * BDMAx)1666 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(BDMA_TypeDef *BDMAx)
1667 {
1668 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF1) == (BDMA_ISR_HTIF1)) ? 1UL : 0UL);
1669 }
1670
1671 /**
1672 * @brief Get Channel 2 half transfer flag.
1673 * @rmtoll ISR HTIF2 LL_BDMA_IsActiveFlag_HT2
1674 * @param BDMAx BDMA Instance
1675 * @retval State of bit (1 or 0).
1676 */
LL_BDMA_IsActiveFlag_HT2(BDMA_TypeDef * BDMAx)1677 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(BDMA_TypeDef *BDMAx)
1678 {
1679 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF2) == (BDMA_ISR_HTIF2)) ? 1UL : 0UL);
1680 }
1681
1682 /**
1683 * @brief Get Channel 3 half transfer flag.
1684 * @rmtoll ISR HTIF3 LL_BDMA_IsActiveFlag_HT3
1685 * @param BDMAx BDMA Instance
1686 * @retval State of bit (1 or 0).
1687 */
LL_BDMA_IsActiveFlag_HT3(BDMA_TypeDef * BDMAx)1688 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(BDMA_TypeDef *BDMAx)
1689 {
1690 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF3) == (BDMA_ISR_HTIF3)) ? 1UL : 0UL);
1691 }
1692
1693 /**
1694 * @brief Get Channel 4 half transfer flag.
1695 * @rmtoll ISR HTIF4 LL_BDMA_IsActiveFlag_HT4
1696 * @param BDMAx BDMA Instance
1697 * @retval State of bit (1 or 0).
1698 */
LL_BDMA_IsActiveFlag_HT4(BDMA_TypeDef * BDMAx)1699 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(BDMA_TypeDef *BDMAx)
1700 {
1701 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF4) == (BDMA_ISR_HTIF4)) ? 1UL : 0UL);
1702 }
1703
1704 /**
1705 * @brief Get Channel 5 half transfer flag.
1706 * @rmtoll ISR HTIF5 LL_BDMA_IsActiveFlag_HT5
1707 * @param BDMAx BDMA Instance
1708 * @retval State of bit (1 or 0).
1709 */
LL_BDMA_IsActiveFlag_HT5(BDMA_TypeDef * BDMAx)1710 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(BDMA_TypeDef *BDMAx)
1711 {
1712 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF5) == (BDMA_ISR_HTIF5)) ? 1UL : 0UL);
1713 }
1714
1715 /**
1716 * @brief Get Channel 6 half transfer flag.
1717 * @rmtoll ISR HTIF6 LL_BDMA_IsActiveFlag_HT6
1718 * @param BDMAx BDMA Instance
1719 * @retval State of bit (1 or 0).
1720 */
LL_BDMA_IsActiveFlag_HT6(BDMA_TypeDef * BDMAx)1721 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(BDMA_TypeDef *BDMAx)
1722 {
1723 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF6) == (BDMA_ISR_HTIF6)) ? 1UL : 0UL);
1724 }
1725
1726 /**
1727 * @brief Get Channel 7 half transfer flag.
1728 * @rmtoll ISR HTIF7 LL_BDMA_IsActiveFlag_HT7
1729 * @param BDMAx BDMA Instance
1730 * @retval State of bit (1 or 0).
1731 */
LL_BDMA_IsActiveFlag_HT7(BDMA_TypeDef * BDMAx)1732 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(BDMA_TypeDef *BDMAx)
1733 {
1734 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF7) == (BDMA_ISR_HTIF7)) ? 1UL : 0UL);
1735 }
1736
1737 /**
1738 * @brief Get Channel 0 transfer error flag.
1739 * @rmtoll ISR TEIF0 LL_BDMA_IsActiveFlag_TE0
1740 * @param BDMAx BDMA Instance
1741 * @retval State of bit (1 or 0).
1742 */
LL_BDMA_IsActiveFlag_TE0(BDMA_TypeDef * BDMAx)1743 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(BDMA_TypeDef *BDMAx)
1744 {
1745 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF0) == (BDMA_ISR_TEIF0)) ? 1UL : 0UL);
1746 }
1747
1748 /**
1749 * @brief Get Channel 1 transfer error flag.
1750 * @rmtoll ISR TEIF1 LL_BDMA_IsActiveFlag_TE1
1751 * @param BDMAx BDMA Instance
1752 * @retval State of bit (1 or 0).
1753 */
LL_BDMA_IsActiveFlag_TE1(BDMA_TypeDef * BDMAx)1754 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(BDMA_TypeDef *BDMAx)
1755 {
1756 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF1) == (BDMA_ISR_TEIF1)) ? 1UL : 0UL);
1757 }
1758
1759 /**
1760 * @brief Get Channel 2 transfer error flag.
1761 * @rmtoll ISR TEIF2 LL_BDMA_IsActiveFlag_TE2
1762 * @param BDMAx BDMA Instance
1763 * @retval State of bit (1 or 0).
1764 */
LL_BDMA_IsActiveFlag_TE2(BDMA_TypeDef * BDMAx)1765 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(BDMA_TypeDef *BDMAx)
1766 {
1767 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF2) == (BDMA_ISR_TEIF2)) ? 1UL : 0UL);
1768 }
1769
1770 /**
1771 * @brief Get Channel 3 transfer error flag.
1772 * @rmtoll ISR TEIF3 LL_BDMA_IsActiveFlag_TE3
1773 * @param BDMAx BDMA Instance
1774 * @retval State of bit (1 or 0).
1775 */
LL_BDMA_IsActiveFlag_TE3(BDMA_TypeDef * BDMAx)1776 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(BDMA_TypeDef *BDMAx)
1777 {
1778 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF3) == (BDMA_ISR_TEIF3)) ? 1UL : 0UL);
1779 }
1780
1781 /**
1782 * @brief Get Channel 4 transfer error flag.
1783 * @rmtoll ISR TEIF4 LL_BDMA_IsActiveFlag_TE4
1784 * @param BDMAx BDMA Instance
1785 * @retval State of bit (1 or 0).
1786 */
LL_BDMA_IsActiveFlag_TE4(BDMA_TypeDef * BDMAx)1787 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(BDMA_TypeDef *BDMAx)
1788 {
1789 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF4) == (BDMA_ISR_TEIF4)) ? 1UL : 0UL);
1790 }
1791
1792 /**
1793 * @brief Get Channel 5 transfer error flag.
1794 * @rmtoll ISR TEIF5 LL_BDMA_IsActiveFlag_TE5
1795 * @param BDMAx BDMA Instance
1796 * @retval State of bit (1 or 0).
1797 */
LL_BDMA_IsActiveFlag_TE5(BDMA_TypeDef * BDMAx)1798 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(BDMA_TypeDef *BDMAx)
1799 {
1800 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF5) == (BDMA_ISR_TEIF5)) ? 1UL : 0UL);
1801 }
1802
1803 /**
1804 * @brief Get Channel 6 transfer error flag.
1805 * @rmtoll ISR TEIF6 LL_BDMA_IsActiveFlag_TE6
1806 * @param BDMAx BDMA Instance
1807 * @retval State of bit (1 or 0).
1808 */
LL_BDMA_IsActiveFlag_TE6(BDMA_TypeDef * BDMAx)1809 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(BDMA_TypeDef *BDMAx)
1810 {
1811 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF6) == (BDMA_ISR_TEIF6)) ? 1UL : 0UL);
1812 }
1813
1814 /**
1815 * @brief Get Channel 7 transfer error flag.
1816 * @rmtoll ISR TEIF7 LL_BDMA_IsActiveFlag_TE7
1817 * @param BDMAx BDMA Instance
1818 * @retval State of bit (1 or 0).
1819 */
LL_BDMA_IsActiveFlag_TE7(BDMA_TypeDef * BDMAx)1820 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7(BDMA_TypeDef *BDMAx)
1821 {
1822 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF7) == (BDMA_ISR_TEIF7)) ? 1UL : 0UL);
1823 }
1824
1825 /**
1826 * @brief Clear Channel 0 global interrupt flag.
1827 * @note Do not Clear Channel 0 global interrupt flag when the channel in ON.
1828 Instead clear specific flags transfer complete, half transfer & transfer
1829 error flag with LL_DMA_ClearFlag_TC0, LL_DMA_ClearFlag_HT0,
1830 LL_DMA_ClearFlag_TE0. bug id 2.3.1 in Product Errata Sheet.
1831 * @rmtoll IFCR CGIF0 LL_BDMA_ClearFlag_GI0
1832 * @param BDMAx BDMA Instance
1833 * @retval None
1834 */
LL_BDMA_ClearFlag_GI0(BDMA_TypeDef * BDMAx)1835 __STATIC_INLINE void LL_BDMA_ClearFlag_GI0(BDMA_TypeDef *BDMAx)
1836 {
1837 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF0);
1838 }
1839
1840 /**
1841 * @brief Clear Channel 1 global interrupt flag.
1842 * @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
1843 Instead clear specific flags transfer complete, half transfer & transfer
1844 error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
1845 LL_DMA_ClearFlag_TE1. bug id 2.3.1 in Product Errata Sheet.
1846 * @rmtoll IFCR CGIF1 LL_BDMA_ClearFlag_GI1
1847 * @param BDMAx BDMA Instance
1848 * @retval None
1849 */
LL_BDMA_ClearFlag_GI1(BDMA_TypeDef * BDMAx)1850 __STATIC_INLINE void LL_BDMA_ClearFlag_GI1(BDMA_TypeDef *BDMAx)
1851 {
1852 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF1);
1853 }
1854
1855 /**
1856 * @brief Clear Channel 2 global interrupt flag.
1857 * @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
1858 Instead clear specific flags transfer complete, half transfer & transfer
1859 error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
1860 LL_DMA_ClearFlag_TE2. bug id 2.3.1 in Product Errata Sheet.
1861 * @rmtoll IFCR CGIF2 LL_BDMA_ClearFlag_GI2
1862 * @param BDMAx BDMA Instance
1863 * @retval None
1864 */
LL_BDMA_ClearFlag_GI2(BDMA_TypeDef * BDMAx)1865 __STATIC_INLINE void LL_BDMA_ClearFlag_GI2(BDMA_TypeDef *BDMAx)
1866 {
1867 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF2);
1868 }
1869
1870 /**
1871 * @brief Clear Channel 3 global interrupt flag.
1872 * @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
1873 Instead clear specific flags transfer complete, half transfer & transfer
1874 error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
1875 LL_DMA_ClearFlag_TE3. bug id 2.3.1 in Product Errata Sheet.
1876 * @rmtoll IFCR CGIF3 LL_BDMA_ClearFlag_GI3
1877 * @param BDMAx BDMA Instance
1878 * @retval None
1879 */
LL_BDMA_ClearFlag_GI3(BDMA_TypeDef * BDMAx)1880 __STATIC_INLINE void LL_BDMA_ClearFlag_GI3(BDMA_TypeDef *BDMAx)
1881 {
1882 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF3);
1883 }
1884
1885 /**
1886 * @brief Clear Channel 4 global interrupt flag.
1887 * @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
1888 Instead clear specific flags transfer complete, half transfer & transfer
1889 error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
1890 LL_DMA_ClearFlag_TE4. bug id 2.3.1 in Product Errata Sheet.
1891 * @rmtoll IFCR CGIF4 LL_BDMA_ClearFlag_GI4
1892 * @param BDMAx BDMA Instance
1893 * @retval None
1894 */
LL_BDMA_ClearFlag_GI4(BDMA_TypeDef * BDMAx)1895 __STATIC_INLINE void LL_BDMA_ClearFlag_GI4(BDMA_TypeDef *BDMAx)
1896 {
1897 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF4);
1898 }
1899
1900 /**
1901 * @brief Clear Channel 5 global interrupt flag.
1902 * @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
1903 Instead clear specific flags transfer complete, half transfer & transfer
1904 error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
1905 LL_DMA_ClearFlag_TE5. bug id 2.3.1 in Product Errata Sheet.
1906 * @rmtoll IFCR CGIF5 LL_BDMA_ClearFlag_GI5
1907 * @param BDMAx BDMA Instance
1908 * @retval None
1909 */
LL_BDMA_ClearFlag_GI5(BDMA_TypeDef * BDMAx)1910 __STATIC_INLINE void LL_BDMA_ClearFlag_GI5(BDMA_TypeDef *BDMAx)
1911 {
1912 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF5);
1913 }
1914
1915 /**
1916 * @brief Clear Channel 6 global interrupt flag.
1917 * @note Do not Clear Channel 6 global interrupt flag when the channel in ON.
1918 Instead clear specific flags transfer complete, half transfer & transfer
1919 error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6,
1920 LL_DMA_ClearFlag_TE6. bug id 2.3.1 in Product Errata Sheet.
1921 * @rmtoll IFCR CGIF6 LL_BDMA_ClearFlag_GI6
1922 * @param BDMAx BDMA Instance
1923 * @retval None
1924 */
LL_BDMA_ClearFlag_GI6(BDMA_TypeDef * BDMAx)1925 __STATIC_INLINE void LL_BDMA_ClearFlag_GI6(BDMA_TypeDef *BDMAx)
1926 {
1927 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF6);
1928 }
1929
1930 /**
1931 * @brief Clear Channel 7 global interrupt flag.
1932 * @note Do not Clear Channel 7 global interrupt flag when the channel in ON.
1933 Instead clear specific flags transfer complete, half transfer & transfer
1934 error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7,
1935 LL_DMA_ClearFlag_TE7. bug id 2.3.1 in Product Errata Sheet.
1936 * @rmtoll IFCR CGIF7 LL_BDMA_ClearFlag_GI7
1937 * @param BDMAx BDMA Instance
1938 * @retval None
1939 */
LL_BDMA_ClearFlag_GI7(BDMA_TypeDef * BDMAx)1940 __STATIC_INLINE void LL_BDMA_ClearFlag_GI7(BDMA_TypeDef *BDMAx)
1941 {
1942 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF7);
1943 }
1944
1945 /**
1946 * @brief Clear Channel 0 transfer complete flag.
1947 * @rmtoll IFCR CTCIF0 LL_BDMA_ClearFlag_TC0
1948 * @param BDMAx BDMA Instance
1949 * @retval None
1950 */
LL_BDMA_ClearFlag_TC0(BDMA_TypeDef * BDMAx)1951 __STATIC_INLINE void LL_BDMA_ClearFlag_TC0(BDMA_TypeDef *BDMAx)
1952 {
1953 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF0);
1954 }
1955
1956 /**
1957 * @brief Clear Channel 1 transfer complete flag.
1958 * @rmtoll IFCR CTCIF1 LL_BDMA_ClearFlag_TC1
1959 * @param BDMAx BDMA Instance
1960 * @retval None
1961 */
LL_BDMA_ClearFlag_TC1(BDMA_TypeDef * BDMAx)1962 __STATIC_INLINE void LL_BDMA_ClearFlag_TC1(BDMA_TypeDef *BDMAx)
1963 {
1964 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF1);
1965 }
1966
1967 /**
1968 * @brief Clear Channel 2 transfer complete flag.
1969 * @rmtoll IFCR CTCIF2 LL_BDMA_ClearFlag_TC2
1970 * @param BDMAx BDMA Instance
1971 * @retval None
1972 */
LL_BDMA_ClearFlag_TC2(BDMA_TypeDef * BDMAx)1973 __STATIC_INLINE void LL_BDMA_ClearFlag_TC2(BDMA_TypeDef *BDMAx)
1974 {
1975 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF2);
1976 }
1977
1978 /**
1979 * @brief Clear Channel 3 transfer complete flag.
1980 * @rmtoll IFCR CTCIF3 LL_BDMA_ClearFlag_TC3
1981 * @param BDMAx BDMA Instance
1982 * @retval None
1983 */
LL_BDMA_ClearFlag_TC3(BDMA_TypeDef * BDMAx)1984 __STATIC_INLINE void LL_BDMA_ClearFlag_TC3(BDMA_TypeDef *BDMAx)
1985 {
1986 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF3);
1987 }
1988
1989 /**
1990 * @brief Clear Channel 4 transfer complete flag.
1991 * @rmtoll IFCR CTCIF4 LL_BDMA_ClearFlag_TC4
1992 * @param BDMAx BDMA Instance
1993 * @retval None
1994 */
LL_BDMA_ClearFlag_TC4(BDMA_TypeDef * BDMAx)1995 __STATIC_INLINE void LL_BDMA_ClearFlag_TC4(BDMA_TypeDef *BDMAx)
1996 {
1997 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF4);
1998 }
1999
2000 /**
2001 * @brief Clear Channel 5 transfer complete flag.
2002 * @rmtoll IFCR CTCIF5 LL_BDMA_ClearFlag_TC5
2003 * @param BDMAx BDMA Instance
2004 * @retval None
2005 */
LL_BDMA_ClearFlag_TC5(BDMA_TypeDef * BDMAx)2006 __STATIC_INLINE void LL_BDMA_ClearFlag_TC5(BDMA_TypeDef *BDMAx)
2007 {
2008 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF5);
2009 }
2010
2011 /**
2012 * @brief Clear Channel 6 transfer complete flag.
2013 * @rmtoll IFCR CTCIF6 LL_BDMA_ClearFlag_TC6
2014 * @param BDMAx BDMA Instance
2015 * @retval None
2016 */
LL_BDMA_ClearFlag_TC6(BDMA_TypeDef * BDMAx)2017 __STATIC_INLINE void LL_BDMA_ClearFlag_TC6(BDMA_TypeDef *BDMAx)
2018 {
2019 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF6);
2020 }
2021
2022 /**
2023 * @brief Clear Channel 7 transfer complete flag.
2024 * @rmtoll IFCR CTCIF7 LL_BDMA_ClearFlag_TC7
2025 * @param BDMAx BDMA Instance
2026 * @retval None
2027 */
LL_BDMA_ClearFlag_TC7(BDMA_TypeDef * BDMAx)2028 __STATIC_INLINE void LL_BDMA_ClearFlag_TC7(BDMA_TypeDef *BDMAx)
2029 {
2030 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF7);
2031 }
2032
2033 /**
2034 * @brief Clear Channel 0 half transfer flag.
2035 * @rmtoll IFCR CHTIF0 LL_BDMA_ClearFlag_HT0
2036 * @param BDMAx BDMA Instance
2037 * @retval None
2038 */
LL_BDMA_ClearFlag_HT0(BDMA_TypeDef * BDMAx)2039 __STATIC_INLINE void LL_BDMA_ClearFlag_HT0(BDMA_TypeDef *BDMAx)
2040 {
2041 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF0);
2042 }
2043
2044 /**
2045 * @brief Clear Channel 1 half transfer flag.
2046 * @rmtoll IFCR CHTIF1 LL_BDMA_ClearFlag_HT1
2047 * @param BDMAx BDMA Instance
2048 * @retval None
2049 */
LL_BDMA_ClearFlag_HT1(BDMA_TypeDef * BDMAx)2050 __STATIC_INLINE void LL_BDMA_ClearFlag_HT1(BDMA_TypeDef *BDMAx)
2051 {
2052 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF1);
2053 }
2054
2055 /**
2056 * @brief Clear Channel 2 half transfer flag.
2057 * @rmtoll IFCR CHTIF2 LL_BDMA_ClearFlag_HT2
2058 * @param BDMAx BDMA Instance
2059 * @retval None
2060 */
LL_BDMA_ClearFlag_HT2(BDMA_TypeDef * BDMAx)2061 __STATIC_INLINE void LL_BDMA_ClearFlag_HT2(BDMA_TypeDef *BDMAx)
2062 {
2063 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF2);
2064 }
2065
2066 /**
2067 * @brief Clear Channel 3 half transfer flag.
2068 * @rmtoll IFCR CHTIF3 LL_BDMA_ClearFlag_HT3
2069 * @param BDMAx BDMA Instance
2070 * @retval None
2071 */
LL_BDMA_ClearFlag_HT3(BDMA_TypeDef * BDMAx)2072 __STATIC_INLINE void LL_BDMA_ClearFlag_HT3(BDMA_TypeDef *BDMAx)
2073 {
2074 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF3);
2075 }
2076
2077 /**
2078 * @brief Clear Channel 4 half transfer flag.
2079 * @rmtoll IFCR CHTIF4 LL_BDMA_ClearFlag_HT4
2080 * @param BDMAx BDMA Instance
2081 * @retval None
2082 */
LL_BDMA_ClearFlag_HT4(BDMA_TypeDef * BDMAx)2083 __STATIC_INLINE void LL_BDMA_ClearFlag_HT4(BDMA_TypeDef *BDMAx)
2084 {
2085 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF4);
2086 }
2087
2088 /**
2089 * @brief Clear Channel 5 half transfer flag.
2090 * @rmtoll IFCR CHTIF5 LL_BDMA_ClearFlag_HT5
2091 * @param BDMAx BDMA Instance
2092 * @retval None
2093 */
LL_BDMA_ClearFlag_HT5(BDMA_TypeDef * BDMAx)2094 __STATIC_INLINE void LL_BDMA_ClearFlag_HT5(BDMA_TypeDef *BDMAx)
2095 {
2096 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF5);
2097 }
2098
2099 /**
2100 * @brief Clear Channel 6 half transfer flag.
2101 * @rmtoll IFCR CHTIF6 LL_BDMA_ClearFlag_HT6
2102 * @param BDMAx BDMA Instance
2103 * @retval None
2104 */
LL_BDMA_ClearFlag_HT6(BDMA_TypeDef * BDMAx)2105 __STATIC_INLINE void LL_BDMA_ClearFlag_HT6(BDMA_TypeDef *BDMAx)
2106 {
2107 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF6);
2108 }
2109
2110 /**
2111 * @brief Clear Channel 7 half transfer flag.
2112 * @rmtoll IFCR CHTIF7 LL_BDMA_ClearFlag_HT7
2113 * @param BDMAx BDMA Instance
2114 * @retval None
2115 */
LL_BDMA_ClearFlag_HT7(BDMA_TypeDef * BDMAx)2116 __STATIC_INLINE void LL_BDMA_ClearFlag_HT7(BDMA_TypeDef *BDMAx)
2117 {
2118 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF7);
2119 }
2120
2121 /**
2122 * @brief Clear Channel 0 transfer error flag.
2123 * @rmtoll IFCR CTEIF0 LL_BDMA_ClearFlag_TE0
2124 * @param BDMAx BDMA Instance
2125 * @retval None
2126 */
LL_BDMA_ClearFlag_TE0(BDMA_TypeDef * BDMAx)2127 __STATIC_INLINE void LL_BDMA_ClearFlag_TE0(BDMA_TypeDef *BDMAx)
2128 {
2129 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF0);
2130 }
2131
2132 /**
2133 * @brief Clear Channel 1 transfer error flag.
2134 * @rmtoll IFCR CTEIF1 LL_BDMA_ClearFlag_TE1
2135 * @param BDMAx BDMA Instance
2136 * @retval None
2137 */
LL_BDMA_ClearFlag_TE1(BDMA_TypeDef * BDMAx)2138 __STATIC_INLINE void LL_BDMA_ClearFlag_TE1(BDMA_TypeDef *BDMAx)
2139 {
2140 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF1);
2141 }
2142
2143 /**
2144 * @brief Clear Channel 2 transfer error flag.
2145 * @rmtoll IFCR CTEIF2 LL_BDMA_ClearFlag_TE2
2146 * @param BDMAx BDMA Instance
2147 * @retval None
2148 */
LL_BDMA_ClearFlag_TE2(BDMA_TypeDef * BDMAx)2149 __STATIC_INLINE void LL_BDMA_ClearFlag_TE2(BDMA_TypeDef *BDMAx)
2150 {
2151 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF2);
2152 }
2153
2154 /**
2155 * @brief Clear Channel 3 transfer error flag.
2156 * @rmtoll IFCR CTEIF3 LL_BDMA_ClearFlag_TE3
2157 * @param BDMAx BDMA Instance
2158 * @retval None
2159 */
LL_BDMA_ClearFlag_TE3(BDMA_TypeDef * BDMAx)2160 __STATIC_INLINE void LL_BDMA_ClearFlag_TE3(BDMA_TypeDef *BDMAx)
2161 {
2162 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF3);
2163 }
2164
2165 /**
2166 * @brief Clear Channel 4 transfer error flag.
2167 * @rmtoll IFCR CTEIF4 LL_BDMA_ClearFlag_TE4
2168 * @param BDMAx BDMA Instance
2169 * @retval None
2170 */
LL_BDMA_ClearFlag_TE4(BDMA_TypeDef * BDMAx)2171 __STATIC_INLINE void LL_BDMA_ClearFlag_TE4(BDMA_TypeDef *BDMAx)
2172 {
2173 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF4);
2174 }
2175
2176 /**
2177 * @brief Clear Channel 5 transfer error flag.
2178 * @rmtoll IFCR CTEIF5 LL_BDMA_ClearFlag_TE5
2179 * @param BDMAx BDMA Instance
2180 * @retval None
2181 */
LL_BDMA_ClearFlag_TE5(BDMA_TypeDef * BDMAx)2182 __STATIC_INLINE void LL_BDMA_ClearFlag_TE5(BDMA_TypeDef *BDMAx)
2183 {
2184 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF5);
2185 }
2186
2187 /**
2188 * @brief Clear Channel 6 transfer error flag.
2189 * @rmtoll IFCR CTEIF6 LL_BDMA_ClearFlag_TE6
2190 * @param BDMAx BDMA Instance
2191 * @retval None
2192 */
LL_BDMA_ClearFlag_TE6(BDMA_TypeDef * BDMAx)2193 __STATIC_INLINE void LL_BDMA_ClearFlag_TE6(BDMA_TypeDef *BDMAx)
2194 {
2195 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF6);
2196 }
2197
2198 /**
2199 * @brief Clear Channel 7 transfer error flag.
2200 * @rmtoll IFCR CTEIF7 LL_BDMA_ClearFlag_TE7
2201 * @param BDMAx BDMA Instance
2202 * @retval None
2203 */
LL_BDMA_ClearFlag_TE7(BDMA_TypeDef * BDMAx)2204 __STATIC_INLINE void LL_BDMA_ClearFlag_TE7(BDMA_TypeDef *BDMAx)
2205 {
2206 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF7);
2207 }
2208
2209 /**
2210 * @}
2211 */
2212
2213 /** @defgroup BDMA_LL_EF_IT_Management IT_Management
2214 * @{
2215 */
2216 /**
2217 * @brief Enable Transfer complete interrupt.
2218 * @rmtoll CCR TCIE LL_BDMA_EnableIT_TC
2219 * @param BDMAx BDMA Instance
2220 * @param Channel This parameter can be one of the following values:
2221 * @arg @ref LL_BDMA_CHANNEL_0
2222 * @arg @ref LL_BDMA_CHANNEL_1
2223 * @arg @ref LL_BDMA_CHANNEL_2
2224 * @arg @ref LL_BDMA_CHANNEL_3
2225 * @arg @ref LL_BDMA_CHANNEL_4
2226 * @arg @ref LL_BDMA_CHANNEL_5
2227 * @arg @ref LL_BDMA_CHANNEL_6
2228 * @arg @ref LL_BDMA_CHANNEL_7
2229 * @retval None
2230 */
LL_BDMA_EnableIT_TC(BDMA_TypeDef * BDMAx,uint32_t Channel)2231 __STATIC_INLINE void LL_BDMA_EnableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)
2232 {
2233 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2234
2235 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE);
2236 }
2237
2238 /**
2239 * @brief Enable Half transfer interrupt.
2240 * @rmtoll CCR HTIE LL_BDMA_EnableIT_HT
2241 * @param BDMAx BDMA Instance
2242 * @param Channel This parameter can be one of the following values:
2243 * @arg @ref LL_BDMA_CHANNEL_0
2244 * @arg @ref LL_BDMA_CHANNEL_1
2245 * @arg @ref LL_BDMA_CHANNEL_2
2246 * @arg @ref LL_BDMA_CHANNEL_3
2247 * @arg @ref LL_BDMA_CHANNEL_4
2248 * @arg @ref LL_BDMA_CHANNEL_5
2249 * @arg @ref LL_BDMA_CHANNEL_6
2250 * @arg @ref LL_BDMA_CHANNEL_7
2251 * @retval None
2252 */
LL_BDMA_EnableIT_HT(BDMA_TypeDef * BDMAx,uint32_t Channel)2253 __STATIC_INLINE void LL_BDMA_EnableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)
2254 {
2255 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2256
2257 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE);
2258 }
2259
2260 /**
2261 * @brief Enable Transfer error interrupt.
2262 * @rmtoll CCR TEIE LL_BDMA_EnableIT_TE
2263 * @param BDMAx BDMA Instance
2264 * @param Channel This parameter can be one of the following values:
2265 * @arg @ref LL_BDMA_CHANNEL_0
2266 * @arg @ref LL_BDMA_CHANNEL_1
2267 * @arg @ref LL_BDMA_CHANNEL_2
2268 * @arg @ref LL_BDMA_CHANNEL_3
2269 * @arg @ref LL_BDMA_CHANNEL_4
2270 * @arg @ref LL_BDMA_CHANNEL_5
2271 * @arg @ref LL_BDMA_CHANNEL_6
2272 * @arg @ref LL_BDMA_CHANNEL_7
2273 * @retval None
2274 */
LL_BDMA_EnableIT_TE(BDMA_TypeDef * BDMAx,uint32_t Channel)2275 __STATIC_INLINE void LL_BDMA_EnableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)
2276 {
2277 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2278
2279 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE);
2280 }
2281
2282 /**
2283 * @brief Disable Transfer complete interrupt.
2284 * @rmtoll CCR TCIE LL_BDMA_DisableIT_TC
2285 * @param BDMAx BDMA Instance
2286 * @param Channel This parameter can be one of the following values:
2287 * @arg @ref LL_BDMA_CHANNEL_0
2288 * @arg @ref LL_BDMA_CHANNEL_1
2289 * @arg @ref LL_BDMA_CHANNEL_2
2290 * @arg @ref LL_BDMA_CHANNEL_3
2291 * @arg @ref LL_BDMA_CHANNEL_4
2292 * @arg @ref LL_BDMA_CHANNEL_5
2293 * @arg @ref LL_BDMA_CHANNEL_6
2294 * @arg @ref LL_BDMA_CHANNEL_7
2295 * @retval None
2296 */
LL_BDMA_DisableIT_TC(BDMA_TypeDef * BDMAx,uint32_t Channel)2297 __STATIC_INLINE void LL_BDMA_DisableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)
2298 {
2299 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2300
2301 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE);
2302 }
2303
2304 /**
2305 * @brief Disable Half transfer interrupt.
2306 * @rmtoll CCR HTIE LL_BDMA_DisableIT_HT
2307 * @param BDMAx BDMA Instance
2308 * @param Channel This parameter can be one of the following values:
2309 * @arg @ref LL_BDMA_CHANNEL_0
2310 * @arg @ref LL_BDMA_CHANNEL_1
2311 * @arg @ref LL_BDMA_CHANNEL_2
2312 * @arg @ref LL_BDMA_CHANNEL_3
2313 * @arg @ref LL_BDMA_CHANNEL_4
2314 * @arg @ref LL_BDMA_CHANNEL_5
2315 * @arg @ref LL_BDMA_CHANNEL_6
2316 * @arg @ref LL_BDMA_CHANNEL_7
2317 * @retval None
2318 */
LL_BDMA_DisableIT_HT(BDMA_TypeDef * BDMAx,uint32_t Channel)2319 __STATIC_INLINE void LL_BDMA_DisableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)
2320 {
2321 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2322
2323 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE);
2324 }
2325
2326 /**
2327 * @brief Disable Transfer error interrupt.
2328 * @rmtoll CCR TEIE LL_BDMA_DisableIT_TE
2329 * @param BDMAx BDMA Instance
2330 * @param Channel This parameter can be one of the following values:
2331 * @arg @ref LL_BDMA_CHANNEL_0
2332 * @arg @ref LL_BDMA_CHANNEL_1
2333 * @arg @ref LL_BDMA_CHANNEL_2
2334 * @arg @ref LL_BDMA_CHANNEL_3
2335 * @arg @ref LL_BDMA_CHANNEL_4
2336 * @arg @ref LL_BDMA_CHANNEL_5
2337 * @arg @ref LL_BDMA_CHANNEL_6
2338 * @arg @ref LL_BDMA_CHANNEL_7
2339 * @retval None
2340 */
LL_BDMA_DisableIT_TE(BDMA_TypeDef * BDMAx,uint32_t Channel)2341 __STATIC_INLINE void LL_BDMA_DisableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)
2342 {
2343 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2344
2345 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE);
2346 }
2347
2348 /**
2349 * @brief Check if Transfer complete Interrupt is enabled.
2350 * @rmtoll CCR TCIE LL_BDMA_IsEnabledIT_TC
2351 * @param BDMAx BDMA Instance
2352 * @param Channel This parameter can be one of the following values:
2353 * @arg @ref LL_BDMA_CHANNEL_0
2354 * @arg @ref LL_BDMA_CHANNEL_1
2355 * @arg @ref LL_BDMA_CHANNEL_2
2356 * @arg @ref LL_BDMA_CHANNEL_3
2357 * @arg @ref LL_BDMA_CHANNEL_4
2358 * @arg @ref LL_BDMA_CHANNEL_5
2359 * @arg @ref LL_BDMA_CHANNEL_6
2360 * @arg @ref LL_BDMA_CHANNEL_7
2361 * @retval State of bit (1 or 0).
2362 */
LL_BDMA_IsEnabledIT_TC(BDMA_TypeDef * BDMAx,uint32_t Channel)2363 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)
2364 {
2365 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2366
2367 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE) == (BDMA_CCR_TCIE)) ? 1UL : 0UL);
2368 }
2369
2370 /**
2371 * @brief Check if Half transfer Interrupt is enabled.
2372 * @rmtoll CCR HTIE LL_BDMA_IsEnabledIT_HT
2373 * @param BDMAx BDMA Instance
2374 * @param Channel This parameter can be one of the following values:
2375 * @arg @ref LL_BDMA_CHANNEL_0
2376 * @arg @ref LL_BDMA_CHANNEL_1
2377 * @arg @ref LL_BDMA_CHANNEL_2
2378 * @arg @ref LL_BDMA_CHANNEL_3
2379 * @arg @ref LL_BDMA_CHANNEL_4
2380 * @arg @ref LL_BDMA_CHANNEL_5
2381 * @arg @ref LL_BDMA_CHANNEL_6
2382 * @arg @ref LL_BDMA_CHANNEL_7
2383 * @retval State of bit (1 or 0).
2384 */
LL_BDMA_IsEnabledIT_HT(BDMA_TypeDef * BDMAx,uint32_t Channel)2385 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)
2386 {
2387 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2388
2389 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE) == (BDMA_CCR_HTIE)) ? 1UL : 0UL);
2390 }
2391
2392 /**
2393 * @brief Check if Transfer error Interrupt is enabled.
2394 * @rmtoll CCR TEIE LL_BDMA_IsEnabledIT_TE
2395 * @param BDMAx BDMA Instance
2396 * @param Channel This parameter can be one of the following values:
2397 * @arg @ref LL_BDMA_CHANNEL_0
2398 * @arg @ref LL_BDMA_CHANNEL_1
2399 * @arg @ref LL_BDMA_CHANNEL_2
2400 * @arg @ref LL_BDMA_CHANNEL_3
2401 * @arg @ref LL_BDMA_CHANNEL_4
2402 * @arg @ref LL_BDMA_CHANNEL_5
2403 * @arg @ref LL_BDMA_CHANNEL_6
2404 * @arg @ref LL_BDMA_CHANNEL_7
2405 * @retval State of bit (1 or 0).
2406 */
LL_BDMA_IsEnabledIT_TE(BDMA_TypeDef * BDMAx,uint32_t Channel)2407 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)
2408 {
2409 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2410
2411 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE) == (BDMA_CCR_TEIE)) ? 1UL : 0UL);
2412 }
2413
2414 /**
2415 * @}
2416 */
2417
2418 #if defined(USE_FULL_LL_DRIVER)
2419 /** @defgroup BDMA_LL_EF_Init Initialization and de-initialization functions
2420 * @{
2421 */
2422
2423 uint32_t LL_BDMA_Init(BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef *BDMA_InitStruct);
2424 uint32_t LL_BDMA_DeInit(BDMA_TypeDef *BDMAx, uint32_t Channel);
2425 void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct);
2426
2427 /**
2428 * @}
2429 */
2430 #endif /* USE_FULL_LL_DRIVER */
2431
2432 /**
2433 * @}
2434 */
2435
2436 /**
2437 * @}
2438 */
2439
2440 #endif /* BDMA || BDMA1 || BDMA2 */
2441 /**
2442 * @}
2443 */
2444
2445 #ifdef __cplusplus
2446 }
2447 #endif
2448
2449 #endif /* STM32H7xx_LL_BDMA_H */
2450
2451
