1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32H7xx_HAL_RCC_EX_H 20 #define STM32H7xx_HAL_RCC_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32h7xx_hal_def.h" 28 29 /** @addtogroup STM32H7xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCCEx 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 39 * @{ 40 */ 41 42 /** 43 * @brief PLL2 Clock structure definition 44 */ 45 typedef struct 46 { 47 48 uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock. 49 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 50 51 uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock. 52 This parameter must be a number between Min_Data = 4 and Max_Data = 512 53 or between Min_Data = 8 and Max_Data = 420(*) 54 (*) : For stm32h7a3xx and stm32h7b3xx family lines. */ 55 56 uint32_t PLL2P; /*!< PLL2P: Division factor for system clock. 57 This parameter must be a number between Min_Data = 2 and Max_Data = 128 58 odd division factors are not allowed */ 59 60 uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks. 61 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 62 63 uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks. 64 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 65 uint32_t PLL2RGE; /*!<PLL2RGE: PLL2 clock Input range 66 This parameter must be a value of @ref RCC_PLL2_VCI_Range */ 67 uint32_t PLL2VCOSEL; /*!<PLL2VCOSEL: PLL2 clock Output range 68 This parameter must be a value of @ref RCC_PLL2_VCO_Range */ 69 70 uint32_t PLL2FRACN; /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for 71 PLL2 VCO It should be a value between 0 and 8191 */ 72 } RCC_PLL2InitTypeDef; 73 74 /** 75 * @brief PLL3 Clock structure definition 76 */ 77 typedef struct 78 { 79 80 uint32_t PLL3M; /*!< PLL3M: Division factor for PLL3 VCO input clock. 81 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 82 83 uint32_t PLL3N; /*!< PLL3N: Multiplication factor for PLL3 VCO output clock. 84 This parameter must be a number between Min_Data = 4 and Max_Data = 512 85 or between Min_Data = 8 and Max_Data = 420(*) 86 (*) : For stm32h7a3xx and stm32h7b3xx family lines. */ 87 88 uint32_t PLL3P; /*!< PLL3P: Division factor for system clock. 89 This parameter must be a number between Min_Data = 2 and Max_Data = 128 90 odd division factors are not allowed */ 91 92 uint32_t PLL3Q; /*!< PLL3Q: Division factor for peripheral clocks. 93 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 94 95 uint32_t PLL3R; /*!< PLL3R: Division factor for peripheral clocks. 96 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 97 uint32_t PLL3RGE; /*!<PLL3RGE: PLL3 clock Input range 98 This parameter must be a value of @ref RCC_PLL3_VCI_Range */ 99 uint32_t PLL3VCOSEL; /*!<PLL3VCOSEL: PLL3 clock Output range 100 This parameter must be a value of @ref RCC_PLL3_VCO_Range */ 101 102 uint32_t PLL3FRACN; /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for 103 PLL3 VCO It should be a value between 0 and 8191 */ 104 } RCC_PLL3InitTypeDef; 105 106 /** 107 * @brief RCC PLL1 Clocks structure definition 108 */ 109 typedef struct 110 { 111 uint32_t PLL1_P_Frequency; 112 uint32_t PLL1_Q_Frequency; 113 uint32_t PLL1_R_Frequency; 114 } PLL1_ClocksTypeDef; 115 116 /** 117 * @brief RCC PLL2 Clocks structure definition 118 */ 119 typedef struct 120 { 121 uint32_t PLL2_P_Frequency; 122 uint32_t PLL2_Q_Frequency; 123 uint32_t PLL2_R_Frequency; 124 } PLL2_ClocksTypeDef; 125 126 /** 127 * @brief RCC PLL3 Clocks structure definition 128 */ 129 typedef struct 130 { 131 uint32_t PLL3_P_Frequency; 132 uint32_t PLL3_Q_Frequency; 133 uint32_t PLL3_R_Frequency; 134 } PLL3_ClocksTypeDef; 135 136 137 /** 138 * @brief RCC extended clocks structure definition 139 */ 140 typedef struct 141 { 142 uint64_t PeriphClockSelection; /*!< The Extended Clock to be configured. 143 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 144 145 RCC_PLL2InitTypeDef PLL2; /*!< PLL2structure parameters. 146 This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */ 147 148 RCC_PLL3InitTypeDef PLL3; /*!< PLL3 structure parameters. 149 This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */ 150 151 uint32_t FmcClockSelection; /*!< Specifies FMC clock source 152 This parameter can be a value of @ref RCCEx_FMC_Clock_Source */ 153 154 #if defined(QUADSPI) 155 uint32_t QspiClockSelection; /*!< Specifies QSPI clock source 156 This parameter can be a value of @ref RCCEx_QSPI_Clock_Source */ 157 #endif /* QUADSPI */ 158 159 #if defined(OCTOSPI1) || defined(OCTOSPI2) 160 uint32_t OspiClockSelection; /*!< Specifies OSPI clock source 161 This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ 162 #endif /*(OCTOSPI1) || (OCTOSPI2)*/ 163 164 165 #if defined(DSI) 166 uint32_t DsiClockSelection; /*!< Specifies DSI clock source 167 This parameter can be a value of @ref RCCEx_DSI_Clock_Source */ 168 #endif /* DSI */ 169 170 uint32_t SdmmcClockSelection; /*!< Specifies SDMMC clock source 171 This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source */ 172 173 uint32_t CkperClockSelection; /*!< Specifies CKPER clock source 174 This parameter can be a value of @ref RCCEx_CLKP_Clock_Source */ 175 176 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source 177 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 178 179 #if defined(SAI3) 180 uint32_t Sai23ClockSelection; /*!< Specifies SAI2/3 clock source 181 This parameter can be a value of @ref RCCEx_SAI23_Clock_Source */ 182 #endif /* SAI3 */ 183 184 #if defined(RCC_CDCCIP1R_SAI2ASEL) 185 uint32_t Sai2AClockSelection; /*!< Specifies SAI2A clock source 186 This parameter can be a value of @ref RCCEx_SAI2A_Clock_Source */ 187 #endif /* RCC_CDCCIP1R_SAI2ASEL */ 188 189 #if defined(RCC_CDCCIP1R_SAI2BSEL) 190 uint32_t Sai2BClockSelection; /*!< Specifies SAI2B clock source 191 This parameter can be a value of @ref RCCEx_SAI2B_Clock_Source */ 192 #endif /* RCC_CDCCIP1R_SAI2BSEL */ 193 194 uint32_t Spi123ClockSelection; /*!< Specifies SPI1/2/3 clock source 195 This parameter can be a value of @ref RCCEx_SPI123_Clock_Source */ 196 197 uint32_t Spi45ClockSelection; /*!< Specifies SPI4/5 clock source 198 This parameter can be a value of @ref RCCEx_SPI45_Clock_Source */ 199 200 uint32_t SpdifrxClockSelection; /*!< Specifies SPDIFRX Clock clock source 201 This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */ 202 203 uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock clock source 204 This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */ 205 206 #if defined(DFSDM2_BASE) 207 uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock clock source 208 This parameter can be a value of @ref RCCEx_DFSDM2_Clock_Source */ 209 #endif /* DFSDM2_BASE */ 210 211 #if defined(FDCAN1) || defined(FDCAN2) 212 uint32_t FdcanClockSelection; /*!< Specifies FDCAN Clock clock source 213 This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ 214 #endif /*FDCAN1 || FDCAN2*/ 215 216 uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 Clock clock source 217 This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */ 218 219 uint32_t Usart234578ClockSelection; /*!< Specifies USART2/3/4/5/7/8 clock source 220 This parameter can be a value of @ref RCCEx_USART234578_Clock_Source */ 221 222 uint32_t Usart16ClockSelection; /*!< Specifies USART1/6 clock source 223 This parameter can be a value of @ref RCCEx_USART16_Clock_Source */ 224 225 uint32_t RngClockSelection; /*!< Specifies RNG clock source 226 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 227 228 #if defined(I2C5) 229 uint32_t I2c1235ClockSelection; /*!< Specifies I2C1/2/3/5 clock source 230 This parameter can be a value of @ref RCCEx_I2C1235_Clock_Source */ 231 #else 232 uint32_t I2c123ClockSelection; /*!< Specifies I2C1/2/3 clock source 233 This parameter can be a value of @ref RCCEx_I2C1235_Clock_Source */ 234 #endif /*I2C5*/ 235 236 uint32_t UsbClockSelection; /*!< Specifies USB clock source 237 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 238 239 uint32_t CecClockSelection; /*!< Specifies CEC clock source 240 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ 241 242 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source 243 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 244 245 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source 246 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 247 248 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source 249 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ 250 251 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source 252 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 253 254 uint32_t Lptim345ClockSelection; /*!< Specifies LPTIM3/4/5 clock source 255 This parameter can be a value of @ref RCCEx_LPTIM345_Clock_Source */ 256 257 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source 258 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ 259 #if defined(SAI4) 260 uint32_t Sai4AClockSelection; /*!< Specifies SAI4A clock source 261 This parameter can be a value of @ref RCCEx_SAI4A_Clock_Source */ 262 263 uint32_t Sai4BClockSelection; /*!< Specifies SAI4B clock source 264 This parameter can be a value of @ref RCCEx_SAI4B_Clock_Source */ 265 #endif /* SAI4 */ 266 267 uint32_t Spi6ClockSelection; /*!< Specifies SPI6 clock source 268 This parameter can be a value of @ref RCCEx_SPI6_Clock_Source */ 269 270 uint32_t RTCClockSelection; /*!< Specifies RTC Clock clock source 271 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 272 273 #if defined(HRTIM1) 274 uint32_t Hrtim1ClockSelection; /*!< Specifies HRTIM1 Clock clock source 275 This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */ 276 #endif /* HRTIM1 */ 277 278 uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. 279 This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ 280 } RCC_PeriphCLKInitTypeDef; 281 282 /*!< Alias for Inter STM32H7 lines compatibility regarding RCC_PeriphCLKInitTypeDef field : I2C5 available on some lines only */ 283 #if defined(I2C5) 284 #define I2c123ClockSelection I2c1235ClockSelection 285 #else 286 #define I2c1235ClockSelection I2c123ClockSelection 287 #endif /*I2C5*/ 288 289 290 /** 291 * @brief RCC_CRS Init structure definition 292 */ 293 typedef struct 294 { 295 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 296 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 297 298 uint32_t Source; /*!< Specifies the SYNC signal source. 299 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 300 301 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 302 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 303 304 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. 305 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 306 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ 307 308 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 309 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ 310 311 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 312 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 313 314 } RCC_CRSInitTypeDef; 315 316 /** 317 * @brief RCC_CRS Synchronization structure definition 318 */ 319 typedef struct 320 { 321 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 322 This parameter must be a number between 0 and 0xFFFF */ 323 324 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 325 This parameter must be a number between 0 and 0x3F */ 326 327 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 328 value latched in the time of the last SYNC event. 329 This parameter must be a number between 0 and 0xFFFF */ 330 331 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 332 frequency error counter latched in the time of the last SYNC event. 333 It shows whether the actual frequency is below or above the target. 334 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 335 336 } RCC_CRSSynchroInfoTypeDef; 337 338 /** 339 * @} 340 */ 341 342 343 /* Exported constants --------------------------------------------------------*/ 344 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 345 * @{ 346 */ 347 348 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection 349 * @{ 350 */ 351 352 #if defined(UART9) && defined(USART10) 353 #define RCC_PERIPHCLK_USART16910 ((uint64_t)(0x00000001U)) 354 #define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16910 355 #define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16910 356 #define RCC_PERIPHCLK_UART9 RCC_PERIPHCLK_USART16910 357 #define RCC_PERIPHCLK_USART10 RCC_PERIPHCLK_USART16910 358 /*alias*/ 359 #define RCC_PERIPHCLK_USART16 RCC_PERIPHCLK_USART16910 360 #else 361 #define RCC_PERIPHCLK_USART16 ((uint64_t)(0x00000001U)) 362 #define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16 363 #define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16 364 /* alias */ 365 #define RCC_PERIPHCLK_USART16910 RCC_PERIPHCLK_USART16 366 #endif /* UART9 && USART10*/ 367 #define RCC_PERIPHCLK_USART234578 ((uint64_t)(0x00000002U)) 368 #define RCC_PERIPHCLK_USART2 RCC_PERIPHCLK_USART234578 369 #define RCC_PERIPHCLK_USART3 RCC_PERIPHCLK_USART234578 370 #define RCC_PERIPHCLK_UART4 RCC_PERIPHCLK_USART234578 371 #define RCC_PERIPHCLK_UART5 RCC_PERIPHCLK_USART234578 372 #define RCC_PERIPHCLK_UART7 RCC_PERIPHCLK_USART234578 373 #define RCC_PERIPHCLK_UART8 RCC_PERIPHCLK_USART234578 374 #define RCC_PERIPHCLK_LPUART1 ((uint64_t)(0x00000004U)) 375 #if defined(I2C5) 376 #define RCC_PERIPHCLK_I2C1235 ((uint64_t)(0x00000008U)) 377 #define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C1235 378 #define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C1235 379 #define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C1235 380 /* alias */ 381 #define RCC_PERIPHCLK_I2C123 RCC_PERIPHCLK_I2C1235 382 #else 383 #define RCC_PERIPHCLK_I2C123 ((uint64_t)(0x00000008U)) 384 #define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C123 385 #define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C123 386 #define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C123 387 #endif /*I2C5*/ 388 #define RCC_PERIPHCLK_I2C4 ((uint64_t)(0x00000010U)) 389 #if defined(I2C5) 390 #define RCC_PERIPHCLK_I2C5 RCC_PERIPHCLK_I2C1235 391 #endif /*I2C5*/ 392 #define RCC_PERIPHCLK_LPTIM1 ((uint64_t)(0x00000020U)) 393 #define RCC_PERIPHCLK_LPTIM2 ((uint64_t)(0x00000040U)) 394 #define RCC_PERIPHCLK_LPTIM345 ((uint64_t)(0x00000080U)) 395 #define RCC_PERIPHCLK_LPTIM3 RCC_PERIPHCLK_LPTIM345 396 #if defined(LPTIM4) 397 #define RCC_PERIPHCLK_LPTIM4 RCC_PERIPHCLK_LPTIM345 398 #endif /*LPTIM4*/ 399 #if defined(LPTIM5) 400 #define RCC_PERIPHCLK_LPTIM5 RCC_PERIPHCLK_LPTIM345 401 #endif /*LPTIM5*/ 402 #define RCC_PERIPHCLK_SAI1 ((uint64_t)(0x00000100U)) 403 #if defined(SAI3) 404 #define RCC_PERIPHCLK_SAI23 ((uint64_t)(0x00000200U)) 405 #define RCC_PERIPHCLK_SAI2 RCC_PERIPHCLK_SAI23 406 #define RCC_PERIPHCLK_SAI3 RCC_PERIPHCLK_SAI23 407 #endif /* SAI3 */ 408 #if defined(RCC_CDCCIP1R_SAI2ASEL_0) 409 #define RCC_PERIPHCLK_SAI2A ((uint64_t)(0x00000200U)) 410 #endif /* RCC_CDCCIP1R_SAI2ASEL_0 */ 411 #if defined(RCC_CDCCIP1R_SAI2BSEL_0) 412 #define RCC_PERIPHCLK_SAI2B ((uint64_t)(0x00000400U)) 413 #endif /* RCC_CDCCIP1R_SAI2BSEL_0 */ 414 #if defined(SAI4) 415 #define RCC_PERIPHCLK_SAI4A ((uint64_t)(0x00000400U)) 416 #define RCC_PERIPHCLK_SAI4B ((uint64_t)(0x00000800U)) 417 #endif /* SAI4 */ 418 #define RCC_PERIPHCLK_SPI123 ((uint64_t)(0x00001000U)) 419 #define RCC_PERIPHCLK_SPI1 RCC_PERIPHCLK_SPI123 420 #define RCC_PERIPHCLK_SPI2 RCC_PERIPHCLK_SPI123 421 #define RCC_PERIPHCLK_SPI3 RCC_PERIPHCLK_SPI123 422 #define RCC_PERIPHCLK_SPI45 ((uint64_t)(0x00002000U)) 423 #define RCC_PERIPHCLK_SPI4 RCC_PERIPHCLK_SPI45 424 #define RCC_PERIPHCLK_SPI5 RCC_PERIPHCLK_SPI45 425 #define RCC_PERIPHCLK_SPI6 ((uint64_t)(0x00004000U)) 426 #define RCC_PERIPHCLK_FDCAN ((uint64_t)(0x00008000U)) 427 #define RCC_PERIPHCLK_SDMMC ((uint64_t)(0x00010000U)) 428 #define RCC_PERIPHCLK_RNG ((uint64_t)(0x00020000U)) 429 #define RCC_PERIPHCLK_USB ((uint64_t)(0x00040000U)) 430 #define RCC_PERIPHCLK_ADC ((uint64_t)(0x00080000U)) 431 #define RCC_PERIPHCLK_SWPMI1 ((uint64_t)(0x00100000U)) 432 #define RCC_PERIPHCLK_DFSDM1 ((uint64_t)(0x00200000U)) 433 #if defined(DFSDM2_BASE) 434 #define RCC_PERIPHCLK_DFSDM2 ((uint64_t)(0x00000800U)) 435 #endif /* DFSDM2 */ 436 #define RCC_PERIPHCLK_RTC ((uint64_t)(0x00400000U)) 437 #define RCC_PERIPHCLK_CEC ((uint64_t)(0x00800000U)) 438 #define RCC_PERIPHCLK_FMC ((uint64_t)(0x01000000U)) 439 #if defined(QUADSPI) 440 #define RCC_PERIPHCLK_QSPI ((uint64_t)(0x02000000U)) 441 #endif /* QUADSPI */ 442 #if defined(OCTOSPI1) || defined(OCTOSPI2) 443 #define RCC_PERIPHCLK_OSPI ((uint64_t)(0x02000000U)) 444 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ 445 #define RCC_PERIPHCLK_DSI ((uint64_t)(0x04000000U)) 446 #define RCC_PERIPHCLK_SPDIFRX ((uint64_t)(0x08000000U)) 447 #if defined(HRTIM1) 448 #define RCC_PERIPHCLK_HRTIM1 ((uint64_t)(0x10000000U)) 449 #endif /* HRTIM1 */ 450 #if defined(LTDC) 451 #define RCC_PERIPHCLK_LTDC ((uint64_t)(0x20000000U)) 452 #endif /* LTDC */ 453 #define RCC_PERIPHCLK_TIM ((uint64_t)(0x40000000U)) 454 #define RCC_PERIPHCLK_CKPER ((uint64_t)(0x80000000U)) 455 456 #define RCC_PERIPHCLK_PLL2_DIVP ((uint64_t)(0x0000000100000000U)) 457 #define RCC_PERIPHCLK_PLL2_DIVQ ((uint64_t)(0x0000000200000000U)) 458 #define RCC_PERIPHCLK_PLL2_DIVR ((uint64_t)(0x0000000400000000U)) 459 #define RCC_PERIPHCLK_PLL3_DIVP ((uint64_t)(0x0000000800000000U)) 460 #define RCC_PERIPHCLK_PLL3_DIVQ ((uint64_t)(0x0000001000000000U)) 461 #define RCC_PERIPHCLK_PLL3_DIVR ((uint64_t)(0x0000002000000000U)) 462 463 /** 464 * @} 465 */ 466 467 468 /** @defgroup RCC_PLL2_Clock_Output RCC PLL2 Clock Output 469 * @{ 470 */ 471 #define RCC_PLL2_DIVP RCC_PLLCFGR_DIVP2EN 472 #define RCC_PLL2_DIVQ RCC_PLLCFGR_DIVQ2EN 473 #define RCC_PLL2_DIVR RCC_PLLCFGR_DIVR2EN 474 475 /** 476 * @} 477 */ 478 479 /** @defgroup RCC_PLL3_Clock_Output RCC PLL3 Clock Output 480 * @{ 481 */ 482 #define RCC_PLL3_DIVP RCC_PLLCFGR_DIVP3EN 483 #define RCC_PLL3_DIVQ RCC_PLLCFGR_DIVQ3EN 484 #define RCC_PLL3_DIVR RCC_PLLCFGR_DIVR3EN 485 486 /** 487 * @} 488 */ 489 490 /** @defgroup RCC_PLL2_VCI_Range RCC PLL2 VCI Range 491 * @{ 492 */ 493 #define RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0 /*!< Clock range frequency between 1 and 2 MHz */ 494 #define RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1 /*!< Clock range frequency between 2 and 4 MHz */ 495 #define RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2 /*!< Clock range frequency between 4 and 8 MHz */ 496 #define RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3 /*!< Clock range frequency between 8 and 16 MHz */ 497 498 /** 499 * @} 500 */ 501 502 503 /** @defgroup RCC_PLL2_VCO_Range RCC PLL2 VCO Range 504 * @{ 505 */ 506 #define RCC_PLL2VCOWIDE (0x00000000U) 507 #define RCC_PLL2VCOMEDIUM RCC_PLLCFGR_PLL2VCOSEL 508 509 /** 510 * @} 511 */ 512 513 /** @defgroup RCC_PLL3_VCI_Range RCC PLL3 VCI Range 514 * @{ 515 */ 516 #define RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0 /*!< Clock range frequency between 1 and 2 MHz */ 517 #define RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1 /*!< Clock range frequency between 2 and 4 MHz */ 518 #define RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2 /*!< Clock range frequency between 4 and 8 MHz */ 519 #define RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3 /*!< Clock range frequency between 8 and 16 MHz */ 520 521 /** 522 * @} 523 */ 524 525 526 /** @defgroup RCC_PLL3_VCO_Range RCC PLL3 VCO Range 527 * @{ 528 */ 529 #define RCC_PLL3VCOWIDE (0x00000000U) 530 #define RCC_PLL3VCOMEDIUM RCC_PLLCFGR_PLL3VCOSEL 531 532 /** 533 * @} 534 */ 535 536 /** @defgroup RCCEx_USART16_Clock_Source RCCEx USART1/6 Clock Source 537 * @{ 538 */ 539 #if defined(RCC_D2CCIP2R_USART16SEL) 540 #define RCC_USART16CLKSOURCE_D2PCLK2 (0x00000000U) 541 /* alias */ 542 #define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 543 #define RCC_USART16CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16SEL_0 544 #define RCC_USART16CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16SEL_1 545 #define RCC_USART16CLKSOURCE_HSI (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1) 546 #define RCC_USART16CLKSOURCE_CSI RCC_D2CCIP2R_USART16SEL_2 547 #define RCC_USART16CLKSOURCE_LSE (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2) 548 549 #elif defined(RCC_CDCCIP2R_USART16910SEL) 550 #define RCC_USART16910CLKSOURCE_CDPCLK2 (0x00000000U) 551 /* alias */ 552 #define RCC_USART16910CLKSOURCE_D2PCLK2 RCC_USART16910CLKSOURCE_CDPCLK2 553 #define RCC_USART16910CLKSOURCE_PLL2 RCC_CDCCIP2R_USART16910SEL_0 554 #define RCC_USART16910CLKSOURCE_PLL3 RCC_CDCCIP2R_USART16910SEL_1 555 #define RCC_USART16910CLKSOURCE_HSI (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1) 556 #define RCC_USART16910CLKSOURCE_CSI RCC_CDCCIP2R_USART16910SEL_2 557 #define RCC_USART16910CLKSOURCE_LSE (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2) 558 559 /* Aliases */ 560 #define RCC_USART16CLKSOURCE_CDPCLK2 RCC_USART16910CLKSOURCE_CDPCLK2 561 #define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16CLKSOURCE_CDPCLK2 562 #define RCC_USART16CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_CDPCLK2 563 #define RCC_USART16CLKSOURCE_PLL2 RCC_USART16910CLKSOURCE_PLL2 564 #define RCC_USART16CLKSOURCE_PLL3 RCC_USART16910CLKSOURCE_PLL3 565 #define RCC_USART16CLKSOURCE_HSI RCC_USART16910CLKSOURCE_HSI 566 #define RCC_USART16CLKSOURCE_CSI RCC_USART16910CLKSOURCE_CSI 567 #define RCC_USART16CLKSOURCE_LSE RCC_USART16910CLKSOURCE_LSE 568 569 #else /* RCC_D2CCIP2R_USART16910SEL */ 570 #define RCC_USART16910CLKSOURCE_D2PCLK2 (0x00000000U) 571 #define RCC_USART16910CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16910SEL_0 572 #define RCC_USART16910CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16910SEL_1 573 #define RCC_USART16910CLKSOURCE_HSI (RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1) 574 #define RCC_USART16910CLKSOURCE_CSI RCC_D2CCIP2R_USART16910SEL_2 575 #define RCC_USART16910CLKSOURCE_LSE (RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2) 576 577 /* Aliases */ 578 #define RCC_USART16CLKSOURCE_D2PCLK2 RCC_USART16910CLKSOURCE_D2PCLK2 579 #define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16910CLKSOURCE_D2PCLK2 580 #define RCC_USART16CLKSOURCE_PLL2 RCC_USART16910CLKSOURCE_PLL2 581 #define RCC_USART16CLKSOURCE_PLL3 RCC_USART16910CLKSOURCE_PLL3 582 #define RCC_USART16CLKSOURCE_HSI RCC_USART16910CLKSOURCE_HSI 583 #define RCC_USART16CLKSOURCE_CSI RCC_USART16910CLKSOURCE_CSI 584 #define RCC_USART16CLKSOURCE_LSE RCC_USART16910CLKSOURCE_LSE 585 #endif /* RCC_D2CCIP2R_USART16SEL */ 586 /** 587 * @} 588 */ 589 590 /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source 591 * @{ 592 */ 593 #define RCC_USART1CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 594 #define RCC_USART1CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2 595 #define RCC_USART1CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3 596 #define RCC_USART1CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI 597 #define RCC_USART1CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI 598 #define RCC_USART1CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE 599 /** 600 * @} 601 */ 602 603 /** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source 604 * @{ 605 */ 606 #define RCC_USART6CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 607 #define RCC_USART6CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2 608 #define RCC_USART6CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3 609 #define RCC_USART6CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI 610 #define RCC_USART6CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI 611 #define RCC_USART6CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE 612 613 /** 614 * @} 615 */ 616 617 #if defined(UART9) 618 /** @defgroup RCCEx_UART9_Clock_Source RCCEx UART9 Clock Source 619 * @{ 620 */ 621 #define RCC_UART9CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 622 #define RCC_UART9CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2 623 #define RCC_UART9CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3 624 #define RCC_UART9CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI 625 #define RCC_UART9CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI 626 #define RCC_UART9CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE 627 /** 628 * @} 629 */ 630 #endif /* UART9 */ 631 632 #if defined(USART10) 633 /** @defgroup RCCEx_USART10_Clock_Source RCCEx USART10 Clock Source 634 * @{ 635 */ 636 #define RCC_USART10CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 637 #define RCC_USART10CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2 638 #define RCC_USART10CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3 639 #define RCC_USART10CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI 640 #define RCC_USART10CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI 641 #define RCC_USART10CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE 642 /** 643 * @} 644 */ 645 #endif /* USART10 */ 646 647 /** @defgroup RCCEx_USART234578_Clock_Source RCCEx USART2/3/4/5/7/8 Clock Source 648 * @{ 649 */ 650 #if defined(RCC_D2CCIP2R_USART28SEL) 651 #define RCC_USART234578CLKSOURCE_D2PCLK1 (0x00000000U) 652 /* alias */ 653 #define RCC_USART234578CLKSOURCE_PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 654 #define RCC_USART234578CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0 655 #define RCC_USART234578CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1 656 #define RCC_USART234578CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1) 657 #define RCC_USART234578CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2 658 #define RCC_USART234578CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2) 659 #else 660 #define RCC_USART234578CLKSOURCE_CDPCLK1 (0x00000000U) 661 /* alias */ 662 #define RCC_USART234578CLKSOURCE_PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1 663 #define RCC_USART234578CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1 664 #define RCC_USART234578CLKSOURCE_PLL2 RCC_CDCCIP2R_USART234578SEL_0 665 #define RCC_USART234578CLKSOURCE_PLL3 RCC_CDCCIP2R_USART234578SEL_1 666 #define RCC_USART234578CLKSOURCE_HSI (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1) 667 #define RCC_USART234578CLKSOURCE_CSI RCC_CDCCIP2R_USART234578SEL_2 668 #define RCC_USART234578CLKSOURCE_LSE (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2) 669 #endif /* RCC_D2CCIP2R_USART28SEL */ 670 /** 671 * @} 672 */ 673 674 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source 675 * @{ 676 */ 677 #define RCC_USART2CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 678 #define RCC_USART2CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 679 #define RCC_USART2CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 680 #define RCC_USART2CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 681 #define RCC_USART2CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 682 #define RCC_USART2CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 683 684 /** 685 * @} 686 */ 687 688 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source 689 * @{ 690 */ 691 #define RCC_USART3CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 692 #define RCC_USART3CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 693 #define RCC_USART3CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 694 #define RCC_USART3CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 695 #define RCC_USART3CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 696 #define RCC_USART3CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 697 698 /** 699 * @} 700 */ 701 702 /** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source 703 * @{ 704 */ 705 #define RCC_UART4CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 706 #define RCC_UART4CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 707 #define RCC_UART4CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 708 #define RCC_UART4CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 709 #define RCC_UART4CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 710 #define RCC_UART4CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 711 712 /** 713 * @} 714 */ 715 716 /** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source 717 * @{ 718 */ 719 #define RCC_UART5CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 720 #define RCC_UART5CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 721 #define RCC_UART5CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 722 #define RCC_UART5CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 723 #define RCC_UART5CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 724 #define RCC_UART5CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 725 726 /** 727 * @} 728 */ 729 730 /** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source 731 * @{ 732 */ 733 #define RCC_UART7CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 734 #define RCC_UART7CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 735 #define RCC_UART7CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 736 #define RCC_UART7CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 737 #define RCC_UART7CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 738 #define RCC_UART7CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 739 740 /** 741 * @} 742 */ 743 744 /** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source 745 * @{ 746 */ 747 #define RCC_UART8CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 748 #define RCC_UART8CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 749 #define RCC_UART8CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 750 #define RCC_UART8CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 751 #define RCC_UART8CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 752 #define RCC_UART8CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 753 754 /** 755 * @} 756 */ 757 758 /** @defgroup RCCEx_LPUART1_Clock_Source RCCEx LPUART1 Clock Source 759 * @{ 760 */ 761 #if defined(RCC_D3CCIPR_LPUART1SEL) 762 #define RCC_LPUART1CLKSOURCE_D3PCLK1 (0x00000000U) 763 /* alias */ 764 #define RCC_LPUART1CLKSOURCE_PCLK4 RCC_LPUART1CLKSOURCE_D3PCLK1 765 #define RCC_LPUART1CLKSOURCE_PLL2 RCC_D3CCIPR_LPUART1SEL_0 766 #define RCC_LPUART1CLKSOURCE_PLL3 RCC_D3CCIPR_LPUART1SEL_1 767 #define RCC_LPUART1CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1) 768 #define RCC_LPUART1CLKSOURCE_CSI RCC_D3CCIPR_LPUART1SEL_2 769 #define RCC_LPUART1CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0) 770 #else 771 #define RCC_LPUART1CLKSOURCE_SRDPCLK4 (0x00000000U) 772 /* alias*/ 773 #define RCC_LPUART1CLKSOURCE_PCLK4 RCC_LPUART1CLKSOURCE_SRDPCLK4 774 #define RCC_LPUART1CLKSOURCE_D3PCLK1 RCC_LPUART1CLKSOURCE_SRDPCLK4 775 #define RCC_LPUART1CLKSOURCE_PLL2 RCC_SRDCCIPR_LPUART1SEL_0 776 #define RCC_LPUART1CLKSOURCE_PLL3 RCC_SRDCCIPR_LPUART1SEL_1 777 #define RCC_LPUART1CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1) 778 #define RCC_LPUART1CLKSOURCE_CSI RCC_SRDCCIPR_LPUART1SEL_2 779 #define RCC_LPUART1CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_2 | RCC_SRDCCIPR_LPUART1SEL_0) 780 #endif /* RCC_D3CCIPR_LPUART1SEL */ 781 /** 782 * @} 783 */ 784 785 /** @defgroup RCCEx_I2C1235_Clock_Source RCCEx I2C1/2/3/5 Clock Source 786 * @{ 787 */ 788 #if defined (RCC_D2CCIP2R_I2C123SEL) 789 #define RCC_I2C123CLKSOURCE_D2PCLK1 (0x00000000U) 790 #define RCC_I2C123CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0 791 #define RCC_I2C123CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1 792 #define RCC_I2C123CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1) 793 /* aliases */ 794 #define RCC_I2C1235CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 795 #define RCC_I2C1235CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 796 #define RCC_I2C1235CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI 797 #define RCC_I2C1235CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI 798 #elif defined(RCC_CDCCIP2R_I2C123SEL) 799 #define RCC_I2C123CLKSOURCE_CDPCLK1 (0x00000000U) 800 /* alias */ 801 #define RCC_I2C123CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_CDPCLK1 802 #define RCC_I2C123CLKSOURCE_PLL3 RCC_CDCCIP2R_I2C123SEL_0 803 #define RCC_I2C123CLKSOURCE_HSI RCC_CDCCIP2R_I2C123SEL_1 804 #define RCC_I2C123CLKSOURCE_CSI (RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1) 805 /* aliases */ 806 #define RCC_I2C1235CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 807 #define RCC_I2C1235CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 808 #define RCC_I2C1235CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI 809 #define RCC_I2C1235CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI 810 #elif defined(I2C5) 811 #define RCC_I2C1235CLKSOURCE_D2PCLK1 (0x00000000U) 812 #define RCC_I2C1235CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C1235SEL_0 813 #define RCC_I2C1235CLKSOURCE_HSI RCC_D2CCIP2R_I2C1235SEL_1 814 #define RCC_I2C1235CLKSOURCE_CSI (RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1) 815 /* aliases */ 816 #define RCC_I2C123CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1 817 #define RCC_I2C123CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3 818 #define RCC_I2C123CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI 819 #define RCC_I2C123CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI 820 #endif /* RCC_D2CCIP2R_I2C123SEL */ 821 /** 822 * @} 823 */ 824 825 /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source 826 * @{ 827 */ 828 #if defined(I2C5) 829 #define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1 830 #define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3 831 #define RCC_I2C1CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI 832 #define RCC_I2C1CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI 833 #else 834 #define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 835 #define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 836 #define RCC_I2C1CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI 837 #define RCC_I2C1CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI 838 #endif /*I2C5*/ 839 840 /** 841 * @} 842 */ 843 844 /** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source 845 * @{ 846 */ 847 #if defined(I2C5) 848 #define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1 849 #define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3 850 #define RCC_I2C2CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI 851 #define RCC_I2C2CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI 852 #else 853 #define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 854 #define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 855 #define RCC_I2C2CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI 856 #define RCC_I2C2CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI 857 #endif /*I2C5*/ 858 859 /** 860 * @} 861 */ 862 863 /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source 864 * @{ 865 */ 866 #if defined(I2C5) 867 #define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1 868 #define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3 869 #define RCC_I2C3CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI 870 #define RCC_I2C3CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI 871 #else 872 #define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 873 #define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 874 #define RCC_I2C3CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI 875 #define RCC_I2C3CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI 876 #endif /*I2C5*/ 877 878 /** 879 * @} 880 */ 881 882 /** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source 883 * @{ 884 */ 885 #if defined(RCC_D3CCIPR_I2C4SEL) 886 #define RCC_I2C4CLKSOURCE_D3PCLK1 (0x00000000U) 887 #define RCC_I2C4CLKSOURCE_PLL3 RCC_D3CCIPR_I2C4SEL_0 888 #define RCC_I2C4CLKSOURCE_HSI RCC_D3CCIPR_I2C4SEL_1 889 #define RCC_I2C4CLKSOURCE_CSI (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1) 890 #else 891 #define RCC_I2C4CLKSOURCE_SRDPCLK4 (0x00000000U) 892 /* alias */ 893 #define RCC_I2C4CLKSOURCE_D3PCLK1 RCC_I2C4CLKSOURCE_SRDPCLK4 894 #define RCC_I2C4CLKSOURCE_PLL3 RCC_SRDCCIPR_I2C4SEL_0 895 #define RCC_I2C4CLKSOURCE_HSI RCC_SRDCCIPR_I2C4SEL_1 896 #define RCC_I2C4CLKSOURCE_CSI (RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1) 897 #endif /* RCC_D3CCIPR_I2C4SEL */ 898 899 /** 900 * @} 901 */ 902 #if defined(I2C5) 903 /** @defgroup RCCEx_I2C5_Clock_Source RCCEx I2C5 Clock Source 904 * @{ 905 */ 906 #define RCC_I2C5CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1 907 #define RCC_I2C5CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3 908 #define RCC_I2C5CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI 909 #define RCC_I2C5CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI 910 911 /** 912 * @} 913 */ 914 #endif /*I2C5*/ 915 916 /** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source 917 * @{ 918 */ 919 #if defined(RCC_D2CCIP2R_RNGSEL) 920 #define RCC_RNGCLKSOURCE_HSI48 (0x00000000U) 921 #define RCC_RNGCLKSOURCE_PLL RCC_D2CCIP2R_RNGSEL_0 922 #define RCC_RNGCLKSOURCE_LSE RCC_D2CCIP2R_RNGSEL_1 923 #define RCC_RNGCLKSOURCE_LSI RCC_D2CCIP2R_RNGSEL 924 #else 925 #define RCC_RNGCLKSOURCE_HSI48 (0x00000000U) 926 #define RCC_RNGCLKSOURCE_PLL RCC_CDCCIP2R_RNGSEL_0 927 #define RCC_RNGCLKSOURCE_LSE RCC_CDCCIP2R_RNGSEL_1 928 #define RCC_RNGCLKSOURCE_LSI RCC_CDCCIP2R_RNGSEL 929 #endif /* RCC_D2CCIP2R_RNGSEL */ 930 931 /** 932 * @} 933 */ 934 #if defined(HRTIM1) 935 936 /** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source 937 * @{ 938 */ 939 #define RCC_HRTIM1CLK_TIMCLK (0x00000000U) 940 #define RCC_HRTIM1CLK_CPUCLK RCC_CFGR_HRTIMSEL 941 942 /** 943 * @} 944 */ 945 #endif /*HRTIM1*/ 946 947 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source 948 * @{ 949 */ 950 #if defined(RCC_D2CCIP2R_USBSEL) 951 #define RCC_USBCLKSOURCE_PLL RCC_D2CCIP2R_USBSEL_0 952 #define RCC_USBCLKSOURCE_PLL3 RCC_D2CCIP2R_USBSEL_1 953 #define RCC_USBCLKSOURCE_HSI48 RCC_D2CCIP2R_USBSEL 954 #else 955 #define RCC_USBCLKSOURCE_PLL RCC_CDCCIP2R_USBSEL_0 956 #define RCC_USBCLKSOURCE_PLL3 RCC_CDCCIP2R_USBSEL_1 957 #define RCC_USBCLKSOURCE_HSI48 RCC_CDCCIP2R_USBSEL 958 #endif /* RCC_D2CCIP2R_USBSEL */ 959 960 /** 961 * @} 962 */ 963 964 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 965 * @{ 966 */ 967 #if defined(RCC_D2CCIP1R_SAI1SEL) 968 #define RCC_SAI1CLKSOURCE_PLL (0x00000000U) 969 #define RCC_SAI1CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI1SEL_0 970 #define RCC_SAI1CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI1SEL_1 971 #define RCC_SAI1CLKSOURCE_PIN (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1) 972 #define RCC_SAI1CLKSOURCE_CLKP RCC_D2CCIP1R_SAI1SEL_2 973 #else 974 #define RCC_SAI1CLKSOURCE_PLL (0x00000000U) 975 #define RCC_SAI1CLKSOURCE_PLL2 RCC_CDCCIP1R_SAI1SEL_0 976 #define RCC_SAI1CLKSOURCE_PLL3 RCC_CDCCIP1R_SAI1SEL_1 977 #define RCC_SAI1CLKSOURCE_PIN (RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1) 978 #define RCC_SAI1CLKSOURCE_CLKP RCC_CDCCIP1R_SAI1SEL_2 979 #endif /* RCC_D2CCIP1R_SAI1SEL */ 980 /** 981 * @} 982 */ 983 984 #if defined(SAI3) 985 /** @defgroup RCCEx_SAI23_Clock_Source SAI2/3 Clock Source 986 * @{ 987 */ 988 #define RCC_SAI23CLKSOURCE_PLL (0x00000000U) 989 #define RCC_SAI23CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI23SEL_0 990 #define RCC_SAI23CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI23SEL_1 991 #define RCC_SAI23CLKSOURCE_PIN (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1) 992 #define RCC_SAI23CLKSOURCE_CLKP RCC_D2CCIP1R_SAI23SEL_2 993 /** 994 * @} 995 */ 996 997 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source 998 * @{ 999 */ 1000 #define RCC_SAI2CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL 1001 #define RCC_SAI2CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2 1002 #define RCC_SAI2CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3 1003 #define RCC_SAI2CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN 1004 #define RCC_SAI2CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP 1005 1006 /** 1007 * @} 1008 */ 1009 1010 /** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source 1011 * @{ 1012 */ 1013 #define RCC_SAI3CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL 1014 #define RCC_SAI3CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2 1015 #define RCC_SAI3CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3 1016 #define RCC_SAI3CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN 1017 #define RCC_SAI3CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP 1018 /** 1019 * @} 1020 */ 1021 #endif /* SAI3 */ 1022 1023 #if defined(RCC_CDCCIP1R_SAI2ASEL) 1024 /** @defgroup RCCEx_SAI2A_Clock_Source SAI2A Clock Source 1025 * @{ 1026 */ 1027 #define RCC_SAI2ACLKSOURCE_PLL (0x00000000U) 1028 #define RCC_SAI2ACLKSOURCE_PLL2 RCC_CDCCIP1R_SAI2ASEL_0 1029 #define RCC_SAI2ACLKSOURCE_PLL3 RCC_CDCCIP1R_SAI2ASEL_1 1030 #define RCC_SAI2ACLKSOURCE_PIN (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1) 1031 #define RCC_SAI2ACLKSOURCE_CLKP RCC_CDCCIP1R_SAI2ASEL_2 1032 #define RCC_SAI2ACLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2) 1033 /** 1034 * @} 1035 */ 1036 #endif /* RCC_CDCCIP1R_SAI2ASEL */ 1037 1038 #if defined(RCC_CDCCIP1R_SAI2BSEL) 1039 /** @defgroup RCCEx_SAI2B_Clock_Source SAI2B Clock Source 1040 * @{ 1041 */ 1042 #define RCC_SAI2BCLKSOURCE_PLL (0x00000000U) 1043 #define RCC_SAI2BCLKSOURCE_PLL2 RCC_CDCCIP1R_SAI2BSEL_0 1044 #define RCC_SAI2BCLKSOURCE_PLL3 RCC_CDCCIP1R_SAI2BSEL_1 1045 #define RCC_SAI2BCLKSOURCE_PIN (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1) 1046 #define RCC_SAI2BCLKSOURCE_CLKP RCC_CDCCIP1R_SAI2BSEL_2 1047 #define RCC_SAI2BCLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2) 1048 /** 1049 * @} 1050 */ 1051 #endif /* RCC_CDCCIP1R_SAI2BSEL */ 1052 1053 1054 /** @defgroup RCCEx_SPI123_Clock_Source SPI1/2/3 Clock Source 1055 * @{ 1056 */ 1057 #if defined(RCC_D2CCIP1R_SPI123SEL) 1058 #define RCC_SPI123CLKSOURCE_PLL (0x00000000U) 1059 #define RCC_SPI123CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL_0 1060 #define RCC_SPI123CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1 1061 #define RCC_SPI123CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1) 1062 #define RCC_SPI123CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2 1063 #else 1064 #define RCC_SPI123CLKSOURCE_PLL (0x00000000U) 1065 #define RCC_SPI123CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI123SEL_0 1066 #define RCC_SPI123CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI123SEL_1 1067 #define RCC_SPI123CLKSOURCE_PIN (RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1) 1068 #define RCC_SPI123CLKSOURCE_CLKP RCC_CDCCIP1R_SPI123SEL_2 1069 #endif /* RCC_D2CCIP1R_SPI123SEL */ 1070 /** 1071 * @} 1072 */ 1073 1074 /** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source 1075 * @{ 1076 */ 1077 #define RCC_SPI1CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL 1078 #define RCC_SPI1CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2 1079 #define RCC_SPI1CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3 1080 #define RCC_SPI1CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN 1081 #define RCC_SPI1CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP 1082 1083 /** 1084 * @} 1085 */ 1086 1087 /** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source 1088 * @{ 1089 */ 1090 #define RCC_SPI2CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL 1091 #define RCC_SPI2CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2 1092 #define RCC_SPI2CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3 1093 #define RCC_SPI2CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN 1094 #define RCC_SPI2CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP 1095 1096 /** 1097 * @} 1098 */ 1099 1100 /** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source 1101 * @{ 1102 */ 1103 #define RCC_SPI3CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL 1104 #define RCC_SPI3CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2 1105 #define RCC_SPI3CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3 1106 #define RCC_SPI3CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN 1107 #define RCC_SPI3CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP 1108 1109 /** 1110 * @} 1111 */ 1112 1113 /** @defgroup RCCEx_SPI45_Clock_Source SPI4/5 Clock Source 1114 * @{ 1115 */ 1116 #if defined(RCC_D2CCIP1R_SPI45SEL) 1117 #define RCC_SPI45CLKSOURCE_D2PCLK2 (0x00000000U) 1118 #define RCC_SPI45CLKSOURCE_PCLK2 RCC_SPI45CLKSOURCE_D2PCLK2 1119 #define RCC_SPI45CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI45SEL_0 1120 #define RCC_SPI45CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI45SEL_1 1121 #define RCC_SPI45CLKSOURCE_HSI (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1) 1122 #define RCC_SPI45CLKSOURCE_CSI RCC_D2CCIP1R_SPI45SEL_2 1123 #define RCC_SPI45CLKSOURCE_HSE (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2) 1124 #else 1125 #define RCC_SPI45CLKSOURCE_CDPCLK2 (0x00000000U) 1126 /* aliases */ 1127 #define RCC_SPI45CLKSOURCE_D2PCLK2 RCC_SPI45CLKSOURCE_CDPCLK2 /* D2PCLK2 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */ 1128 #define RCC_SPI45CLKSOURCE_PCLK2 RCC_SPI45CLKSOURCE_CDPCLK2 1129 #define RCC_SPI45CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI45SEL_0 1130 #define RCC_SPI45CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI45SEL_1 1131 #define RCC_SPI45CLKSOURCE_HSI (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1) 1132 #define RCC_SPI45CLKSOURCE_CSI RCC_CDCCIP1R_SPI45SEL_2 1133 #define RCC_SPI45CLKSOURCE_HSE (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2) 1134 #endif /* RCC_D2CCIP1R_SPI45SEL */ 1135 /** 1136 * @} 1137 */ 1138 1139 /** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source 1140 * @{ 1141 */ 1142 #define RCC_SPI4CLKSOURCE_D2PCLK2 RCC_SPI45CLKSOURCE_D2PCLK2 1143 #define RCC_SPI4CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2 1144 #define RCC_SPI4CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3 1145 #define RCC_SPI4CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI 1146 #define RCC_SPI4CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI 1147 #define RCC_SPI4CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE 1148 1149 /** 1150 * @} 1151 */ 1152 1153 /** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source 1154 * @{ 1155 */ 1156 #define RCC_SPI5CLKSOURCE_D2PCLK2 RCC_SPI45CLKSOURCE_D2PCLK2 1157 #define RCC_SPI5CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2 1158 #define RCC_SPI5CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3 1159 #define RCC_SPI5CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI 1160 #define RCC_SPI5CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI 1161 #define RCC_SPI5CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE 1162 1163 /** 1164 * @} 1165 */ 1166 1167 /** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source 1168 * @{ 1169 */ 1170 #if defined(RCC_D3CCIPR_SPI6SEL) 1171 #define RCC_SPI6CLKSOURCE_D3PCLK1 (0x00000000U) 1172 #define RCC_SPI6CLKSOURCE_PCLK4 RCC_SPI6CLKSOURCE_D3PCLK1 1173 #define RCC_SPI6CLKSOURCE_PLL2 RCC_D3CCIPR_SPI6SEL_0 1174 #define RCC_SPI6CLKSOURCE_PLL3 RCC_D3CCIPR_SPI6SEL_1 1175 #define RCC_SPI6CLKSOURCE_HSI (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1) 1176 #define RCC_SPI6CLKSOURCE_CSI RCC_D3CCIPR_SPI6SEL_2 1177 #define RCC_SPI6CLKSOURCE_HSE (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2) 1178 #else 1179 #define RCC_SPI6CLKSOURCE_SRDPCLK4 (0x00000000U) 1180 /* alias */ 1181 #define RCC_SPI6CLKSOURCE_D3PCLK1 RCC_SPI6CLKSOURCE_SRDPCLK4 /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */ 1182 #define RCC_SPI6CLKSOURCE_PCLK4 RCC_SPI6CLKSOURCE_SRDPCLK4 1183 #define RCC_SPI6CLKSOURCE_PLL2 RCC_SRDCCIPR_SPI6SEL_0 1184 #define RCC_SPI6CLKSOURCE_PLL3 RCC_SRDCCIPR_SPI6SEL_1 1185 #define RCC_SPI6CLKSOURCE_HSI (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1) 1186 #define RCC_SPI6CLKSOURCE_CSI RCC_SRDCCIPR_SPI6SEL_2 1187 #define RCC_SPI6CLKSOURCE_HSE (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2) 1188 #define RCC_SPI6CLKSOURCE_PIN (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2) 1189 #endif /* RCC_D3CCIPR_SPI6SEL */ 1190 1191 /** 1192 * @} 1193 */ 1194 1195 1196 #if defined(SAI4_Block_A) 1197 /** @defgroup RCCEx_SAI4A_Clock_Source SAI4A Clock Source 1198 * @{ 1199 */ 1200 #define RCC_SAI4ACLKSOURCE_PLL (0x00000000U) 1201 #define RCC_SAI4ACLKSOURCE_PLL2 RCC_D3CCIPR_SAI4ASEL_0 1202 #define RCC_SAI4ACLKSOURCE_PLL3 RCC_D3CCIPR_SAI4ASEL_1 1203 #define RCC_SAI4ACLKSOURCE_PIN (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1) 1204 #define RCC_SAI4ACLKSOURCE_CLKP RCC_D3CCIPR_SAI4ASEL_2 1205 #if defined(RCC_VER_3_0) 1206 #define RCC_SAI4ACLKSOURCE_SPDIF (RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0) 1207 #endif /*RCC_VER_3_0*/ 1208 1209 /** 1210 * @} 1211 */ 1212 #endif /* SAI4_Block_A */ 1213 1214 1215 1216 #if defined(SAI4_Block_B) 1217 /** @defgroup RCCEx_SAI4B_Clock_Source SAI4B Clock Source 1218 * @{ 1219 */ 1220 #define RCC_SAI4BCLKSOURCE_PLL (0x00000000U) 1221 #define RCC_SAI4BCLKSOURCE_PLL2 RCC_D3CCIPR_SAI4BSEL_0 1222 #define RCC_SAI4BCLKSOURCE_PLL3 RCC_D3CCIPR_SAI4BSEL_1 1223 #define RCC_SAI4BCLKSOURCE_PIN (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1) 1224 #define RCC_SAI4BCLKSOURCE_CLKP RCC_D3CCIPR_SAI4BSEL_2 1225 #if defined(RCC_VER_3_0) 1226 #define RCC_SAI4BCLKSOURCE_SPDIF (RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0) 1227 #endif /* RCC_VER_3_0 */ 1228 1229 /** 1230 * @} 1231 */ 1232 #endif /* SAI4_Block_B */ 1233 1234 1235 /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source 1236 * @{ 1237 */ 1238 #if defined(RCC_D2CCIP2R_LPTIM1SEL) 1239 #define RCC_LPTIM1CLKSOURCE_D2PCLK1 (0x00000000U) 1240 /* alias */ 1241 #define RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CLKSOURCE_D2PCLK1 1242 #define RCC_LPTIM1CLKSOURCE_PLL2 RCC_D2CCIP2R_LPTIM1SEL_0 1243 #define RCC_LPTIM1CLKSOURCE_PLL3 RCC_D2CCIP2R_LPTIM1SEL_1 1244 #define RCC_LPTIM1CLKSOURCE_LSE (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1) 1245 #define RCC_LPTIM1CLKSOURCE_LSI RCC_D2CCIP2R_LPTIM1SEL_2 1246 #define RCC_LPTIM1CLKSOURCE_CLKP (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2) 1247 #else 1248 #define RCC_LPTIM1CLKSOURCE_CDPCLK1 (0x00000000U) 1249 /* alias */ 1250 #define RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1 1251 #define RCC_LPTIM1CLKSOURCE_D2PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1 1252 #define RCC_LPTIM1CLKSOURCE_PLL2 RCC_CDCCIP2R_LPTIM1SEL_0 1253 #define RCC_LPTIM1CLKSOURCE_PLL3 RCC_CDCCIP2R_LPTIM1SEL_1 1254 #define RCC_LPTIM1CLKSOURCE_LSE (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1) 1255 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CDCCIP2R_LPTIM1SEL_2 1256 #define RCC_LPTIM1CLKSOURCE_CLKP (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2) 1257 #endif /* RCC_D2CCIP2R_LPTIM1SEL */ 1258 1259 /** 1260 * @} 1261 */ 1262 1263 /** @defgroup RCCEx_LPTIM2_Clock_Source RCCEx LPTIM2 Clock Source 1264 * @{ 1265 */ 1266 #if defined(RCC_D3CCIPR_LPTIM2SEL) 1267 #define RCC_LPTIM2CLKSOURCE_D3PCLK1 (0x00000000U) 1268 /* alias */ 1269 #define RCC_LPTIM2CLKSOURCE_PCLK4 RCC_LPTIM2CLKSOURCE_D3PCLK1 1270 #define RCC_LPTIM2CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM2SEL_0 1271 #define RCC_LPTIM2CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM2SEL_1 1272 #define RCC_LPTIM2CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1) 1273 #define RCC_LPTIM2CLKSOURCE_LSI RCC_D3CCIPR_LPTIM2SEL_2 1274 #define RCC_LPTIM2CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2) 1275 #else 1276 #define RCC_LPTIM2CLKSOURCE_SRDPCLK4 (0x00000000U) 1277 /*alias*/ 1278 #define RCC_LPTIM2CLKSOURCE_PCLK4 RCC_LPTIM2CLKSOURCE_SRDPCLK4 1279 #define RCC_LPTIM2CLKSOURCE_D3PCLK1 RCC_LPTIM2CLKSOURCE_SRDPCLK4 1280 #define RCC_LPTIM2CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM2SEL_0 1281 #define RCC_LPTIM2CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM2SEL_1 1282 #define RCC_LPTIM2CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1) 1283 #define RCC_LPTIM2CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM2SEL_2 1284 #define RCC_LPTIM2CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2) 1285 #endif /* RCC_D3CCIPR_LPTIM2SEL */ 1286 /** 1287 * @} 1288 */ 1289 1290 /** @defgroup RCCEx_LPTIM345_Clock_Source RCCEx LPTIM3/4/5 Clock Source 1291 * @{ 1292 */ 1293 #if defined(RCC_D3CCIPR_LPTIM345SEL) 1294 #define RCC_LPTIM345CLKSOURCE_D3PCLK1 (0x00000000U) 1295 /* alias*/ 1296 #define RCC_LPTIM345CLKSOURCE_PCLK4 RCC_LPTIM345CLKSOURCE_D3PCLK1 1297 #define RCC_LPTIM345CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0 1298 #define RCC_LPTIM345CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1 1299 #define RCC_LPTIM345CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1) 1300 #define RCC_LPTIM345CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2 1301 #define RCC_LPTIM345CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2) 1302 #else 1303 #define RCC_LPTIM345CLKSOURCE_SRDPCLK4 (0x00000000U) 1304 /* alias */ 1305 #define RCC_LPTIM345CLKSOURCE_PCLK4 RCC_LPTIM345CLKSOURCE_SRDPCLK4 1306 #define RCC_LPTIM345CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_SRDPCLK4 1307 #define RCC_LPTIM345CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM3SEL_0 1308 #define RCC_LPTIM345CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM3SEL_1 1309 #define RCC_LPTIM345CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1) 1310 #define RCC_LPTIM345CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM3SEL_2 1311 #define RCC_LPTIM345CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2) 1312 #endif /* RCC_D3CCIPR_LPTIM345SEL */ 1313 /** 1314 * @} 1315 */ 1316 1317 /** @defgroup RCCEx_LPTIM3_Clock_Source RCCEx LPTIM3 Clock Source 1318 * @{ 1319 */ 1320 #define RCC_LPTIM3CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1 1321 #define RCC_LPTIM3CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2 1322 #define RCC_LPTIM3CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3 1323 #define RCC_LPTIM3CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE 1324 #define RCC_LPTIM3CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI 1325 #define RCC_LPTIM3CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP 1326 1327 /** 1328 * @} 1329 */ 1330 #if defined(LPTIM4) 1331 /** @defgroup RCCEx_LPTIM4_Clock_Source RCCEx LPTIM4 Clock Source 1332 * @{ 1333 */ 1334 #define RCC_LPTIM4CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1 1335 #define RCC_LPTIM4CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2 1336 #define RCC_LPTIM4CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3 1337 #define RCC_LPTIM4CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE 1338 #define RCC_LPTIM4CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI 1339 #define RCC_LPTIM4CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP 1340 /** 1341 * @} 1342 */ 1343 #endif /* LPTIM4 */ 1344 1345 #if defined(LPTIM5) 1346 /** @defgroup RCCEx_LPTIM5_Clock_Source RCCEx LPTIM5 Clock Source 1347 * @{ 1348 */ 1349 #define RCC_LPTIM5CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1 1350 #define RCC_LPTIM5CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2 1351 #define RCC_LPTIM5CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3 1352 #define RCC_LPTIM5CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE 1353 #define RCC_LPTIM5CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI 1354 #define RCC_LPTIM5CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP 1355 1356 /** 1357 * @} 1358 */ 1359 #endif /* LPTIM5 */ 1360 1361 #if defined(QUADSPI) 1362 /** @defgroup RCCEx_QSPI_Clock_Source RCCEx QSPI Clock Source 1363 * @{ 1364 */ 1365 #define RCC_QSPICLKSOURCE_D1HCLK (0x00000000U) 1366 #define RCC_QSPICLKSOURCE_PLL RCC_D1CCIPR_QSPISEL_0 1367 #define RCC_QSPICLKSOURCE_PLL2 RCC_D1CCIPR_QSPISEL_1 1368 #define RCC_QSPICLKSOURCE_CLKP RCC_D1CCIPR_QSPISEL 1369 1370 /** 1371 * @} 1372 */ 1373 #endif /* QUADSPI */ 1374 1375 1376 #if defined(OCTOSPI1) || defined(OCTOSPI2) 1377 /** @defgroup RCCEx_OSPI_Clock_Source RCCEx OSPI Clock Source 1378 * @{ 1379 */ 1380 1381 #if defined(RCC_CDCCIPR_OCTOSPISEL) 1382 #define RCC_OSPICLKSOURCE_CDHCLK (0x00000000U) 1383 /*aliases*/ 1384 #define RCC_OSPICLKSOURCE_D1HCLK RCC_OSPICLKSOURCE_CDHCLK 1385 #define RCC_OSPICLKSOURCE_HCLK RCC_OSPICLKSOURCE_CDHCLK 1386 #define RCC_OSPICLKSOURCE_PLL RCC_CDCCIPR_OCTOSPISEL_0 1387 #define RCC_OSPICLKSOURCE_PLL2 RCC_CDCCIPR_OCTOSPISEL_1 1388 #define RCC_OSPICLKSOURCE_CLKP RCC_CDCCIPR_OCTOSPISEL 1389 #else 1390 #define RCC_OSPICLKSOURCE_D1HCLK (0x00000000U) 1391 #define RCC_OSPICLKSOURCE_HCLK RCC_OSPICLKSOURCE_D1HCLK 1392 #define RCC_OSPICLKSOURCE_PLL RCC_D1CCIPR_OCTOSPISEL_0 1393 #define RCC_OSPICLKSOURCE_PLL2 RCC_D1CCIPR_OCTOSPISEL_1 1394 #define RCC_OSPICLKSOURCE_CLKP RCC_D1CCIPR_OCTOSPISEL 1395 #endif /* RCC_CDCCIPR_OCTOSPISEL */ 1396 1397 1398 /** 1399 * @} 1400 */ 1401 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ 1402 1403 #if defined(DSI) 1404 /** @defgroup RCCEx_DSI_Clock_Source RCCEx DSI Clock Source 1405 * @{ 1406 */ 1407 #define RCC_DSICLKSOURCE_PHY (0x00000000U) 1408 #define RCC_DSICLKSOURCE_PLL2 RCC_D1CCIPR_DSISEL 1409 1410 /** 1411 * @} 1412 */ 1413 #endif /* DSI */ 1414 1415 /** @defgroup RCCEx_FMC_Clock_Source RCCEx FMC Clock Source 1416 * @{ 1417 */ 1418 #if defined(RCC_D1CCIPR_FMCSEL) 1419 #define RCC_FMCCLKSOURCE_D1HCLK (0x00000000U) 1420 #define RCC_FMCCLKSOURCE_HCLK RCC_FMCCLKSOURCE_D1HCLK 1421 #define RCC_FMCCLKSOURCE_PLL RCC_D1CCIPR_FMCSEL_0 1422 #define RCC_FMCCLKSOURCE_PLL2 RCC_D1CCIPR_FMCSEL_1 1423 #define RCC_FMCCLKSOURCE_CLKP RCC_D1CCIPR_FMCSEL 1424 #else 1425 #define RCC_FMCCLKSOURCE_CDHCLK (0x00000000U) 1426 #define RCC_FMCCLKSOURCE_HCLK RCC_FMCCLKSOURCE_CDHCLK 1427 /*alias*/ 1428 #define RCC_FMCCLKSOURCE_D1HCLK RCC_FMCCLKSOURCE_CDHCLK 1429 #define RCC_FMCCLKSOURCE_PLL RCC_CDCCIPR_FMCSEL_0 1430 #define RCC_FMCCLKSOURCE_PLL2 RCC_CDCCIPR_FMCSEL_1 1431 #define RCC_FMCCLKSOURCE_CLKP RCC_CDCCIPR_FMCSEL 1432 #endif /* RCC_D1CCIPR_FMCSEL */ 1433 /** 1434 * @} 1435 */ 1436 1437 #if defined(FDCAN1) || defined(FDCAN2) 1438 /** @defgroup RCCEx_FDCAN_Clock_Source RCCEx FDCAN Clock Source 1439 * @{ 1440 */ 1441 #if defined(RCC_D2CCIP1R_FDCANSEL) 1442 #define RCC_FDCANCLKSOURCE_HSE (0x00000000U) 1443 #define RCC_FDCANCLKSOURCE_PLL RCC_D2CCIP1R_FDCANSEL_0 1444 #define RCC_FDCANCLKSOURCE_PLL2 RCC_D2CCIP1R_FDCANSEL_1 1445 #else 1446 #define RCC_FDCANCLKSOURCE_HSE (0x00000000U) 1447 #define RCC_FDCANCLKSOURCE_PLL RCC_CDCCIP1R_FDCANSEL_0 1448 #define RCC_FDCANCLKSOURCE_PLL2 RCC_CDCCIP1R_FDCANSEL_1 1449 #endif /* D3_SRAM_BASE */ 1450 /** 1451 * @} 1452 */ 1453 #endif /*FDCAN1 || FDCAN2*/ 1454 1455 1456 /** @defgroup RCCEx_SDMMC_Clock_Source RCCEx SDMMC Clock Source 1457 * @{ 1458 */ 1459 #if defined(RCC_D1CCIPR_SDMMCSEL) 1460 #define RCC_SDMMCCLKSOURCE_PLL (0x00000000U) 1461 #define RCC_SDMMCCLKSOURCE_PLL2 RCC_D1CCIPR_SDMMCSEL 1462 #else 1463 #define RCC_SDMMCCLKSOURCE_PLL (0x00000000U) 1464 #define RCC_SDMMCCLKSOURCE_PLL2 RCC_CDCCIPR_SDMMCSEL 1465 #endif /* RCC_D1CCIPR_SDMMCSEL */ 1466 /** 1467 * @} 1468 */ 1469 1470 1471 /** @defgroup RCCEx_ADC_Clock_Source RCCEx ADC Clock Source 1472 * @{ 1473 */ 1474 #if defined(RCC_D3CCIPR_ADCSEL_0) 1475 #define RCC_ADCCLKSOURCE_PLL2 (0x00000000U) 1476 #define RCC_ADCCLKSOURCE_PLL3 RCC_D3CCIPR_ADCSEL_0 1477 #define RCC_ADCCLKSOURCE_CLKP RCC_D3CCIPR_ADCSEL_1 1478 #else 1479 #define RCC_ADCCLKSOURCE_PLL2 (0x00000000U) 1480 #define RCC_ADCCLKSOURCE_PLL3 RCC_SRDCCIPR_ADCSEL_0 1481 #define RCC_ADCCLKSOURCE_CLKP RCC_SRDCCIPR_ADCSEL_1 1482 #endif /* RCC_D3CCIPR_ADCSEL_0 */ 1483 /** 1484 * @} 1485 */ 1486 1487 /** @defgroup RCCEx_SWPMI1_Clock_Source RCCEx SWPMI1 Clock Source 1488 * @{ 1489 */ 1490 #if defined(RCC_D2CCIP1R_SWPSEL) 1491 #define RCC_SWPMI1CLKSOURCE_D2PCLK1 (0x00000000U) 1492 #define RCC_SWPMI1CLKSOURCE_HSI RCC_D2CCIP1R_SWPSEL 1493 #else 1494 #define RCC_SWPMI1CLKSOURCE_CDPCLK1 (0x00000000U) 1495 /* alias */ 1496 #define RCC_SWPMI1CLKSOURCE_D2PCLK1 RCC_SWPMI1CLKSOURCE_CDPCLK1 1497 #define RCC_SWPMI1CLKSOURCE_HSI RCC_CDCCIP1R_SWPSEL 1498 #endif /* RCC_D2CCIP1R_SWPSEL */ 1499 /** 1500 * @} 1501 */ 1502 1503 /** @defgroup RCCEx_DFSDM1_Clock_Source RCCEx DFSDM1 Clock Source 1504 * @{ 1505 */ 1506 #if defined(RCC_D2CCIP1R_DFSDM1SEL) 1507 #define RCC_DFSDM1CLKSOURCE_D2PCLK1 (0x00000000U) 1508 #define RCC_DFSDM1CLKSOURCE_SYS RCC_D2CCIP1R_DFSDM1SEL 1509 #else 1510 #define RCC_DFSDM1CLKSOURCE_CDPCLK1 (0x00000000U) 1511 /* alias */ 1512 #define RCC_DFSDM1CLKSOURCE_D2PCLK1 RCC_DFSDM1CLKSOURCE_CDPCLK1 1513 #define RCC_DFSDM1CLKSOURCE_SYS RCC_CDCCIP1R_DFSDM1SEL 1514 #endif /* RCC_D2CCIP1R_DFSDM1SEL */ 1515 /** 1516 * @} 1517 */ 1518 1519 #if defined(DFSDM2_BASE) 1520 /** @defgroup RCCEx_DFSDM2_Clock_Source RCCEx DFSDM2 Clock Source 1521 * @{ 1522 */ 1523 #define RCC_DFSDM2CLKSOURCE_SRDPCLK4 (0x00000000U) 1524 /* alias */ 1525 #define RCC_DFSDM2CLKSOURCE_SRDPCLK1 RCC_DFSDM2CLKSOURCE_SRDPCLK4 1526 #define RCC_DFSDM2CLKSOURCE_SYS RCC_SRDCCIPR_DFSDM2SEL 1527 /** 1528 * @} 1529 */ 1530 #endif /* DFSDM2 */ 1531 1532 /** @defgroup RCCEx_SPDIFRX_Clock_Source RCCEx SPDIFRX Clock Source 1533 * @{ 1534 */ 1535 #if defined(RCC_D2CCIP1R_SPDIFSEL_0) 1536 #define RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U) 1537 #define RCC_SPDIFRXCLKSOURCE_PLL2 RCC_D2CCIP1R_SPDIFSEL_0 1538 #define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_D2CCIP1R_SPDIFSEL_1 1539 #define RCC_SPDIFRXCLKSOURCE_HSI RCC_D2CCIP1R_SPDIFSEL 1540 #else 1541 #define RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U) 1542 #define RCC_SPDIFRXCLKSOURCE_PLL2 RCC_CDCCIP1R_SPDIFSEL_0 1543 #define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_CDCCIP1R_SPDIFSEL_1 1544 #define RCC_SPDIFRXCLKSOURCE_HSI RCC_CDCCIP1R_SPDIFSEL 1545 #endif /* RCC_D2CCIP1R_SPDIFSEL_0 */ 1546 /** 1547 * @} 1548 */ 1549 1550 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source 1551 * @{ 1552 */ 1553 #if defined(RCC_D2CCIP2R_CECSEL_0) 1554 #define RCC_CECCLKSOURCE_LSE (0x00000000U) 1555 #define RCC_CECCLKSOURCE_LSI RCC_D2CCIP2R_CECSEL_0 1556 #define RCC_CECCLKSOURCE_CSI RCC_D2CCIP2R_CECSEL_1 1557 #else 1558 #define RCC_CECCLKSOURCE_LSE (0x00000000U) 1559 #define RCC_CECCLKSOURCE_LSI RCC_CDCCIP2R_CECSEL_0 1560 #define RCC_CECCLKSOURCE_CSI RCC_CDCCIP2R_CECSEL_1 1561 #endif /* RCC_D2CCIP2R_CECSEL_0 */ 1562 /** 1563 * @} 1564 */ 1565 1566 1567 /** @defgroup RCCEx_CLKP_Clock_Source RCCEx CLKP Clock Source 1568 * @{ 1569 */ 1570 #if defined(RCC_D1CCIPR_CKPERSEL_0) 1571 #define RCC_CLKPSOURCE_HSI (0x00000000U) 1572 #define RCC_CLKPSOURCE_CSI RCC_D1CCIPR_CKPERSEL_0 1573 #define RCC_CLKPSOURCE_HSE RCC_D1CCIPR_CKPERSEL_1 1574 #else 1575 #define RCC_CLKPSOURCE_HSI (0x00000000U) 1576 #define RCC_CLKPSOURCE_CSI RCC_CDCCIPR_CKPERSEL_0 1577 #define RCC_CLKPSOURCE_HSE RCC_CDCCIPR_CKPERSEL_1 1578 #endif /* RCC_D1CCIPR_CKPERSEL_0 */ 1579 /** 1580 * @} 1581 */ 1582 1583 /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection 1584 * @{ 1585 */ 1586 #define RCC_TIMPRES_DESACTIVATED (0x00000000U) 1587 #define RCC_TIMPRES_ACTIVATED RCC_CFGR_TIMPRE 1588 1589 /** 1590 * @} 1591 */ 1592 1593 #if defined(DUAL_CORE) 1594 1595 /** @defgroup RCCEx_RCC_BootCx RCCEx RCC BootCx 1596 * @{ 1597 */ 1598 #define RCC_BOOT_C1 RCC_GCR_BOOT_C1 1599 #define RCC_BOOT_C2 RCC_GCR_BOOT_C2 1600 1601 /** 1602 * @} 1603 */ 1604 #endif /*DUAL_CORE*/ 1605 1606 #if defined(DUAL_CORE) 1607 /** @defgroup RCCEx_RCC_WWDGx RCCEx RCC WWDGx 1608 * @{ 1609 */ 1610 #define RCC_WWDG1 RCC_GCR_WW1RSC 1611 #define RCC_WWDG2 RCC_GCR_WW2RSC 1612 1613 /** 1614 * @} 1615 */ 1616 1617 #else 1618 1619 /** @defgroup RCCEx_RCC_WWDGx RCCEx RCC WWDGx 1620 * @{ 1621 */ 1622 #define RCC_WWDG1 RCC_GCR_WW1RSC 1623 1624 /** 1625 * @} 1626 */ 1627 1628 #endif /*DUAL_CORE*/ 1629 1630 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line 1631 * @{ 1632 */ 1633 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18 /*!< External interrupt line 18 connected to the LSE CSS EXTI Line */ 1634 /** 1635 * @} 1636 */ 1637 1638 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 1639 * @{ 1640 */ 1641 #define RCC_CRS_NONE (0x00000000U) 1642 #define RCC_CRS_TIMEOUT (0x00000001U) 1643 #define RCC_CRS_SYNCOK (0x00000002U) 1644 #define RCC_CRS_SYNCWARN (0x00000004U) 1645 #define RCC_CRS_SYNCERR (0x00000008U) 1646 #define RCC_CRS_SYNCMISS (0x00000010U) 1647 #define RCC_CRS_TRIMOVF (0x00000020U) 1648 /** 1649 * @} 1650 */ 1651 1652 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 1653 * @{ 1654 */ 1655 #define RCC_CRS_SYNC_SOURCE_PIN (0x00000000U) /*!< Synchro Signal source external pin, Available on STM32H7 Rev.B and above devices only */ 1656 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 1657 #define RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB1 SOF (default) */ 1658 #define RCC_CRS_SYNC_SOURCE_USB2 (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0) /*!< Synchro Signal source USB2 SOF */ 1659 1660 1661 /** 1662 * @} 1663 */ 1664 1665 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 1666 * @{ 1667 */ 1668 #define RCC_CRS_SYNC_DIV1 (0x00000000U) /*!< Synchro Signal not divided (default) */ 1669 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 1670 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 1671 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 1672 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 1673 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 1674 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 1675 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 1676 /** 1677 * @} 1678 */ 1679 1680 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 1681 * @{ 1682 */ 1683 #define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /*!< Synchro Active on rising edge (default) */ 1684 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 1685 /** 1686 * @} 1687 */ 1688 1689 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 1690 * @{ 1691 */ 1692 #define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds 1693 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ 1694 /** 1695 * @} 1696 */ 1697 1698 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 1699 * @{ 1700 */ 1701 #define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /*!< Default Frequency error limit */ 1702 /** 1703 * @} 1704 */ 1705 1706 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 1707 * @{ 1708 */ 1709 #define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. 1710 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value 1711 corresponds to a higher output frequency */ 1712 /** 1713 * @} 1714 */ 1715 1716 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 1717 * @{ 1718 */ 1719 #define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ 1720 #define RCC_CRS_FREQERRORDIR_DOWN (CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ 1721 /** 1722 * @} 1723 */ 1724 1725 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 1726 * @{ 1727 */ 1728 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 1729 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 1730 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 1731 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 1732 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 1733 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 1734 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 1735 1736 /** 1737 * @} 1738 */ 1739 1740 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 1741 * @{ 1742 */ 1743 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 1744 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 1745 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 1746 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 1747 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 1748 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 1749 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 1750 1751 /** 1752 * @} 1753 */ 1754 1755 /** 1756 * @} 1757 */ 1758 1759 1760 1761 /* Exported macro ------------------------------------------------------------*/ 1762 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 1763 * @{ 1764 */ 1765 1766 /** @brief Macros to enable or disable PLL2. 1767 * @note After enabling PLL2, the application software should wait on 1768 * PLL2RDY flag to be set indicating that PLL2 clock is stable and can 1769 * be used as kernel clock source. 1770 * @note PLL2 is disabled by hardware when entering STOP and STANDBY modes. 1771 */ 1772 #define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON) 1773 #define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) 1774 1775 /** 1776 * @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK) 1777 * @note Enabling/disabling those Clocks can be done only when the PLL2 is disabled, 1778 * This is mainly used to save Power. 1779 * @param __RCC_PLL2ClockOut__ Specifies the PLL2 clock to be outputted 1780 * This parameter can be one of the following values: 1781 * @arg RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 1782 * @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 1783 * @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 1784 * 1785 * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. 1786 * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. 1787 * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. 1788 * 1789 * @retval None 1790 */ 1791 #define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) 1792 1793 #define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) 1794 1795 /** 1796 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO 1797 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL2 1798 * @retval None 1799 */ 1800 #define __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) 1801 1802 #define __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) 1803 1804 /** 1805 * @brief Macro to configures the PLL2 multiplication and division factors. 1806 * @note This function must be used only when PLL2 is disabled. 1807 * 1808 * @param __PLL2M__ specifies the division factor for PLL2 VCO input clock 1809 * This parameter must be a number between 1 and 63. 1810 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 1811 * frequency ranges from 1 to 16 MHz. 1812 * 1813 * @param __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock 1814 * This parameter must be a number between 4 and 512 or between 8 and 420(*). 1815 * @note You have to set the PLL2N parameter correctly to ensure that the VCO 1816 * output frequency is between 150 and 420 MHz (when in medium VCO range) or 1817 * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) 1818 * 1819 * @param __PLL2P__ specifies the division factor for peripheral kernel clocks 1820 * This parameter must be a number between 1 and 128. 1821 * 1822 * @param __PLL2Q__ specifies the division factor for peripheral kernel clocks 1823 * This parameter must be a number between 1 and 128. 1824 * 1825 * @param __PLL2R__ specifies the division factor for peripheral kernel clocks 1826 * This parameter must be a number between 1 and 128. 1827 * 1828 * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) 1829 * is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible 1830 * value to __PLL2P__, __PLL2Q__ or __PLL2R__ parameters. 1831 * @retval None 1832 * 1833 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 1834 */ 1835 1836 #define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \ 1837 do{ \ 1838 MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U)); \ 1839 WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \ 1840 ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \ 1841 } while(0) 1842 1843 /** 1844 * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor 1845 * 1846 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO 1847 * 1848 * @param __RCC_PLL2FRACN__ Specifies Fractional Part Of The Multiplication factor for PLL2 VCO 1849 * It should be a value between 0 and 8191 1850 * @note Warning: the software has to set correctly these bits to insure that the VCO 1851 * output frequency is between its valid frequency range, which is: 1852 * 192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0 1853 * 150 to 420 MHz if PLL2VCOSEL = 1. 1854 * 1855 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 1856 * 1857 * @retval None 1858 */ 1859 #define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) \ 1860 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos)) 1861 1862 /** @brief Macro to select the PLL2 reference frequency range. 1863 * @param __RCC_PLL2VCIRange__ specifies the PLL2 input frequency range 1864 * This parameter can be one of the following values: 1865 * @arg RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz 1866 * @arg RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz 1867 * @arg RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz 1868 * @arg RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz 1869 * @retval None 1870 */ 1871 #define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \ 1872 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__)) 1873 1874 1875 /** @brief Macro to select the PLL2 reference frequency range. 1876 * @param __RCC_PLL2VCORange__ Specifies the PLL2 input frequency range 1877 * This parameter can be one of the following values: 1878 * @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) 1879 * @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz 1880 * 1881 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 1882 * 1883 * @retval None 1884 */ 1885 #define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \ 1886 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__)) 1887 1888 /** @brief Macros to enable or disable the main PLL3. 1889 * @note After enabling PLL3, the application software should wait on 1890 * PLL3RDY flag to be set indicating that PLL3 clock is stable and can 1891 * be used as kernel clock source. 1892 * @note PLL3 is disabled by hardware when entering STOP and STANDBY modes. 1893 */ 1894 #define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) 1895 #define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) 1896 1897 /** 1898 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO 1899 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL3 1900 * @retval None 1901 */ 1902 #define __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) 1903 1904 #define __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) 1905 1906 /** 1907 * @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK) 1908 * @note Enabling/disabling those Clocks can be done only when the PLL3 is disabled, 1909 * This is mainly used to save Power. 1910 * @param __RCC_PLL3ClockOut__ specifies the PLL3 clock to be outputted 1911 * This parameter can be one of the following values: 1912 * @arg RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 1913 * @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 1914 * @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 1915 * 1916 * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. 1917 * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. 1918 * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. 1919 * 1920 * @retval None 1921 */ 1922 #define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) 1923 1924 #define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) 1925 1926 /** 1927 * @brief Macro to configures the PLL3 multiplication and division factors. 1928 * @note This function must be used only when PLL3 is disabled. 1929 * 1930 * @param __PLL3M__ specifies the division factor for PLL3 VCO input clock 1931 * This parameter must be a number between 1 and 63. 1932 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 1933 * frequency ranges from 1 to 16 MHz. 1934 * 1935 * @param __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock 1936 * This parameter must be a number between 4 and 512. 1937 * @note You have to set the PLL3N parameter correctly to ensure that the VCO 1938 * output frequency is between 150 and 420 MHz (when in medium VCO range) or 1939 * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) 1940 * 1941 * @param __PLL3P__ specifies the division factor for peripheral kernel clocks 1942 * This parameter must be a number between 2 and 128 (where odd numbers not allowed) 1943 * 1944 * @param __PLL3Q__ specifies the division factor for peripheral kernel clocks 1945 * This parameter must be a number between 1 and 128 1946 * 1947 * @param __PLL3R__ specifies the division factor for peripheral kernel clocks 1948 * This parameter must be a number between 1 and 128 1949 * 1950 * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) 1951 * is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible 1952 * value to __PLL3P__, __PLL3Q__ or __PLL3R__ parameters. 1953 * @retval None 1954 * 1955 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 1956 */ 1957 1958 #define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \ 1959 do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U)); \ 1960 WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \ 1961 ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \ 1962 } while(0) 1963 1964 1965 1966 /** 1967 * @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor 1968 * 1969 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO 1970 * 1971 * @param __RCC_PLL3FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO 1972 * It should be a value between 0 and 8191 1973 * @note Warning: the software has to set correctly these bits to insure that the VCO 1974 * output frequency is between its valid frequency range, which is: 1975 * 192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0 1976 * 150 to 420 MHz if PLL3VCOSEL = 1. 1977 * 1978 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 1979 * 1980 * @retval None 1981 */ 1982 #define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos) 1983 1984 /** @brief Macro to select the PLL3 reference frequency range. 1985 * @param __RCC_PLL3VCIRange__ specifies the PLL1 input frequency range 1986 * This parameter can be one of the following values: 1987 * @arg RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz 1988 * @arg RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz 1989 * @arg RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz 1990 * @arg RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz 1991 * @retval None 1992 */ 1993 #define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \ 1994 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__)) 1995 1996 1997 /** @brief Macro to select the PLL3 reference frequency range. 1998 * @param __RCC_PLL3VCORange__ specifies the PLL1 input frequency range 1999 * This parameter can be one of the following values: 2000 * @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) 2001 * @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz 2002 * 2003 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 2004 * 2005 * @retval None 2006 */ 2007 #define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \ 2008 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__)) 2009 /** 2010 * @brief Macro to Configure the SAI1 clock source. 2011 * @param __RCC_SAI1CLKSource__ defines the SAI1 clock source. This clock is derived 2012 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 2013 * This parameter can be one of the following values: 2014 * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL 2015 * @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2 2016 * @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3 2017 * @arg RCC_SAI1CLKSOURCE_OSC: SAI1 clock = OSC 2018 * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock 2019 * @retval None 2020 */ 2021 #if defined(RCC_D2CCIP1R_SAI1SEL) 2022 #define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\ 2023 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) 2024 #else 2025 #define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\ 2026 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) 2027 #endif /* RCC_D2CCIP1R_SAI1SEL */ 2028 2029 /** @brief Macro to get the SAI1 clock source. 2030 * @retval The clock source can be one of the following values: 2031 * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL 2032 * @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2 2033 * @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3 2034 * @arg RCC_SAI1CLKSOURCE_CLKP: SAI1 clock = CLKP 2035 * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock 2036 */ 2037 #if defined(RCC_D2CCIP1R_SAI1SEL) 2038 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL))) 2039 #else 2040 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL))) 2041 #endif /* RCC_D2CCIP1R_SAI1SEL */ 2042 2043 /** 2044 * @brief Macro to Configure the SPDIFRX clock source. 2045 * @param __RCC_SPDIFCLKSource__ defines the SPDIFRX clock source. This clock is derived 2046 * from system PLL, PLL2, PLL3, or internal OSC clock 2047 * This parameter can be one of the following values: 2048 * @arg RCC_SPDIFRXCLKSOURCE_PLL: SPDIFRX clock = PLL 2049 * @arg RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2 2050 * @arg RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3 2051 * @arg RCC_SPDIFRXCLKSOURCE_HSI: SPDIFRX clock = HSI 2052 * @retval None 2053 */ 2054 #if defined(RCC_D2CCIP1R_SPDIFSEL) 2055 #define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\ 2056 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) 2057 #else 2058 #define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\ 2059 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) 2060 #endif /* RCC_D2CCIP1R_SPDIFSEL */ 2061 2062 /** 2063 * @brief Macro to get the SPDIFRX clock source. 2064 * @retval None 2065 */ 2066 #if defined(RCC_D2CCIP1R_SPDIFSEL) 2067 #define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL))) 2068 #else 2069 #define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL))) 2070 #endif /* RCC_D2CCIP1R_SPDIFSEL */ 2071 2072 #if defined(SAI3) 2073 /** 2074 * @brief Macro to Configure the SAI2/3 clock source. 2075 * @param __RCC_SAI23CLKSource__ defines the SAI2/3 clock source. This clock is derived 2076 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 2077 * This parameter can be one of the following values: 2078 * @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL 2079 * @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2 2080 * @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3 2081 * @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP 2082 * @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock 2083 * @retval None 2084 */ 2085 #define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\ 2086 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__)) 2087 2088 /** @brief Macro to get the SAI2/3 clock source. 2089 * @retval The clock source can be one of the following values: 2090 * @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL 2091 * @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2 2092 * @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3 2093 * @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP 2094 * @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock 2095 */ 2096 #define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL))) 2097 2098 /** 2099 * @brief Macro to Configure the SAI2 clock source. 2100 * @param __RCC_SAI2CLKSource__ defines the SAI2 clock source. This clock is derived 2101 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 2102 * This parameter can be one of the following values: 2103 * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL 2104 * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2 2105 * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3 2106 * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP 2107 * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock 2108 * @retval None 2109 */ 2110 #define __HAL_RCC_SAI2_CONFIG __HAL_RCC_SAI23_CONFIG 2111 2112 /** @brief Macro to get the SAI2 clock source. 2113 * @retval The clock source can be one of the following values: 2114 * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL 2115 * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2 2116 * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3 2117 * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP 2118 * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock 2119 */ 2120 #define __HAL_RCC_GET_SAI2_SOURCE __HAL_RCC_GET_SAI23_SOURCE 2121 2122 /** 2123 * @brief Macro to Configure the SAI3 clock source. 2124 * @param __RCC_SAI3CLKSource__ defines the SAI3 clock source. This clock is derived 2125 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 2126 * This parameter can be one of the following values: 2127 * @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL 2128 * @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2 2129 * @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3 2130 * @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP 2131 * @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock 2132 * @retval None 2133 */ 2134 #define __HAL_RCC_SAI3_CONFIG __HAL_RCC_SAI23_CONFIG 2135 2136 /** @brief Macro to get the SAI3 clock source. 2137 * @retval The clock source can be one of the following values: 2138 * @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL 2139 * @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2 2140 * @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3 2141 * @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP 2142 * @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock 2143 */ 2144 #define __HAL_RCC_GET_SAI3_SOURCE __HAL_RCC_GET_SAI23_SOURCE 2145 #endif /* SAI3 */ 2146 2147 #if defined(RCC_CDCCIP1R_SAI2ASEL) 2148 /** 2149 * @brief Macro to Configure the SAI2A clock source. 2150 * @param __RCC_SAI2ACLKSource__ defines the SAI2A clock source. This clock is derived 2151 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 2152 * This parameter can be one of the following values: 2153 * @arg RCC_SAI2ACLKSOURCE_PLL: SAI2A clock = PLL 2154 * @arg RCC_SAI2ACLKSOURCE_PLL2: SAI2A clock = PLL2 2155 * @arg RCC_SAI2ACLKSOURCE_PLL3: SAI2A clock = PLL3 2156 * @arg RCC_SAI2ACLKSOURCE_CLKP: SAI2A clock = CLKP 2157 * @arg RCC_SAI2ACLKSOURCE_PIN: SAI2A clock = External Clock 2158 * @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock 2159 * @retval None 2160 */ 2161 #define __HAL_RCC_SAI2A_CONFIG(__RCC_SAI2ACLKSource__ )\ 2162 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__)) 2163 2164 /** @brief Macro to get the SAI2A clock source. 2165 * @retval The clock source can be one of the following values: 2166 * @arg RCC_SAI2CLKSOURCE_PLL: SAI2A clock = PLL 2167 * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2A clock = PLL2 2168 * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2A clock = PLL3 2169 * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2A clock = CLKP 2170 * @arg RCC_SAI2CLKSOURCE_PIN: SAI2A clock = External Clock 2171 * @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock 2172 */ 2173 #define __HAL_RCC_GET_SAI2A_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL))) 2174 #endif /* defined(RCC_CDCCIP1R_SAI2ASEL) */ 2175 2176 #if defined(RCC_CDCCIP1R_SAI2BSEL) 2177 /** 2178 * @brief Macro to Configure the SAI2B clock source. 2179 * @param __RCC_SAI2BCLKSource__ defines the SAI2B clock source. This clock is derived 2180 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 2181 * This parameter can be one of the following values: 2182 * @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL 2183 * @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2 2184 * @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3 2185 * @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock = CLKP 2186 * @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock 2187 * @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock 2188 * @retval None 2189 */ 2190 #define __HAL_RCC_SAI2B_CONFIG(__RCC_SAI2BCLKSource__ )\ 2191 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__)) 2192 2193 /** @brief Macro to get the SAI2B clock source. 2194 * @retval The clock source can be one of the following values: 2195 * @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL 2196 * @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2 2197 * @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3 2198 * @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock = CLKP 2199 * @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock 2200 * @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock 2201 */ 2202 #define __HAL_RCC_GET_SAI2B_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL))) 2203 #endif /* defined(RCC_CDCCIP1R_SAI2BSEL) */ 2204 2205 2206 #if defined(SAI4_Block_A) 2207 /** 2208 * @brief Macro to Configure the SAI4A clock source. 2209 * @param __RCC_SAI4ACLKSource__ defines the SAI4A clock source. This clock is derived 2210 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 2211 * This parameter can be one of the following values: 2212 * @arg RCC_SAI4ACLKSOURCE_PLL: SAI4A clock = PLL 2213 * @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4A clock = PLL2 2214 * @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4A clock = PLL3 2215 * @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4A clock = CLKP 2216 * @arg RCC_SAI4ACLKSOURCE_PIN: SAI4A clock = External Clock 2217 * @retval None 2218 */ 2219 #define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\ 2220 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__)) 2221 2222 /** @brief Macro to get the SAI4A clock source. 2223 * @retval The clock source can be one of the following values: 2224 * @arg RCC_SAI4ACLKSOURCE_PLL: SAI4B clock = PLL 2225 * @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4B clock = PLL2 2226 * @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4B clock = PLL3 2227 * @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4B clock = CLKP 2228 * @arg RCC_SAI4ACLKSOURCE_PIN: SAI4B clock = External Clock 2229 */ 2230 #define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL))) 2231 #endif /* SAI4_Block_A */ 2232 2233 #if defined(SAI4_Block_B) 2234 /** 2235 * @brief Macro to Configure the SAI4B clock source. 2236 * @param __RCC_SAI4BCLKSource__ defines the SAI4B clock source. This clock is derived 2237 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 2238 * This parameter can be one of the following values: 2239 * @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL 2240 * @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2 2241 * @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3 2242 * @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP 2243 * @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock 2244 * @retval None 2245 */ 2246 #define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\ 2247 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__)) 2248 2249 /** @brief Macro to get the SAI4B clock source. 2250 * @retval The clock source can be one of the following values: 2251 * @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL 2252 * @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2 2253 * @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3 2254 * @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP 2255 * @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock 2256 */ 2257 #define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL))) 2258 #endif /* SAI4_Block_B */ 2259 2260 /** @brief macro to configure the I2C1/2/3/5* clock (I2C123CLK). 2261 * 2262 * @param __I2C1235CLKSource__ specifies the I2C1/2/3/5* clock source. 2263 * This parameter can be one of the following values: 2264 * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock 2265 * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock 2266 * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock 2267 * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock 2268 * 2269 * (**): Available on stm32h72xxx and stm32h73xxx family lines. 2270 */ 2271 #if defined(RCC_D2CCIP2R_I2C123SEL) 2272 #define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \ 2273 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__)) 2274 #elif defined(RCC_CDCCIP2R_I2C123SEL) 2275 #define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \ 2276 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__)) 2277 #else /* RCC_D2CCIP2R_I2C1235SEL */ 2278 #define __HAL_RCC_I2C1235_CONFIG(__I2C1235CLKSource__) \ 2279 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__)) 2280 /* alias */ 2281 #define __HAL_RCC_I2C123_CONFIG __HAL_RCC_I2C1235_CONFIG 2282 #endif /* RCC_D2CCIP2R_I2C123SEL */ 2283 2284 /** @brief macro to get the I2C1/2/3/5* clock source. 2285 * @retval The clock source can be one of the following values: 2286 * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock 2287 * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock 2288 * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock 2289 * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock 2290 * 2291 * (**): Available on stm32h72xxx and stm32h73xxx family lines. 2292 */ 2293 #if defined(RCC_D2CCIP2R_I2C123SEL) 2294 #define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL))) 2295 #elif defined(RCC_CDCCIP2R_I2C123SEL) 2296 #define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL))) 2297 #else /* RCC_D2CCIP2R_I2C1235SEL */ 2298 #define __HAL_RCC_GET_I2C1235_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL))) 2299 /* alias */ 2300 #define __HAL_RCC_GET_I2C123_SOURCE __HAL_RCC_GET_I2C1235_SOURCE 2301 #endif /* RCC_D2CCIP2R_I2C123SEL */ 2302 2303 /** @brief macro to configure the I2C1 clock (I2C1CLK). 2304 * 2305 * @param __I2C1CLKSource__ specifies the I2C1 clock source. 2306 * This parameter can be one of the following values: 2307 * @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock 2308 * @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock 2309 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock 2310 * @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock 2311 */ 2312 #if defined(I2C5) 2313 #define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C1235_CONFIG 2314 #else 2315 #define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C123_CONFIG 2316 #endif /*I2C5*/ 2317 2318 /** @brief macro to get the I2C1 clock source. 2319 * @retval The clock source can be one of the following values: 2320 * @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock 2321 * @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock 2322 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock 2323 * @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock 2324 */ 2325 #if defined(I2C5) 2326 #define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C1235_SOURCE 2327 #else 2328 #define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE 2329 #endif /*I2C5*/ 2330 2331 /** @brief macro to configure the I2C2 clock (I2C2CLK). 2332 * 2333 * @param __I2C2CLKSource__ specifies the I2C2 clock source. 2334 * This parameter can be one of the following values: 2335 * @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock 2336 * @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock 2337 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock 2338 * @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock 2339 */ 2340 #if defined(I2C5) 2341 #define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C1235_CONFIG 2342 #else 2343 #define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG 2344 #endif /*I2C5*/ 2345 2346 /** @brief macro to get the I2C2 clock source. 2347 * @retval The clock source can be one of the following values: 2348 * @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock 2349 * @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock 2350 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock 2351 * @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock 2352 */ 2353 #if defined(I2C5) 2354 #define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C1235_SOURCE 2355 #else 2356 #define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE 2357 #endif /*I2C5*/ 2358 2359 /** @brief macro to configure the I2C3 clock (I2C3CLK). 2360 * 2361 * @param __I2C3CLKSource__ specifies the I2C3 clock source. 2362 * This parameter can be one of the following values: 2363 * @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock 2364 * @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock 2365 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock 2366 * @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock 2367 */ 2368 #if defined(I2C5) 2369 #define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C1235_CONFIG 2370 #else 2371 #define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG 2372 #endif /*I2C5*/ 2373 2374 /** @brief macro to get the I2C3 clock source. 2375 * @retval The clock source can be one of the following values: 2376 * @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock 2377 * @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock 2378 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock 2379 * @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock 2380 */ 2381 #if defined(I2C5) 2382 #define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C1235_SOURCE 2383 #else 2384 #define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE 2385 #endif /*I2C5*/ 2386 2387 /** @brief macro to configure the I2C4 clock (I2C4CLK). 2388 * 2389 * @param __I2C4CLKSource__ specifies the I2C4 clock source. 2390 * This parameter can be one of the following values: 2391 * @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock 2392 * @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock 2393 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock 2394 * @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock 2395 */ 2396 #if defined(RCC_D3CCIPR_I2C4SEL) 2397 #define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \ 2398 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) 2399 #else 2400 #define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \ 2401 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) 2402 #endif /* RCC_D3CCIPR_I2C4SEL */ 2403 2404 /** @brief macro to get the I2C4 clock source. 2405 * @retval The clock source can be one of the following values: 2406 * @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock 2407 * @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock 2408 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock 2409 * @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock 2410 */ 2411 #if defined(RCC_D3CCIPR_I2C4SEL) 2412 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL))) 2413 #else 2414 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL))) 2415 #endif /* RCC_D3CCIPR_I2C4SEL */ 2416 2417 #if defined(I2C5) 2418 /** @brief macro to configure the I2C5 clock (I2C5CLK). 2419 * 2420 * @param __I2C5CLKSource__ specifies the I2C5 clock source. 2421 * This parameter can be one of the following values: 2422 * @arg RCC_I2C5CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C5 clock 2423 * @arg RCC_I2C5CLKSOURCE_PLL3: PLL3 selected as I2C5 clock 2424 * @arg RCC_I2C5CLKSOURCE_HSI: HSI selected as I2C5 clock 2425 * @arg RCC_I2C5CLKSOURCE_CSI: CSI selected as I2C5 clock 2426 */ 2427 #define __HAL_RCC_I2C5_CONFIG __HAL_RCC_I2C1235_CONFIG 2428 #endif /* I2C5 */ 2429 2430 #if defined(I2C5) 2431 /** @brief macro to get the I2C5 clock source. 2432 * @retval The clock source can be one of the following values: 2433 * @arg RCC_I2C5CLKSOURCE_D2PCLK1: D2PCLK5 selected as I2C5 clock 2434 * @arg RCC_I2C5CLKSOURCE_PLL3: PLL3 selected as I2C5 clock 2435 * @arg RCC_I2C5CLKSOURCE_HSI: HSI selected as I2C5 clock 2436 * @arg RCC_I2C5CLKSOURCE_CSI: CSI selected as I2C5 clock 2437 */ 2438 #define __HAL_RCC_GET_I2C5_SOURCE __HAL_RCC_GET_I2C1235_SOURCE 2439 #endif /* I2C5 */ 2440 2441 /** @brief macro to configure the USART1/6/9* /10* clock (USART16CLK). 2442 * 2443 * @param __USART16910CLKSource__ specifies the USART1/6/9* /10* clock source. 2444 * This parameter can be one of the following values: 2445 * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock 2446 * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock 2447 * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock 2448 * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock 2449 * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock 2450 * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock 2451 * 2452 * (*) : Available on some STM32H7 lines only. 2453 */ 2454 #if defined(RCC_D2CCIP2R_USART16SEL) 2455 #define __HAL_RCC_USART16_CONFIG(__USART16910CLKSource__) \ 2456 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16910CLKSource__)) 2457 #elif defined(RCC_CDCCIP2R_USART16910SEL) 2458 #define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \ 2459 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__)) 2460 /* alias */ 2461 #define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG 2462 #else /* RCC_D2CCIP2R_USART16910SEL */ 2463 #define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \ 2464 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__)) 2465 /* alias */ 2466 #define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG 2467 #endif /* RCC_D2CCIP2R_USART16SEL */ 2468 2469 /** @brief macro to get the USART1/6/9* /10* clock source. 2470 * @retval The clock source can be one of the following values: 2471 * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock 2472 * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock 2473 * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock 2474 * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock 2475 * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock 2476 * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock 2477 * 2478 * (*) : Available on some STM32H7 lines only. 2479 */ 2480 #if defined(RCC_D2CCIP2R_USART16SEL) 2481 #define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL))) 2482 #elif defined(RCC_CDCCIP2R_USART16910SEL) 2483 #define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL))) 2484 /* alias*/ 2485 #define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE 2486 #else /* RCC_D2CCIP2R_USART16910SEL */ 2487 #define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL))) 2488 /* alias */ 2489 #define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE 2490 #endif /* RCC_D2CCIP2R_USART16SEL */ 2491 2492 /** @brief macro to configure the USART234578 clock (USART234578CLK). 2493 * 2494 * @param __USART234578CLKSource__ specifies the USART2/3/4/5/7/8 clock source. 2495 * This parameter can be one of the following values: 2496 * @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock 2497 * @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock 2498 * @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock 2499 * @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock 2500 * @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock 2501 * @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock 2502 */ 2503 #if defined(RCC_D2CCIP2R_USART28SEL) 2504 #define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \ 2505 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__)) 2506 #else 2507 #define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \ 2508 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__)) 2509 #endif /* RCC_D2CCIP2R_USART28SEL */ 2510 2511 /** @brief macro to get the USART2/3/4/5/7/8 clock source. 2512 * @retval The clock source can be one of the following values: 2513 * @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock 2514 * @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock 2515 * @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock 2516 * @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock 2517 * @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock 2518 * @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock 2519 */ 2520 #if defined(RCC_D2CCIP2R_USART28SEL) 2521 #define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) 2522 #else 2523 #define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL))) 2524 #endif /* RCC_D2CCIP2R_USART28SEL */ 2525 2526 /** @brief macro to configure the USART1 clock (USART1CLK). 2527 * 2528 * @param __USART1CLKSource__ specifies the USART1 clock source. 2529 * This parameter can be one of the following values: 2530 * @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock 2531 * @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock 2532 * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock 2533 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock 2534 * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock 2535 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock 2536 */ 2537 #define __HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG 2538 2539 /** @brief macro to get the USART1 clock source. 2540 * @retval The clock source can be one of the following values: 2541 * @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock 2542 * @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock 2543 * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock 2544 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock 2545 * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock 2546 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock 2547 */ 2548 #define __HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE 2549 2550 /** @brief macro to configure the USART2 clock (USART2CLK). 2551 * 2552 * @param __USART2CLKSource__ specifies the USART2 clock source. 2553 * This parameter can be one of the following values: 2554 * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock 2555 * @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock 2556 * @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock 2557 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock 2558 * @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock 2559 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock 2560 */ 2561 #define __HAL_RCC_USART2_CONFIG __HAL_RCC_USART234578_CONFIG 2562 2563 /** @brief macro to get the USART2 clock source. 2564 * @retval The clock source can be one of the following values: 2565 * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock 2566 * @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock 2567 * @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock 2568 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock 2569 * @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock 2570 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock 2571 */ 2572 #define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE 2573 2574 /** @brief macro to configure the USART3 clock (USART3CLK). 2575 * 2576 * @param __USART3CLKSource__ specifies the USART3 clock source. 2577 * This parameter can be one of the following values: 2578 * @arg RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock 2579 * @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock 2580 * @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock 2581 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock 2582 * @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock 2583 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock 2584 */ 2585 #define __HAL_RCC_USART3_CONFIG __HAL_RCC_USART234578_CONFIG 2586 2587 /** @brief macro to get the USART3 clock source. 2588 * @retval The clock source can be one of the following values: 2589 * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock 2590 * @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock 2591 * @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock 2592 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock 2593 * @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock 2594 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock 2595 */ 2596 #define __HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE 2597 2598 /** @brief macro to configure the UART4 clock (UART4CLK). 2599 * 2600 * @param __UART4CLKSource__ specifies the UART4 clock source. 2601 * This parameter can be one of the following values: 2602 * @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock 2603 * @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock 2604 * @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock 2605 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock 2606 * @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock 2607 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock 2608 */ 2609 #define __HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG 2610 2611 /** @brief macro to get the UART4 clock source. 2612 * @retval The clock source can be one of the following values: 2613 * @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock 2614 * @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock 2615 * @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock 2616 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock 2617 * @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock 2618 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock 2619 */ 2620 #define __HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE 2621 2622 /** @brief macro to configure the UART5 clock (UART5CLK). 2623 * 2624 * @param __UART5CLKSource__ specifies the UART5 clock source. 2625 * This parameter can be one of the following values: 2626 * @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock 2627 * @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock 2628 * @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock 2629 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock 2630 * @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock 2631 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock 2632 */ 2633 #define __HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG 2634 2635 /** @brief macro to get the UART5 clock source. 2636 * @retval The clock source can be one of the following values: 2637 * @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock 2638 * @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock 2639 * @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock 2640 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock 2641 * @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock 2642 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock 2643 */ 2644 #define __HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE 2645 2646 /** @brief macro to configure the USART6 clock (USART6CLK). 2647 * 2648 * @param __USART6CLKSource__ specifies the USART6 clock source. 2649 * This parameter can be one of the following values: 2650 * @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock 2651 * @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock 2652 * @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock 2653 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock 2654 * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock 2655 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock 2656 */ 2657 #define __HAL_RCC_USART6_CONFIG __HAL_RCC_USART16_CONFIG 2658 2659 /** @brief macro to get the USART6 clock source. 2660 * @retval The clock source can be one of the following values: 2661 * @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock 2662 * @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock 2663 * @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock 2664 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock 2665 * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock 2666 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock 2667 */ 2668 #define __HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE 2669 2670 /** @brief macro to configure the UART5 clock (UART7CLK). 2671 * 2672 * @param __UART7CLKSource__ specifies the UART7 clock source. 2673 * This parameter can be one of the following values: 2674 * @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock 2675 * @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock 2676 * @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock 2677 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock 2678 * @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock 2679 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock 2680 */ 2681 #define __HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG 2682 2683 /** @brief macro to get the UART7 clock source. 2684 * @retval The clock source can be one of the following values: 2685 * @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock 2686 * @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock 2687 * @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock 2688 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock 2689 * @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock 2690 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock 2691 */ 2692 #define __HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE 2693 2694 /** @brief macro to configure the UART8 clock (UART8CLK). 2695 * 2696 * @param __UART8CLKSource__ specifies the UART8 clock source. 2697 * This parameter can be one of the following values: 2698 * @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock 2699 * @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock 2700 * @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock 2701 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock 2702 * @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock 2703 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock 2704 */ 2705 #define __HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG 2706 2707 /** @brief macro to get the UART8 clock source. 2708 * @retval The clock source can be one of the following values: 2709 * @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock 2710 * @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock 2711 * @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock 2712 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock 2713 * @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock 2714 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock 2715 */ 2716 #define __HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE 2717 2718 #if defined(UART9) 2719 /** @brief macro to configure the UART9 clock (UART9CLK). 2720 * 2721 * @param __UART8CLKSource__ specifies the UART8 clock source. 2722 * This parameter can be one of the following values: 2723 * @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART9 clock 2724 * @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART9 clock 2725 * @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART9 clock 2726 * @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock 2727 * @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock 2728 * @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock 2729 */ 2730 #define __HAL_RCC_UART9_CONFIG __HAL_RCC_USART16_CONFIG 2731 2732 /** @brief macro to get the UART9 clock source. 2733 * @retval The clock source can be one of the following values: 2734 * @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART99 clock 2735 * @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART99 clock 2736 * @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART99 clock 2737 * @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock 2738 * @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock 2739 * @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock 2740 */ 2741 #define __HAL_RCC_GET_UART9_SOURCE __HAL_RCC_GET_USART16_SOURCE 2742 #endif /* UART9 */ 2743 2744 #if defined(USART10) 2745 /** @brief macro to configure the USART10 clock (USART10CLK). 2746 * 2747 * @param __UART8CLKSource__ specifies the UART8 clock source. 2748 * This parameter can be one of the following values: 2749 * @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock 2750 * @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock 2751 * @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock 2752 * @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock 2753 * @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock 2754 * @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock 2755 */ 2756 #define __HAL_RCC_USART10_CONFIG __HAL_RCC_USART16_CONFIG 2757 2758 /** @brief macro to get the USART10 clock source. 2759 * @retval The clock source can be one of the following values: 2760 * @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock 2761 * @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock 2762 * @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock 2763 * @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock 2764 * @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock 2765 * @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock 2766 */ 2767 #define __HAL_RCC_GET_USART10_SOURCE __HAL_RCC_GET_USART16_SOURCE 2768 #endif /* USART10 */ 2769 2770 /** @brief macro to configure the LPUART1 clock (LPUART1CLK). 2771 * 2772 * @param __LPUART1CLKSource__ specifies the LPUART1 clock source. 2773 * This parameter can be one of the following values: 2774 * @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock 2775 * @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock 2776 * @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock 2777 * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock 2778 * @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock 2779 * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock 2780 */ 2781 #if defined (RCC_D3CCIPR_LPUART1SEL) 2782 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \ 2783 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) 2784 #else 2785 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \ 2786 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) 2787 #endif /* RCC_D3CCIPR_LPUART1SEL */ 2788 2789 /** @brief macro to get the LPUART1 clock source. 2790 * @retval The clock source can be one of the following values: 2791 * @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock 2792 * @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock 2793 * @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock 2794 * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock 2795 * @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock 2796 * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock 2797 */ 2798 #if defined (RCC_D3CCIPR_LPUART1SEL) 2799 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL))) 2800 #else 2801 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL))) 2802 #endif /* RCC_D3CCIPR_LPUART1SEL */ 2803 2804 /** @brief macro to configure the LPTIM1 clock source. 2805 * 2806 * @param __LPTIM1CLKSource__ specifies the LPTIM1 clock source. 2807 * This parameter can be one of the following values: 2808 * @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock 2809 * @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock 2810 * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock 2811 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 2812 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock 2813 * @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock 2814 */ 2815 #if defined(RCC_D2CCIP2R_LPTIM1SEL) 2816 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \ 2817 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) 2818 #else 2819 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \ 2820 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) 2821 #endif /* RCC_D2CCIP2R_LPTIM1SEL */ 2822 2823 /** @brief macro to get the LPTIM1 clock source. 2824 * @retval The clock source can be one of the following values: 2825 * @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock 2826 * @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock 2827 * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock 2828 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 2829 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock 2830 * @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock 2831 */ 2832 #if defined(RCC_D2CCIP2R_LPTIM1SEL) 2833 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL))) 2834 #else 2835 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL))) 2836 #endif /* RCC_D2CCIP2R_LPTIM1SEL */ 2837 2838 /** @brief macro to configure the LPTIM2 clock source. 2839 * 2840 * @param __LPTIM2CLKSource__ specifies the LPTIM2 clock source. 2841 * This parameter can be one of the following values: 2842 * @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock 2843 * @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock 2844 * @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock 2845 * @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock 2846 * @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock 2847 * @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock 2848 */ 2849 #if defined(RCC_D3CCIPR_LPTIM2SEL) 2850 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \ 2851 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) 2852 #else 2853 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \ 2854 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) 2855 #endif /* RCC_D3CCIPR_LPTIM2SEL */ 2856 2857 /** @brief macro to get the LPTIM2 clock source. 2858 * @retval The clock source can be one of the following values: 2859 * @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock 2860 * @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock 2861 * @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock 2862 * @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock 2863 * @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock 2864 * @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock 2865 */ 2866 #if defined(RCC_D3CCIPR_LPTIM2SEL) 2867 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL))) 2868 #else 2869 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL))) 2870 #endif /* RCC_D3CCIPR_LPTIM2SEL */ 2871 2872 /** @brief macro to configure the LPTIM3/4/5 clock source. 2873 * 2874 * @param __LPTIM345CLKSource__ specifies the LPTIM3/4/5 clock source. 2875 * @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock 2876 * @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock 2877 * @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock 2878 * @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock 2879 * @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock 2880 * @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock 2881 */ 2882 #if defined(RCC_D3CCIPR_LPTIM345SEL) 2883 #define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \ 2884 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__)) 2885 #else 2886 #define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \ 2887 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM345CLKSource__)) 2888 #endif /* RCC_D3CCIPR_LPTIM345SEL */ 2889 2890 /** @brief macro to get the LPTIM3/4/5 clock source. 2891 * @retval The clock source can be one of the following values: 2892 * @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock 2893 * @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock 2894 * @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock 2895 * @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock 2896 * @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock 2897 * @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock 2898 */ 2899 #if defined(RCC_D3CCIPR_LPTIM345SEL) 2900 #define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL))) 2901 #else 2902 #define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL))) 2903 #endif /* RCC_D3CCIPR_LPTIM345SEL */ 2904 2905 /** @brief macro to configure the LPTIM3 clock source. 2906 * 2907 * @param __LPTIM3CLKSource__ specifies the LPTIM3 clock source. 2908 * @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock 2909 * @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock 2910 * @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock 2911 * @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock 2912 * @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock 2913 * @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock 2914 */ 2915 #define __HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG 2916 2917 /** @brief macro to get the LPTIM3 clock source. 2918 * @retval The clock source can be one of the following values: 2919 * @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock 2920 * @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock 2921 * @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock 2922 * @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock 2923 * @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock 2924 * @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock 2925 */ 2926 #define __HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE 2927 2928 #if defined(LPTIM4) 2929 /** @brief macro to configure the LPTIM4 clock source. 2930 * 2931 * @param __LPTIM4CLKSource__ specifies the LPTIM4 clock source. 2932 * @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock 2933 * @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock 2934 * @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock 2935 * @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock 2936 * @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock 2937 * @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock 2938 */ 2939 #define __HAL_RCC_LPTIM4_CONFIG __HAL_RCC_LPTIM345_CONFIG 2940 2941 2942 /** @brief macro to get the LPTIM4 clock source. 2943 * @retval The clock source can be one of the following values: 2944 * @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock 2945 * @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock 2946 * @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock 2947 * @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock 2948 * @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock 2949 * @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock 2950 */ 2951 #define __HAL_RCC_GET_LPTIM4_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE 2952 #endif /* LPTIM4 */ 2953 2954 #if defined(LPTIM5) 2955 /** @brief macro to configure the LPTIM5 clock source. 2956 * 2957 * @param __LPTIM5CLKSource__ specifies the LPTIM5 clock source. 2958 * @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock 2959 * @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock 2960 * @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock 2961 * @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock 2962 * @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock 2963 * @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock 2964 */ 2965 #define __HAL_RCC_LPTIM5_CONFIG __HAL_RCC_LPTIM345_CONFIG 2966 2967 2968 /** @brief macro to get the LPTIM5 clock source. 2969 * @retval The clock source can be one of the following values: 2970 * @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock 2971 * @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock 2972 * @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock 2973 * @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock 2974 * @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock 2975 * @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock 2976 */ 2977 #define __HAL_RCC_GET_LPTIM5_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE 2978 #endif /* LPTIM5 */ 2979 2980 #if defined(QUADSPI) 2981 /** @brief macro to configure the QSPI clock source. 2982 * 2983 * @param __QSPICLKSource__ specifies the QSPI clock source. 2984 * @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock 2985 * @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock 2986 * @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock 2987 * @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock 2988 */ 2989 #define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \ 2990 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__)) 2991 2992 2993 /** @brief macro to get the QSPI clock source. 2994 * @retval The clock source can be one of the following values: 2995 * @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock 2996 * @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock 2997 * @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock 2998 * @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock 2999 */ 3000 #define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL))) 3001 #endif /* QUADSPI */ 3002 3003 #if defined(OCTOSPI1) || defined(OCTOSPI2) 3004 /** @brief macro to configure the OSPI clock source. 3005 * 3006 * @param __OSPICLKSource__ specifies the OSPI clock source. 3007 * @arg RCC_RCC_OSPICLKSOURCE_CDHCLK: Domain1 HCLK Clock selected as OSPI clock 3008 * @arg RCC_RCC_OSPICLKSOURCE_PLL : PLL1_Q Clock selected as OSPI clock 3009 * @arg RCC_RCC_OSPICLKSOURCE_PLL2 : PLL2_R Clock selected as OSPI clock 3010 * @arg RCC_RCC_OSPICLKSOURCE_CLKP CLKP selected as OSPI clock 3011 */ 3012 #if defined(RCC_CDCCIPR_OCTOSPISEL) 3013 #define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \ 3014 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__)) 3015 #else 3016 #define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \ 3017 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__)) 3018 #endif /* RCC_CDCCIPR_OCTOSPISEL */ 3019 3020 /** @brief macro to get the OSPI clock source. 3021 * @retval The clock source can be one of the following values: 3022 * @arg RCC_RCC_OSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as OSPI clock 3023 * @arg RCC_RCC_OSPICLKSOURCE_PLL : PLL1_Q Clock selected as OSPI clock 3024 * @arg RCC_RCC_OSPICLKSOURCE_PLL2 : PLL2_R Clock selected as OSPI clock 3025 * @arg RCC_RCC_OSPICLKSOURCE_CLKP CLKP selected as OSPI clock 3026 */ 3027 #if defined(RCC_CDCCIPR_OCTOSPISEL) 3028 #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL))) 3029 #else 3030 #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL))) 3031 #endif /* RCC_CDCCIPR_OCTOSPISEL */ 3032 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ 3033 3034 3035 #if defined(DSI) 3036 /** @brief macro to configure the DSI clock source. 3037 * 3038 * @param __DSICLKSource__ specifies the DSI clock source. 3039 * @arg RCC_RCC_DSICLKSOURCE_PHY:DSI clock from PHY is selected as DSI byte lane clock 3040 * @arg RCC_RCC_DSICLKSOURCE_PLL2 : PLL2_Q Clock clock is selected as DSI byte lane clock 3041 */ 3042 #define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \ 3043 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, (uint32_t)(__DSICLKSource__)) 3044 3045 3046 /** @brief macro to get the DSI clock source. 3047 * @retval The clock source can be one of the following values: 3048 * @arg RCC_RCC_DSICLKSOURCE_PHY: DSI clock from PHY is selected as DSI byte lane clock 3049 * @arg RCC_RCC_DSICLKSOURCE_PLL2: PLL2_Q Clock clock is selected as DSI byte lane clock 3050 */ 3051 #define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL))) 3052 #endif /*DSI*/ 3053 3054 /** @brief macro to configure the FMC clock source. 3055 * 3056 * @param __FMCCLKSource__ specifies the FMC clock source. 3057 * @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock 3058 * @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock 3059 * @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock 3060 * @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock 3061 */ 3062 #if defined(RCC_D1CCIPR_FMCSEL) 3063 #define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \ 3064 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) 3065 #else 3066 #define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \ 3067 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) 3068 #endif /* RCC_D1CCIPR_FMCSEL */ 3069 3070 /** @brief macro to get the FMC clock source. 3071 * @retval The clock source can be one of the following values: 3072 * @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock 3073 * @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock 3074 * @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock 3075 * @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock 3076 */ 3077 #if defined(RCC_D1CCIPR_FMCSEL) 3078 #define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL))) 3079 #else 3080 #define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL))) 3081 #endif /* RCC_D1CCIPR_FMCSEL */ 3082 3083 /** @brief Macro to configure the USB clock (USBCLK). 3084 * @param __USBCLKSource__ specifies the USB clock source. 3085 * This parameter can be one of the following values: 3086 * @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock 3087 * @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock 3088 * @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock 3089 */ 3090 #if defined(RCC_D2CCIP2R_USBSEL) 3091 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ 3092 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) 3093 #else 3094 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ 3095 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) 3096 #endif /* RCC_D2CCIP2R_USBSEL */ 3097 3098 /** @brief Macro to get the USB clock source. 3099 * @retval The clock source can be one of the following values: 3100 * @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock 3101 * @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock 3102 * @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock 3103 */ 3104 #if defined(RCC_D2CCIP2R_USBSEL) 3105 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL))) 3106 #else 3107 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL))) 3108 #endif /* RCC_D2CCIP2R_USBSEL */ 3109 3110 /** @brief Macro to configure the ADC clock 3111 * @param __ADCCLKSource__ specifies the ADC digital interface clock source. 3112 * This parameter can be one of the following values: 3113 * @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock 3114 * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock 3115 * @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock 3116 */ 3117 #if defined(RCC_D3CCIPR_ADCSEL) 3118 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \ 3119 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) 3120 #else 3121 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \ 3122 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) 3123 #endif /* RCC_D3CCIPR_ADCSEL */ 3124 3125 /** @brief Macro to get the ADC clock source. 3126 * @retval The clock source can be one of the following values: 3127 * @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock 3128 * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock 3129 * @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock 3130 */ 3131 #if defined(RCC_D3CCIPR_ADCSEL) 3132 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL))) 3133 #else 3134 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL))) 3135 #endif /* RCC_D3CCIPR_ADCSEL */ 3136 3137 /** @brief Macro to configure the SWPMI1 clock 3138 * @param __SWPMI1CLKSource__ specifies the SWPMI1 clock source. 3139 * This parameter can be one of the following values: 3140 * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock 3141 * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock 3142 */ 3143 #if defined(RCC_D2CCIP1R_SWPSEL) 3144 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \ 3145 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) 3146 #else 3147 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \ 3148 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) 3149 #endif /* RCC_D2CCIP1R_SWPSEL */ 3150 3151 /** @brief Macro to get the SWPMI1 clock source. 3152 * @retval The clock source can be one of the following values: 3153 * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock 3154 * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock 3155 */ 3156 #if defined(RCC_D2CCIP1R_SWPSEL) 3157 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL))) 3158 #else 3159 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL))) 3160 #endif /* RCC_D2CCIP1R_SWPSEL */ 3161 3162 /** @brief Macro to configure the DFSDM1 clock 3163 * @param __DFSDM1CLKSource__ specifies the DFSDM1 clock source. 3164 * This parameter can be one of the following values: 3165 * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock 3166 * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock 3167 */ 3168 #if defined(RCC_D2CCIP1R_DFSDM1SEL) 3169 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \ 3170 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) 3171 #else 3172 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \ 3173 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) 3174 #endif /* RCC_D2CCIP1R_DFSDM1SEL */ 3175 3176 /** @brief Macro to get the DFSDM1 clock source. 3177 * @retval The clock source can be one of the following values: 3178 * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock 3179 * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock 3180 */ 3181 #if defined (RCC_D2CCIP1R_DFSDM1SEL) 3182 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL))) 3183 #else 3184 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL))) 3185 #endif /* RCC_D2CCIP1R_DFSDM1SEL */ 3186 3187 #if defined(DFSDM2_BASE) 3188 /** @brief Macro to configure the DFSDM2 clock 3189 * @param __DFSDM2CLKSource__ specifies the DFSDM2 clock source. 3190 * This parameter can be one of the following values: 3191 * @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1: SRDPCLK1 (APB4) selected as DFSDM2 clock 3192 * @arg RCC_DFSDM2CLKSOURCE_SYS: System Clock selected as DFSDM2 clock 3193 */ 3194 #define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \ 3195 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__)) 3196 3197 /** @brief Macro to get the DFSDM2 clock source. 3198 * @retval The clock source can be one of the following values: 3199 * @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1: SRDPCLK1 (APB4) Clock selected as DFSDM2 clock 3200 * @arg RCC_DFSDM2CLKSOURCE_SYS: System Clock selected as DFSDM2 clock 3201 */ 3202 #define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL))) 3203 #endif /* DFSDM2 */ 3204 3205 /** @brief macro to configure the CEC clock (CECCLK). 3206 * 3207 * @param __CECCLKSource__ specifies the CEC clock source. 3208 * This parameter can be one of the following values: 3209 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 3210 * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock 3211 * @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock 3212 */ 3213 #if defined(RCC_D2CCIP2R_CECSEL) 3214 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ 3215 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) 3216 #else 3217 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ 3218 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) 3219 #endif /* RCC_D2CCIP2R_CECSEL */ 3220 3221 /** @brief macro to get the CEC clock source. 3222 * @retval The clock source can be one of the following values: 3223 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 3224 * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock 3225 * @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock 3226 */ 3227 #if defined(RCC_D2CCIP2R_CECSEL) 3228 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL))) 3229 #else 3230 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL))) 3231 #endif /* RCC_D2CCIP2R_CECSEL */ 3232 3233 /** @brief Macro to configure the CLKP : Oscillator clock for peripheral 3234 * @param __CLKPSource__ specifies Oscillator clock for peripheral 3235 * This parameter can be one of the following values: 3236 * @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral 3237 * @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral 3238 * @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral 3239 */ 3240 #if defined(RCC_D1CCIPR_CKPERSEL) 3241 #define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \ 3242 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) 3243 #else 3244 #define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \ 3245 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) 3246 #endif /* RCC_D1CCIPR_CKPERSEL */ 3247 3248 /** @brief Macro to get the Oscillator clock for peripheral source. 3249 * @retval The clock source can be one of the following values: 3250 * @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral 3251 * @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral 3252 * @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral 3253 */ 3254 #if defined(RCC_D1CCIPR_CKPERSEL) 3255 #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL))) 3256 #else 3257 #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL))) 3258 #endif /* RCC_D1CCIPR_CKPERSEL */ 3259 3260 #if defined(FDCAN1) || defined(FDCAN2) 3261 /** @brief Macro to configure the FDCAN clock 3262 * @param __FDCANCLKSource__ specifies clock source for FDCAN 3263 * This parameter can be one of the following values: 3264 * @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock 3265 * @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock 3266 * @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock 3267 */ 3268 #if defined(RCC_D2CCIP1R_FDCANSEL) 3269 #define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \ 3270 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__)) 3271 #else 3272 #define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \ 3273 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__)) 3274 #endif /* RCC_D2CCIP1R_FDCANSEL */ 3275 3276 /** @brief Macro to get the FDCAN clock 3277 * @retval The clock source can be one of the following values: 3278 * @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock 3279 * @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock 3280 * @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock 3281 */ 3282 #if defined(RCC_D2CCIP1R_FDCANSEL) 3283 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL))) 3284 #else 3285 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL))) 3286 #endif /* RCC_D2CCIP1R_FDCANSEL */ 3287 3288 #endif /*FDCAN1 || FDCAN2*/ 3289 3290 /** 3291 * @brief Macro to Configure the SPI1/2/3 clock source. 3292 * @param __RCC_SPI123CLKSource__ defines the SPI1/2/3 clock source. This clock is derived 3293 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 3294 * This parameter can be one of the following values: 3295 * @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL 3296 * @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2 3297 * @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3 3298 * @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP 3299 * @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock 3300 * @retval None 3301 */ 3302 #if defined(RCC_D2CCIP1R_SPI123SEL) 3303 #define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\ 3304 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) 3305 #else 3306 #define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\ 3307 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) 3308 #endif /* RCC_D2CCIP1R_SPI123SEL */ 3309 3310 /** @brief Macro to get the SPI1/2/3 clock source. 3311 * @retval The clock source can be one of the following values: 3312 * @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL 3313 * @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2 3314 * @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3 3315 * @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP 3316 * @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock 3317 */ 3318 #if defined(RCC_D2CCIP1R_SPI123SEL) 3319 #define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL))) 3320 #else 3321 #define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL))) 3322 #endif /* RCC_D2CCIP1R_SPI123SEL */ 3323 3324 /** 3325 * @brief Macro to Configure the SPI1 clock source. 3326 * @param __RCC_SPI1CLKSource__ defines the SPI1 clock source. This clock is derived 3327 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 3328 * This parameter can be one of the following values: 3329 * @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL 3330 * @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2 3331 * @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3 3332 * @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP 3333 * @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock 3334 * @retval None 3335 */ 3336 #define __HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG 3337 3338 /** @brief Macro to get the SPI1 clock source. 3339 * @retval The clock source can be one of the following values: 3340 * @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL 3341 * @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2 3342 * @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3 3343 * @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP 3344 * @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock 3345 */ 3346 #define __HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE 3347 3348 /** 3349 * @brief Macro to Configure the SPI2 clock source. 3350 * @param __RCC_SPI2CLKSource__ defines the SPI2 clock source. This clock is derived 3351 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 3352 * This parameter can be one of the following values: 3353 * @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL 3354 * @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2 3355 * @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3 3356 * @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP 3357 * @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock 3358 * @retval None 3359 */ 3360 #define __HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG 3361 3362 /** @brief Macro to get the SPI2 clock source. 3363 * @retval The clock source can be one of the following values: 3364 * @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL 3365 * @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2 3366 * @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3 3367 * @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP 3368 * @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock 3369 */ 3370 #define __HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE 3371 3372 /** 3373 * @brief Macro to Configure the SPI3 clock source. 3374 * @param __RCC_SPI3CLKSource__ defines the SPI3 clock source. This clock is derived 3375 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 3376 * This parameter can be one of the following values: 3377 * @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL 3378 * @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2 3379 * @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3 3380 * @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP 3381 * @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock 3382 * @retval None 3383 */ 3384 #define __HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG 3385 3386 /** @brief Macro to get the SPI3 clock source. 3387 * @retval The clock source can be one of the following values: 3388 * @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL 3389 * @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2 3390 * @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3 3391 * @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP 3392 * @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock 3393 */ 3394 #define __HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE 3395 3396 /** 3397 * @brief Macro to Configure the SPI4/5 clock source. 3398 * @param __RCC_SPI45CLKSource__ defines the SPI4/5 clock source. This clock is derived 3399 * from system PCLK, PLL2, PLL3, OSC 3400 * This parameter can be one of the following values: 3401 * @arg RCC_SPI45CLKSOURCE_D2PCLK2:SPI4/5 clock = D2PCLK2 3402 * @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2 3403 * @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3 3404 * @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI 3405 * @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI 3406 * @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE 3407 * @retval None 3408 */ 3409 #if defined(RCC_D2CCIP1R_SPI45SEL) 3410 #define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\ 3411 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) 3412 #else 3413 #define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\ 3414 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) 3415 #endif /* RCC_D2CCIP1R_SPI45SEL */ 3416 3417 /** @brief Macro to get the SPI4/5 clock source. 3418 * @retval The clock source can be one of the following values: 3419 * @arg RCC_SPI45CLKSOURCE_D2PCLK2:SPI4/5 clock = D2PCLK2 3420 * @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2 3421 * @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3 3422 * @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI 3423 * @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI 3424 * @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE 3425 */ 3426 #if defined(RCC_D2CCIP1R_SPI45SEL) 3427 #define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL))) 3428 #else 3429 #define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL))) 3430 #endif /* RCC_D2CCIP1R_SPI45SEL */ 3431 3432 /** 3433 * @brief Macro to Configure the SPI4 clock source. 3434 * @param __RCC_SPI4CLKSource__ defines the SPI4 clock source. This clock is derived 3435 * from system PCLK, PLL2, PLL3, OSC 3436 * This parameter can be one of the following values: 3437 * @arg RCC_SPI4CLKSOURCE_D2PCLK2:SPI4 clock = D2PCLK2 3438 * @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2 3439 * @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3 3440 * @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI 3441 * @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI 3442 * @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE 3443 * @retval None 3444 */ 3445 #define __HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG 3446 3447 /** @brief Macro to get the SPI4 clock source. 3448 * @retval The clock source can be one of the following values: 3449 * @arg RCC_SPI4CLKSOURCE_D2PCLK2:SPI4 clock = D2PCLK2 3450 * @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2 3451 * @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3 3452 * @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI 3453 * @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI 3454 * @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE 3455 */ 3456 #define __HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE 3457 3458 /** 3459 * @brief Macro to Configure the SPI5 clock source. 3460 * @param __RCC_SPI5CLKSource__ defines the SPI5 clock source. This clock is derived 3461 * from system PCLK, PLL2, PLL3, OSC 3462 * This parameter can be one of the following values: 3463 * @arg RCC_SPI5CLKSOURCE_D2PCLK2:SPI5 clock = D2PCLK2 3464 * @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2 3465 * @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3 3466 * @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI 3467 * @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI 3468 * @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE 3469 * @retval None 3470 */ 3471 #define __HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG 3472 3473 /** @brief Macro to get the SPI5 clock source. 3474 * @retval The clock source can be one of the following values: 3475 * @arg RCC_SPI5CLKSOURCE_D2PCLK2:SPI5 clock = D2PCLK2 3476 * @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2 3477 * @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3 3478 * @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI 3479 * @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI 3480 * @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE 3481 */ 3482 #define __HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE 3483 3484 /** 3485 * @brief Macro to Configure the SPI6 clock source. 3486 * @param __RCC_SPI6CLKSource__ defines the SPI6 clock source. This clock is derived 3487 * from system PCLK, PLL2, PLL3, OSC 3488 * This parameter can be one of the following values: 3489 * @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1 3490 * @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2 3491 * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3 3492 * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI 3493 * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI 3494 * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE 3495 * @arg RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN (*) 3496 * 3497 * @retval None 3498 * 3499 * (*) : Available on stm32h7a3xx and stm32h7b3xx family lines. 3500 * 3501 */ 3502 #if defined(RCC_D3CCIPR_SPI6SEL) 3503 #define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\ 3504 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) 3505 #else 3506 #define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\ 3507 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) 3508 #endif /* RCC_D3CCIPR_SPI6SEL */ 3509 3510 /** @brief Macro to get the SPI6 clock source. 3511 * @retval The clock source can be one of the following values: 3512 * @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1 3513 * @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2 3514 * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3 3515 * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI 3516 * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI 3517 * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE 3518 * @arg RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN 3519 */ 3520 #if defined(RCC_D3CCIPR_SPI6SEL) 3521 #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL))) 3522 #else 3523 #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL))) 3524 #endif /* RCC_D3CCIPR_SPI6SEL */ 3525 3526 /** @brief Macro to configure the SDMMC clock 3527 * @param __SDMMCCLKSource__ specifies clock source for SDMMC 3528 * This parameter can be one of the following values: 3529 * @arg RCC_SDMMCCLKSOURCE_PLL: PLLQ selected as SDMMC clock 3530 * @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock 3531 */ 3532 #if defined(RCC_D1CCIPR_SDMMCSEL) 3533 #define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \ 3534 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) 3535 #else 3536 #define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \ 3537 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) 3538 #endif /* RCC_D1CCIPR_SDMMCSEL */ 3539 3540 /** @brief Macro to get the SDMMC clock 3541 */ 3542 #if defined(RCC_D1CCIPR_SDMMCSEL) 3543 #define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL))) 3544 #else 3545 #define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL))) 3546 #endif /* RCC_D1CCIPR_SDMMCSEL */ 3547 3548 /** @brief macro to configure the RNG clock (RNGCLK). 3549 * 3550 * @param __RNGCLKSource__ specifies the RNG clock source. 3551 * This parameter can be one of the following values: 3552 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock 3553 * @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock 3554 * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock 3555 * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock 3556 */ 3557 #if defined(RCC_D2CCIP2R_RNGSEL) 3558 #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \ 3559 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) 3560 #else 3561 #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \ 3562 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) 3563 #endif /* RCC_D2CCIP2R_RNGSEL */ 3564 3565 /** @brief macro to get the RNG clock source. 3566 * @retval The clock source can be one of the following values: 3567 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock 3568 * @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock 3569 * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock 3570 * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock 3571 */ 3572 #if defined(RCC_D2CCIP2R_RNGSEL) 3573 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL))) 3574 #else 3575 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL))) 3576 #endif /* RCC_D2CCIP2R_RNGSEL */ 3577 3578 #if defined(HRTIM1) 3579 /** @brief Macro to configure the HRTIM1 prescaler clock source. 3580 * @param __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source. 3581 * This parameter can be one of the following values: 3582 * @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock 3583 * @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock 3584 */ 3585 #define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \ 3586 MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__)) 3587 3588 /** @brief Macro to get the HRTIM1 clock source. 3589 * @retval The clock source can be one of the following values: 3590 * @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock 3591 * @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock 3592 */ 3593 #define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL))) 3594 #endif /* HRTIM1 */ 3595 3596 /** @brief Macro to configure the Timers clocks prescalers 3597 * @param __PRESC__ specifies the Timers clocks prescalers selection 3598 * This parameter can be one of the following values: 3599 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is 3600 * equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2, 3601 * else it is equal to 2 x Frcc_pclkx_d2 (default after reset) 3602 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is 3603 * equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4, 3604 * else it is equal to 4 x Frcc_pclkx_d2 3605 */ 3606 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\ 3607 RCC->CFGR |= (__PRESC__); \ 3608 }while(0) 3609 3610 /** 3611 * @brief Enable the RCC LSE CSS Extended Interrupt Line. 3612 * @retval None 3613 */ 3614 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 3615 3616 /** 3617 * @brief Disable the RCC LSE CSS Extended Interrupt Line. 3618 * @retval None 3619 */ 3620 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 3621 3622 /** 3623 * @brief Enable the RCC LSE CSS Event Line. 3624 * @retval None. 3625 */ 3626 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 3627 3628 /** 3629 * @brief Disable the RCC LSE CSS Event Line. 3630 * @retval None. 3631 */ 3632 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 3633 3634 #if defined(DUAL_CORE) 3635 /** 3636 * @brief Enable the RCC LSE CSS Extended Interrupt Line for CM4. 3637 * @retval None 3638 */ 3639 #define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS) 3640 3641 /** 3642 * @brief Disable the RCC LSE CSS Extended Interrupt Line for CM4. 3643 * @retval None 3644 */ 3645 #define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS) 3646 3647 /** 3648 * @brief Enable the RCC LSE CSS Event Line for CM4. 3649 * @retval None. 3650 */ 3651 #define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS) 3652 3653 /** 3654 * @brief Disable the RCC LSE CSS Event Line for CM4. 3655 * @retval None. 3656 */ 3657 #define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS) 3658 #endif /* DUAL_CORE */ 3659 3660 /** 3661 * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. 3662 * @retval None. 3663 */ 3664 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 3665 3666 3667 /** 3668 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. 3669 * @retval None. 3670 */ 3671 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 3672 3673 3674 /** 3675 * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. 3676 * @retval None. 3677 */ 3678 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 3679 3680 /** 3681 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. 3682 * @retval None. 3683 */ 3684 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 3685 3686 /** 3687 * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 3688 * @retval None. 3689 */ 3690 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ 3691 do { \ 3692 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ 3693 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ 3694 } while(0) 3695 3696 /** 3697 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 3698 * @retval None. 3699 */ 3700 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ 3701 do { \ 3702 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ 3703 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ 3704 } while(0) 3705 3706 /** 3707 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. 3708 * @retval EXTI RCC LSE CSS Line Status. 3709 */ 3710 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) 3711 3712 /** 3713 * @brief Clear the RCC LSE CSS EXTI flag. 3714 * @retval None. 3715 */ 3716 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) 3717 3718 #if defined(DUAL_CORE) 3719 /** 3720 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not for CM4. 3721 * @retval EXTI RCC LSE CSS Line Status. 3722 */ 3723 #define __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) 3724 3725 /** 3726 * @brief Clear the RCC LSE CSS EXTI flag or not for CM4. 3727 * @retval None. 3728 */ 3729 #define __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) 3730 #endif /* DUAL_CORE */ 3731 /** 3732 * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. 3733 * @retval None. 3734 */ 3735 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) 3736 3737 /** 3738 * @brief Enable the specified CRS interrupts. 3739 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 3740 * This parameter can be any combination of the following values: 3741 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 3742 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 3743 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 3744 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 3745 * @retval None 3746 */ 3747 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 3748 3749 /** 3750 * @brief Disable the specified CRS interrupts. 3751 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 3752 * This parameter can be any combination of the following values: 3753 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 3754 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 3755 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 3756 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 3757 * @retval None 3758 */ 3759 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 3760 3761 /** @brief Check whether the CRS interrupt has occurred or not. 3762 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 3763 * This parameter can be one of the following values: 3764 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 3765 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 3766 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 3767 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 3768 * @retval The new state of __INTERRUPT__ (SET or RESET). 3769 */ 3770 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) 3771 3772 /** @brief Clear the CRS interrupt pending bits 3773 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 3774 * This parameter can be any combination of the following values: 3775 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 3776 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 3777 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 3778 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 3779 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 3780 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 3781 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 3782 */ 3783 /* CRS IT Error Mask */ 3784 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) 3785 3786 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 3787 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 3788 { \ 3789 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 3790 } \ 3791 else \ 3792 { \ 3793 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 3794 } \ 3795 } while(0) 3796 3797 /** 3798 * @brief Check whether the specified CRS flag is set or not. 3799 * @param __FLAG__ specifies the flag to check. 3800 * This parameter can be one of the following values: 3801 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 3802 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 3803 * @arg @ref RCC_CRS_FLAG_ERR Error 3804 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 3805 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 3806 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 3807 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 3808 * @retval The new state of _FLAG_ (TRUE or FALSE). 3809 */ 3810 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 3811 3812 /** 3813 * @brief Clear the CRS specified FLAG. 3814 * @param __FLAG__ specifies the flag to clear. 3815 * This parameter can be one of the following values: 3816 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 3817 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 3818 * @arg @ref RCC_CRS_FLAG_ERR Error 3819 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 3820 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 3821 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 3822 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 3823 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR 3824 * @retval None 3825 */ 3826 3827 /* CRS Flag Error Mask */ 3828 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) 3829 3830 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 3831 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 3832 { \ 3833 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 3834 } \ 3835 else \ 3836 { \ 3837 WRITE_REG(CRS->ICR, (__FLAG__)); \ 3838 } \ 3839 } while(0) 3840 3841 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 3842 * @{ 3843 */ 3844 /** 3845 * @brief Enable the oscillator clock for frequency error counter. 3846 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 3847 * @retval None 3848 */ 3849 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 3850 3851 /** 3852 * @brief Disable the oscillator clock for frequency error counter. 3853 * @retval None 3854 */ 3855 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 3856 3857 /** 3858 * @brief Enable the automatic hardware adjustment of TRIM bits. 3859 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 3860 * @retval None 3861 */ 3862 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 3863 3864 /** 3865 * @brief Enable or disable the automatic hardware adjustment of TRIM bits. 3866 * @retval None 3867 */ 3868 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 3869 3870 /** 3871 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 3872 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 3873 * of the synchronization source after pre-scaling. It is then decreased by one in order to 3874 * reach the expected synchronization on the zero value. The formula is the following: 3875 * RELOAD = (fTARGET / fSYNC) -1 3876 * @param __FTARGET__ Target frequency (value in Hz) 3877 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 3878 * @retval None 3879 */ 3880 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 3881 3882 3883 /** 3884 * @} 3885 */ 3886 3887 3888 /** 3889 * @} 3890 */ 3891 3892 3893 /* Exported functions --------------------------------------------------------*/ 3894 /** @addtogroup RCCEx_Exported_Functions 3895 * @{ 3896 */ 3897 3898 /** @addtogroup RCCEx_Exported_Functions_Group1 3899 * @{ 3900 */ 3901 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 3902 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 3903 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk); 3904 uint32_t HAL_RCCEx_GetD1PCLK1Freq(void); 3905 uint32_t HAL_RCCEx_GetD3PCLK1Freq(void); 3906 uint32_t HAL_RCCEx_GetD1SysClockFreq(void); 3907 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks); 3908 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks); 3909 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks); 3910 /** 3911 * @} 3912 */ 3913 3914 /** @addtogroup RCCEx_Exported_Functions_Group2 3915 * @{ 3916 */ 3917 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); 3918 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); 3919 void HAL_RCCEx_EnableLSECSS(void); 3920 void HAL_RCCEx_DisableLSECSS(void); 3921 void HAL_RCCEx_EnableLSECSS_IT(void); 3922 void HAL_RCCEx_LSECSS_IRQHandler(void); 3923 void HAL_RCCEx_LSECSS_Callback(void); 3924 #if defined(DUAL_CORE) 3925 void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx); 3926 #endif /*DUAL_CORE*/ 3927 #if defined(RCC_GCR_WW1RSC) 3928 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx); 3929 #endif /*RCC_GCR_WW1RSC*/ 3930 /** 3931 * @} 3932 */ 3933 3934 3935 /** @addtogroup RCCEx_Exported_Functions_Group3 3936 * @{ 3937 */ 3938 3939 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 3940 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 3941 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 3942 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 3943 void HAL_RCCEx_CRS_IRQHandler(void); 3944 void HAL_RCCEx_CRS_SyncOkCallback(void); 3945 void HAL_RCCEx_CRS_SyncWarnCallback(void); 3946 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 3947 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 3948 3949 /** 3950 * @} 3951 */ 3952 3953 /** 3954 * @} 3955 */ 3956 3957 /* Private macros ------------------------------------------------------------*/ 3958 /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros 3959 * @{ 3960 */ 3961 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters 3962 * @{ 3963 */ 3964 3965 #define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \ 3966 ((VALUE) == RCC_PLL2_DIVQ) || \ 3967 ((VALUE) == RCC_PLL2_DIVR)) 3968 3969 #define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \ 3970 ((VALUE) == RCC_PLL3_DIVQ) || \ 3971 ((VALUE) == RCC_PLL3_DIVR)) 3972 3973 #if defined(RCC_D2CCIP2R_USART16SEL) 3974 #define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \ 3975 ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \ 3976 ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \ 3977 ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \ 3978 ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \ 3979 ((SOURCE) == RCC_USART16CLKSOURCE_HSI)) 3980 #else 3981 #define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \ 3982 ((SOURCE) == RCC_USART16CLKSOURCE_CDPCLK2)|| \ 3983 ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \ 3984 ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \ 3985 ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \ 3986 ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \ 3987 ((SOURCE) == RCC_USART16CLKSOURCE_HSI)) 3988 /* alias*/ 3989 #define IS_RCC_USART16910CLKSOURCE IS_RCC_USART16CLKSOURCE 3990 #endif /* RCC_D2CCIP2R_USART16SEL */ 3991 3992 #if defined(RCC_D2CCIP2R_USART28SEL) 3993 #define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \ 3994 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \ 3995 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \ 3996 ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \ 3997 ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \ 3998 ((SOURCE) == RCC_USART234578CLKSOURCE_HSI)) 3999 #else 4000 #define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \ 4001 ((SOURCE) == RCC_USART234578CLKSOURCE_CDPCLK1)|| \ 4002 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \ 4003 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \ 4004 ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \ 4005 ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \ 4006 ((SOURCE) == RCC_USART234578CLKSOURCE_HSI)) 4007 #endif /* RCC_D2CCIP2R_USART28SEL */ 4008 4009 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \ 4010 ((SOURCE) == RCC_USART1CLKSOURCE_PLL2) || \ 4011 ((SOURCE) == RCC_USART1CLKSOURCE_PLL3) || \ 4012 ((SOURCE) == RCC_USART1CLKSOURCE_CSI) || \ 4013 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ 4014 ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) 4015 4016 #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \ 4017 ((SOURCE) == RCC_USART2CLKSOURCE_PLL2) || \ 4018 ((SOURCE) == RCC_USART2CLKSOURCE_PLL3) || \ 4019 ((SOURCE) == RCC_USART2CLKSOURCE_CSI) || \ 4020 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ 4021 ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) 4022 4023 #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \ 4024 ((SOURCE) == RCC_USART3CLKSOURCE_PLL2) || \ 4025 ((SOURCE) == RCC_USART3CLKSOURCE_PLL3) || \ 4026 ((SOURCE) == RCC_USART3CLKSOURCE_CSI) || \ 4027 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ 4028 ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) 4029 4030 #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \ 4031 ((SOURCE) == RCC_UART4CLKSOURCE_PLL2) || \ 4032 ((SOURCE) == RCC_UART4CLKSOURCE_PLL3) || \ 4033 ((SOURCE) == RCC_UART4CLKSOURCE_CSI) || \ 4034 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ 4035 ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) 4036 4037 #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \ 4038 ((SOURCE) == RCC_UART5CLKSOURCE_PLL2) || \ 4039 ((SOURCE) == RCC_UART5CLKSOURCE_PLL3) || \ 4040 ((SOURCE) == RCC_UART5CLKSOURCE_CSI) || \ 4041 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ 4042 ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) 4043 4044 #define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \ 4045 ((SOURCE) == RCC_USART6CLKSOURCE_PLL2) || \ 4046 ((SOURCE) == RCC_USART6CLKSOURCE_PLL3) || \ 4047 ((SOURCE) == RCC_USART6CLKSOURCE_CSI) || \ 4048 ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \ 4049 ((SOURCE) == RCC_USART6CLKSOURCE_HSI)) 4050 4051 #define IS_RCC_UART7CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || \ 4052 ((SOURCE) == RCC_UART7CLKSOURCE_PLL2) || \ 4053 ((SOURCE) == RCC_UART7CLKSOURCE_PLL3) || \ 4054 ((SOURCE) == RCC_UART7CLKSOURCE_CSI) || \ 4055 ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \ 4056 ((SOURCE) == RCC_UART7CLKSOURCE_HSI)) 4057 4058 #define IS_RCC_UART8CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || \ 4059 ((SOURCE) == RCC_UART8CLKSOURCE_PLL2) || \ 4060 ((SOURCE) == RCC_UART8CLKSOURCE_PLL3) || \ 4061 ((SOURCE) == RCC_UART8CLKSOURCE_CSI) || \ 4062 ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \ 4063 ((SOURCE) == RCC_UART8CLKSOURCE_HSI)) 4064 4065 #if defined(UART9) 4066 #define IS_RCC_UART9CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART9CLKSOURCE_D2PCLK2)|| \ 4067 ((SOURCE) == RCC_UART9CLKSOURCE_PLL2) || \ 4068 ((SOURCE) == RCC_UART9CLKSOURCE_PLL3) || \ 4069 ((SOURCE) == RCC_UART9CLKSOURCE_CSI) || \ 4070 ((SOURCE) == RCC_UART9CLKSOURCE_LSE) || \ 4071 ((SOURCE) == RCC_UART9CLKSOURCE_HSI)) 4072 #endif 4073 4074 #if defined(USART10) 4075 #define IS_RCC_USART10CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART10CLKSOURCE_D2PCLK2)|| \ 4076 ((SOURCE) == RCC_USART10CLKSOURCE_PLL2) || \ 4077 ((SOURCE) == RCC_USART10CLKSOURCE_PLL3) || \ 4078 ((SOURCE) == RCC_USART10CLKSOURCE_CSI) || \ 4079 ((SOURCE) == RCC_USART10CLKSOURCE_LSE) || \ 4080 ((SOURCE) == RCC_USART10CLKSOURCE_HSI)) 4081 #endif 4082 4083 #define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \ 4084 ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2) || \ 4085 ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3) || \ 4086 ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI) || \ 4087 ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) || \ 4088 ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI)) 4089 4090 #if defined(I2C5) 4091 #define IS_RCC_I2C1235CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1235CLKSOURCE_PLL3) || \ 4092 ((SOURCE) == RCC_I2C1235CLKSOURCE_HSI) || \ 4093 ((SOURCE) == RCC_I2C1235CLKSOURCE_D2PCLK1) || \ 4094 ((SOURCE) == RCC_I2C1235CLKSOURCE_CSI)) 4095 4096 #define IS_RCC_I2C123CLKSOURCE IS_RCC_I2C1235CLKSOURCE /* For API Backward compatibility */ 4097 #else 4098 #define IS_RCC_I2C123CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3) || \ 4099 ((SOURCE) == RCC_I2C123CLKSOURCE_HSI) || \ 4100 ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \ 4101 ((SOURCE) == RCC_I2C123CLKSOURCE_CSI)) 4102 #endif /*I2C5*/ 4103 4104 #define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3) || \ 4105 ((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \ 4106 ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \ 4107 ((SOURCE) == RCC_I2C1CLKSOURCE_CSI)) 4108 4109 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3) || \ 4110 ((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ 4111 ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \ 4112 ((SOURCE) == RCC_I2C2CLKSOURCE_CSI)) 4113 4114 #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3) || \ 4115 ((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \ 4116 ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \ 4117 ((SOURCE) == RCC_I2C3CLKSOURCE_CSI)) 4118 4119 #define IS_RCC_I2C4CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3) || \ 4120 ((SOURCE) == RCC_I2C4CLKSOURCE_HSI) || \ 4121 ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \ 4122 ((SOURCE) == RCC_I2C4CLKSOURCE_CSI)) 4123 4124 #if defined(I2C5) 4125 #define IS_RCC_I2C5CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C5CLKSOURCE_PLL3) || \ 4126 ((SOURCE) == RCC_I2C5CLKSOURCE_HSI) || \ 4127 ((SOURCE) == RCC_I2C5CLKSOURCE_D2PCLK1)|| \ 4128 ((SOURCE) == RCC_I2C5CLKSOURCE_CSI)) 4129 #endif /*I2C5*/ 4130 4131 #define IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \ 4132 ((SOURCE) == RCC_RNGCLKSOURCE_PLL) || \ 4133 ((SOURCE) == RCC_RNGCLKSOURCE_LSE) || \ 4134 ((SOURCE) == RCC_RNGCLKSOURCE_LSI)) 4135 4136 #if defined(HRTIM1) 4137 #define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \ 4138 ((SOURCE) == RCC_HRTIM1CLK_CPUCLK)) 4139 #endif 4140 4141 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \ 4142 ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \ 4143 ((SOURCE) == RCC_USBCLKSOURCE_HSI48)) 4144 4145 #define IS_RCC_SAI1CLK(__SOURCE__) \ 4146 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 4147 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \ 4148 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \ 4149 ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \ 4150 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) 4151 4152 #if defined(SAI3) 4153 #define IS_RCC_SAI23CLK(__SOURCE__) \ 4154 (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL) || \ 4155 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \ 4156 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || \ 4157 ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || \ 4158 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN)) 4159 4160 #define IS_RCC_SAI2CLK(__SOURCE__) \ 4161 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ 4162 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \ 4163 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \ 4164 ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \ 4165 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)) 4166 4167 4168 #define IS_RCC_SAI3CLK(__SOURCE__) \ 4169 (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL) || \ 4170 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \ 4171 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \ 4172 ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \ 4173 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN)) 4174 #endif 4175 4176 #if defined(RCC_CDCCIP1R_SAI2ASEL) 4177 #define IS_RCC_SAI2ACLK(__SOURCE__) \ 4178 (((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL) || \ 4179 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL2) || \ 4180 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL3) || \ 4181 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_CLKP) || \ 4182 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PIN) || \ 4183 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_SPDIF)) 4184 #endif 4185 4186 #if defined(RCC_CDCCIP1R_SAI2BSEL) 4187 #define IS_RCC_SAI2BCLK(__SOURCE__) \ 4188 (((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL) || \ 4189 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL2) || \ 4190 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL3) || \ 4191 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_CLKP) || \ 4192 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PIN) || \ 4193 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_SPDIF)) 4194 #endif 4195 4196 #define IS_RCC_SPI123CLK(__SOURCE__) \ 4197 (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL) || \ 4198 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \ 4199 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \ 4200 ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \ 4201 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN)) 4202 4203 #define IS_RCC_SPI1CLK(__SOURCE__) \ 4204 (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL) || \ 4205 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \ 4206 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \ 4207 ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \ 4208 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN)) 4209 4210 #define IS_RCC_SPI2CLK(__SOURCE__) \ 4211 (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL) || \ 4212 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \ 4213 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \ 4214 ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \ 4215 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN)) 4216 4217 #define IS_RCC_SPI3CLK(__SOURCE__) \ 4218 (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL) || \ 4219 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \ 4220 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \ 4221 ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \ 4222 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN)) 4223 4224 #define IS_RCC_SPI45CLK(__SOURCE__) \ 4225 (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK2) || \ 4226 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2) || \ 4227 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3) || \ 4228 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || \ 4229 ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) || \ 4230 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE)) 4231 4232 #define IS_RCC_SPI4CLK(__SOURCE__) \ 4233 (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK2) || \ 4234 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2) || \ 4235 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3) || \ 4236 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \ 4237 ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) || \ 4238 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE)) 4239 4240 #define IS_RCC_SPI5CLK(__SOURCE__) \ 4241 (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK2)|| \ 4242 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2) || \ 4243 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3) || \ 4244 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \ 4245 ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) || \ 4246 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE)) 4247 4248 #if defined(RCC_D3CCIPR_SPI6SEL) 4249 #define IS_RCC_SPI6CLK(__SOURCE__) \ 4250 (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \ 4251 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \ 4252 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \ 4253 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ 4254 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ 4255 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)) 4256 #else 4257 #define IS_RCC_SPI6CLK(__SOURCE__) \ 4258 (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \ 4259 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \ 4260 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \ 4261 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ 4262 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ 4263 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE) || \ 4264 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN)) 4265 #endif /* RCC_D3CCIPR_SPI6SEL */ 4266 4267 #if defined(SAI4) 4268 #define IS_RCC_SAI4ACLK(__SOURCE__) \ 4269 (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL) || \ 4270 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \ 4271 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \ 4272 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \ 4273 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN)) 4274 4275 #define IS_RCC_SAI4BCLK(__SOURCE__) \ 4276 (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL) || \ 4277 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \ 4278 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \ 4279 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \ 4280 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN)) 4281 #endif /*SAI4*/ 4282 4283 #define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) 4284 #define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 4285 #define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4286 #define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4287 #define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4288 4289 #define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) 4290 #define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 4291 #define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4292 #define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4293 #define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4294 4295 #define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0) || \ 4296 ((VALUE) == RCC_PLL2VCIRANGE_1) || \ 4297 ((VALUE) == RCC_PLL2VCIRANGE_2) || \ 4298 ((VALUE) == RCC_PLL2VCIRANGE_3)) 4299 4300 #define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0) || \ 4301 ((VALUE) == RCC_PLL3VCIRANGE_1) || \ 4302 ((VALUE) == RCC_PLL3VCIRANGE_2) || \ 4303 ((VALUE) == RCC_PLL3VCIRANGE_3)) 4304 4305 #define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE) || \ 4306 ((VALUE) == RCC_PLL2VCOMEDIUM)) 4307 4308 #define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE) || \ 4309 ((VALUE) == RCC_PLL3VCOMEDIUM)) 4310 4311 #define IS_RCC_LPTIM1CLK(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \ 4312 ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2) || \ 4313 ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) || \ 4314 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE) || \ 4315 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \ 4316 ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP)) 4317 4318 #define IS_RCC_LPTIM2CLK(SOURCE) (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \ 4319 ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2) || \ 4320 ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3) || \ 4321 ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE) || \ 4322 ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI) || \ 4323 ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP)) 4324 4325 #define IS_RCC_LPTIM345CLK(SOURCE) (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \ 4326 ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2) || \ 4327 ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3) || \ 4328 ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE) || \ 4329 ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI) || \ 4330 ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP)) 4331 4332 #define IS_RCC_LPTIM3CLK(SOURCE) (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1) || \ 4333 ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2) || \ 4334 ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3) || \ 4335 ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE) || \ 4336 ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI) || \ 4337 ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP)) 4338 4339 #if defined(LPTIM4) 4340 #define IS_RCC_LPTIM4CLK(SOURCE) (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \ 4341 ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2) || \ 4342 ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3) || \ 4343 ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE) || \ 4344 ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI) || \ 4345 ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP)) 4346 #endif /* LPTIM4*/ 4347 4348 #if defined(LPTIM5) 4349 #define IS_RCC_LPTIM5CLK(SOURCE) (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \ 4350 ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2) || \ 4351 ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3) || \ 4352 ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE) || \ 4353 ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI) || \ 4354 ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP)) 4355 #endif /*LPTIM5*/ 4356 4357 #if defined(QUADSPI) 4358 #define IS_RCC_QSPICLK(__SOURCE__) \ 4359 (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK) || \ 4360 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL) || \ 4361 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2) || \ 4362 ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP)) 4363 #endif /*QUADSPI*/ 4364 4365 #if defined(OCTOSPI1) || defined(OCTOSPI1) 4366 #define IS_RCC_OSPICLK(__SOURCE__) \ 4367 (((__SOURCE__) == RCC_OSPICLKSOURCE_D1HCLK) || \ 4368 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL) || \ 4369 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2) || \ 4370 ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP)) 4371 #endif /*OCTOSPI1 || OCTOSPI1*/ 4372 4373 #if defined(DSI) 4374 #define IS_RCC_DSICLK(__SOURCE__) \ 4375 (((__SOURCE__) == RCC_DSICLKSOURCE_PHY) || \ 4376 ((__SOURCE__) == RCC_DSICLKSOURCE_PLL2)) 4377 #endif /*DSI*/ 4378 4379 #define IS_RCC_FMCCLK(__SOURCE__) \ 4380 (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK) || \ 4381 ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL) || \ 4382 ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2) || \ 4383 ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP)) 4384 4385 #if defined(FDCAN1) || defined(FDCAN2) 4386 #define IS_RCC_FDCANCLK(__SOURCE__) \ 4387 (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ 4388 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \ 4389 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2)) 4390 #endif /*FDCAN1 || FDCAN2*/ 4391 4392 #define IS_RCC_SDMMC(__SOURCE__) \ 4393 (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL) || \ 4394 ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2)) 4395 4396 #define IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \ 4397 ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \ 4398 ((SOURCE) == RCC_ADCCLKSOURCE_CLKP)) 4399 4400 #define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \ 4401 ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI)) 4402 4403 #define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \ 4404 ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS)) 4405 4406 #if defined(DFSDM2_BASE) 4407 #define IS_RCC_DFSDM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM2CLKSOURCE_SRDPCLK1) || \ 4408 ((SOURCE) == RCC_DFSDM2CLKSOURCE_SYS)) 4409 #endif /*DFSDM2*/ 4410 4411 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL) || \ 4412 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \ 4413 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \ 4414 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI)) 4415 4416 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \ 4417 ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \ 4418 ((SOURCE) == RCC_CECCLKSOURCE_CSI)) 4419 4420 #define IS_RCC_CLKPSOURCE(SOURCE) (((SOURCE) == RCC_CLKPSOURCE_HSI) || \ 4421 ((SOURCE) == RCC_CLKPSOURCE_CSI) || \ 4422 ((SOURCE) == RCC_CLKPSOURCE_HSE)) 4423 #define IS_RCC_TIMPRES(VALUE) \ 4424 (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \ 4425 ((VALUE) == RCC_TIMPRES_ACTIVATED)) 4426 4427 #if defined(DUAL_CORE) 4428 #define IS_RCC_BOOT_CORE(CORE) (((CORE) == RCC_BOOT_C1) || \ 4429 ((CORE) == RCC_BOOT_C2)) 4430 #endif /*DUAL_CORE*/ 4431 4432 #if defined(DUAL_CORE) 4433 #define IS_RCC_SCOPE_WWDG(WWDG) (((WWDG) == RCC_WWDG1) || \ 4434 ((WWDG) == RCC_WWDG2)) 4435 #else 4436 #define IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1) 4437 4438 #endif /*DUAL_CORE*/ 4439 4440 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \ 4441 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 4442 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \ 4443 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN)) 4444 4445 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 4446 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 4447 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 4448 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 4449 4450 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 4451 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 4452 4453 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 4454 4455 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 4456 4457 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) 4458 4459 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 4460 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 4461 /** 4462 * @} 4463 */ 4464 4465 /** 4466 * @} 4467 */ 4468 4469 /** 4470 * @} 4471 */ 4472 4473 /** 4474 * @} 4475 */ 4476 4477 #ifdef __cplusplus 4478 } 4479 #endif 4480 4481 #endif /* STM32H7xx_HAL_RCC_EX_H */ 4482 4483
