1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_qspi.h 4 * @author MCD Application Team 5 * @brief Header file of QSPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H7xx_HAL_QSPI_H 21 #define STM32H7xx_HAL_QSPI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h7xx_hal_def.h" 29 30 #if defined(QUADSPI) 31 32 /** @addtogroup STM32H7xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup QSPI 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup QSPI_Exported_Types QSPI Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief QSPI Init structure definition 47 */ 48 typedef struct 49 { 50 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. 51 This parameter can be a number between 0 and 255 */ 52 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) 53 This parameter can be a value between 1 and 32 */ 54 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to 55 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) 56 This parameter can be a value of @ref QSPI_SampleShifting */ 57 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits 58 required to address the flash memory. The flash capacity can be up to 4GB 59 (addressed using 32 bits) in indirect mode, but the addressable space in 60 memory-mapped mode is limited to 256MB 61 This parameter can be a number between 0 and 31 */ 62 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number 63 of clock cycles which the chip select must remain high between commands. 64 This parameter can be a value of @ref QSPI_ChipSelectHighTime */ 65 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. 66 This parameter can be a value of @ref QSPI_ClockMode */ 67 uint32_t FlashID; /* Specifies the Flash which will be used, 68 This parameter can be a value of @ref QSPI_Flash_Select */ 69 uint32_t DualFlash; /* Specifies the Dual Flash Mode State 70 This parameter can be a value of @ref QSPI_DualFlash_Mode */ 71 }QSPI_InitTypeDef; 72 73 /** 74 * @brief HAL QSPI State structures definition 75 */ 76 typedef enum 77 { 78 HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ 79 HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ 80 HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ 81 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ 82 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ 83 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ 84 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ 85 HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ 86 HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ 87 }HAL_QSPI_StateTypeDef; 88 89 /** 90 * @brief QSPI Handle Structure definition 91 */ 92 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 93 typedef struct __QSPI_HandleTypeDef 94 #else 95 typedef struct 96 #endif 97 { 98 QUADSPI_TypeDef *Instance; /* QSPI registers base address */ 99 QSPI_InitTypeDef Init; /* QSPI communication parameters */ 100 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ 101 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ 102 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ 103 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ 104 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ 105 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ 106 MDMA_HandleTypeDef *hmdma; /* QSPI Rx/Tx MDMA Handle parameters */ 107 __IO HAL_LockTypeDef Lock; /* Locking object */ 108 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ 109 __IO uint32_t ErrorCode; /* QSPI Error code */ 110 uint32_t Timeout; /* Timeout for the QSPI memory access */ 111 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 112 void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi); 113 void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 114 void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi); 115 void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 116 void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 117 void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 118 void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi); 119 void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi); 120 121 void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 122 void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 123 #endif 124 }QSPI_HandleTypeDef; 125 126 /** 127 * @brief QSPI Command structure definition 128 */ 129 typedef struct 130 { 131 uint32_t Instruction; /* Specifies the Instruction to be sent 132 This parameter can be a value (8-bit) between 0x00 and 0xFF */ 133 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) 134 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 135 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) 136 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 137 uint32_t AddressSize; /* Specifies the Address Size 138 This parameter can be a value of @ref QSPI_AddressSize */ 139 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size 140 This parameter can be a value of @ref QSPI_AlternateBytesSize */ 141 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. 142 This parameter can be a number between 0 and 31 */ 143 uint32_t InstructionMode; /* Specifies the Instruction Mode 144 This parameter can be a value of @ref QSPI_InstructionMode */ 145 uint32_t AddressMode; /* Specifies the Address Mode 146 This parameter can be a value of @ref QSPI_AddressMode */ 147 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode 148 This parameter can be a value of @ref QSPI_AlternateBytesMode */ 149 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) 150 This parameter can be a value of @ref QSPI_DataMode */ 151 uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes) 152 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length 153 until end of memory)*/ 154 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase 155 This parameter can be a value of @ref QSPI_DdrMode */ 156 uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data 157 output by one half of system clock in DDR mode. 158 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ 159 uint32_t SIOOMode; /* Specifies the send instruction only once mode 160 This parameter can be a value of @ref QSPI_SIOOMode */ 161 }QSPI_CommandTypeDef; 162 163 /** 164 * @brief QSPI Auto Polling mode configuration structure definition 165 */ 166 typedef struct 167 { 168 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. 169 This parameter can be any value between 0 and 0xFFFFFFFF */ 170 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. 171 This parameter can be any value between 0 and 0xFFFFFFFF */ 172 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. 173 This parameter can be any value between 0 and 0xFFFF */ 174 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. 175 This parameter can be any value between 1 and 4 */ 176 uint32_t MatchMode; /* Specifies the method used for determining a match. 177 This parameter can be a value of @ref QSPI_MatchMode */ 178 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. 179 This parameter can be a value of @ref QSPI_AutomaticStop */ 180 }QSPI_AutoPollingTypeDef; 181 182 /** 183 * @brief QSPI Memory Mapped mode configuration structure definition 184 */ 185 typedef struct 186 { 187 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. 188 This parameter can be any value between 0 and 0xFFFF */ 189 uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. 190 This parameter can be a value of @ref QSPI_TimeOutActivation */ 191 }QSPI_MemoryMappedTypeDef; 192 193 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 194 /** 195 * @brief HAL QSPI Callback ID enumeration definition 196 */ 197 typedef enum 198 { 199 HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */ 200 HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */ 201 HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */ 202 HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */ 203 HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */ 204 HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */ 205 HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */ 206 HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */ 207 208 HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */ 209 HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */ 210 }HAL_QSPI_CallbackIDTypeDef; 211 212 /** 213 * @brief HAL QSPI Callback pointer definition 214 */ 215 typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); 216 #endif 217 /** 218 * @} 219 */ 220 221 /* Exported constants --------------------------------------------------------*/ 222 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants 223 * @{ 224 */ 225 226 /** @defgroup QSPI_ErrorCode QSPI Error Code 227 * @{ 228 */ 229 #define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ 230 #define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ 231 #define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ 232 #define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ 233 #define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ 234 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 235 #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */ 236 #endif 237 /** 238 * @} 239 */ 240 241 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting 242 * @{ 243 */ 244 #define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/ 245 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ 246 /** 247 * @} 248 */ 249 250 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time 251 * @{ 252 */ 253 #define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/ 254 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ 255 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ 256 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ 257 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ 258 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ 259 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ 260 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ 261 /** 262 * @} 263 */ 264 265 /** @defgroup QSPI_ClockMode QSPI Clock Mode 266 * @{ 267 */ 268 #define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/ 269 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ 270 /** 271 * @} 272 */ 273 274 /** @defgroup QSPI_Flash_Select QSPI Flash Select 275 * @{ 276 */ 277 #define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/ 278 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/ 279 /** 280 * @} 281 */ 282 283 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode 284 * @{ 285 */ 286 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/ 287 #define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/ 288 /** 289 * @} 290 */ 291 292 /** @defgroup QSPI_AddressSize QSPI Address Size 293 * @{ 294 */ 295 #define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/ 296 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ 297 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ 298 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ 299 /** 300 * @} 301 */ 302 303 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size 304 * @{ 305 */ 306 #define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/ 307 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ 308 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ 309 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ 310 /** 311 * @} 312 */ 313 314 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode 315 * @{ 316 */ 317 #define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/ 318 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ 319 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ 320 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ 321 /** 322 * @} 323 */ 324 325 /** @defgroup QSPI_AddressMode QSPI Address Mode 326 * @{ 327 */ 328 #define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/ 329 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ 330 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ 331 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ 332 /** 333 * @} 334 */ 335 336 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode 337 * @{ 338 */ 339 #define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/ 340 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ 341 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ 342 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ 343 /** 344 * @} 345 */ 346 347 /** @defgroup QSPI_DataMode QSPI Data Mode 348 * @{ 349 */ 350 #define QSPI_DATA_NONE 0x00000000U /*!<No data*/ 351 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ 352 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ 353 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ 354 /** 355 * @} 356 */ 357 358 /** @defgroup QSPI_DdrMode QSPI DDR Mode 359 * @{ 360 */ 361 #define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/ 362 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ 363 /** 364 * @} 365 */ 366 367 /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay 368 * @{ 369 */ 370 #define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/ 371 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/ 372 /** 373 * @} 374 */ 375 376 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode 377 * @{ 378 */ 379 #define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/ 380 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ 381 /** 382 * @} 383 */ 384 385 /** @defgroup QSPI_MatchMode QSPI Match Mode 386 * @{ 387 */ 388 #define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/ 389 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ 390 /** 391 * @} 392 */ 393 394 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop 395 * @{ 396 */ 397 #define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/ 398 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ 399 /** 400 * @} 401 */ 402 403 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation 404 * @{ 405 */ 406 #define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/ 407 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ 408 /** 409 * @} 410 */ 411 412 /** @defgroup QSPI_Flags QSPI Flags 413 * @{ 414 */ 415 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ 416 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ 417 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ 418 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ 419 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ 420 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ 421 /** 422 * @} 423 */ 424 425 /** @defgroup QSPI_Interrupts QSPI Interrupts 426 * @{ 427 */ 428 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ 429 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ 430 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ 431 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ 432 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ 433 /** 434 * @} 435 */ 436 437 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition 438 * @brief QSPI Timeout definition 439 * @{ 440 */ 441 #define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */ 442 /** 443 * @} 444 */ 445 446 /** 447 * @} 448 */ 449 450 /* Exported macros -----------------------------------------------------------*/ 451 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros 452 * @{ 453 */ 454 /** @brief Reset QSPI handle state. 455 * @param __HANDLE__ QSPI handle. 456 * @retval None 457 */ 458 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 459 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 460 (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \ 461 (__HANDLE__)->MspInitCallback = NULL; \ 462 (__HANDLE__)->MspDeInitCallback = NULL; \ 463 } while(0) 464 #else 465 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) 466 #endif 467 468 /** @brief Enable the QSPI peripheral. 469 * @param __HANDLE__ specifies the QSPI Handle. 470 * @retval None 471 */ 472 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 473 474 /** @brief Disable the QSPI peripheral. 475 * @param __HANDLE__ specifies the QSPI Handle. 476 * @retval None 477 */ 478 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 479 480 /** @brief Enable the specified QSPI interrupt. 481 * @param __HANDLE__ specifies the QSPI Handle. 482 * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. 483 * This parameter can be one of the following values: 484 * @arg QSPI_IT_TO: QSPI Timeout interrupt 485 * @arg QSPI_IT_SM: QSPI Status match interrupt 486 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 487 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 488 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 489 * @retval None 490 */ 491 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 492 493 494 /** @brief Disable the specified QSPI interrupt. 495 * @param __HANDLE__ specifies the QSPI Handle. 496 * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. 497 * This parameter can be one of the following values: 498 * @arg QSPI_IT_TO: QSPI Timeout interrupt 499 * @arg QSPI_IT_SM: QSPI Status match interrupt 500 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 501 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 502 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 503 * @retval None 504 */ 505 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 506 507 /** @brief Check whether the specified QSPI interrupt source is enabled or not. 508 * @param __HANDLE__ specifies the QSPI Handle. 509 * @param __INTERRUPT__ specifies the QSPI interrupt source to check. 510 * This parameter can be one of the following values: 511 * @arg QSPI_IT_TO: QSPI Timeout interrupt 512 * @arg QSPI_IT_SM: QSPI Status match interrupt 513 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 514 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 515 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 516 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 517 */ 518 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 519 520 /** 521 * @brief Check whether the selected QSPI flag is set or not. 522 * @param __HANDLE__ specifies the QSPI Handle. 523 * @param __FLAG__ specifies the QSPI flag to check. 524 * This parameter can be one of the following values: 525 * @arg QSPI_FLAG_BUSY: QSPI Busy flag 526 * @arg QSPI_FLAG_TO: QSPI Timeout flag 527 * @arg QSPI_FLAG_SM: QSPI Status match flag 528 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag 529 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 530 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 531 * @retval None 532 */ 533 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) 534 535 /** @brief Clears the specified QSPI's flag status. 536 * @param __HANDLE__ specifies the QSPI Handle. 537 * @param __FLAG__ specifies the QSPI clear register flag that needs to be set 538 * This parameter can be one of the following values: 539 * @arg QSPI_FLAG_TO: QSPI Timeout flag 540 * @arg QSPI_FLAG_SM: QSPI Status match flag 541 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 542 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 543 * @retval None 544 */ 545 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 546 /** 547 * @} 548 */ 549 550 /* Exported functions --------------------------------------------------------*/ 551 /** @addtogroup QSPI_Exported_Functions 552 * @{ 553 */ 554 555 /** @addtogroup QSPI_Exported_Functions_Group1 556 * @{ 557 */ 558 /* Initialization/de-initialization functions ********************************/ 559 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); 560 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); 561 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); 562 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); 563 /** 564 * @} 565 */ 566 567 /** @addtogroup QSPI_Exported_Functions_Group2 568 * @{ 569 */ 570 /* IO operation functions *****************************************************/ 571 /* QSPI IRQ handler method */ 572 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); 573 574 /* QSPI indirect mode */ 575 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); 576 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 577 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 578 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); 579 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 580 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 581 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 582 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 583 584 /* QSPI status flag polling mode */ 585 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 586 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); 587 588 /* QSPI memory-mapped mode */ 589 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); 590 591 /* Callback functions in non-blocking modes ***********************************/ 592 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); 593 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); 594 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); 595 596 /* QSPI indirect mode */ 597 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); 598 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); 599 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); 600 601 /* QSPI status flag polling mode */ 602 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); 603 604 /* QSPI memory-mapped mode */ 605 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); 606 607 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 608 /* QSPI callback registering/unregistering */ 609 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback); 610 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId); 611 #endif 612 /** 613 * @} 614 */ 615 616 /** @addtogroup QSPI_Exported_Functions_Group3 617 * @{ 618 */ 619 /* Peripheral Control and State functions ************************************/ 620 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); 621 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); 622 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); 623 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); 624 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); 625 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); 626 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); 627 HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID); 628 /** 629 * @} 630 */ 631 632 /** 633 * @} 634 */ 635 /* End of exported functions -------------------------------------------------*/ 636 637 /* Private macros ------------------------------------------------------------*/ 638 /** @defgroup QSPI_Private_Macros QSPI Private Macros 639 * @{ 640 */ 641 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) 642 643 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U)) 644 645 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ 646 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) 647 648 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) 649 650 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ 651 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ 652 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ 653 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ 654 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ 655 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ 656 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ 657 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) 658 659 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ 660 ((CLKMODE) == QSPI_CLOCK_MODE_3)) 661 662 #define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \ 663 ((FLASH_ID) == QSPI_FLASH_ID_2)) 664 665 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ 666 ((MODE) == QSPI_DUALFLASH_DISABLE)) 667 668 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) 669 670 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ 671 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ 672 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ 673 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) 674 675 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ 676 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ 677 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ 678 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) 679 680 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) 681 682 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ 683 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ 684 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ 685 ((MODE) == QSPI_INSTRUCTION_4_LINES)) 686 687 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ 688 ((MODE) == QSPI_ADDRESS_1_LINE) || \ 689 ((MODE) == QSPI_ADDRESS_2_LINES) || \ 690 ((MODE) == QSPI_ADDRESS_4_LINES)) 691 692 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ 693 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ 694 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ 695 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) 696 697 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ 698 ((MODE) == QSPI_DATA_1_LINE) || \ 699 ((MODE) == QSPI_DATA_2_LINES) || \ 700 ((MODE) == QSPI_DATA_4_LINES)) 701 702 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ 703 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) 704 705 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ 706 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) 707 708 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ 709 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) 710 711 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) 712 713 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 714 715 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ 716 ((MODE) == QSPI_MATCH_MODE_OR)) 717 718 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ 719 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) 720 721 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ 722 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) 723 724 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 725 /** 726 * @} 727 */ 728 /* End of private macros -----------------------------------------------------*/ 729 730 /** 731 * @} 732 */ 733 734 /** 735 * @} 736 */ 737 738 #endif /* defined(QUADSPI) */ 739 740 #ifdef __cplusplus 741 } 742 #endif 743 744 #endif /* STM32H7xx_HAL_QSPI_H */ 745
