1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_pwr_ex.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H7xx_HAL_PWR_EX_H 21 #define STM32H7xx_HAL_PWR_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif /* __cplusplus */ 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h7xx_hal_def.h" 29 30 /** @addtogroup STM32H7xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup PWREx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup PWREx_Exported_Types PWREx Exported Types 40 * @{ 41 */ 42 /** 43 * @brief PWREx AVD configuration structure definition 44 */ 45 typedef struct 46 { 47 uint32_t AVDLevel; /*!< AVDLevel : Specifies the AVD detection level. This 48 parameter can be a value of @ref 49 PWREx_AVD_detection_level 50 */ 51 52 uint32_t Mode; /*!< Mode : Specifies the EXTI operating mode for the AVD 53 event. This parameter can be a value of @ref 54 PWREx_AVD_Mode. 55 */ 56 }PWREx_AVDTypeDef; 57 58 /** 59 * @brief PWREx Wakeup pin configuration structure definition 60 */ 61 typedef struct 62 { 63 uint32_t WakeUpPin; /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled. 64 This parameter can be a value of @ref 65 PWREx_WakeUp_Pins 66 */ 67 68 uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity. 69 This parameter can be a value of @ref 70 PWREx_PIN_Polarity 71 */ 72 73 uint32_t PinPull; /*!< PinPull: Specifies the Wake-Up pin pull. This 74 parameter can be a value of @ref 75 PWREx_PIN_Pull 76 */ 77 }PWREx_WakeupPinTypeDef; 78 79 #if defined (PWR_CSR1_MMCVDO) 80 /** 81 * @brief PWR VDDMMC voltage level enum definition 82 */ 83 typedef enum 84 { 85 PWR_MMC_VOLTAGE_BELOW_1V2, /*!< VDDMMC is below 1V2 */ 86 PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2 /*!< VDDMMC is above or equal 1V2 */ 87 } PWREx_MMC_VoltageLevel; 88 #endif /* defined (PWR_CSR1_MMCVDO) */ 89 90 /** 91 * @} 92 */ 93 94 /* Exported constants --------------------------------------------------------*/ 95 96 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants 97 * @{ 98 */ 99 /** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins 100 * @{ 101 */ 102 /* High level and No pull (default configuration) */ 103 #define PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 104 #if defined (PWR_WKUPEPR_WKUPEN5) 105 #define PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 106 #endif /* defined (PWR_WKUPEPR_WKUPEN5) */ 107 #define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 108 #if defined (PWR_WKUPEPR_WKUPEN3) 109 #define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 110 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */ 111 #define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 112 #define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 113 114 /* High level and No pull */ 115 #define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6 116 #if defined (PWR_WKUPEPR_WKUPEN5) 117 #define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5 118 #endif /* defined (PWR_WKUPEPR_WKUPEN5) */ 119 #define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4 120 #if defined (PWR_WKUPEPR_WKUPEN3) 121 #define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3 122 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */ 123 #define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2 124 #define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1 125 126 /* Low level and No pull */ 127 #define PWR_WAKEUP_PIN6_LOW (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6) 128 #if defined (PWR_WKUPEPR_WKUPP5) 129 #define PWR_WAKEUP_PIN5_LOW (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5) 130 #endif /* defined (PWR_WKUPEPR_WKUPP5) */ 131 #define PWR_WAKEUP_PIN4_LOW (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4) 132 #if defined (PWR_WKUPEPR_WKUPP3) 133 #define PWR_WAKEUP_PIN3_LOW (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3) 134 #endif /* defined (PWR_WKUPEPR_WKUPP3) */ 135 #define PWR_WAKEUP_PIN2_LOW (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2) 136 #define PWR_WAKEUP_PIN1_LOW (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1) 137 /** 138 * @} 139 */ 140 141 /** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration 142 * @{ 143 */ 144 #define PWR_PIN_POLARITY_HIGH (0x00000000U) 145 #define PWR_PIN_POLARITY_LOW (0x00000001U) 146 /** 147 * @} 148 */ 149 150 /** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration 151 * @{ 152 */ 153 #define PWR_PIN_NO_PULL (0x00000000U) 154 #define PWR_PIN_PULL_UP (0x00000001U) 155 #define PWR_PIN_PULL_DOWN (0x00000002U) 156 /** 157 * @} 158 */ 159 160 /** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags. 161 * @{ 162 */ 163 #define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0 */ 164 #define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2 */ 165 #if defined (PWR_WKUPFR_WKUPF3) 166 #define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8 */ 167 #endif /* defined (PWR_WKUPFR_WKUPF3) */ 168 #define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */ 169 #if defined (PWR_WKUPFR_WKUPF5) 170 #define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */ 171 #endif /* defined (PWR_WKUPFR_WKUPF5) */ 172 #define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1 */ 173 #if defined (PWR_WKUPFR_WKUPF3) 174 #define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\ 175 PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4 |\ 176 PWR_WKUPFR_WKUPF5 | PWR_WKUPFR_WKUPF6) 177 #else 178 #define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\ 179 PWR_WKUPFR_WKUPF4 | PWR_WKUPFR_WKUPF6) 180 #endif /* defined (PWR_WKUPFR_WKUPF3) */ 181 /** 182 * @} 183 */ 184 185 #if defined (DUAL_CORE) 186 /** @defgroup PWREx_Core_Select PWREx Core definition 187 * @{ 188 */ 189 #define PWR_CORE_CPU1 (0x00000000U) 190 #define PWR_CORE_CPU2 (0x00000001U) 191 /** 192 * @} 193 */ 194 #endif /* defined (DUAL_CORE) */ 195 196 /** @defgroup PWREx_Domains PWREx Domains definition 197 * @{ 198 */ 199 #define PWR_D1_DOMAIN (0x00000000U) 200 #if defined (PWR_CPUCR_PDDS_D2) 201 #define PWR_D2_DOMAIN (0x00000001U) 202 #endif /* defined (PWR_CPUCR_PDDS_D2) */ 203 #define PWR_D3_DOMAIN (0x00000002U) 204 /** 205 * @} 206 */ 207 208 /** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition 209 * @{ 210 */ 211 #if defined (DUAL_CORE) 212 #define PWR_D1_DOMAIN_FLAGS (0x00000000U) 213 #define PWR_D2_DOMAIN_FLAGS (0x00000001U) 214 #define PWR_ALL_DOMAIN_FLAGS (0x00000002U) 215 #else 216 #define PWR_CPU_FLAGS (0x00000000U) 217 #endif /* defined (DUAL_CORE) */ 218 /** 219 * @} 220 */ 221 222 /** @defgroup PWREx_D3_State PWREx D3 Domain State 223 * @{ 224 */ 225 #define PWR_D3_DOMAIN_STOP (0x00000000U) 226 #define PWR_D3_DOMAIN_RUN (0x00000800U) 227 228 /** 229 * @} 230 */ 231 232 /** @defgroup PWREx_Supply_configuration PWREx Supply configuration 233 * @{ 234 */ 235 #define PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are supplied from the LDO */ 236 #if defined (SMPS) 237 #define PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are supplied from the SMPS only */ 238 #define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */ 239 #define PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */ 240 #define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ 241 #define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ 242 #define PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */ 243 #define PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */ 244 #endif /* defined (SMPS) */ 245 #define PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source */ 246 247 #if defined (SMPS) 248 #define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \ 249 PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS) 250 #else 251 #define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS) 252 #endif /* defined (SMPS) */ 253 /** 254 * @} 255 */ 256 257 258 /** @defgroup PWREx_AVD_detection_level PWREx AVD detection level 259 * @{ 260 */ 261 #define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog voltage detector level 0 262 selection : 1V7 */ 263 #define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog voltage detector level 1 264 selection : 2V1 */ 265 #define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog voltage detector level 2 266 selection : 2V5 */ 267 #define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog voltage detector level 3 268 selection : 2V8 */ 269 /** 270 * @} 271 */ 272 273 /** @defgroup PWREx_AVD_Mode PWREx AVD Mode 274 * @{ 275 */ 276 #define PWR_AVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ 277 #define PWR_AVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ 278 #define PWR_AVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ 279 #define PWR_AVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 280 #define PWR_AVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ 281 #define PWR_AVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ 282 #define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ 283 /** 284 * @} 285 */ 286 287 /** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale 288 * @{ 289 */ 290 #define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0) 291 #define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1) 292 #define PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) 293 /** 294 * @} 295 */ 296 297 /** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection 298 * @{ 299 */ 300 #define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor */ 301 #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ 302 /** 303 * @} 304 */ 305 306 /** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds 307 * @{ 308 */ 309 #define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U) 310 #define PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL 311 #define PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH 312 /** 313 * @} 314 */ 315 316 /** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds 317 * @{ 318 */ 319 #define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U) 320 #define PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL 321 #define PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH 322 /** 323 * @} 324 */ 325 /** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16 326 * @{ 327 */ 328 #define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16 329 Connected to the AVD EXTI Line */ 330 /** 331 * @} 332 */ 333 334 #if defined (PWR_CR1_SRDRAMSO) 335 /** @defgroup PWREx_Memory_Shut_Off Memory shut-off block selection 336 * @{ 337 */ 338 #define PWR_SRD_AHB_MEMORY_BLOCK PWR_CR1_SRDRAMSO /*!< SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode */ 339 #define PWR_USB_FDCAN_MEMORY_BLOCK PWR_CR1_HSITFSO /*!< High-speed interfaces USB and FDCAN memories shut-off in DStop/DStop2 mode */ 340 #define PWR_GFXMMU_JPEG_MEMORY_BLOCK PWR_CR1_GFXSO /*!< GFXMMU and JPEG memories shut-off in DStop/DStop2 mode */ 341 #define PWR_TCM_ECM_MEMORY_BLOCK PWR_CR1_ITCMSO /*!< Instruction TCM and ETM memories shut-off in DStop/DStop2 mode */ 342 #define PWR_RAM1_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM1SO /*!< AHB RAM1 shut-off in DStop/DStop2 mode */ 343 #define PWR_RAM2_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM2SO /*!< AHB RAM2 shut-off in DStop/DStop2 mode */ 344 #define PWR_RAM1_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM1SO /*!< AXI RAM1 shut-off in DStop/DStop2 mode */ 345 #define PWR_RAM2_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM2SO /*!< AXI RAM2 shut-off in DStop/DStop2 mode */ 346 #define PWR_RAM3_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM3SO /*!< AXI RAM3 shut-off in DStop/DStop2 mode */ 347 #define PWR_MEMORY_BLOCK_KEEP_ON 0U /*!< Memory content is kept in DStop or DStop2 mode */ 348 #define PWR_MEMORY_BLOCK_SHUT_OFF 1U /*!< Memory content is lost in DStop or DStop2 mode */ 349 /** 350 * @} 351 */ 352 #endif /* defined (PWR_CR1_SRDRAMSO) */ 353 /** 354 * @} 355 */ 356 357 /* Exported macro ------------------------------------------------------------*/ 358 359 /** @defgroup PWREx_Exported_Macro PWREx Exported Macro 360 * @{ 361 */ 362 363 /** 364 * @brief Enable the AVD EXTI Line 16. 365 * @retval None. 366 */ 367 #define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) 368 369 #if defined (DUAL_CORE) 370 /** 371 * @brief Enable the AVD EXTI D2 Line 16. 372 * @retval None. 373 */ 374 #define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD) 375 #endif /* defined (DUAL_CORE) */ 376 377 /** 378 * @brief Disable the AVD EXTI Line 16 379 * @retval None. 380 */ 381 #define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) 382 383 #if defined (DUAL_CORE) 384 /** 385 * @brief Disable the AVD EXTI D2 Line 16. 386 * @retval None. 387 */ 388 #define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD) 389 #endif /* defined (DUAL_CORE) */ 390 391 /** 392 * @brief Enable event on AVD EXTI Line 16. 393 * @retval None. 394 */ 395 #define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) 396 397 #if defined (DUAL_CORE) 398 /** 399 * @brief Enable event on AVD EXTI D2 Line 16. 400 * @retval None. 401 */ 402 #define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD) 403 #endif /* defined (DUAL_CORE) */ 404 405 /** 406 * @brief Disable event on AVD EXTI Line 16. 407 * @retval None. 408 */ 409 #define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) 410 411 #if defined (DUAL_CORE) 412 /** 413 * @brief Disable event on AVD EXTI D2 Line 16. 414 * @retval None. 415 */ 416 #define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD) 417 #endif /* defined (DUAL_CORE) */ 418 419 /** 420 * @brief Enable the AVD Extended Interrupt Rising Trigger. 421 * @retval None. 422 */ 423 #define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) 424 425 /** 426 * @brief Disable the AVD Extended Interrupt Rising Trigger. 427 * @retval None. 428 */ 429 #define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) 430 431 /** 432 * @brief Enable the AVD Extended Interrupt Falling Trigger. 433 * @retval None. 434 */ 435 #define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) 436 437 /** 438 * @brief Disable the AVD Extended Interrupt Falling Trigger. 439 * @retval None. 440 */ 441 #define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) 442 443 /** 444 * @brief Enable the AVD Extended Interrupt Rising and Falling Trigger. 445 * @retval None. 446 */ 447 #define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ 448 do { \ 449 __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \ 450 __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \ 451 } while(0); 452 453 /** 454 * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger. 455 * @retval None. 456 */ 457 #define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ 458 do { \ 459 __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \ 460 __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \ 461 } while(0); 462 463 /** 464 * @brief Check whether the specified AVD EXTI interrupt flag is set or not. 465 * @retval EXTI AVD Line Status. 466 */ 467 #define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL) 468 469 #if defined (DUAL_CORE) 470 /** 471 * @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not. 472 * @retval EXTI D2 AVD Line Status. 473 */ 474 #define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL) 475 #endif /* defined (DUAL_CORE) */ 476 477 /** 478 * @brief Clear the AVD EXTI flag. 479 * @retval None. 480 */ 481 #define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) 482 483 #if defined (DUAL_CORE) 484 /** 485 * @brief Clear the AVD EXTI D2 flag. 486 * @retval None. 487 */ 488 #define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) 489 #endif /* defined (DUAL_CORE) */ 490 491 /** 492 * @brief Generates a Software interrupt on AVD EXTI line. 493 * @retval None. 494 */ 495 #define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD) 496 /** 497 * @} 498 */ 499 500 /* Exported functions --------------------------------------------------------*/ 501 502 /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions 503 * @{ 504 */ 505 506 /** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions 507 * @{ 508 */ 509 HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource); 510 uint32_t HAL_PWREx_GetSupplyConfig (void); 511 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling); 512 uint32_t HAL_PWREx_GetVoltageRange (void); 513 HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling); 514 uint32_t HAL_PWREx_GetStopModeVoltageRange (void); 515 /** 516 * @} 517 */ 518 519 /** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions 520 * @{ 521 */ 522 /* System low power control functions */ 523 #if defined (PWR_CPUCR_RETDS_CD) 524 void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry); 525 #endif /* defined (PWR_CPUCR_RETDS_CD) */ 526 void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain); 527 void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain); 528 void HAL_PWREx_ConfigD3Domain (uint32_t D3State); 529 /* Clear Cortex-Mx pending flag */ 530 void HAL_PWREx_ClearPendingEvent (void); 531 #if defined (DUAL_CORE) 532 /* Clear domain flags */ 533 void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags); 534 /* Core Hold/Release functions */ 535 HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU); 536 void HAL_PWREx_ReleaseCore (uint32_t CPU); 537 #endif /* defined (DUAL_CORE) */ 538 /* Flash low power control functions */ 539 void HAL_PWREx_EnableFlashPowerDown (void); 540 void HAL_PWREx_DisableFlashPowerDown (void); 541 #if defined (PWR_CR1_SRDRAMSO) 542 /* Memory shut-off functions */ 543 void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock); 544 void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock); 545 #endif /* defined(PWR_CR1_SRDRAMSO) */ 546 /* Wakeup Pins control functions */ 547 void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams); 548 void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin); 549 uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag); 550 HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag); 551 /* Power Wakeup PIN IRQ Handler */ 552 void HAL_PWREx_WAKEUP_PIN_IRQHandler (void); 553 void HAL_PWREx_WKUP1_Callback (void); 554 void HAL_PWREx_WKUP2_Callback (void); 555 #if defined (PWR_WKUPEPR_WKUPEN3) 556 void HAL_PWREx_WKUP3_Callback (void); 557 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */ 558 void HAL_PWREx_WKUP4_Callback (void); 559 #if defined (PWR_WKUPEPR_WKUPEN5) 560 void HAL_PWREx_WKUP5_Callback (void); 561 #endif /* defined (PWR_WKUPEPR_WKUPEN5) */ 562 void HAL_PWREx_WKUP6_Callback (void); 563 /** 564 * @} 565 */ 566 567 /** @addtogroup PWREx_Exported_Functions_Group3 Peripherals control functions 568 * @{ 569 */ 570 /* Backup regulator control functions */ 571 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void); 572 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void); 573 /* USB regulator control functions */ 574 HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void); 575 HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void); 576 void HAL_PWREx_EnableUSBVoltageDetector (void); 577 void HAL_PWREx_DisableUSBVoltageDetector (void); 578 /* Battery control functions */ 579 void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue); 580 void HAL_PWREx_DisableBatteryCharging (void); 581 #if defined (PWR_CR1_BOOSTE) 582 /* Analog Booster functions */ 583 void HAL_PWREx_EnableAnalogBooster (void); 584 void HAL_PWREx_DisableAnalogBooster (void); 585 #endif /* PWR_CR1_BOOSTE */ 586 /** 587 * @} 588 */ 589 590 /** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions 591 * @{ 592 */ 593 /* Power VBAT/Temperature monitoring functions */ 594 void HAL_PWREx_EnableMonitoring (void); 595 void HAL_PWREx_DisableMonitoring (void); 596 uint32_t HAL_PWREx_GetTemperatureLevel (void); 597 uint32_t HAL_PWREx_GetVBATLevel (void); 598 #if defined (PWR_CSR1_MMCVDO) 599 PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void); 600 #endif /* PWR_CSR1_MMCVDO */ 601 /* Power AVD configuration functions */ 602 void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD); 603 void HAL_PWREx_EnableAVD (void); 604 void HAL_PWREx_DisableAVD (void); 605 /* Power PVD/AVD IRQ Handler */ 606 void HAL_PWREx_PVD_AVD_IRQHandler (void); 607 void HAL_PWREx_AVDCallback (void); 608 /** 609 * @} 610 */ 611 612 /** 613 * @} 614 */ 615 /* Private types -------------------------------------------------------------*/ 616 /* Private variables ---------------------------------------------------------*/ 617 /* Private constants ---------------------------------------------------------*/ 618 /* Private macros ------------------------------------------------------------*/ 619 /** @defgroup PWREx_Private_Macros PWREx Private Macros 620 * @{ 621 */ 622 623 /** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters 624 * @{ 625 */ 626 /* Check PWR regulator configuration parameter */ 627 #if defined (SMPS) 628 #define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ 629 ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY) ||\ 630 ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO) ||\ 631 ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO) ||\ 632 ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\ 633 ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||\ 634 ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT) ||\ 635 ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT) ||\ 636 ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY)) 637 638 #else 639 #define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ 640 ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY)) 641 #endif /* defined (SMPS) */ 642 643 /* Check PWR regulator configuration in STOP mode parameter */ 644 #define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3) ||\ 645 ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4) ||\ 646 ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5)) 647 648 /* Check PWR domain parameter */ 649 #if defined (PWR_CPUCR_PDDS_D2) 650 #define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\ 651 ((DOMAIN) == PWR_D2_DOMAIN) ||\ 652 ((DOMAIN) == PWR_D3_DOMAIN)) 653 #else 654 #define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\ 655 ((DOMAIN) == PWR_D3_DOMAIN)) 656 #endif /* defined (PWR_CPUCR_PDDS_D2) */ 657 658 /* Check D3/SRD domain state parameter */ 659 #define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) ||\ 660 ((STATE) == PWR_D3_DOMAIN_RUN)) 661 662 /* Check wake up pin parameter */ 663 #if defined (PWR_WKUPEPR_WKUPEN3) 664 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\ 665 ((PIN) == PWR_WAKEUP_PIN2) ||\ 666 ((PIN) == PWR_WAKEUP_PIN3) ||\ 667 ((PIN) == PWR_WAKEUP_PIN4) ||\ 668 ((PIN) == PWR_WAKEUP_PIN5) ||\ 669 ((PIN) == PWR_WAKEUP_PIN6) ||\ 670 ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\ 671 ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\ 672 ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\ 673 ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\ 674 ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\ 675 ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\ 676 ((PIN) == PWR_WAKEUP_PIN1_LOW) ||\ 677 ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ 678 ((PIN) == PWR_WAKEUP_PIN3_LOW) ||\ 679 ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\ 680 ((PIN) == PWR_WAKEUP_PIN5_LOW) ||\ 681 ((PIN) == PWR_WAKEUP_PIN6_LOW)) 682 #else 683 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\ 684 ((PIN) == PWR_WAKEUP_PIN2) ||\ 685 ((PIN) == PWR_WAKEUP_PIN4) ||\ 686 ((PIN) == PWR_WAKEUP_PIN6) ||\ 687 ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\ 688 ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\ 689 ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\ 690 ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\ 691 ((PIN) == PWR_WAKEUP_PIN1_LOW) ||\ 692 ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ 693 ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\ 694 ((PIN) == PWR_WAKEUP_PIN6_LOW)) 695 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */ 696 697 /* Check wake up pin polarity parameter */ 698 #define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\ 699 ((POLARITY) == PWR_PIN_POLARITY_LOW)) 700 701 /* Check wake up pin pull configuration parameter */ 702 #define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\ 703 ((PULL) == PWR_PIN_PULL_UP) ||\ 704 ((PULL) == PWR_PIN_PULL_DOWN)) 705 706 /* Check wake up flag parameter */ 707 #if defined (PWR_WKUPEPR_WKUPEN3) 708 #define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\ 709 ((FLAG) == PWR_WAKEUP_FLAG2) ||\ 710 ((FLAG) == PWR_WAKEUP_FLAG3) ||\ 711 ((FLAG) == PWR_WAKEUP_FLAG4) ||\ 712 ((FLAG) == PWR_WAKEUP_FLAG5) ||\ 713 ((FLAG) == PWR_WAKEUP_FLAG6) ||\ 714 ((FLAG) == PWR_WAKEUP_FLAG_ALL)) 715 #else 716 #define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\ 717 ((FLAG) == PWR_WAKEUP_FLAG2) ||\ 718 ((FLAG) == PWR_WAKEUP_FLAG4) ||\ 719 ((FLAG) == PWR_WAKEUP_FLAG6) ||\ 720 ((FLAG) == PWR_WAKEUP_FLAG_ALL)) 721 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */ 722 723 /* Check wake up flag parameter */ 724 #define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) ||\ 725 ((LEVEL) == PWR_AVDLEVEL_1) ||\ 726 ((LEVEL) == PWR_AVDLEVEL_2) ||\ 727 ((LEVEL) == PWR_AVDLEVEL_3)) 728 729 /* Check AVD mode parameter */ 730 #define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING) ||\ 731 ((MODE) == PWR_AVD_MODE_IT_FALLING) ||\ 732 ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\ 733 ((MODE) == PWR_AVD_MODE_EVENT_RISING) ||\ 734 ((MODE) == PWR_AVD_MODE_EVENT_FALLING) ||\ 735 ((MODE) == PWR_AVD_MODE_NORMAL) ||\ 736 ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING)) 737 738 /* Check resistor battery parameter */ 739 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ 740 ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) 741 /* Check D1/CD CPU ID parameter */ 742 #define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID) 743 744 #if defined (DUAL_CORE) 745 /* Check CPU parameter */ 746 #define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2)) 747 748 /* Check D2 CPU ID parameter */ 749 #define IS_PWR_D2_CPU(CPU) ((CPU) == CM4_CPUID) 750 751 /* Check PWR domain flag parameter */ 752 #define IS_PWR_DOMAIN_FLAG(FLAG) (((FLAG) == PWR_D1_DOMAIN_FLAGS) || \ 753 ((FLAG) == PWR_D2_DOMAIN_FLAGS) || \ 754 ((FLAG) == PWR_ALL_DOMAIN_FLAGS)) 755 #endif /* defined (DUAL_CORE) */ 756 757 #if defined (PWR_CR1_SRDRAMSO) 758 /* Check memory block parameter */ 759 #define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_SRD_AHB_MEMORY_BLOCK) || \ 760 ((BLOCK) == PWR_USB_FDCAN_MEMORY_BLOCK) || \ 761 ((BLOCK) == PWR_GFXMMU_JPEG_MEMORY_BLOCK) || \ 762 ((BLOCK) == PWR_TCM_ECM_MEMORY_BLOCK) || \ 763 ((BLOCK) == PWR_RAM1_AHB_MEMORY_BLOCK) || \ 764 ((BLOCK) == PWR_RAM2_AHB_MEMORY_BLOCK) || \ 765 ((BLOCK) == PWR_RAM1_AXI_MEMORY_BLOCK) || \ 766 ((BLOCK) == PWR_RAM2_AXI_MEMORY_BLOCK) || \ 767 ((BLOCK) == PWR_RAM3_AXI_MEMORY_BLOCK)) 768 #endif /* defined (PWR_CR1_SRDRAMSO) */ 769 /** 770 * @} 771 */ 772 /** 773 * @} 774 */ 775 776 /** 777 * @} 778 */ 779 780 /** 781 * @} 782 */ 783 #ifdef __cplusplus 784 } 785 #endif /* __cplusplus */ 786 787 788 #endif /* STM32H7xx_HAL_PWR_EX_H */ 789 790
