1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_pwr.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H7xx_HAL_PWR_H 21 #define STM32H7xx_HAL_PWR_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif /* __cplusplus */ 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h7xx_hal_def.h" 29 30 /** @addtogroup STM32H7xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup PWR 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup PWR_Exported_Types PWR Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief PWR PVD configuration structure definition 46 */ 47 typedef struct 48 { 49 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This 50 parameter can be a value of @ref 51 PWR_PVD_detection_level. 52 */ 53 54 uint32_t Mode; /*!< Mode: Specifies the EXTI operating mode for the PVD 55 event. This parameter can be a value of @ref 56 PWR_PVD_Mode. 57 */ 58 }PWR_PVDTypeDef; 59 60 /** 61 * @} 62 */ 63 64 /* Exported constants --------------------------------------------------------*/ 65 /** @defgroup PWR_Exported_Constants PWR Exported Constants 66 * @{ 67 */ 68 69 /** @defgroup PWR_PVD_detection_level PWR PVD detection level 70 * @{ 71 */ 72 #define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Programmable voltage detector 73 level 0 selection : 1V95 */ 74 #define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Programmable voltage detector 75 level 1 selection : 2V1 */ 76 #define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Programmable voltage detector 77 level 2 selection : 2V25 */ 78 #define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Programmable voltage detector 79 level 3 selection : 2V4 */ 80 #define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Programmable voltage detector 81 level 4 selection : 2V55 */ 82 #define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Programmable voltage detector 83 level 5 selection : 2V7 */ 84 #define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Programmable voltage detector 85 level 6 selection : 2V85 */ 86 #define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External input analog voltage 87 (Compare internally to VREF) */ 88 /** 89 * @} 90 */ 91 92 /** @defgroup PWR_PVD_Mode PWR PVD Mode 93 * @{ 94 */ 95 #define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ 96 #define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection */ 97 #define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection */ 98 #define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */ 99 #define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ 100 #define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ 101 #define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ 102 /** 103 * @} 104 */ 105 106 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode 107 * @{ 108 */ 109 #define PWR_MAINREGULATOR_ON (0U) 110 #define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS 111 /** 112 * @} 113 */ 114 115 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry 116 * @{ 117 */ 118 #define PWR_SLEEPENTRY_WFI (0x01U) 119 #define PWR_SLEEPENTRY_WFE (0x02U) 120 /** 121 * @} 122 */ 123 124 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry 125 * @{ 126 */ 127 #define PWR_STOPENTRY_WFI (0x01U) 128 #define PWR_STOPENTRY_WFE (0x02U) 129 /** 130 * @} 131 */ 132 133 /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale 134 * @{ 135 */ 136 #if defined(PWR_SRDCR_VOS) 137 #define PWR_REGULATOR_VOLTAGE_SCALE0 (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0) 138 #define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_SRDCR_VOS_1) 139 #define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_SRDCR_VOS_0) 140 #define PWR_REGULATOR_VOLTAGE_SCALE3 (0U) 141 #else 142 #define PWR_REGULATOR_VOLTAGE_SCALE0 (0U) 143 #define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0) 144 #define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1) 145 #define PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0) 146 #endif /* PWR_SRDCR_VOS */ 147 /** 148 * @} 149 */ 150 151 /** @defgroup PWR_Flag PWR Flag 152 * @{ 153 */ 154 /* PWR CPU flag */ 155 #define PWR_FLAG_STOP (0x01U) 156 #if defined (PWR_CPUCR_SBF_D2) 157 #define PWR_FLAG_SB_D1 (0x02U) 158 #define PWR_FLAG_SB_D2 (0x03U) 159 #endif /* defined (PWR_CPUCR_SBF_D2) */ 160 #define PWR_FLAG_SB (0x04U) 161 #if defined (DUAL_CORE) 162 #define PWR_FLAG_CPU_HOLD (0x05U) 163 #define PWR_FLAG_CPU2_HOLD (0x06U) 164 #define PWR_FLAG2_STOP (0x07U) 165 #define PWR_FLAG2_SB_D1 (0x08U) 166 #define PWR_FLAG2_SB_D2 (0x09U) 167 #define PWR_FLAG2_SB (0x0AU) 168 #endif /* defined (DUAL_CORE) */ 169 #define PWR_FLAG_PVDO (0x0BU) 170 #define PWR_FLAG_AVDO (0x0CU) 171 #define PWR_FLAG_ACTVOSRDY (0x0DU) 172 #define PWR_FLAG_ACTVOS (0x0EU) 173 #define PWR_FLAG_BRR (0x0FU) 174 #define PWR_FLAG_VOSRDY (0x10U) 175 #if defined (SMPS) 176 #define PWR_FLAG_SMPSEXTRDY (0x11U) 177 #else 178 #define PWR_FLAG_SCUEN (0x11U) 179 #endif /* defined (SMPS) */ 180 #if defined (PWR_CSR1_MMCVDO) 181 #define PWR_FLAG_MMCVDO (0x12U) 182 #endif /* defined (PWR_CSR1_MMCVDO) */ 183 #define PWR_FLAG_USB33RDY (0x13U) 184 #define PWR_FLAG_TEMPH (0x14U) 185 #define PWR_FLAG_TEMPL (0x15U) 186 #define PWR_FLAG_VBATH (0x16U) 187 #define PWR_FLAG_VBATL (0x17U) 188 189 /* PWR Wake up flag */ 190 #define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1 191 #define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2 192 #define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3 193 #define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4 194 #define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5 195 #define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6 196 /** 197 * @} 198 */ 199 200 /** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask 201 * @{ 202 */ 203 #define PWR_EWUP_MASK (0x0FFF3F3FU) 204 /** 205 * @} 206 */ 207 208 /** 209 * @} 210 */ 211 /* Exported macro ------------------------------------------------------------*/ 212 /** @defgroup PWR_Exported_Macro PWR Exported Macro 213 * @{ 214 */ 215 216 /** @brief Configure the main internal regulator output voltage. 217 * @param __REGULATOR__ : Specifies the regulator output voltage to achieve a 218 * trade-off between performance and power consumption 219 * when the device does not operate at the maximum 220 * frequency (refer to the datasheet for more details). 221 * This parameter can be one of the following values: 222 * @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output 223 * Scale 0 mode. 224 * @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output 225 * Scale 1 mode. 226 * @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output 227 * Scale 2 mode. 228 * @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output 229 * Scale 3 mode. 230 * @note For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is 231 * only possible when Vcore is supplied from LDO (Low DropOut). The 232 * SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE() 233 * macro before configuring Voltage Scale 0 using 234 * __HAL_PWR_VOLTAGESCALING_CONFIG(). 235 * Transition to Voltage Scale 0 is only possible when the system is 236 * already in Voltage Scale 1. 237 * Transition from Voltage Scale 0 is only possible to Voltage Scale 1 238 * then once in Voltage Scale 1 it is possible to switch to another 239 * voltage scale. 240 * After each regulator voltage setting, wait on VOSRDY flag to be set 241 * using macro __HAL_PWR_GET_FLAG(). 242 * To enter low power mode , and if current regulator voltage is 243 * Voltage Scale 0 then first switch to Voltage Scale 1 before entering 244 * low power mode. 245 * @retval None. 246 */ 247 #if defined (PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */ 248 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ 249 do { \ 250 __IO uint32_t tmpreg = 0x00; \ 251 /* Configure the Voltage Scaling */ \ 252 MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__)); \ 253 /* Delay after setting the voltage scaling */ \ 254 tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS); \ 255 UNUSED(tmpreg); \ 256 } while(0) 257 #else /* 3 power domains devices */ 258 #if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */ 259 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ 260 do { \ 261 __IO uint32_t tmpreg = 0x00; \ 262 /* Check the voltage scaling to be configured */ \ 263 if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0) \ 264 { \ 265 /* Configure the Voltage Scaling 1 */ \ 266 MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); \ 267 /* Delay after setting the voltage scaling */ \ 268 tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ 269 /* Enable the PWR overdrive */ \ 270 SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ 271 /* Delay after setting the syscfg boost setting */ \ 272 tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ 273 } \ 274 else \ 275 { \ 276 /* Disable the PWR overdrive */ \ 277 CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ 278 /* Delay after setting the syscfg boost setting */ \ 279 tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ 280 /* Configure the Voltage Scaling x */ \ 281 MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \ 282 /* Delay after setting the voltage scaling */ \ 283 tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ 284 } \ 285 UNUSED(tmpreg); \ 286 } while(0) 287 #else /* STM32H72xxx and STM32H73xxx lines */ 288 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ 289 do { \ 290 __IO uint32_t tmpreg = 0x00; \ 291 /* Configure the Voltage Scaling */ \ 292 MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \ 293 /* Delay after setting the voltage scaling */ \ 294 tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ 295 UNUSED(tmpreg); \ 296 } while(0) 297 #endif /* defined(SYSCFG_PWRCR_ODEN) */ 298 #endif /* defined (PWR_SRDCR_VOS) */ 299 300 /** @brief Check PWR flags are set or not. 301 * @param __FLAG__ : Specifies the flag to check. 302 * This parameter can be one of the following values: 303 * @arg PWR_FLAG_PVDO : PVD Output. This flag is valid only if PVD 304 * is enabled by the HAL_PWR_EnablePVD() 305 * function. 306 * The PVD is stopped by STANDBY mode. For this 307 * reason, this bit is equal to 0 after STANDBY 308 * or reset until the PVDE bit is set. 309 * @arg PWR_FLAG_AVDO : AVD Output. This flag is valid only if AVD 310 * is enabled by the HAL_PWREx_EnableAVD() 311 * function. The AVD is stopped by STANDBY mode. 312 * For this reason, this bit is equal to 0 313 * after STANDBY or reset until the AVDE bit 314 * is set. 315 * @arg PWR_FLAG_ACTVOSRDY : This flag indicates that the Regulator 316 * voltage scaling output selection is 317 * ready. 318 * @arg PWR_FLAG_BRR : Backup regulator ready flag. This bit is not 319 * reset when the device wakes up from STANDBY 320 * mode or by a system reset or power-on reset. 321 * @arg PWR_FLAG_VOSRDY : This flag indicates that the Regulator 322 * voltage scaling output selection is ready. 323 * mode or by a system reset or power-on reset. 324 * @arg PWR_FLAG_USB33RDY : This flag indicates that the USB supply 325 * from regulator is ready. 326 * @arg PWR_FLAG_TEMPH : This flag indicates that the temperature 327 * equal or above high threshold level. 328 * @arg PWR_FLAG_TEMPL : This flag indicates that the temperature 329 * equal or below low threshold level. 330 * @arg PWR_FLAG_VBATH : This flag indicates that VBAT level equal 331 * or above high threshold level. 332 * @arg PWR_FLAG_VBATL : This flag indicates that VBAT level equal 333 * or below low threshold level. 334 * @arg PWR_FLAG_STOP : This flag indicates that the system entered 335 * in STOP mode. 336 * @arg PWR_FLAG_SB : This flag indicates that the system entered in 337 * STANDBY mode. 338 * @arg PWR_FLAG_SB_D1 : This flag indicates that the D1 domain 339 * entered in STANDBY mode. 340 * @arg PWR_FLAG_SB_D2 : This flag indicates that the D2 domain 341 * entered in STANDBY mode. 342 * @arg PWR_FLAG2_STOP : This flag indicates that the system entered 343 * in STOP mode. 344 * @arg PWR_FLAG2_SB : This flag indicates that the system entered 345 * in STANDBY mode. 346 * @arg PWR_FLAG2_SB_D1 : This flag indicates that the D1 domain 347 * entered in STANDBY mode. 348 * @arg PWR_FLAG2_SB_D2 : This flag indicates that the D2 domain 349 * entered in STANDBY mode. 350 * @arg PWR_FLAG_CPU_HOLD : This flag indicates that the CPU1 wakes 351 * up with hold. 352 * @arg PWR_FLAG_CPU2_HOLD : This flag indicates that the CPU2 wakes 353 * up with hold. 354 * @arg PWR_FLAG_SMPSEXTRDY : This flag indicates that the SMPS 355 * External supply is sready. 356 * @arg PWR_FLAG_SCUEN : This flag indicates that the supply 357 * configuration update is enabled. 358 * @arg PWR_FLAG_MMCVDO : This flag indicates that the VDDMMC is 359 * above or equal to 1.2 V. 360 * @note The PWR_FLAG_PVDO, PWR_FLAG_AVDO, PWR_FLAG_ACTVOSRDY, PWR_FLAG_BRR, 361 * PWR_FLAG_VOSRDY, PWR_FLAG_USB33RDY, PWR_FLAG_TEMPH, PWR_FLAG_TEMPL, 362 * PWR_FLAG_VBATH, PWR_FLAG_VBATL, PWR_FLAG_STOP and PWR_FLAG_SB flags 363 * are used for all H7 family lines. 364 * The PWR_FLAG2_STOP, PWR_FLAG2_SB, PWR_FLAG2_SB_D1, PWR_FLAG2_SB_D2, 365 * PWR_FLAG_CPU_HOLD and PWR_FLAG_CPU2_HOLD flags are used only for H7 366 * dual core lines. 367 * The PWR_FLAG_SB_D1 and PWR_FLAG_SB_D2 flags are used for all H7 368 * family except STM32H7Axxx and STM32H7Bxxx lines. 369 * The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and 370 * STM32H7Bxxx lines. 371 * The PWR_FLAG_SCUEN flag is used for devices that support only LDO 372 * regulator. 373 * The PWR_FLAG_SMPSEXTRDY flag is used for devices that support LDO 374 * and SMPS regulators. 375 * @retval The (__FLAG__) state (TRUE or FALSE). 376 */ 377 #if defined (DUAL_CORE) /* Dual core lines */ 378 #define __HAL_PWR_GET_FLAG(__FLAG__) \ 379 (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ 380 ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ 381 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ 382 ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\ 383 ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) :\ 384 ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ 385 ((__FLAG__) == PWR_FLAG_CPU_HOLD) ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F) :\ 386 ((__FLAG__) == PWR_FLAG_CPU2_HOLD) ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F) == PWR_CPUCR_HOLD2F) :\ 387 ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ 388 ((__FLAG__) == PWR_FLAG2_SB) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF) == PWR_CPU2CR_SBF) :\ 389 ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ 390 ((__FLAG__) == PWR_FLAG2_STOP) ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF) == PWR_CPU2CR_STOPF) :\ 391 ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\ 392 ((__FLAG__) == PWR_FLAG2_SB_D1) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1) :\ 393 ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\ 394 ((__FLAG__) == PWR_FLAG2_SB_D2) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2) :\ 395 ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ 396 ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ 397 ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ 398 ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ 399 ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) 400 #else /* Single core lines */ 401 #if defined (PWR_CPUCR_SBF_D2) /* STM32H72x, STM32H73x, STM32H74x and STM32H75x lines */ 402 #if defined (SMPS) /* STM32H725 and STM32H735 lines */ 403 #define __HAL_PWR_GET_FLAG(__FLAG__) \ 404 (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ 405 ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ 406 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ 407 ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\ 408 ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_FLAG_SMPSEXTRDY) == PWR_FLAG_SMPSEXTRDY) :\ 409 ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ 410 ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ 411 ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ 412 ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\ 413 ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\ 414 ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ 415 ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ 416 ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ 417 ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ 418 ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) 419 #else /* STM32H723, STM32H733, STM32H742, STM32H743, STM32H750 and STM32H753 lines */ 420 #define __HAL_PWR_GET_FLAG(__FLAG__) \ 421 (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ 422 ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ 423 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ 424 ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\ 425 ((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) :\ 426 ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ 427 ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ 428 ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ 429 ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\ 430 ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\ 431 ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ 432 ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ 433 ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ 434 ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ 435 ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) 436 #endif /* defined (SMPS) */ 437 #else /* STM32H7Axxx and STM32H7Bxxx lines */ 438 #if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ lines */ 439 #define __HAL_PWR_GET_FLAG(__FLAG__) \ 440 (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ 441 ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ 442 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ 443 ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ 444 ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY) == PWR_SRDCR_VOSRDY) :\ 445 ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ 446 ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ 447 ((__FLAG__) == PWR_FLAG_MMCVDO) ? ((PWR->CSR1 & PWR_CSR1_MMCVDO) == PWR_CSR1_MMCVDO) :\ 448 ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) :\ 449 ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ 450 ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ 451 ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ 452 ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ 453 ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) 454 #else /* STM32H7Axx and STM32H7Bxx lines */ 455 #define __HAL_PWR_GET_FLAG(__FLAG__) \ 456 (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ 457 ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ 458 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ 459 ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ 460 ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY) == PWR_SRDCR_VOSRDY) :\ 461 ((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) :\ 462 ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ 463 ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ 464 ((__FLAG__) == PWR_FLAG_MMCVDO) ? ((PWR->CSR1 & PWR_CSR1_MMCVDO) == PWR_CSR1_MMCVDO) :\ 465 ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ 466 ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ 467 ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ 468 ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ 469 ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) 470 #endif /* SMPS */ 471 #endif /* PWR_CPUCR_SBF_D2 */ 472 #endif /* DUAL_CORE */ 473 474 /** @brief Check PWR wake up flags are set or not. 475 * @param __FLAG__: specifies the wake up flag to check. 476 * This parameter can be one of the following values: 477 * @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag. 478 * @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag. 479 * @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag. 480 * @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag. 481 * @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag. 482 * @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag. 483 * @note The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices 484 * that support GPIOI port. 485 * @retval The (__FLAG__) state (TRUE or FALSE). 486 */ 487 #define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1) 488 489 #if defined (DUAL_CORE) 490 /** @brief Clear CPU PWR flags. 491 * @param __FLAG__ : Specifies the flag to clear. 492 * @note This parameter is not used for the STM32H7 family and is kept as 493 * parameter just to maintain compatibility with other families. 494 * @note This macro clear all CPU flags STOPF, SBF, SBF_D1, and SBF_D2. 495 * This parameter can be one of the following values : 496 * @arg PWR_CPU_FLAGS : Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2 497 * CPU flags. 498 * @retval None. 499 */ 500 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) \ 501 do { \ 502 SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); \ 503 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \ 504 } while(0) 505 #else 506 /** @brief Clear CPU PWR flags. 507 * @param __FLAG__ : Specifies the flag to clear. 508 * @note This parameter is not used for the STM32H7 family and is kept as 509 * parameter just to maintain compatibility with other families. 510 * @note This macro clear all CPU flags. 511 * For single core devices except STM32H7Axxx and STM32H7Bxxx, CPU 512 * flags are STOPF, SBF, SBF_D1 and SBF_D2. 513 * For STM32H7Axxx and STM32H7Bxxx lines, CPU flags are STOPF and SBF. 514 * @retval None. 515 */ 516 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF) 517 #endif /* defined (DUAL_CORE) */ 518 519 /** @brief Clear PWR wake up flags. 520 * @param __FLAG__ : Specifies the wake up flag to be cleared. 521 * This parameter can be one of the following values : 522 * @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag. 523 * @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag. 524 * @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag. 525 * @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag. 526 * @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag. 527 * @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag. 528 * @note The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices 529 * that support GPIOI port. 530 * @retval None. 531 */ 532 #define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__)) 533 534 /** 535 * @brief Enable the PVD EXTI Line 16. 536 * @retval None. 537 */ 538 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) 539 540 #if defined (DUAL_CORE) 541 /** 542 * @brief Enable the PVD EXTI D2 Line 16. 543 * @retval None. 544 */ 545 #define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD) 546 #endif /* defined (DUAL_CORE) */ 547 548 /** 549 * @brief Disable the PVD EXTI Line 16. 550 * @retval None. 551 */ 552 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) 553 554 #if defined (DUAL_CORE) 555 /** 556 * @brief Disable the PVD EXTI D2 Line 16. 557 * @retval None. 558 */ 559 #define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD) 560 #endif /* defined (DUAL_CORE) */ 561 562 /** 563 * @brief Enable event on PVD EXTI Line 16. 564 * @retval None. 565 */ 566 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) 567 568 #if defined (DUAL_CORE) 569 /** 570 * @brief Enable event on PVD EXTI D2 Line. 571 * @retval None. 572 */ 573 #define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD) 574 #endif /* defined (DUAL_CORE) */ 575 576 /** 577 * @brief Disable event on PVD EXTI Line 16. 578 * @retval None. 579 */ 580 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) 581 582 #if defined (DUAL_CORE) 583 /** 584 * @brief Disable event on PVD EXTI D2 Line. 585 * @retval None. 586 */ 587 #define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD) 588 #endif /* defined (DUAL_CORE) */ 589 590 /** 591 * @brief Enable the PVD Rising Interrupt Trigger. 592 * @retval None. 593 */ 594 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) 595 596 /** 597 * @brief Disable the PVD Rising Interrupt Trigger. 598 * @retval None. 599 */ 600 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) 601 602 /** 603 * @brief Enable the PVD Falling Interrupt Trigger. 604 * @retval None. 605 */ 606 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) 607 608 /** 609 * @brief Disable the PVD Falling Interrupt Trigger. 610 * @retval None. 611 */ 612 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) 613 614 /** 615 * @brief Enable the PVD Rising & Falling Interrupt Trigger. 616 * @retval None. 617 */ 618 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ 619 do { \ 620 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ 621 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ 622 } while(0); 623 624 /** 625 * @brief Disable the PVD Rising & Falling Interrupt Trigger. 626 * @retval None. 627 */ 628 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ 629 do { \ 630 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ 631 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ 632 } while(0); 633 634 /** 635 * @brief Check whether the specified PVD EXTI interrupt flag is set or not. 636 * @retval EXTI PVD Line Status. 637 */ 638 #define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL) 639 640 #if defined (DUAL_CORE) 641 /** 642 * @brief Checks whether the specified PVD EXTI interrupt flag is set or not. 643 * @retval EXTI D2 PVD Line Status. 644 */ 645 #define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL) 646 #endif /* defined (DUAL_CORE) */ 647 648 /** 649 * @brief Clear the PVD EXTI flag. 650 * @retval None. 651 */ 652 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) 653 654 #if defined (DUAL_CORE) 655 /** 656 * @brief Clear the PVD EXTI D2 flag. 657 * @retval None. 658 */ 659 #define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) 660 #endif /* defined (DUAL_CORE) */ 661 662 /** 663 * @brief Generates a Software interrupt on PVD EXTI line. 664 * @retval None. 665 */ 666 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) 667 /** 668 * @} 669 */ 670 671 /* Include PWR HAL Extension module */ 672 #include "stm32h7xx_hal_pwr_ex.h" 673 674 /* Exported functions --------------------------------------------------------*/ 675 /** @addtogroup PWR_Exported_Functions PWR Exported Functions 676 * @{ 677 */ 678 679 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions 680 * @{ 681 */ 682 /* Initialization and de-initialization functions *****************************/ 683 void HAL_PWR_DeInit (void); 684 void HAL_PWR_EnableBkUpAccess (void); 685 void HAL_PWR_DisableBkUpAccess (void); 686 /** 687 * @} 688 */ 689 690 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control Functions 691 * @{ 692 */ 693 /* Peripheral Control functions **********************************************/ 694 /* PVD configuration */ 695 void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD); 696 void HAL_PWR_EnablePVD (void); 697 void HAL_PWR_DisablePVD (void); 698 699 /* WakeUp pins configuration */ 700 void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity); 701 void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx); 702 703 /* Low Power modes entry */ 704 void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry); 705 void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry); 706 void HAL_PWR_EnterSTANDBYMode (void); 707 708 /* Power PVD IRQ Handler */ 709 void HAL_PWR_PVD_IRQHandler (void); 710 void HAL_PWR_PVDCallback (void); 711 712 /* Cortex System Control functions *******************************************/ 713 void HAL_PWR_EnableSleepOnExit (void); 714 void HAL_PWR_DisableSleepOnExit (void); 715 void HAL_PWR_EnableSEVOnPend (void); 716 void HAL_PWR_DisableSEVOnPend (void); 717 /** 718 * @} 719 */ 720 721 /** 722 * @} 723 */ 724 725 /* Private types -------------------------------------------------------------*/ 726 /* Private variables ---------------------------------------------------------*/ 727 /* Private constants ---------------------------------------------------------*/ 728 /** @defgroup PWR_Private_Constants PWR Private Constants 729 * @{ 730 */ 731 732 /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line 733 * @{ 734 */ 735 #define PWR_EXTI_LINE_PVD EXTI_IMR1_IM16 /*!< External interrupt line 16 736 Connected to the PVD EXTI Line */ 737 /** 738 * @} 739 */ 740 741 /** 742 * @} 743 */ 744 /* Private macros ------------------------------------------------------------*/ 745 /** @defgroup PWR_Private_Macros PWR Private Macros 746 * @{ 747 */ 748 749 /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters 750 * @{ 751 */ 752 /* Check PVD level parameter */ 753 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) ||\ 754 ((LEVEL) == PWR_PVDLEVEL_1) ||\ 755 ((LEVEL) == PWR_PVDLEVEL_2) ||\ 756 ((LEVEL) == PWR_PVDLEVEL_3) ||\ 757 ((LEVEL) == PWR_PVDLEVEL_4) ||\ 758 ((LEVEL) == PWR_PVDLEVEL_5) ||\ 759 ((LEVEL) == PWR_PVDLEVEL_6) ||\ 760 ((LEVEL) == PWR_PVDLEVEL_7)) 761 762 /* Check PVD mode parameter */ 763 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING) ||\ 764 ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ 765 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ 766 ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ 767 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ 768 ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\ 769 ((MODE) == PWR_PVD_MODE_NORMAL)) 770 771 /* Check low power regulator parameter */ 772 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) ||\ 773 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) 774 775 /* Check low power mode entry parameter */ 776 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\ 777 ((ENTRY) == PWR_SLEEPENTRY_WFE)) 778 779 /* Check low power mode entry parameter */ 780 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\ 781 ((ENTRY) == PWR_STOPENTRY_WFE)) 782 783 /* Check voltage scale level parameter */ 784 #define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \ 785 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ 786 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ 787 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) 788 /** 789 * @} 790 */ 791 792 /** 793 * @} 794 */ 795 796 /** 797 * @} 798 */ 799 800 /** 801 * @} 802 */ 803 804 #ifdef __cplusplus 805 } 806 #endif /* __cplusplus */ 807 808 #endif /* STM32H7xx_HAL_PWR_H */ 809 810
