1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_fdcan.h 4 * @author MCD Application Team 5 * @brief Header file of FDCAN HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H7xx_HAL_FDCAN_H 21 #define STM32H7xx_HAL_FDCAN_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h7xx_hal_def.h" 29 30 #if defined(FDCAN1) 31 32 /** @addtogroup STM32H7xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup FDCAN 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup FDCAN_Exported_Types FDCAN Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief HAL State structures definition 47 */ 48 typedef enum 49 { 50 HAL_FDCAN_STATE_RESET = 0x00U, /*!< FDCAN not yet initialized or disabled */ 51 HAL_FDCAN_STATE_READY = 0x01U, /*!< FDCAN initialized and ready for use */ 52 HAL_FDCAN_STATE_BUSY = 0x02U, /*!< FDCAN process is ongoing */ 53 HAL_FDCAN_STATE_ERROR = 0x03U /*!< FDCAN error state */ 54 } HAL_FDCAN_StateTypeDef; 55 56 /** 57 * @brief FDCAN Init structure definition 58 */ 59 typedef struct 60 { 61 uint32_t FrameFormat; /*!< Specifies the FDCAN frame format. 62 This parameter can be a value of @ref FDCAN_frame_format */ 63 64 uint32_t Mode; /*!< Specifies the FDCAN mode. 65 This parameter can be a value of @ref FDCAN_operating_mode */ 66 67 FunctionalState AutoRetransmission; /*!< Enable or disable the automatic retransmission mode. 68 This parameter can be set to ENABLE or DISABLE */ 69 70 FunctionalState TransmitPause; /*!< Enable or disable the Transmit Pause feature. 71 This parameter can be set to ENABLE or DISABLE */ 72 73 FunctionalState ProtocolException; /*!< Enable or disable the Protocol Exception Handling. 74 This parameter can be set to ENABLE or DISABLE */ 75 76 uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator frequency is 77 divided for generating the nominal bit time quanta. 78 This parameter must be a number between 1 and 512 */ 79 80 uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN 81 hardware is allowed to lengthen or shorten a bit to perform 82 resynchronization. 83 This parameter must be a number between 1 and 128 */ 84 85 uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. 86 This parameter must be a number between 2 and 256 */ 87 88 uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. 89 This parameter must be a number between 2 and 128 */ 90 91 uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator frequency is 92 divided for generating the data bit time quanta. 93 This parameter must be a number between 1 and 32 */ 94 95 uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN 96 hardware is allowed to lengthen or shorten a data bit to 97 perform resynchronization. 98 This parameter must be a number between 1 and 16 */ 99 100 uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit Segment 1. 101 This parameter must be a number between 1 and 32 */ 102 103 uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit Segment 2. 104 This parameter must be a number between 1 and 16 */ 105 106 uint32_t MessageRAMOffset; /*!< Specifies the message RAM start address. 107 This parameter must be a number between 0 and 2560 */ 108 109 uint32_t StdFiltersNbr; /*!< Specifies the number of standard Message ID filters. 110 This parameter must be a number between 0 and 128 */ 111 112 uint32_t ExtFiltersNbr; /*!< Specifies the number of extended Message ID filters. 113 This parameter must be a number between 0 and 64 */ 114 115 uint32_t RxFifo0ElmtsNbr; /*!< Specifies the number of Rx FIFO0 Elements. 116 This parameter must be a number between 0 and 64 */ 117 118 uint32_t RxFifo0ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 0 element. 119 This parameter can be a value of @ref FDCAN_data_field_size */ 120 121 uint32_t RxFifo1ElmtsNbr; /*!< Specifies the number of Rx FIFO 1 Elements. 122 This parameter must be a number between 0 and 64 */ 123 124 uint32_t RxFifo1ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 1 element. 125 This parameter can be a value of @ref FDCAN_data_field_size */ 126 127 uint32_t RxBuffersNbr; /*!< Specifies the number of Dedicated Rx Buffer elements. 128 This parameter must be a number between 0 and 64 */ 129 130 uint32_t RxBufferSize; /*!< Specifies the Data Field Size in an Rx Buffer element. 131 This parameter can be a value of @ref FDCAN_data_field_size */ 132 133 uint32_t TxEventsNbr; /*!< Specifies the number of Tx Event FIFO elements. 134 This parameter must be a number between 0 and 32 */ 135 136 uint32_t TxBuffersNbr; /*!< Specifies the number of Dedicated Tx Buffers. 137 This parameter must be a number between 0 and 32 */ 138 139 uint32_t TxFifoQueueElmtsNbr; /*!< Specifies the number of Tx Buffers used for Tx FIFO/Queue. 140 This parameter must be a number between 0 and 32 */ 141 142 uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection. 143 This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */ 144 145 uint32_t TxElmtSize; /*!< Specifies the Data Field Size in a Tx Element. 146 This parameter can be a value of @ref FDCAN_data_field_size */ 147 148 } FDCAN_InitTypeDef; 149 150 /** 151 * @brief FDCAN clock calibration unit structure definition 152 */ 153 typedef struct 154 { 155 uint32_t ClockCalibration; /*!< Enable or disable the clock calibration. 156 This parameter can be a value of @ref FDCAN_clock_calibration. */ 157 158 uint32_t ClockDivider; /*!< Specifies the FDCAN kernel clock divider when the clock calibration 159 is bypassed. 160 This parameter can be a value of @ref FDCAN_clock_divider */ 161 162 uint32_t MinOscClkPeriods; /*!< Configures the minimum number of periods in two CAN bit times. The 163 actual configured number of periods is MinOscClkPeriods x 32. 164 This parameter must be a number between 0x00 and 0xFF */ 165 166 uint32_t CalFieldLength; /*!< Specifies the calibration field length. 167 This parameter can be a value of @ref FDCAN_calibration_field_length */ 168 169 uint32_t TimeQuantaPerBitTime; /*!< Configures the number of time quanta per bit time. 170 This parameter must be a number between 4 and 25 */ 171 172 uint32_t WatchdogStartValue; /*!< Start value of the Calibration Watchdog Counter. 173 If set to zero the counter is disabled. 174 This parameter must be a number between 0x0000 and 0xFFFF */ 175 176 } FDCAN_ClkCalUnitTypeDef; 177 178 /** 179 * @brief FDCAN filter structure definition 180 */ 181 typedef struct 182 { 183 uint32_t IdType; /*!< Specifies the identifier type. 184 This parameter can be a value of @ref FDCAN_id_type */ 185 186 uint32_t FilterIndex; /*!< Specifies the filter which will be initialized. 187 This parameter must be a number between: 188 - 0 and 127, if IdType is FDCAN_STANDARD_ID 189 - 0 and 63, if IdType is FDCAN_EXTENDED_ID */ 190 191 uint32_t FilterType; /*!< Specifies the filter type. 192 This parameter can be a value of @ref FDCAN_filter_type. 193 The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted 194 only when IdType is FDCAN_EXTENDED_ID. 195 This parameter is ignored if FilterConfig is set to 196 FDCAN_FILTER_TO_RXBUFFER */ 197 198 uint32_t FilterConfig; /*!< Specifies the filter configuration. 199 This parameter can be a value of @ref FDCAN_filter_config */ 200 201 uint32_t FilterID1; /*!< Specifies the filter identification 1. 202 This parameter must be a number between: 203 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 204 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 205 206 uint32_t FilterID2; /*!< Specifies the filter identification 2. 207 This parameter is ignored if FilterConfig is set to 208 FDCAN_FILTER_TO_RXBUFFER. 209 This parameter must be a number between: 210 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 211 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 212 213 uint32_t RxBufferIndex; /*!< Contains the index of the Rx buffer in which the 214 matching message will be stored. 215 This parameter must be a number between 0 and 63. 216 This parameter is ignored if FilterConfig is different 217 from FDCAN_FILTER_TO_RXBUFFER */ 218 219 uint32_t IsCalibrationMsg; /*!< Specifies whether the filter is configured for 220 calibration messages. 221 This parameter is ignored if FilterConfig is different 222 from FDCAN_FILTER_TO_RXBUFFER. 223 This parameter can be: 224 - 0 : ordinary message 225 - 1 : calibration message */ 226 227 } FDCAN_FilterTypeDef; 228 229 /** 230 * @brief FDCAN Tx header structure definition 231 */ 232 typedef struct 233 { 234 uint32_t Identifier; /*!< Specifies the identifier. 235 This parameter must be a number between: 236 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 237 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 238 239 uint32_t IdType; /*!< Specifies the identifier type for the message that will be 240 transmitted. 241 This parameter can be a value of @ref FDCAN_id_type */ 242 243 uint32_t TxFrameType; /*!< Specifies the frame type of the message that will be transmitted. 244 This parameter can be a value of @ref FDCAN_frame_type */ 245 246 uint32_t DataLength; /*!< Specifies the length of the frame that will be transmitted. 247 This parameter can be a value of @ref FDCAN_data_length_code */ 248 249 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 250 This parameter can be a value of @ref FDCAN_error_state_indicator */ 251 252 uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame will be transmitted with or without 253 bit rate switching. 254 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 255 256 uint32_t FDFormat; /*!< Specifies whether the Tx frame will be transmitted in classic or 257 FD format. 258 This parameter can be a value of @ref FDCAN_format */ 259 260 uint32_t TxEventFifoControl; /*!< Specifies the event FIFO control. 261 This parameter can be a value of @ref FDCAN_EFC */ 262 263 uint32_t MessageMarker; /*!< Specifies the message marker to be copied into Tx Event FIFO 264 element for identification of Tx message status. 265 This parameter must be a number between 0 and 0xFF */ 266 267 } FDCAN_TxHeaderTypeDef; 268 269 /** 270 * @brief FDCAN Rx header structure definition 271 */ 272 typedef struct 273 { 274 uint32_t Identifier; /*!< Specifies the identifier. 275 This parameter must be a number between: 276 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 277 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 278 279 uint32_t IdType; /*!< Specifies the identifier type of the received message. 280 This parameter can be a value of @ref FDCAN_id_type */ 281 282 uint32_t RxFrameType; /*!< Specifies the the received message frame type. 283 This parameter can be a value of @ref FDCAN_frame_type */ 284 285 uint32_t DataLength; /*!< Specifies the received frame length. 286 This parameter can be a value of @ref FDCAN_data_length_code */ 287 288 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 289 This parameter can be a value of @ref FDCAN_error_state_indicator */ 290 291 uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with or without bit 292 rate switching. 293 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 294 295 uint32_t FDFormat; /*!< Specifies whether the Rx frame is received in classic or FD 296 format. 297 This parameter can be a value of @ref FDCAN_format */ 298 299 uint32_t RxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame 300 reception. 301 This parameter must be a number between 0 and 0xFFFF */ 302 303 uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element. 304 This parameter must be a number between: 305 - 0 and 127, if IdType is FDCAN_STANDARD_ID 306 - 0 and 63, if IdType is FDCAN_EXTENDED_ID 307 When the frame is a Non-Filter matching frame, this parameter 308 is unused. */ 309 310 uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter. 311 Acceptance of non-matching frames may be enabled via 312 HAL_FDCAN_ConfigGlobalFilter(). 313 This parameter takes 0 if the frame matched an Rx filter or 314 1 if it did not match any Rx filter */ 315 316 } FDCAN_RxHeaderTypeDef; 317 318 /** 319 * @brief FDCAN Tx event FIFO structure definition 320 */ 321 typedef struct 322 { 323 uint32_t Identifier; /*!< Specifies the identifier. 324 This parameter must be a number between: 325 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 326 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 327 328 uint32_t IdType; /*!< Specifies the identifier type for the transmitted message. 329 This parameter can be a value of @ref FDCAN_id_type */ 330 331 uint32_t TxFrameType; /*!< Specifies the frame type of the transmitted message. 332 This parameter can be a value of @ref FDCAN_frame_type */ 333 334 uint32_t DataLength; /*!< Specifies the length of the transmitted frame. 335 This parameter can be a value of @ref FDCAN_data_length_code */ 336 337 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 338 This parameter can be a value of @ref FDCAN_error_state_indicator */ 339 340 uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame is transmitted with or without bit 341 rate switching. 342 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 343 344 uint32_t FDFormat; /*!< Specifies whether the Tx frame is transmitted in classic or FD 345 format. 346 This parameter can be a value of @ref FDCAN_format */ 347 348 uint32_t TxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame 349 transmission. 350 This parameter must be a number between 0 and 0xFFFF */ 351 352 uint32_t MessageMarker; /*!< Specifies the message marker copied into Tx Event FIFO element 353 for identification of Tx message status. 354 This parameter must be a number between 0 and 0xFF */ 355 356 uint32_t EventType; /*!< Specifies the event type. 357 This parameter can be a value of @ref FDCAN_event_type */ 358 359 } FDCAN_TxEventFifoTypeDef; 360 361 /** 362 * @brief FDCAN High Priority Message Status structure definition 363 */ 364 typedef struct 365 { 366 uint32_t FilterList; /*!< Specifies the filter list of the matching filter element. 367 This parameter can be: 368 - 0 : Standard Filter List 369 - 1 : Extended Filter List */ 370 371 uint32_t FilterIndex; /*!< Specifies the index of matching filter element. 372 This parameter can be a number between: 373 - 0 and 127, if FilterList is 0 (Standard) 374 - 0 and 63, if FilterList is 1 (Extended) */ 375 376 uint32_t MessageStorage; /*!< Specifies the HP Message Storage. 377 This parameter can be a value of @ref FDCAN_hp_msg_storage */ 378 379 uint32_t MessageIndex; /*!< Specifies the Index of Rx FIFO element to which the 380 message was stored. 381 This parameter is valid only when MessageStorage is: 382 FDCAN_HP_STORAGE_RXFIFO0 383 or 384 FDCAN_HP_STORAGE_RXFIFO1 */ 385 386 } FDCAN_HpMsgStatusTypeDef; 387 388 /** 389 * @brief FDCAN Protocol Status structure definition 390 */ 391 typedef struct 392 { 393 uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus. 394 This parameter can be a value of @ref FDCAN_protocol_error_code */ 395 396 uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format 397 frame with its BRS flag set. 398 This parameter can be a value of @ref FDCAN_protocol_error_code */ 399 400 uint32_t Activity; /*!< Specifies the FDCAN module communication state. 401 This parameter can be a value of @ref FDCAN_communication_state */ 402 403 uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status. 404 This parameter can be: 405 - 0 : The FDCAN is in Error_Active state 406 - 1 : The FDCAN is in Error_Passive state */ 407 408 uint32_t Warning; /*!< Specifies the FDCAN module warning status. 409 This parameter can be: 410 - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96 411 - 1 : at least one of error counters has reached the Error_Warning limit of 96 */ 412 413 uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status. 414 This parameter can be: 415 - 0 : The FDCAN is not in Bus_Off state 416 - 1 : The FDCAN is in Bus_Off state */ 417 418 uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message. 419 This parameter can be: 420 - 0 : Last received CAN FD message did not have its ESI flag set 421 - 1 : Last received CAN FD message had its ESI flag set */ 422 423 uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message. 424 This parameter can be: 425 - 0 : Last received CAN FD message did not have its BRS flag set 426 - 1 : Last received CAN FD message had its BRS flag set */ 427 428 uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status. 429 This parameter can be: 430 - 0 : no CAN FD message received 431 - 1 : CAN FD message received */ 432 433 uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status. 434 This parameter can be: 435 - 0 : No protocol exception event occurred since last read access 436 - 1 : Protocol exception event occurred */ 437 438 uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value. 439 This parameter can be a number between 0 and 127 */ 440 441 } FDCAN_ProtocolStatusTypeDef; 442 443 /** 444 * @brief FDCAN Error Counters structure definition 445 */ 446 typedef struct 447 { 448 uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value. 449 This parameter can be a number between 0 and 255 */ 450 451 uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value. 452 This parameter can be a number between 0 and 127 */ 453 454 uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status. 455 This parameter can be: 456 - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128 457 - 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */ 458 459 uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value. 460 This parameter can be a number between 0 and 255. 461 This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt 462 or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of 463 TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */ 464 465 } FDCAN_ErrorCountersTypeDef; 466 467 /** 468 * @brief FDCAN TT Init structure definition 469 */ 470 typedef struct 471 { 472 uint32_t OperationMode; /*!< Specifies the FDCAN Operation Mode. 473 This parameter can be a value of @ref FDCAN_operation_mode */ 474 475 uint32_t GapEnable; /*!< Specifies the FDCAN TT Operation. 476 This parameter can be a value of @ref FDCAN_TT_operation. 477 This parameter is ignored if OperationMode is set to 478 FDCAN_TT_COMMUNICATION_LEVEL0 */ 479 480 uint32_t TimeMaster; /*!< Specifies whether the instance is a slave or a potential master. 481 This parameter can be a value of @ref FDCAN_TT_time_master */ 482 483 uint32_t SyncDevLimit; /*!< Specifies the Synchronization Deviation Limit SDL of the TUR 484 numerator : TUR = (Numerator +/- SDL) / Denominator. 485 With : SDL = 2^(SyncDevLimit+5). 486 This parameter must be a number between 0 and 7 */ 487 488 uint32_t InitRefTrigOffset; /*!< Specifies the Initial Reference Trigger Offset. 489 This parameter must be a number between 0 and 127 */ 490 491 uint32_t ExternalClkSync; /*!< Enable or disable External Clock Synchronization. 492 This parameter can be a value of @ref FDCAN_TT_external_clk_sync. 493 This parameter is ignored if OperationMode is set to 494 FDCAN_TT_COMMUNICATION_LEVEL1 */ 495 496 uint32_t AppWdgLimit; /*!< Specifies the Application Watchdog Limit : maximum time after 497 which the application has to serve the application watchdog. 498 The application watchdog is incremented once each 256 NTUs. 499 The application watchdog can be disabled by setting AppWdgLimit to 0. 500 This parameter must be a number between 0 and 255. 501 This parameter is ignored if OperationMode is set to 502 FDCAN_TT_COMMUNICATION_LEVEL0 */ 503 504 uint32_t GlobalTimeFilter; /*!< Enable or disable Global Time Filtering. 505 This parameter can be a value of @ref FDCAN_TT_global_time_filtering. 506 This parameter is ignored if OperationMode is set to 507 FDCAN_TT_COMMUNICATION_LEVEL1 */ 508 509 uint32_t ClockCalibration; /*!< Enable or disable Automatic Clock Calibration. 510 This parameter can be a value of @ref FDCAN_TT_auto_clk_calibration. 511 This parameter is ignored if OperationMode is set to 512 FDCAN_TT_COMMUNICATION_LEVEL1 */ 513 514 uint32_t EvtTrigPolarity; /*!< Specifies the Event Trigger Polarity. 515 This parameter can be a value of @ref FDCAN_TT_event_trig_polarity. 516 This parameter is ignored if OperationMode is set to 517 FDCAN_TT_COMMUNICATION_LEVEL0 */ 518 519 uint32_t BasicCyclesNbr; /*!< Specifies the number of basic cycles in the system matrix. 520 This parameter can be a value of @ref FDCAN_TT_basic_cycle_number */ 521 522 uint32_t CycleStartSync; /*!< Enable or disable synchronization pulse output at pin fdcan1_soc. 523 This parameter can be a value of @ref FDCAN_TT_cycle_start_sync */ 524 525 uint32_t TxEnableWindow; /*!< Specifies the length of Tx enable window in NTUs. 526 This parameter must be a number between 1 and 16 */ 527 528 uint32_t ExpTxTrigNbr; /*!< Specifies the number of expected Tx_Triggers in the system matrix. 529 This is the sum of Tx_Triggers for exclusive, single arbitrating and 530 merged arbitrating windows. 531 This parameter must be a number between 0 and 4095 */ 532 533 uint32_t TURNumerator; /*!< Specifies the TUR (Time Unit Ratio) numerator. 534 It is advised to set this parameter to the largest applicable value. 535 This parameter must be a number between 0x10000 and 0x1FFFF */ 536 537 uint32_t TURDenominator; /*!< Specifies the TUR (Time Unit Ratio) denominator. 538 This parameter must be a number between 0x0001 and 0x3FFF */ 539 540 uint32_t TriggerMemoryNbr; /*!< Specifies the number of trigger memory elements. 541 This parameter must be a number between 0 and 64 */ 542 543 uint32_t StopWatchTrigSel; /*!< Specifies the input to be used as stop watch trigger. 544 This parameter can be a value of @ref FDCAN_TT_stop_watch_trig_selection */ 545 546 uint32_t EventTrigSel; /*!< Specifies the input to be used as event trigger. 547 This parameter can be a value of @ref FDCAN_TT_event_trig_selection */ 548 549 } FDCAN_TT_ConfigTypeDef; 550 551 /** 552 * @brief FDCAN Trigger structure definition 553 */ 554 typedef struct 555 { 556 uint32_t TriggerIndex; /*!< Specifies the trigger which will be configured. 557 This parameter must be a number between 0 and 63 */ 558 559 uint32_t TimeMark; /*!< Specifies the cycle time for which the trigger becomes active. 560 This parameter must be a number between 0 and 0xFFFF */ 561 562 uint32_t RepeatFactor; /*!< Specifies the trigger repeat factor. 563 This parameter can be a value of @ref FDCAN_TT_Repeat_Factor */ 564 565 uint32_t StartCycle; /*!< Specifies the index of the first cycle in which the trigger becomes active. 566 This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE. 567 This parameter must be a number between 0 and RepeatFactor */ 568 569 uint32_t TmEventInt; /*!< Enable or disable the internal time mark event. 570 If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element 571 becomes active. 572 This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_Internal */ 573 574 uint32_t TmEventExt; /*!< Enable or disable the external time mark event. 575 If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when 576 trigger memory element becomes active. 577 This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_External */ 578 579 uint32_t TriggerType; /*!< Specifies the trigger type. 580 This parameter can be a value of @ref FDCAN_TT_Trigger_Type */ 581 582 uint32_t FilterType; /*!< Specifies the filter identifier type. 583 This parameter can be a value of @ref FDCAN_id_type */ 584 585 uint32_t TxBufferIndex; /*!< Specifies the index of the Tx buffer for which the trigger is valid. 586 This parameter can be a value of @ref FDCAN_Tx_location. 587 This parameter is taken in consideration only if the trigger is configured for 588 transmission. */ 589 590 uint32_t FilterIndex; /*!< Specifies the filter for which the trigger is valid. 591 This parameter is taken in consideration only if the trigger is configured for 592 reception. 593 This parameter must be a number between: 594 - 0 and 127, if FilterType is FDCAN_STANDARD_ID 595 - 0 and 63, if FilterType is FDCAN_EXTENDED_ID */ 596 597 } FDCAN_TriggerTypeDef; 598 599 /** 600 * @brief FDCAN TT Operation Status structure definition 601 */ 602 typedef struct 603 { 604 uint32_t ErrorLevel; /*!< Specifies the type of the TT operation error level. 605 This parameter can be a value of @ref FDCAN_TT_error_level */ 606 607 uint32_t MasterState; /*!< Specifies the type of the TT master state. 608 This parameter can be a value of @ref FDCAN_TT_master_state */ 609 610 uint32_t SyncState; /*!< Specifies the type of the TT synchronization state. 611 This parameter can be a value of @ref FDCAN_TT_sync_state */ 612 613 uint32_t GTimeQuality; /*!< Specifies the Quality of Global Time Phase. 614 This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0. 615 This parameter can be: 616 - 0 : Global time not valid 617 - 1 : Global time in phase with Time Master */ 618 619 uint32_t ClockQuality; /*!< Specifies the Quality of Clock Speed. 620 This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1. 621 This parameter can be: 622 - 0 : Local clock speed not synchronized to Time Master clock speed 623 - 1 : Synchronization Deviation = SDL */ 624 625 uint32_t RefTrigOffset; /*!< Specifies the Actual Reference Trigger Offset Value. 626 This parameter can be a number between 0 and 0xFF */ 627 628 uint32_t GTimeDiscPending; /*!< Specifies the Global Time Discontinuity State. 629 This parameter can be: 630 - 0 : No global time preset pending 631 - 1 : Node waits for the global time preset to take effect */ 632 633 uint32_t GapFinished; /*!< Specifies whether a Gap is finished. 634 This parameter can be: 635 - 0 : Reset at the end of each reference message 636 - 1 : Gap finished */ 637 638 uint32_t MasterPriority; /*!< Specifies the Priority of actual Time Master. 639 This parameter can be a number between 0 and 0x7 */ 640 641 uint32_t GapStarted; /*!< Specifies whether a Gap is started. 642 This parameter can be: 643 - 0 : No Gap in schedule 644 - 1 : Gap time after Basic Cycle has started */ 645 646 uint32_t WaitForEvt; /*!< Specifies whether a Gap is announced. 647 This parameter can be: 648 - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0 649 - 1 : Reference message with Next_is_Gap = 1 received */ 650 651 uint32_t AppWdgEvt; /*!< Specifies the Application Watchdog State. 652 This parameter can be: 653 - 0 : Application Watchdog served in time 654 - 1 : Failed to serve Application Watchdog in time */ 655 656 uint32_t ECSPending; /*!< Specifies the External Clock Synchronization State. 657 This parameter can be: 658 - 0 : No external clock synchronization pending 659 - 1 : Node waits for external clock synchronization to take effect */ 660 661 uint32_t PhaseLock; /*!< Specifies the Phase Lock State. 662 This parameter can be: 663 - 0 : Phase outside range 664 - 1 : Phase inside range */ 665 666 } FDCAN_TTOperationStatusTypeDef; 667 668 /** 669 * @brief FDCAN Message RAM blocks 670 */ 671 typedef struct 672 { 673 uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address. 674 This parameter must be a 32-bit word address */ 675 676 uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address. 677 This parameter must be a 32-bit word address */ 678 679 uint32_t RxFIFO0SA; /*!< Specifies the Rx FIFO 0 Start Address. 680 This parameter must be a 32-bit word address */ 681 682 uint32_t RxFIFO1SA; /*!< Specifies the Rx FIFO 1 Start Address. 683 This parameter must be a 32-bit word address */ 684 685 uint32_t RxBufferSA; /*!< Specifies the Rx Buffer Start Address. 686 This parameter must be a 32-bit word address */ 687 688 uint32_t TxEventFIFOSA; /*!< Specifies the Tx Event FIFO Start Address. 689 This parameter must be a 32-bit word address */ 690 691 uint32_t TxBufferSA; /*!< Specifies the Tx Buffers Start Address. 692 This parameter must be a 32-bit word address */ 693 694 uint32_t TxFIFOQSA; /*!< Specifies the Tx FIFO/Queue Start Address. 695 This parameter must be a 32-bit word address */ 696 697 uint32_t TTMemorySA; /*!< Specifies the Trigger Memory Start Address. 698 This parameter must be a 32-bit word address */ 699 700 uint32_t EndAddress; /*!< Specifies the End Address of the allocated RAM. 701 This parameter must be a 32-bit word address */ 702 703 } FDCAN_MsgRamAddressTypeDef; 704 705 /** 706 * @brief FDCAN handle structure definition 707 */ 708 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 709 typedef struct __FDCAN_HandleTypeDef 710 #else 711 typedef struct 712 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 713 { 714 FDCAN_GlobalTypeDef *Instance; /*!< Register base address */ 715 716 TTCAN_TypeDef *ttcan; /*!< TT register base address */ 717 718 FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */ 719 720 FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */ 721 722 uint32_t LatestTxFifoQRequest; /*!< FDCAN Tx buffer index 723 of latest Tx FIFO/Queue request */ 724 725 __IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */ 726 727 HAL_LockTypeDef Lock; /*!< FDCAN locking object */ 728 729 __IO uint32_t ErrorCode; /*!< FDCAN Error code */ 730 731 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 732 void (* ClockCalibrationCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs); /*!< FDCAN Clock Calibration callback */ 733 void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< FDCAN Tx Event Fifo callback */ 734 void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< FDCAN Rx Fifo 0 callback */ 735 void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< FDCAN Rx Fifo 1 callback */ 736 void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Tx Fifo Empty callback */ 737 void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer complete callback */ 738 void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer abort callback */ 739 void (* RxBufferNewMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Rx Buffer New Message callback */ 740 void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN High priority message callback */ 741 void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timestamp wraparound callback */ 742 void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timeout occurred callback */ 743 void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Error callback */ 744 void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< FDCAN Error status callback */ 745 void (* TT_ScheduleSyncCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs); /*!< FDCAN T Schedule Synchronization callback */ 746 void (* TT_TimeMarkCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs); /*!< FDCAN TT Time Mark callback */ 747 void (* TT_StopWatchCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< FDCAN TT Stop Watch callback */ 748 void (* TT_GlobalTimeCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs); /*!< FDCAN TT Global Time callback */ 749 750 void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp Init callback */ 751 void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp DeInit callback */ 752 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 753 754 } FDCAN_HandleTypeDef; 755 756 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 757 /** 758 * @brief HAL FDCAN common Callback ID enumeration definition 759 */ 760 typedef enum 761 { 762 HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */ 763 HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID = 0x01U, /*!< FDCAN Rx buffer new message callback ID */ 764 HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x02U, /*!< FDCAN High priority message callback ID */ 765 HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U, /*!< FDCAN Timestamp wraparound callback ID */ 766 HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x04U, /*!< FDCAN Timeout occurred callback ID */ 767 HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x05U, /*!< FDCAN Error callback ID */ 768 769 HAL_FDCAN_MSPINIT_CB_ID = 0x06U, /*!< FDCAN MspInit callback ID */ 770 HAL_FDCAN_MSPDEINIT_CB_ID = 0x07U, /*!< FDCAN MspDeInit callback ID */ 771 772 } HAL_FDCAN_CallbackIDTypeDef; 773 774 /** 775 * @brief HAL FDCAN Callback pointer definition 776 */ 777 typedef void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan); /*!< pointer to a common FDCAN callback function */ 778 typedef void (*pFDCAN_ClockCalibrationCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs); /*!< pointer to Clock Calibration FDCAN callback function */ 779 typedef void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< pointer to Tx event Fifo FDCAN callback function */ 780 typedef void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< pointer to Rx Fifo 0 FDCAN callback function */ 781 typedef void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< pointer to Rx Fifo 1 FDCAN callback function */ 782 typedef void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer complete FDCAN callback function */ 783 typedef void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer abort FDCAN callback function */ 784 typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< pointer to Error Status callback function */ 785 typedef void (*pFDCAN_TT_ScheduleSyncCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs); /*!< pointer to TT Schedule Synchronization FDCAN callback function */ 786 typedef void (*pFDCAN_TT_TimeMarkCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs); /*!< pointer to TT Time Mark FDCAN callback function */ 787 typedef void (*pFDCAN_TT_StopWatchCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< pointer to TT Stop Watch FDCAN callback function */ 788 typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs); /*!< pointer to TT Global Time FDCAN callback function */ 789 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 790 791 /** 792 * @} 793 */ 794 795 /* Exported constants --------------------------------------------------------*/ 796 /** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants 797 * @{ 798 */ 799 800 /** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code 801 * @{ 802 */ 803 #define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 804 #define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ 805 #define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized */ 806 #define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U) /*!< Peripheral not ready */ 807 #define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U) /*!< Peripheral not started */ 808 #define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U) /*!< Mode not supported */ 809 #define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */ 810 #define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */ 811 #define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */ 812 #define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */ 813 #define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */ 814 #define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */ 815 #define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */ 816 #define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */ 817 #define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED /*!< Protocol Error in Data Phase (Data Bit Time is used) */ 818 #define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA /*!< Access to Reserved Address */ 819 #define HAL_FDCAN_ERROR_TT_GLOBAL_TIME FDCAN_TTIR_GTE /*!< Global Time Error : Synchronization deviation exceeded limit */ 820 #define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */ 821 #define HAL_FDCAN_ERROR_TT_TX_OVERFLOW FDCAN_TTIR_TXO /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle */ 822 #define HAL_FDCAN_ERROR_TT_SCHEDULE1 FDCAN_TTIR_SE1 /*!< Scheduling error 1 */ 823 #define HAL_FDCAN_ERROR_TT_SCHEDULE2 FDCAN_TTIR_SE2 /*!< Scheduling error 2 */ 824 #define HAL_FDCAN_ERROR_TT_NO_INIT_REF FDCAN_TTIR_IWT /*!< No system startup due to missing reference message */ 825 #define HAL_FDCAN_ERROR_TT_NO_REF FDCAN_TTIR_WT /*!< Missing reference message */ 826 #define HAL_FDCAN_ERROR_TT_APPL_WDG FDCAN_TTIR_AW /*!< Application watchdog not served in time */ 827 #define HAL_FDCAN_ERROR_TT_CONFIG FDCAN_TTIR_CER /*!< Error found in trigger list */ 828 829 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 830 #define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error */ 831 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 832 /** 833 * @} 834 */ 835 836 /** @defgroup FDCAN_frame_format FDCAN Frame Format 837 * @{ 838 */ 839 #define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /*!< Classic mode */ 840 #define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE) /*!< FD mode without BitRate Switching */ 841 #define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching */ 842 /** 843 * @} 844 */ 845 846 /** @defgroup FDCAN_operating_mode FDCAN Operating Mode 847 * @{ 848 */ 849 #define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ 850 #define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */ 851 #define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U) /*!< Bus Monitoring mode */ 852 #define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U) /*!< Internal LoopBack mode */ 853 #define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U) /*!< External LoopBack mode */ 854 /** 855 * @} 856 */ 857 858 /** @defgroup FDCAN_clock_calibration FDCAN Clock Calibration 859 * @{ 860 */ 861 #define FDCAN_CLOCK_CALIBRATION_DISABLE ((uint32_t)0x00000000U) /*!< Disable Clock Calibration */ 862 #define FDCAN_CLOCK_CALIBRATION_ENABLE ((uint32_t)0x00000001U) /*!< Enable Clock Calibration */ 863 /** 864 * @} 865 */ 866 867 /** @defgroup FDCAN_clock_divider FDCAN Clock Divider 868 * @{ 869 */ 870 #define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */ 871 #define FDCAN_CLOCK_DIV2 ((uint32_t)0x00010000U) /*!< Divide kernel clock by 2 */ 872 #define FDCAN_CLOCK_DIV4 ((uint32_t)0x00020000U) /*!< Divide kernel clock by 4 */ 873 #define FDCAN_CLOCK_DIV6 ((uint32_t)0x00030000U) /*!< Divide kernel clock by 6 */ 874 #define FDCAN_CLOCK_DIV8 ((uint32_t)0x00040000U) /*!< Divide kernel clock by 8 */ 875 #define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U) /*!< Divide kernel clock by 10 */ 876 #define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U) /*!< Divide kernel clock by 12 */ 877 #define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U) /*!< Divide kernel clock by 14 */ 878 #define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U) /*!< Divide kernel clock by 16 */ 879 #define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U) /*!< Divide kernel clock by 18 */ 880 #define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U) /*!< Divide kernel clock by 20 */ 881 #define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U) /*!< Divide kernel clock by 22 */ 882 #define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U) /*!< Divide kernel clock by 24 */ 883 #define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U) /*!< Divide kernel clock by 26 */ 884 #define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U) /*!< Divide kernel clock by 28 */ 885 #define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U) /*!< Divide kernel clock by 30 */ 886 /** 887 * @} 888 */ 889 890 /** @defgroup FDCAN_calibration_field_length FDCAN Calibration Field Length 891 * @{ 892 */ 893 #define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U) /*!< Calibration field length is 32 bits */ 894 #define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL) /*!< Calibration field length is 64 bits */ 895 /** 896 * @} 897 */ 898 899 /** @defgroup FDCAN_calibration_state FDCAN Calibration State 900 * @{ 901 */ 902 #define FDCAN_CLOCK_NOT_CALIBRATED ((uint32_t)0x00000000U) /*!< Clock not calibrated */ 903 #define FDCAN_CLOCK_BASIC_CALIBRATED ((uint32_t)0x40000000U) /*!< Clock basic calibrated */ 904 #define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U) /*!< Clock precision calibrated */ 905 /** 906 * @} 907 */ 908 909 /** @defgroup FDCAN_calibration_counter FDCAN Calibration Counter 910 * @{ 911 */ 912 #define FDCAN_CALIB_TIME_QUANTA_COUNTER ((uint32_t)0x00000000U) /*!< Time Quanta Counter */ 913 #define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U) /*!< Oscillator Clock Period Counter */ 914 #define FDCAN_CALIB_WATCHDOG_COUNTER ((uint32_t)0x00000002U) /*!< Calibration Watchdog Counter */ 915 /** 916 * @} 917 */ 918 919 /** @defgroup FDCAN_data_field_size FDCAN Data Field Size 920 * @{ 921 */ 922 #define FDCAN_DATA_BYTES_8 ((uint32_t)0x00000004U) /*!< 8 bytes data field */ 923 #define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */ 924 #define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */ 925 #define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */ 926 #define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */ 927 #define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */ 928 #define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */ 929 #define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */ 930 /** 931 * @} 932 */ 933 934 /** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode 935 * @{ 936 */ 937 #define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U) /*!< FIFO mode */ 938 #define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */ 939 /** 940 * @} 941 */ 942 943 /** @defgroup FDCAN_id_type FDCAN ID Type 944 * @{ 945 */ 946 #define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */ 947 #define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */ 948 /** 949 * @} 950 */ 951 952 /** @defgroup FDCAN_frame_type FDCAN Frame Type 953 * @{ 954 */ 955 #define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */ 956 #define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote frame */ 957 /** 958 * @} 959 */ 960 961 /** @defgroup FDCAN_data_length_code FDCAN Data Length Code 962 * @{ 963 */ 964 #define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */ 965 #define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */ 966 #define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */ 967 #define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */ 968 #define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */ 969 #define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */ 970 #define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */ 971 #define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */ 972 #define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */ 973 #define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */ 974 #define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */ 975 #define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */ 976 #define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */ 977 #define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */ 978 #define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */ 979 #define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */ 980 /** 981 * @} 982 */ 983 984 /** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator 985 * @{ 986 */ 987 #define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< Transmitting node is error active */ 988 #define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */ 989 /** 990 * @} 991 */ 992 993 /** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching 994 * @{ 995 */ 996 #define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */ 997 #define FDCAN_BRS_ON ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching */ 998 /** 999 * @} 1000 */ 1001 1002 /** @defgroup FDCAN_format FDCAN format 1003 * @{ 1004 */ 1005 #define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */ 1006 #define FDCAN_FD_CAN ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format */ 1007 /** 1008 * @} 1009 */ 1010 1011 /** @defgroup FDCAN_EFC FDCAN Event FIFO control 1012 * @{ 1013 */ 1014 #define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U) /*!< Do not store Tx events */ 1015 #define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events */ 1016 /** 1017 * @} 1018 */ 1019 1020 /** @defgroup FDCAN_filter_type FDCAN Filter Type 1021 * @{ 1022 */ 1023 #define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2 */ 1024 #define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2 */ 1025 #define FDCAN_FILTER_MASK ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask */ 1026 #define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */ 1027 /** 1028 * @} 1029 */ 1030 1031 /** @defgroup FDCAN_filter_config FDCAN Filter Configuration 1032 * @{ 1033 */ 1034 #define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Disable filter element */ 1035 #define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches */ 1036 #define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches */ 1037 #define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U) /*!< Reject ID if filter matches */ 1038 #define FDCAN_FILTER_HP ((uint32_t)0x00000004U) /*!< Set high priority if filter matches */ 1039 #define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches */ 1040 #define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches */ 1041 #define FDCAN_FILTER_TO_RXBUFFER ((uint32_t)0x00000007U) /*!< Store into Rx Buffer, configuration of FilterType ignored */ 1042 /** 1043 * @} 1044 */ 1045 1046 /** @defgroup FDCAN_Tx_location FDCAN Tx Location 1047 * @{ 1048 */ 1049 #define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0 */ 1050 #define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1 */ 1051 #define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2 */ 1052 #define FDCAN_TX_BUFFER3 ((uint32_t)0x00000008U) /*!< Add message to Tx Buffer 3 */ 1053 #define FDCAN_TX_BUFFER4 ((uint32_t)0x00000010U) /*!< Add message to Tx Buffer 4 */ 1054 #define FDCAN_TX_BUFFER5 ((uint32_t)0x00000020U) /*!< Add message to Tx Buffer 5 */ 1055 #define FDCAN_TX_BUFFER6 ((uint32_t)0x00000040U) /*!< Add message to Tx Buffer 6 */ 1056 #define FDCAN_TX_BUFFER7 ((uint32_t)0x00000080U) /*!< Add message to Tx Buffer 7 */ 1057 #define FDCAN_TX_BUFFER8 ((uint32_t)0x00000100U) /*!< Add message to Tx Buffer 8 */ 1058 #define FDCAN_TX_BUFFER9 ((uint32_t)0x00000200U) /*!< Add message to Tx Buffer 9 */ 1059 #define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U) /*!< Add message to Tx Buffer 10 */ 1060 #define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U) /*!< Add message to Tx Buffer 11 */ 1061 #define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U) /*!< Add message to Tx Buffer 12 */ 1062 #define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U) /*!< Add message to Tx Buffer 13 */ 1063 #define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U) /*!< Add message to Tx Buffer 14 */ 1064 #define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U) /*!< Add message to Tx Buffer 15 */ 1065 #define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U) /*!< Add message to Tx Buffer 16 */ 1066 #define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U) /*!< Add message to Tx Buffer 17 */ 1067 #define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U) /*!< Add message to Tx Buffer 18 */ 1068 #define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U) /*!< Add message to Tx Buffer 19 */ 1069 #define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U) /*!< Add message to Tx Buffer 20 */ 1070 #define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U) /*!< Add message to Tx Buffer 21 */ 1071 #define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U) /*!< Add message to Tx Buffer 22 */ 1072 #define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U) /*!< Add message to Tx Buffer 23 */ 1073 #define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U) /*!< Add message to Tx Buffer 24 */ 1074 #define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U) /*!< Add message to Tx Buffer 25 */ 1075 #define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U) /*!< Add message to Tx Buffer 26 */ 1076 #define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U) /*!< Add message to Tx Buffer 27 */ 1077 #define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U) /*!< Add message to Tx Buffer 28 */ 1078 #define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U) /*!< Add message to Tx Buffer 29 */ 1079 #define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U) /*!< Add message to Tx Buffer 30 */ 1080 #define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U) /*!< Add message to Tx Buffer 31 */ 1081 /** 1082 * @} 1083 */ 1084 1085 /** @defgroup FDCAN_Rx_location FDCAN Rx Location 1086 * @{ 1087 */ 1088 #define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0 */ 1089 #define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1 */ 1090 #define FDCAN_RX_BUFFER0 ((uint32_t)0x00000000U) /*!< Get received message from Rx Buffer 0 */ 1091 #define FDCAN_RX_BUFFER1 ((uint32_t)0x00000001U) /*!< Get received message from Rx Buffer 1 */ 1092 #define FDCAN_RX_BUFFER2 ((uint32_t)0x00000002U) /*!< Get received message from Rx Buffer 2 */ 1093 #define FDCAN_RX_BUFFER3 ((uint32_t)0x00000003U) /*!< Get received message from Rx Buffer 3 */ 1094 #define FDCAN_RX_BUFFER4 ((uint32_t)0x00000004U) /*!< Get received message from Rx Buffer 4 */ 1095 #define FDCAN_RX_BUFFER5 ((uint32_t)0x00000005U) /*!< Get received message from Rx Buffer 5 */ 1096 #define FDCAN_RX_BUFFER6 ((uint32_t)0x00000006U) /*!< Get received message from Rx Buffer 6 */ 1097 #define FDCAN_RX_BUFFER7 ((uint32_t)0x00000007U) /*!< Get received message from Rx Buffer 7 */ 1098 #define FDCAN_RX_BUFFER8 ((uint32_t)0x00000008U) /*!< Get received message from Rx Buffer 8 */ 1099 #define FDCAN_RX_BUFFER9 ((uint32_t)0x00000009U) /*!< Get received message from Rx Buffer 9 */ 1100 #define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /*!< Get received message from Rx Buffer 10 */ 1101 #define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /*!< Get received message from Rx Buffer 11 */ 1102 #define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /*!< Get received message from Rx Buffer 12 */ 1103 #define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /*!< Get received message from Rx Buffer 13 */ 1104 #define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /*!< Get received message from Rx Buffer 14 */ 1105 #define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /*!< Get received message from Rx Buffer 15 */ 1106 #define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /*!< Get received message from Rx Buffer 16 */ 1107 #define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /*!< Get received message from Rx Buffer 17 */ 1108 #define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /*!< Get received message from Rx Buffer 18 */ 1109 #define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /*!< Get received message from Rx Buffer 19 */ 1110 #define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /*!< Get received message from Rx Buffer 20 */ 1111 #define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /*!< Get received message from Rx Buffer 21 */ 1112 #define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /*!< Get received message from Rx Buffer 22 */ 1113 #define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /*!< Get received message from Rx Buffer 23 */ 1114 #define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /*!< Get received message from Rx Buffer 24 */ 1115 #define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /*!< Get received message from Rx Buffer 25 */ 1116 #define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /*!< Get received message from Rx Buffer 26 */ 1117 #define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /*!< Get received message from Rx Buffer 27 */ 1118 #define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /*!< Get received message from Rx Buffer 28 */ 1119 #define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /*!< Get received message from Rx Buffer 29 */ 1120 #define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /*!< Get received message from Rx Buffer 30 */ 1121 #define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /*!< Get received message from Rx Buffer 31 */ 1122 #define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /*!< Get received message from Rx Buffer 32 */ 1123 #define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /*!< Get received message from Rx Buffer 33 */ 1124 #define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /*!< Get received message from Rx Buffer 34 */ 1125 #define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /*!< Get received message from Rx Buffer 35 */ 1126 #define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /*!< Get received message from Rx Buffer 36 */ 1127 #define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /*!< Get received message from Rx Buffer 37 */ 1128 #define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /*!< Get received message from Rx Buffer 38 */ 1129 #define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /*!< Get received message from Rx Buffer 39 */ 1130 #define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /*!< Get received message from Rx Buffer 40 */ 1131 #define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /*!< Get received message from Rx Buffer 41 */ 1132 #define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /*!< Get received message from Rx Buffer 42 */ 1133 #define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /*!< Get received message from Rx Buffer 43 */ 1134 #define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /*!< Get received message from Rx Buffer 44 */ 1135 #define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /*!< Get received message from Rx Buffer 45 */ 1136 #define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /*!< Get received message from Rx Buffer 46 */ 1137 #define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /*!< Get received message from Rx Buffer 47 */ 1138 #define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /*!< Get received message from Rx Buffer 48 */ 1139 #define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /*!< Get received message from Rx Buffer 49 */ 1140 #define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /*!< Get received message from Rx Buffer 50 */ 1141 #define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /*!< Get received message from Rx Buffer 51 */ 1142 #define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /*!< Get received message from Rx Buffer 52 */ 1143 #define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /*!< Get received message from Rx Buffer 53 */ 1144 #define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /*!< Get received message from Rx Buffer 54 */ 1145 #define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /*!< Get received message from Rx Buffer 55 */ 1146 #define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /*!< Get received message from Rx Buffer 56 */ 1147 #define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /*!< Get received message from Rx Buffer 57 */ 1148 #define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /*!< Get received message from Rx Buffer 58 */ 1149 #define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /*!< Get received message from Rx Buffer 59 */ 1150 #define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /*!< Get received message from Rx Buffer 60 */ 1151 #define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /*!< Get received message from Rx Buffer 61 */ 1152 #define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /*!< Get received message from Rx Buffer 62 */ 1153 #define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /*!< Get received message from Rx Buffer 63 */ 1154 /** 1155 * @} 1156 */ 1157 1158 /** @defgroup FDCAN_event_type FDCAN Event Type 1159 * @{ 1160 */ 1161 #define FDCAN_TX_EVENT ((uint32_t)0x00400000U) /*!< Tx event */ 1162 #define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */ 1163 /** 1164 * @} 1165 */ 1166 1167 /** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage 1168 * @{ 1169 */ 1170 #define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U) /*!< No FIFO selected */ 1171 #define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost */ 1172 #define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */ 1173 #define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */ 1174 /** 1175 * @} 1176 */ 1177 1178 /** @defgroup FDCAN_protocol_error_code FDCAN protocol error code 1179 * @{ 1180 */ 1181 #define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error occurred */ 1182 #define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U) /*!< Stuff error */ 1183 #define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U) /*!< Form error */ 1184 #define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U) /*!< Acknowledge error */ 1185 #define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error */ 1186 #define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error */ 1187 #define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U) /*!< CRC check sum error */ 1188 #define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */ 1189 /** 1190 * @} 1191 */ 1192 1193 /** @defgroup FDCAN_communication_state FDCAN communication state 1194 * @{ 1195 */ 1196 #define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */ 1197 #define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter */ 1198 #define FDCAN_COM_STATE_RX ((uint32_t)0x00000010U) /*!< Node is operating as receiver */ 1199 #define FDCAN_COM_STATE_TX ((uint32_t)0x00000018U) /*!< Node is operating as transmitter */ 1200 /** 1201 * @} 1202 */ 1203 1204 /** @defgroup FDCAN_FIFO_watermark FDCAN FIFO watermark 1205 * @{ 1206 */ 1207 #define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U) /*!< Tx event FIFO */ 1208 #define FDCAN_CFG_RX_FIFO0 ((uint32_t)0x00000001U) /*!< Rx FIFO0 */ 1209 #define FDCAN_CFG_RX_FIFO1 ((uint32_t)0x00000002U) /*!< Rx FIFO1 */ 1210 /** 1211 * @} 1212 */ 1213 1214 /** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode 1215 * @{ 1216 */ 1217 #define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */ 1218 #define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */ 1219 /** 1220 * @} 1221 */ 1222 1223 /** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames 1224 * @{ 1225 */ 1226 #define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */ 1227 #define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */ 1228 #define FDCAN_REJECT ((uint32_t)0x00000002U) /*!< Reject */ 1229 /** 1230 * @} 1231 */ 1232 1233 /** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames 1234 * @{ 1235 */ 1236 #define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */ 1237 #define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */ 1238 /** 1239 * @} 1240 */ 1241 1242 /** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line 1243 * @{ 1244 */ 1245 #define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */ 1246 #define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */ 1247 /** 1248 * @} 1249 */ 1250 1251 /** @defgroup FDCAN_Timestamp FDCAN timestamp 1252 * @{ 1253 */ 1254 #define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */ 1255 #define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used */ 1256 /** 1257 * @} 1258 */ 1259 1260 /** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler 1261 * @{ 1262 */ 1263 #define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */ 1264 #define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2 */ 1265 #define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3 */ 1266 #define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4 */ 1267 #define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5 */ 1268 #define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6 */ 1269 #define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7 */ 1270 #define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8 */ 1271 #define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9 */ 1272 #define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */ 1273 #define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */ 1274 #define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */ 1275 #define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */ 1276 #define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */ 1277 #define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */ 1278 #define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */ 1279 /** 1280 * @} 1281 */ 1282 1283 /** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation 1284 * @{ 1285 */ 1286 #define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U) /*!< Timeout continuous operation */ 1287 #define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */ 1288 #define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0 */ 1289 #define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1 */ 1290 /** 1291 * @} 1292 */ 1293 1294 /** @defgroup FDCAN_TT_Reference_Message_Payload FDCAN TT reference message payload 1295 * @{ 1296 */ 1297 #define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ((uint32_t)0x00000000U) /*!< Reference message has no additional payload */ 1298 #define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS) /*!< Additional payload is taken from Tx Buffer 0 */ 1299 /** 1300 * @} 1301 */ 1302 1303 /** @defgroup FDCAN_TT_Repeat_Factor FDCAN TT repeat factor 1304 * @{ 1305 */ 1306 #define FDCAN_TT_REPEAT_EVERY_CYCLE ((uint32_t)0x00000000U) /*!< Trigger valid for all cycles */ 1307 #define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ((uint32_t)0x00000002U) /*!< Trigger valid every 2dn cycle */ 1308 #define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ((uint32_t)0x00000004U) /*!< Trigger valid every 4th cycle */ 1309 #define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ((uint32_t)0x00000008U) /*!< Trigger valid every 8th cycle */ 1310 #define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U) /*!< Trigger valid every 16th cycle */ 1311 #define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U) /*!< Trigger valid every 32nd cycle */ 1312 #define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U) /*!< Trigger valid every 64th cycle */ 1313 /** 1314 * @} 1315 */ 1316 1317 /** @defgroup FDCAN_TT_Trigger_Type FDCAN TT trigger type 1318 * @{ 1319 */ 1320 #define FDCAN_TT_TX_REF_TRIGGER ((uint32_t)0x00000000U) /*!< Transmit reference message in strictly time-triggered operation */ 1321 #define FDCAN_TT_TX_REF_TRIGGER_GAP ((uint32_t)0x00000001U) /*!< Transmit reference message in external event-synchronized time-triggered operation */ 1322 #define FDCAN_TT_TX_TRIGGER_SINGLE ((uint32_t)0x00000002U) /*!< Start a single transmission in an exclusive time window */ 1323 #define FDCAN_TT_TX_TRIGGER_CONTINUOUS ((uint32_t)0x00000003U) /*!< Start a continuous transmission in an exclusive time window */ 1324 #define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U) /*!< Start a transmission in an arbitration time window */ 1325 #define FDCAN_TT_TX_TRIGGER_MERGED ((uint32_t)0x00000005U) /*!< Start a merged arbitration window */ 1326 #define FDCAN_TT_WATCH_TRIGGER ((uint32_t)0x00000006U) /*!< Check for missing reference messages in strictly time-triggered operation */ 1327 #define FDCAN_TT_WATCH_TRIGGER_GAP ((uint32_t)0x00000007U) /*!< Check for missing reference messages in external event-synchronized time-triggered operation */ 1328 #define FDCAN_TT_RX_TRIGGER ((uint32_t)0x00000008U) /*!< Check for the reception of periodic messages in exclusive time windows */ 1329 #define FDCAN_TT_TIME_BASE_TRIGGER ((uint32_t)0x00000009U) /*!< Generate internal/external events depending on TmEventInt/TmEventExt configuration */ 1330 #define FDCAN_TT_END_OF_LIST ((uint32_t)0x0000000AU) /*!< Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */ 1331 /** 1332 * @} 1333 */ 1334 1335 /** @defgroup FDCAN_TT_Time_Mark_Event_Internal FDCAN TT time mark event internal 1336 * @{ 1337 */ 1338 #define FDCAN_TT_TM_NO_INTERNAL_EVENT ((uint32_t)0x00000000U) /*!< No action */ 1339 #define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U) /*!< Internal event is generated when trigger becomes active */ 1340 /** 1341 * @} 1342 */ 1343 1344 /** @defgroup FDCAN_TT_Time_Mark_Event_External FDCAN TT time mark event external 1345 * @{ 1346 */ 1347 #define FDCAN_TT_TM_NO_EXTERNAL_EVENT ((uint32_t)0x00000000U) /*!< No action */ 1348 #define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U) /*!< External event (pulse) is generated when trigger becomes active */ 1349 /** 1350 * @} 1351 */ 1352 1353 /** @defgroup FDCAN_operation_mode FDCAN Operation Mode 1354 * @{ 1355 */ 1356 #define FDCAN_TT_COMMUNICATION_LEVEL1 ((uint32_t)0x00000001U) /*!< Time triggered communication, level 1 */ 1357 #define FDCAN_TT_COMMUNICATION_LEVEL2 ((uint32_t)0x00000002U) /*!< Time triggered communication, level 2 */ 1358 #define FDCAN_TT_COMMUNICATION_LEVEL0 ((uint32_t)0x00000003U) /*!< Time triggered communication, level 0 */ 1359 /** 1360 * @} 1361 */ 1362 1363 /** @defgroup FDCAN_TT_operation FDCAN TT Operation 1364 * @{ 1365 */ 1366 #define FDCAN_STRICTLY_TT_OPERATION ((uint32_t)0x00000000U) /*!< Strictly time-triggered operation */ 1367 #define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN) /*!< External event-synchronized time-triggered operation */ 1368 /** 1369 * @} 1370 */ 1371 1372 /** @defgroup FDCAN_TT_time_master FDCAN TT Time Master 1373 * @{ 1374 */ 1375 #define FDCAN_TT_SLAVE ((uint32_t)0x00000000U) /*!< Time slave */ 1376 #define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM) /*!< Potential time master */ 1377 /** 1378 * @} 1379 */ 1380 1381 /** @defgroup FDCAN_TT_external_clk_sync FDCAN TT External Clock Synchronization 1382 * @{ 1383 */ 1384 #define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U) /*!< External clock synchronization in Level 0,2 disabled */ 1385 #define FDCAN_TT_EXT_CLK_SYNC_ENABLE ((uint32_t)FDCAN_TTOCF_EECS) /*!< External clock synchronization in Level 0,2 enabled */ 1386 /** 1387 * @} 1388 */ 1389 1390 /** @defgroup FDCAN_TT_global_time_filtering FDCAN TT Global Time Filtering 1391 * @{ 1392 */ 1393 #define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U) /*!< Global time filtering in Level 0,2 disabled */ 1394 #define FDCAN_TT_GLOB_TIME_FILT_ENABLE ((uint32_t)FDCAN_TTOCF_EGTF) /*!< Global time filtering in Level 0,2 enabled */ 1395 /** 1396 * @} 1397 */ 1398 1399 /** @defgroup FDCAN_TT_auto_clk_calibration FDCAN TT Automatic Clock Calibration 1400 * @{ 1401 */ 1402 #define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U) /*!< Automatic clock calibration in Level 0,2 disabled */ 1403 #define FDCAN_TT_AUTO_CLK_CALIB_ENABLE ((uint32_t)FDCAN_TTOCF_ECC) /*!< Automatic clock calibration in Level 0,2 enabled */ 1404 /** 1405 * @} 1406 */ 1407 1408 /** @defgroup FDCAN_TT_event_trig_polarity FDCAN TT Event Trigger Polarity 1409 * @{ 1410 */ 1411 #define FDCAN_TT_EVT_TRIG_POL_RISING ((uint32_t)0x00000000U) /*!< Rising edge trigger */ 1412 #define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP) /*!< Falling edge trigger */ 1413 /** 1414 * @} 1415 */ 1416 1417 /** @defgroup FDCAN_TT_basic_cycle_number FDCAN TT Basic Cycle Number 1418 * @{ 1419 */ 1420 #define FDCAN_TT_CYCLES_PER_MATRIX_1 ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix */ 1421 #define FDCAN_TT_CYCLES_PER_MATRIX_2 ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix */ 1422 #define FDCAN_TT_CYCLES_PER_MATRIX_4 ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix */ 1423 #define FDCAN_TT_CYCLES_PER_MATRIX_8 ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix */ 1424 #define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */ 1425 #define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */ 1426 #define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU) /*!< 64 Basic Cycles per Matrix */ 1427 /** 1428 * @} 1429 */ 1430 1431 /** @defgroup FDCAN_TT_cycle_start_sync FDCAN TT Cycle Start Sync 1432 * @{ 1433 */ 1434 #define FDCAN_TT_NO_SYNC_PULSE ((uint32_t)0x00000000U) /*!< No sync pulse */ 1435 #define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U) /*!< Sync pulse at start of basic cycle */ 1436 #define FDCAN_TT_SYNC_MATRIX_START ((uint32_t)0x00000080U) /*!< Sync pulse at start of matrix */ 1437 /** 1438 * @} 1439 */ 1440 1441 /** @defgroup FDCAN_TT_stop_watch_trig_selection FDCAN TT Stop Watch Trigger Selection 1442 * @{ 1443 */ 1444 #define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as stop watch trigger */ 1445 #define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U) /*!< TIM3 selected as stop watch trigger */ 1446 #define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U) /*!< ETH selected as stop watch trigger */ 1447 #define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U) /*!< HRTIM selected as stop watch trigger */ 1448 /** 1449 * @} 1450 */ 1451 1452 /** @defgroup FDCAN_TT_event_trig_selection FDCAN TT Event Trigger Selection 1453 * @{ 1454 */ 1455 #define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as event trigger */ 1456 #define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U) /*!< TIM3 selected as event trigger */ 1457 #define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U) /*!< ETH selected as event trigger */ 1458 #define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U) /*!< HRTIM selected as event trigger */ 1459 /** 1460 * @} 1461 */ 1462 1463 /** @defgroup FDCAN_TT_stop_watch_source FDCAN TT Stop Watch Source 1464 * @{ 1465 */ 1466 #define FDCAN_TT_STOP_WATCH_DISABLED ((uint32_t)0x00000000U) /*!< Stop Watch disabled */ 1467 #define FDCAN_TT_STOP_WATCH_CYCLE_TIME ((uint32_t)0x00000008U) /*!< Actual value of cycle time is copied to Capture Time register (TTCPT.SWV) */ 1468 #define FDCAN_TT_STOP_WATCH_LOCAL_TIME ((uint32_t)0x00000010U) /*!< Actual value of local time is copied to Capture Time register (TTCPT.SWV) */ 1469 #define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U) /*!< Actual value of global time is copied to Capture Time register (TTCPT.SWV) */ 1470 /** 1471 * @} 1472 */ 1473 1474 /** @defgroup FDCAN_TT_stop_watch_polarity FDCAN TT Stop Watch Polarity 1475 * @{ 1476 */ 1477 #define FDCAN_TT_STOP_WATCH_RISING ((uint32_t)0x00000000U) /*!< Selected stop watch source is captured at rising edge of fdcan1_swt */ 1478 #define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U) /*!< Selected stop watch source is captured at falling edge of fdcan1_swt */ 1479 /** 1480 * @} 1481 */ 1482 1483 /** @defgroup FDCAN_TT_time_mark_source FDCAN TT Time Mark Source 1484 * @{ 1485 */ 1486 #define FDCAN_TT_REG_TIMEMARK_DIABLED ((uint32_t)0x00000000U) /*!< No Register Time Mark Interrupt generated */ 1487 #define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U) /*!< Register Time Mark Interrupt if Time Mark = cycle time */ 1488 #define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U) /*!< Register Time Mark Interrupt if Time Mark = local time */ 1489 #define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U) /*!< Register Time Mark Interrupt if Time Mark = global time */ 1490 /** 1491 * @} 1492 */ 1493 1494 /** @defgroup FDCAN_TT_error_level FDCAN TT Error Level 1495 * @{ 1496 */ 1497 #define FDCAN_TT_NO_ERROR ((uint32_t)0x00000000U) /*!< Severity 0 - No Error */ 1498 #define FDCAN_TT_WARNING ((uint32_t)0x00000001U) /*!< Severity 1 - Warning */ 1499 #define FDCAN_TT_ERROR ((uint32_t)0x00000002U) /*!< Severity 2 - Error */ 1500 #define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U) /*!< Severity 3 - Severe Error */ 1501 /** 1502 * @} 1503 */ 1504 1505 /** @defgroup FDCAN_TT_master_state FDCAN TT Master State 1506 * @{ 1507 */ 1508 #define FDCAN_TT_MASTER_OFF ((uint32_t)0x00000000U) /*!< Master_Off, no master properties relevant */ 1509 #define FDCAN_TT_TIME_SLAVE ((uint32_t)0x00000004U) /*!< Operating as Time Slave */ 1510 #define FDCAN_TT_BACKUP_TIME_MASTER ((uint32_t)0x00000008U) /*!< Operating as Backup Time Master */ 1511 #define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU) /*!< Operating as current Time Master */ 1512 /** 1513 * @} 1514 */ 1515 1516 /** @defgroup FDCAN_TT_sync_state FDCAN TT Synchronization State 1517 * @{ 1518 */ 1519 #define FDCAN_TT_OUT_OF_SYNC ((uint32_t)0x00000000U) /*!< Out of Synchronization */ 1520 #define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U) /*!< Synchronizing to communication */ 1521 #define FDCAN_TT_IN_GAP ((uint32_t)0x00000020U) /*!< Schedule suspended by Gap */ 1522 #define FDCAN_TT_IN_SCHEDULE ((uint32_t)0x00000030U) /*!< Synchronized to schedule */ 1523 /** 1524 * @} 1525 */ 1526 1527 /** @defgroup Interrupt_Masks Interrupt masks 1528 * @{ 1529 */ 1530 #define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU) /*!< FDCAN interrupts mask */ 1531 #define CCU_IR_MASK ((uint32_t)0xC0000000U) /*!< CCU interrupts mask */ 1532 /** 1533 * @} 1534 */ 1535 1536 /** @defgroup FDCAN_flags FDCAN Flags 1537 * @{ 1538 */ 1539 #define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC /*!< Transmission Completed */ 1540 #define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF /*!< Transmission Cancellation Finished */ 1541 #define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE /*!< Tx FIFO Empty */ 1542 #define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM /*!< High priority message received */ 1543 #define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE FDCAN_IR_DRX /*!< At least one received message stored into a Rx Buffer */ 1544 #define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL /*!< Tx Event FIFO element lost */ 1545 #define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF /*!< Tx Event FIFO full */ 1546 #define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK FDCAN_IR_TEFW /*!< Tx Event FIFO fill level reached watermark */ 1547 #define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN /*!< Tx Handler wrote Tx Event FIFO element */ 1548 #define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L /*!< Rx FIFO 0 message lost */ 1549 #define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F /*!< Rx FIFO 0 full */ 1550 #define FDCAN_FLAG_RX_FIFO0_WATERMARK FDCAN_IR_RF0W /*!< Rx FIFO 0 fill level reached watermark */ 1551 #define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N /*!< New message written to Rx FIFO 0 */ 1552 #define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L /*!< Rx FIFO 1 message lost */ 1553 #define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F /*!< Rx FIFO 1 full */ 1554 #define FDCAN_FLAG_RX_FIFO1_WATERMARK FDCAN_IR_RF1W /*!< Rx FIFO 1 fill level reached watermark */ 1555 #define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N /*!< New message written to Rx FIFO 1 */ 1556 #define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF /*!< Message RAM access failure occurred */ 1557 #define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO /*!< Overflow of FDCAN Error Logging Counter occurred */ 1558 #define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP /*!< Error_Passive status changed */ 1559 #define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW /*!< Error_Warning status changed */ 1560 #define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO /*!< Bus_Off status changed */ 1561 #define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI /*!< Message RAM Watchdog event due to missing READY */ 1562 #define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA /*!< Protocol error in arbitration phase detected */ 1563 #define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED /*!< Protocol error in data phase detected */ 1564 #define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA /*!< Access to reserved address occurred */ 1565 #define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW /*!< Timestamp counter wrapped around */ 1566 #define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO /*!< Timeout reached */ 1567 #define FDCAN_FLAG_CALIB_STATE_CHANGED (FDCANCCU_IR_CSC << 30) /*!< Clock calibration state changed */ 1568 #define FDCAN_FLAG_CALIB_WATCHDOG_EVENT (FDCANCCU_IR_CWE << 30) /*!< Clock calibration watchdog event occurred */ 1569 /** 1570 * @} 1571 */ 1572 1573 /** @defgroup FDCAN_Interrupts FDCAN Interrupts 1574 * @{ 1575 */ 1576 1577 /** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts 1578 * @{ 1579 */ 1580 #define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE /*!< Transmission Completed */ 1581 #define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE /*!< Transmission Cancellation Finished */ 1582 #define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE /*!< Tx FIFO Empty */ 1583 /** 1584 * @} 1585 */ 1586 1587 /** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts 1588 * @{ 1589 */ 1590 #define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME /*!< High priority message received */ 1591 #define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE /*!< At least one received message stored into a Rx Buffer */ 1592 /** 1593 * @} 1594 */ 1595 1596 /** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts 1597 * @{ 1598 */ 1599 #define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE /*!< Timestamp counter wrapped around */ 1600 #define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE /*!< Timeout reached */ 1601 /** 1602 * @} 1603 */ 1604 1605 /** @defgroup FDCAN_Clock_Calibration_Interrupts Clock Calibration Interrupts 1606 * @{ 1607 */ 1608 #define FDCAN_IT_CALIB_STATE_CHANGED (FDCANCCU_IE_CSCE << 30) /*!< Clock calibration state changed */ 1609 #define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30) /*!< Clock calibration watchdog event occurred */ 1610 /** 1611 * @} 1612 */ 1613 1614 /** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts 1615 * @{ 1616 */ 1617 #define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost */ 1618 #define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE /*!< Tx Event FIFO full */ 1619 #define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE /*!< Tx Event FIFO fill level reached watermark */ 1620 #define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element */ 1621 /** 1622 * @} 1623 */ 1624 1625 /** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts 1626 * @{ 1627 */ 1628 #define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost */ 1629 #define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE /*!< Rx FIFO 0 full */ 1630 #define FDCAN_IT_RX_FIFO0_WATERMARK FDCAN_IE_RF0WE /*!< Rx FIFO 0 fill level reached watermark */ 1631 #define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0 */ 1632 /** 1633 * @} 1634 */ 1635 1636 /** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts 1637 * @{ 1638 */ 1639 #define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost */ 1640 #define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE /*!< Rx FIFO 1 full */ 1641 #define FDCAN_IT_RX_FIFO1_WATERMARK FDCAN_IE_RF1WE /*!< Rx FIFO 1 fill level reached watermark */ 1642 #define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1 */ 1643 /** 1644 * @} 1645 */ 1646 1647 /** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts 1648 * @{ 1649 */ 1650 #define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE /*!< Message RAM access failure occurred */ 1651 #define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE /*!< Overflow of FDCAN Error Logging Counter occurred */ 1652 #define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE /*!< Message RAM Watchdog event due to missing READY */ 1653 #define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE /*!< Protocol error in arbitration phase detected */ 1654 #define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE /*!< Protocol error in data phase detected */ 1655 #define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE /*!< Access to reserved address occurred */ 1656 /** 1657 * @} 1658 */ 1659 1660 /** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts 1661 * @{ 1662 */ 1663 #define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */ 1664 #define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */ 1665 #define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */ 1666 /** 1667 * @} 1668 */ 1669 1670 /** 1671 * @} 1672 */ 1673 1674 /** @defgroup FDCAN_TTflags FDCAN TT Flags 1675 * @{ 1676 */ 1677 #define FDCAN_TT_FLAG_BASIC_CYCLE_START FDCAN_TTIR_SBC /*!< Start of Basic Cycle */ 1678 #define FDCAN_TT_FLAG_MATRIX_CYCLE_START FDCAN_TTIR_SMC /*!< Start of Matrix Cycle */ 1679 #define FDCAN_TT_FLAG_SYNC_MODE_CHANGE FDCAN_TTIR_CSM /*!< Change of Synchronization Mode */ 1680 #define FDCAN_TT_FLAG_START_OF_GAP FDCAN_TTIR_SOG /*!< Start of Gap */ 1681 #define FDCAN_TT_FLAG_REG_TIME_MARK FDCAN_TTIR_RTMI /*!< Register Time Mark Interrupt */ 1682 #define FDCAN_TT_FLAG_TRIG_TIME_MARK FDCAN_TTIR_TTMI /*!< Trigger Time Mark Event Internal */ 1683 #define FDCAN_TT_FLAG_STOP_WATCH FDCAN_TTIR_SWE /*!< Stop Watch Event */ 1684 #define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP FDCAN_TTIR_GTW /*!< Global Time Wrap */ 1685 #define FDCAN_TT_FLAG_GLOBAL_TIME_DISC FDCAN_TTIR_GTD /*!< Global Time Discontinuity */ 1686 #define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR FDCAN_TTIR_GTE /*!< Global Time Error */ 1687 #define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW FDCAN_TTIR_TXU /*!< Tx Count Underflow */ 1688 #define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW FDCAN_TTIR_TXO /*!< Tx Count Overflow */ 1689 #define FDCAN_TT_FLAG_SCHEDULING_ERROR_1 FDCAN_TTIR_SE1 /*!< Scheduling Error 1 */ 1690 #define FDCAN_TT_FLAG_SCHEDULING_ERROR_2 FDCAN_TTIR_SE2 /*!< Scheduling Error 2 */ 1691 #define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE FDCAN_TTIR_ELC /*!< Error Level Changed */ 1692 #define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER FDCAN_TTIR_IWT /*!< Initialization Watch Trigger */ 1693 #define FDCAN_TT_FLAG_WATCH_TRIGGER FDCAN_TTIR_WT /*!< Watch Trigger */ 1694 #define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW /*!< Application Watchdog */ 1695 #define FDCAN_TT_FLAG_CONFIG_ERROR FDCAN_TTIR_CER /*!< Configuration Error */ 1696 /** 1697 * @} 1698 */ 1699 1700 /** @defgroup FDCAN_TTInterrupts FDCAN TT Interrupts 1701 * @{ 1702 */ 1703 1704 /** @defgroup FDCAN_TTScheduleSynchronization_Interrupts FDCAN TT Schedule Synchronization Interrupts 1705 * @{ 1706 */ 1707 #define FDCAN_TT_IT_BASIC_CYCLE_START FDCAN_TTIE_SBCE /*!< Start of Basic Cycle */ 1708 #define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE /*!< Start of Matrix Cycle */ 1709 #define FDCAN_TT_IT_SYNC_MODE_CHANGE FDCAN_TTIE_CSME /*!< Change of Synchronization Mode */ 1710 #define FDCAN_TT_IT_START_OF_GAP FDCAN_TTIE_SOGE /*!< Start of Gap */ 1711 /** 1712 * @} 1713 */ 1714 1715 /** @defgroup FDCAN_TTTimeMark_Interrupts FDCAN TT Time Mark Interrupts 1716 * @{ 1717 */ 1718 #define FDCAN_TT_IT_REG_TIME_MARK FDCAN_TTIE_RTMIE /*!< Register Time Mark Interrupt */ 1719 #define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE /*!< Trigger Time Mark Event Internal */ 1720 /** 1721 * @} 1722 */ 1723 1724 /** @defgroup FDCAN_TTStopWatch_Interrupt FDCAN TT Stop Watch Interrupt 1725 * @{ 1726 */ 1727 #define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE /*!< Stop Watch Event */ 1728 /** 1729 * @} 1730 */ 1731 1732 /** @defgroup FDCAN_TTGlobalTime_Interrupts FDCAN TT Global Time Interrupts 1733 * @{ 1734 */ 1735 #define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE /*!< Global Time Wrap */ 1736 #define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE /*!< Global Time Discontinuity */ 1737 /** 1738 * @} 1739 */ 1740 1741 /** @defgroup FDCAN_TTDisturbingError_Interrupts FDCAN TT Disturbing Error Interrupts 1742 * @{ 1743 */ 1744 #define FDCAN_TT_IT_GLOBAL_TIME_ERROR FDCAN_TTIE_GTEE /*!< Global Time Error */ 1745 #define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE /*!< Tx Count Underflow */ 1746 #define FDCAN_TT_IT_TX_COUNT_OVERFLOW FDCAN_TTIE_TXOE /*!< Tx Count Overflow */ 1747 #define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E /*!< Scheduling Error 1 */ 1748 #define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E /*!< Scheduling Error 2 */ 1749 #define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE /*!< Error Level Changed */ 1750 /** 1751 * @} 1752 */ 1753 1754 /** @defgroup FDCAN_TTFatalError_Interrupts FDCAN TT Fatal Error Interrupts 1755 * @{ 1756 */ 1757 #define FDCAN_TT_IT_INIT_WATCH_TRIGGER FDCAN_TTIE_IWTE /*!< Initialization Watch Trigger */ 1758 #define FDCAN_TT_IT_WATCH_TRIGGER FDCAN_TTIE_WTE /*!< Watch Trigger */ 1759 #define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE /*!< Application Watchdog */ 1760 #define FDCAN_TT_IT_CONFIG_ERROR FDCAN_TTIE_CERE /*!< Configuration Error */ 1761 /** 1762 * @} 1763 */ 1764 1765 /** 1766 * @} 1767 */ 1768 1769 /** 1770 * @} 1771 */ 1772 1773 /* Exported macro ------------------------------------------------------------*/ 1774 /** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros 1775 * @{ 1776 */ 1777 1778 /** @brief Reset FDCAN handle state. 1779 * @param __HANDLE__ FDCAN handle. 1780 * @retval None 1781 */ 1782 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 1783 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ 1784 (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \ 1785 (__HANDLE__)->MspInitCallback = NULL; \ 1786 (__HANDLE__)->MspDeInitCallback = NULL; \ 1787 } while(0) 1788 #else 1789 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET) 1790 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 1791 1792 /** 1793 * @brief Enable the specified FDCAN interrupts. 1794 * @param __HANDLE__ FDCAN handle. 1795 * @param __INTERRUPT__ FDCAN interrupt. 1796 * This parameter can be any combination of @arg FDCAN_Interrupts 1797 * @retval None 1798 */ 1799 #define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1800 do{ \ 1801 (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \ 1802 FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30); \ 1803 }while(0) 1804 1805 1806 /** 1807 * @brief Disable the specified FDCAN interrupts. 1808 * @param __HANDLE__ FDCAN handle. 1809 * @param __INTERRUPT__ FDCAN interrupt. 1810 * This parameter can be any combination of @arg FDCAN_Interrupts 1811 * @retval None 1812 */ 1813 #define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1814 do{ \ 1815 ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \ 1816 FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30); \ 1817 }while(0) 1818 1819 /** 1820 * @brief Check whether the specified FDCAN interrupt is set or not. 1821 * @param __HANDLE__ FDCAN handle. 1822 * @param __INTERRUPT__ FDCAN interrupt. 1823 * This parameter can be one of @arg FDCAN_Interrupts 1824 * @retval ITStatus 1825 */ 1826 #define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__))) 1827 1828 /** 1829 * @brief Clear the specified FDCAN interrupts. 1830 * @param __HANDLE__ FDCAN handle. 1831 * @param __INTERRUPT__ specifies the interrupts to clear. 1832 * This parameter can be any combination of @arg FDCAN_Interrupts 1833 * @retval None 1834 */ 1835 #define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \ 1836 do{ \ 1837 ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \ 1838 FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30); \ 1839 }while(0) 1840 1841 /** 1842 * @brief Check whether the specified FDCAN flag is set or not. 1843 * @param __HANDLE__ FDCAN handle. 1844 * @param __FLAG__ FDCAN flag. 1845 * This parameter can be one of @arg FDCAN_flags 1846 * @retval FlagStatus 1847 */ 1848 #define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__))) 1849 1850 /** 1851 * @brief Clear the specified FDCAN flags. 1852 * @param __HANDLE__ FDCAN handle. 1853 * @param __FLAG__ specifies the flags to clear. 1854 * This parameter can be any combination of @arg FDCAN_flags 1855 * @retval None 1856 */ 1857 #define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1858 do{ \ 1859 ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \ 1860 FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30); \ 1861 }while(0) 1862 1863 /** @brief Check if the specified FDCAN interrupt source is enabled or disabled. 1864 * @param __HANDLE__ FDCAN handle. 1865 * @param __INTERRUPT__ specifies the FDCAN interrupt source to check. 1866 * This parameter can be a value of @arg FDCAN_Interrupts 1867 * @retval ITStatus 1868 */ 1869 #define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__))) 1870 1871 /** 1872 * @brief Enable the specified FDCAN TT interrupts. 1873 * @param __HANDLE__ FDCAN handle. 1874 * @param __INTERRUPT__ FDCAN TT interrupt. 1875 * This parameter can be any combination of @arg FDCAN_TTInterrupts 1876 * @retval None 1877 */ 1878 #define __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__)) 1879 1880 /** 1881 * @brief Disable the specified FDCAN TT interrupts. 1882 * @param __HANDLE__ FDCAN handle. 1883 * @param __INTERRUPT__ FDCAN TT interrupt. 1884 * This parameter can be any combination of @arg FDCAN_TTInterrupts 1885 * @retval None 1886 */ 1887 #define __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__)) 1888 1889 /** 1890 * @brief Check whether the specified FDCAN TT interrupt is set or not. 1891 * @param __HANDLE__ FDCAN handle. 1892 * @param __INTERRUPT__ FDCAN TT interrupt. 1893 * This parameter can be one of @arg FDCAN_TTInterrupts 1894 * @retval ITStatus 1895 */ 1896 #define __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__)) 1897 1898 /** 1899 * @brief Clear the specified FDCAN TT interrupts. 1900 * @param __HANDLE__ FDCAN handle. 1901 * @param __INTERRUPT__ specifies the TT interrupts to clear. 1902 * This parameter can be any combination of @arg FDCAN_TTInterrupts 1903 * @retval None 1904 */ 1905 #define __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__)) 1906 1907 /** 1908 * @brief Check whether the specified FDCAN TT flag is set or not. 1909 * @param __HANDLE__ FDCAN handle. 1910 * @param __FLAG__ FDCAN TT flag. 1911 * This parameter can be one of @arg FDCAN_TTflags 1912 * @retval FlagStatus 1913 */ 1914 #define __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__)) 1915 1916 /** 1917 * @brief Clear the specified FDCAN TT flags. 1918 * @param __HANDLE__ FDCAN handle. 1919 * @param __FLAG__ specifies the TT flags to clear. 1920 * This parameter can be any combination of @arg FDCAN_TTflags 1921 * @retval None 1922 */ 1923 #define __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__)) 1924 1925 /** @brief Check if the specified FDCAN TT interrupt source is enabled or disabled. 1926 * @param __HANDLE__ FDCAN handle. 1927 * @param __INTERRUPT__ specifies the FDCAN TT interrupt source to check. 1928 * This parameter can be a value of @arg FDCAN_TTInterrupts 1929 * @retval ITStatus 1930 */ 1931 #define __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__)) 1932 1933 /** 1934 * @} 1935 */ 1936 1937 /* Exported functions --------------------------------------------------------*/ 1938 /** @addtogroup FDCAN_Exported_Functions 1939 * @{ 1940 */ 1941 1942 /** @addtogroup FDCAN_Exported_Functions_Group1 1943 * @{ 1944 */ 1945 /* Initialization and de-initialization functions *****************************/ 1946 HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan); 1947 HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan); 1948 void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan); 1949 void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan); 1950 HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan); 1951 HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan); 1952 1953 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 1954 /* Callbacks Register/UnRegister functions ***********************************/ 1955 HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback); 1956 HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID); 1957 HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback); 1958 HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan); 1959 HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback); 1960 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan); 1961 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback); 1962 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan); 1963 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback); 1964 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan); 1965 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback); 1966 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan); 1967 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback); 1968 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan); 1969 HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback); 1970 HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan); 1971 HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback); 1972 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan); 1973 HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback); 1974 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan); 1975 HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback); 1976 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan); 1977 HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback); 1978 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan); 1979 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 1980 /** 1981 * @} 1982 */ 1983 1984 /** @addtogroup FDCAN_Exported_Functions_Group2 1985 * @{ 1986 */ 1987 /* Configuration functions ****************************************************/ 1988 HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig); 1989 uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan); 1990 HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan); 1991 uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter); 1992 HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig); 1993 HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt); 1994 HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask); 1995 HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode); 1996 HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark); 1997 HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue); 1998 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler); 1999 HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation); 2000 HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan); 2001 uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); 2002 HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); 2003 HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod); 2004 HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 2005 HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 2006 uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 2007 HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 2008 HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter); 2009 HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); 2010 HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); 2011 HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan); 2012 HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan); 2013 HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); 2014 HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); 2015 /** 2016 * @} 2017 */ 2018 2019 /** @addtogroup FDCAN_Exported_Functions_Group3 2020 * @{ 2021 */ 2022 /* Control functions **********************************************************/ 2023 HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan); 2024 HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan); 2025 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData); 2026 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex); 2027 HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); 2028 uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan); 2029 HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); 2030 HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData); 2031 HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent); 2032 HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus); 2033 HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus); 2034 HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters); 2035 uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex); 2036 uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex); 2037 uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo); 2038 uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan); 2039 uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); 2040 HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); 2041 /** 2042 * @} 2043 */ 2044 2045 /** @addtogroup FDCAN_Exported_Functions_Group4 2046 * @{ 2047 */ 2048 /* TT Configuration and control functions**************************************/ 2049 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams); 2050 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload); 2051 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig); 2052 HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset); 2053 HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator); 2054 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity); 2055 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle); 2056 HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); 2057 HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); 2058 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); 2059 HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); 2060 HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan); 2061 HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan); 2062 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan); 2063 HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan); 2064 HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan); 2065 HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan); 2066 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase); 2067 HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan); 2068 HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan); 2069 HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus); 2070 /** 2071 * @} 2072 */ 2073 2074 /** @addtogroup FDCAN_Exported_Functions_Group5 2075 * @{ 2076 */ 2077 /* Interrupts management ******************************************************/ 2078 HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine); 2079 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine); 2080 HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes); 2081 HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs); 2082 HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs); 2083 HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs); 2084 void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan); 2085 /** 2086 * @} 2087 */ 2088 2089 /** @addtogroup FDCAN_Exported_Functions_Group6 2090 * @{ 2091 */ 2092 /* Callback functions *********************************************************/ 2093 void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs); 2094 void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); 2095 void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); 2096 void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); 2097 void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan); 2098 void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); 2099 void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); 2100 void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan); 2101 void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan); 2102 void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan); 2103 void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan); 2104 void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan); 2105 void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); 2106 void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs); 2107 void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs); 2108 void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); 2109 void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs); 2110 /** 2111 * @} 2112 */ 2113 2114 /** @addtogroup FDCAN_Exported_Functions_Group7 2115 * @{ 2116 */ 2117 /* Peripheral State functions *************************************************/ 2118 uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan); 2119 HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan); 2120 /** 2121 * @} 2122 */ 2123 2124 /** 2125 * @} 2126 */ 2127 2128 /* Private types -------------------------------------------------------------*/ 2129 /** @defgroup FDCAN_Private_Types FDCAN Private Types 2130 * @{ 2131 */ 2132 2133 /** 2134 * @} 2135 */ 2136 2137 /* Private variables ---------------------------------------------------------*/ 2138 /** @defgroup FDCAN_Private_Variables FDCAN Private Variables 2139 * @{ 2140 */ 2141 2142 /** 2143 * @} 2144 */ 2145 2146 /* Private constants ---------------------------------------------------------*/ 2147 /** @defgroup FDCAN_Private_Constants FDCAN Private Constants 2148 * @{ 2149 */ 2150 2151 /** 2152 * @} 2153 */ 2154 2155 /* Private macros ------------------------------------------------------------*/ 2156 /** @defgroup FDCAN_Private_Macros FDCAN Private Macros 2157 * @{ 2158 */ 2159 #define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC ) || \ 2160 ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \ 2161 ((FORMAT) == FDCAN_FRAME_FD_BRS )) 2162 #define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL ) || \ 2163 ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \ 2164 ((MODE) == FDCAN_MODE_BUS_MONITORING ) || \ 2165 ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK ) || \ 2166 ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK )) 2167 2168 #define IS_FDCAN_CLOCK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_DISABLE) || \ 2169 ((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_ENABLE )) 2170 2171 #define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \ 2172 ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \ 2173 ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \ 2174 ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \ 2175 ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \ 2176 ((CKDIV) == FDCAN_CLOCK_DIV10) || \ 2177 ((CKDIV) == FDCAN_CLOCK_DIV12) || \ 2178 ((CKDIV) == FDCAN_CLOCK_DIV14) || \ 2179 ((CKDIV) == FDCAN_CLOCK_DIV16) || \ 2180 ((CKDIV) == FDCAN_CLOCK_DIV18) || \ 2181 ((CKDIV) == FDCAN_CLOCK_DIV20) || \ 2182 ((CKDIV) == FDCAN_CLOCK_DIV22) || \ 2183 ((CKDIV) == FDCAN_CLOCK_DIV24) || \ 2184 ((CKDIV) == FDCAN_CLOCK_DIV26) || \ 2185 ((CKDIV) == FDCAN_CLOCK_DIV28) || \ 2186 ((CKDIV) == FDCAN_CLOCK_DIV30)) 2187 #define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U)) 2188 #define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U)) 2189 #define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U)) 2190 #define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U)) 2191 #define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U)) 2192 #define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U)) 2193 #define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U)) 2194 #define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U)) 2195 #define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX)) 2196 #define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN)) 2197 #define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \ 2198 ((SIZE) == FDCAN_DATA_BYTES_12) || \ 2199 ((SIZE) == FDCAN_DATA_BYTES_16) || \ 2200 ((SIZE) == FDCAN_DATA_BYTES_20) || \ 2201 ((SIZE) == FDCAN_DATA_BYTES_24) || \ 2202 ((SIZE) == FDCAN_DATA_BYTES_32) || \ 2203 ((SIZE) == FDCAN_DATA_BYTES_48) || \ 2204 ((SIZE) == FDCAN_DATA_BYTES_64)) 2205 #define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \ 2206 ((MODE) == FDCAN_TX_QUEUE_OPERATION)) 2207 #define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \ 2208 ((ID_TYPE) == FDCAN_EXTENDED_ID)) 2209 #define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE ) || \ 2210 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0 ) || \ 2211 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1 ) || \ 2212 ((CONFIG) == FDCAN_FILTER_REJECT ) || \ 2213 ((CONFIG) == FDCAN_FILTER_HP ) || \ 2214 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \ 2215 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \ 2216 ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER )) 2217 #define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \ 2218 ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \ 2219 ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \ 2220 ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \ 2221 ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \ 2222 ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \ 2223 ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \ 2224 ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \ 2225 ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \ 2226 ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \ 2227 ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \ 2228 ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \ 2229 ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \ 2230 ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \ 2231 ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \ 2232 ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31)) 2233 #define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \ 2234 ((FIFO) == FDCAN_RX_FIFO1)) 2235 #define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \ 2236 ((MODE) == FDCAN_RX_FIFO_OVERWRITE)) 2237 #define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \ 2238 ((TYPE) == FDCAN_FILTER_DUAL ) || \ 2239 ((TYPE) == FDCAN_FILTER_MASK )) 2240 #define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE ) || \ 2241 ((TYPE) == FDCAN_FILTER_DUAL ) || \ 2242 ((TYPE) == FDCAN_FILTER_MASK ) || \ 2243 ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM)) 2244 #define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME ) || \ 2245 ((TYPE) == FDCAN_REMOTE_FRAME)) 2246 #define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \ 2247 ((DLC) == FDCAN_DLC_BYTES_1 ) || \ 2248 ((DLC) == FDCAN_DLC_BYTES_2 ) || \ 2249 ((DLC) == FDCAN_DLC_BYTES_3 ) || \ 2250 ((DLC) == FDCAN_DLC_BYTES_4 ) || \ 2251 ((DLC) == FDCAN_DLC_BYTES_5 ) || \ 2252 ((DLC) == FDCAN_DLC_BYTES_6 ) || \ 2253 ((DLC) == FDCAN_DLC_BYTES_7 ) || \ 2254 ((DLC) == FDCAN_DLC_BYTES_8 ) || \ 2255 ((DLC) == FDCAN_DLC_BYTES_12) || \ 2256 ((DLC) == FDCAN_DLC_BYTES_16) || \ 2257 ((DLC) == FDCAN_DLC_BYTES_20) || \ 2258 ((DLC) == FDCAN_DLC_BYTES_24) || \ 2259 ((DLC) == FDCAN_DLC_BYTES_32) || \ 2260 ((DLC) == FDCAN_DLC_BYTES_48) || \ 2261 ((DLC) == FDCAN_DLC_BYTES_64)) 2262 #define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \ 2263 ((ESI) == FDCAN_ESI_PASSIVE)) 2264 #define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \ 2265 ((BRS) == FDCAN_BRS_ON )) 2266 #define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \ 2267 ((FDF) == FDCAN_FD_CAN )) 2268 #define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS ) || \ 2269 ((EFC) == FDCAN_STORE_TX_EVENTS)) 2270 #define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK | CCU_IR_MASK)) == 0U) 2271 #define IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == 0U) 2272 #define IS_FDCAN_FIFO_WATERMARK(FIFO) (((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \ 2273 ((FIFO) == FDCAN_CFG_RX_FIFO0 ) || \ 2274 ((FIFO) == FDCAN_CFG_RX_FIFO1 )) 2275 #define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \ 2276 ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \ 2277 ((DESTINATION) == FDCAN_REJECT )) 2278 #define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \ 2279 ((DESTINATION) == FDCAN_REJECT_REMOTE)) 2280 #define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \ 2281 ((IT_LINE) == FDCAN_INTERRUPT_LINE1)) 2282 #define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \ 2283 ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL)) 2284 #define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \ 2285 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \ 2286 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \ 2287 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \ 2288 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \ 2289 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \ 2290 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \ 2291 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \ 2292 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \ 2293 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \ 2294 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \ 2295 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \ 2296 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \ 2297 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \ 2298 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \ 2299 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16)) 2300 #define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS ) || \ 2301 ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \ 2302 ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0 ) || \ 2303 ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1 )) 2304 #define IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH) (((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \ 2305 ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64)) 2306 #define IS_FDCAN_CALIBRATION_COUNTER(COUNTER) (((COUNTER) == FDCAN_CALIB_TIME_QUANTA_COUNTER ) || \ 2307 ((COUNTER) == FDCAN_CALIB_CLOCK_PERIOD_COUNTER) || \ 2308 ((COUNTER) == FDCAN_CALIB_WATCHDOG_COUNTER )) 2309 #define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD) (((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \ 2310 ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD)) 2311 #define IS_FDCAN_TT_REPEAT_FACTOR(FACTOR) (((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE ) || \ 2312 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \ 2313 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \ 2314 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \ 2315 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \ 2316 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \ 2317 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE)) 2318 #define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER ) || \ 2319 ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP ) || \ 2320 ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE ) || \ 2321 ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \ 2322 ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \ 2323 ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED ) || \ 2324 ((TYPE) == FDCAN_TT_WATCH_TRIGGER ) || \ 2325 ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP ) || \ 2326 ((TYPE) == FDCAN_TT_RX_TRIGGER ) || \ 2327 ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER ) || \ 2328 ((TYPE) == FDCAN_TT_END_OF_LIST )) 2329 #define IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \ 2330 ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT)) 2331 #define IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \ 2332 ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT)) 2333 #define IS_FDCAN_OPERATION_MODE(MODE) (((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \ 2334 ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \ 2335 ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 )) 2336 #define IS_FDCAN_TT_OPERATION(OPERATION) (((OPERATION) == FDCAN_STRICTLY_TT_OPERATION ) || \ 2337 ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION)) 2338 #define IS_FDCAN_TT_TIME_MASTER(FUNCTION) (((FUNCTION) == FDCAN_TT_SLAVE ) || \ 2339 ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER)) 2340 #define IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC) (((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \ 2341 ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE )) 2342 #define IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING) (((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \ 2343 ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE )) 2344 #define IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \ 2345 ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE )) 2346 #define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \ 2347 ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING)) 2348 #define IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER) (((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \ 2349 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \ 2350 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \ 2351 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \ 2352 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \ 2353 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \ 2354 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64)) 2355 #define IS_FDCAN_TT_CYCLE_START_SYNC(SYNC) (((SYNC) == FDCAN_TT_NO_SYNC_PULSE ) || \ 2356 ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \ 2357 ((SYNC) == FDCAN_TT_SYNC_MATRIX_START )) 2358 #define IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1U) && ((NTU) <= 16U)) 2359 #define IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000U) && ((NUMERATOR) <= 0x1FFFFU)) 2360 #define IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001U) && ((DENOMINATOR) <= 0x3FFFU)) 2361 #define IS_FDCAN_TT_TUR_LEVEL_1(NC,DC) ((NC) >= (4U * (DC))) 2362 #define IS_FDCAN_TT_TUR_LEVEL_0_2(NC,DC) ((NC) >= (8U * (DC))) 2363 #define IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \ 2364 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \ 2365 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \ 2366 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3)) 2367 #define IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \ 2368 ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \ 2369 ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \ 2370 ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3)) 2371 #define IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFFU) && ((TIME) != 0x8000U)) 2372 #define IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED ) || \ 2373 ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \ 2374 ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \ 2375 ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME)) 2376 #define IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_STOP_WATCH_RISING ) || \ 2377 ((POLARITY) == FDCAN_TT_STOP_WATCH_FALLING)) 2378 #define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \ 2379 ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \ 2380 ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \ 2381 ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME)) 2382 2383 #define FDCAN_CHECK_IT_SOURCE(__IE__, __IT__) ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET) 2384 2385 #define FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) 2386 /** 2387 * @} 2388 */ 2389 2390 /* Private functions prototypes ----------------------------------------------*/ 2391 /** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes 2392 * @{ 2393 */ 2394 2395 /** 2396 * @} 2397 */ 2398 2399 /* Private functions ---------------------------------------------------------*/ 2400 /** @defgroup FDCAN_Private_Functions FDCAN Private Functions 2401 * @{ 2402 */ 2403 2404 /** 2405 * @} 2406 */ 2407 /** 2408 * @} 2409 */ 2410 2411 /** 2412 * @} 2413 */ 2414 #endif /* FDCAN1 */ 2415 2416 #ifdef __cplusplus 2417 } 2418 #endif 2419 2420 #endif /* STM32H7xx_HAL_FDCAN_H */ 2421 2422 2423
