1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_eth.h 4 * @author MCD Application Team 5 * @brief Header file of ETH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H7xx_HAL_ETH_H 21 #define STM32H7xx_HAL_ETH_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32h7xx_hal_def.h" 30 31 #if defined(ETH) 32 33 /** @addtogroup STM32H7xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup ETH 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 #ifndef ETH_TX_DESC_CNT 43 #define ETH_TX_DESC_CNT 4U 44 #endif /* ETH_TX_DESC_CNT */ 45 46 #ifndef ETH_RX_DESC_CNT 47 #define ETH_RX_DESC_CNT 4U 48 #endif /* ETH_RX_DESC_CNT */ 49 50 #ifndef ETH_SWRESET_TIMEOUT 51 #define ETH_SWRESET_TIMEOUT 500U 52 #endif /* ETH_SWRESET_TIMEOUT */ 53 54 #ifndef ETH_MDIO_BUS_TIMEOUT 55 #define ETH_MDIO_BUS_TIMEOUT 1000U 56 #endif /* ETH_MDIO_BUS_TIMEOUT */ 57 58 #ifndef ETH_MAC_US_TICK 59 #define ETH_MAC_US_TICK 1000000U 60 #endif /* ETH_MAC_US_TICK */ 61 62 /*********************** Descriptors struct def section ************************/ 63 /** @defgroup ETH_Exported_Types ETH Exported Types 64 * @{ 65 */ 66 67 /** 68 * @brief ETH DMA Descriptor structure definition 69 */ 70 typedef struct 71 { 72 __IO uint32_t DESC0; 73 __IO uint32_t DESC1; 74 __IO uint32_t DESC2; 75 __IO uint32_t DESC3; 76 uint32_t BackupAddr0; /* used to store rx buffer 1 address */ 77 uint32_t BackupAddr1; /* used to store rx buffer 2 address */ 78 } ETH_DMADescTypeDef; 79 /** 80 * 81 */ 82 83 /** 84 * @brief ETH Buffers List structure definition 85 */ 86 typedef struct __ETH_BufferTypeDef 87 { 88 uint8_t *buffer; /*<! buffer address */ 89 90 uint32_t len; /*<! buffer length */ 91 92 struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */ 93 } ETH_BufferTypeDef; 94 /** 95 * 96 */ 97 98 /** 99 * @brief DMA Transmit Descriptors Wrapper structure definition 100 */ 101 typedef struct 102 { 103 uint32_t TxDesc[ETH_TX_DESC_CNT]; /*<! Tx DMA descriptors addresses */ 104 105 uint32_t CurTxDesc; /*<! Current Tx descriptor index for packet transmission */ 106 107 uint32_t *PacketAddress[ETH_TX_DESC_CNT]; /*<! Ethernet packet addresses array */ 108 109 uint32_t *CurrentPacketAddress; /*<! Current transmit NX_PACKET addresses */ 110 111 uint32_t BuffersInUse; /*<! Buffers in Use */ 112 113 uint32_t releaseIndex; /*<! Release index */ 114 } ETH_TxDescListTypeDef; 115 /** 116 * 117 */ 118 119 /** 120 * @brief Transmit Packet Configuration structure definition 121 */ 122 typedef struct 123 { 124 uint32_t Attributes; /*!< Tx packet HW features capabilities. 125 This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/ 126 127 uint32_t Length; /*!< Total packet length */ 128 129 ETH_BufferTypeDef *TxBuffer; /*!< Tx buffers pointers */ 130 131 uint32_t SrcAddrCtrl; /*!< Specifies the source address insertion control. 132 This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */ 133 134 uint32_t CRCPadCtrl; /*!< Specifies the CRC and Pad insertion and replacement control. 135 This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control */ 136 137 uint32_t ChecksumCtrl; /*!< Specifies the checksum insertion control. 138 This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control */ 139 140 uint32_t MaxSegmentSize; /*!< Sets TCP maximum segment size only when TCP segmentation is enabled. 141 This parameter can be a value from 0x0 to 0x3FFF */ 142 143 uint32_t PayloadLen; /*!< Sets Total payload length only when TCP segmentation is enabled. 144 This parameter can be a value from 0x0 to 0x3FFFF */ 145 146 uint32_t TCPHeaderLen; /*!< Sets TCP header length only when TCP segmentation is enabled. 147 This parameter can be a value from 0x5 to 0xF */ 148 149 uint32_t VlanTag; /*!< Sets VLAN Tag only when VLAN is enabled. 150 This parameter can be a value from 0x0 to 0xFFFF*/ 151 152 uint32_t VlanCtrl; /*!< Specifies VLAN Tag insertion control only when VLAN is enabled. 153 This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */ 154 155 uint32_t InnerVlanTag; /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled. 156 This parameter can be a value from 0x0 to 0x3FFFF */ 157 158 uint32_t InnerVlanCtrl; /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled. 159 This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control */ 160 161 void *pData; /*!< Specifies Application packet pointer to save */ 162 163 } ETH_TxPacketConfig; 164 /** 165 * 166 */ 167 168 /** 169 * @brief ETH Timestamp structure definition 170 */ 171 typedef struct 172 { 173 uint32_t TimeStampLow; 174 uint32_t TimeStampHigh; 175 176 } ETH_TimeStampTypeDef; 177 /** 178 * 179 */ 180 181 #ifdef HAL_ETH_USE_PTP 182 /** 183 * @brief ETH Timeupdate structure definition 184 */ 185 typedef struct 186 { 187 uint32_t Seconds; 188 uint32_t NanoSeconds; 189 } ETH_TimeTypeDef; 190 /** 191 * 192 */ 193 #endif /* HAL_ETH_USE_PTP */ 194 195 /** 196 * @brief DMA Receive Descriptors Wrapper structure definition 197 */ 198 typedef struct 199 { 200 uint32_t RxDesc[ETH_RX_DESC_CNT]; /*<! Rx DMA descriptors addresses. */ 201 202 uint32_t ItMode; /*<! If 1, DMA will generate the Rx complete interrupt. 203 If 0, DMA will not generate the Rx complete interrupt. */ 204 205 uint32_t RxDescIdx; /*<! Current Rx descriptor. */ 206 207 uint32_t RxDescCnt; /*<! Number of descriptors . */ 208 209 uint32_t RxDataLength; /*<! Received Data Length. */ 210 211 uint32_t RxBuildDescIdx; /*<! Current Rx Descriptor for building descriptors. */ 212 213 uint32_t RxBuildDescCnt; /*<! Number of Rx Descriptors awaiting building. */ 214 215 uint32_t pRxLastRxDesc; /*<! Last received descriptor. */ 216 217 ETH_TimeStampTypeDef TimeStamp; /*<! Time Stamp Low value for receive. */ 218 219 void *pRxStart; /*<! Pointer to the first buff. */ 220 221 void *pRxEnd; /*<! Pointer to the last buff. */ 222 223 } ETH_RxDescListTypeDef; 224 /** 225 * 226 */ 227 228 /** 229 * @brief ETH MAC Configuration Structure definition 230 */ 231 typedef struct 232 { 233 uint32_t 234 SourceAddrControl; /*!< Selects the Source Address Insertion or Replacement Control. 235 This parameter can be a value of @ref ETH_Source_Addr_Control */ 236 237 FunctionalState 238 ChecksumOffload; /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */ 239 240 uint32_t InterPacketGapVal; /*!< Sets the minimum IPG between Packet during transmission. 241 This parameter can be a value of @ref ETH_Inter_Packet_Gap */ 242 243 FunctionalState GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */ 244 245 FunctionalState Support2KPacket; /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */ 246 247 FunctionalState CRCStripTypePacket; /*!< Enables or disables the CRC stripping for Type packets.*/ 248 249 FunctionalState AutomaticPadCRCStrip; /*!< Enables or disables the Automatic MAC Pad/CRC Stripping.*/ 250 251 FunctionalState Watchdog; /*!< Enables or disables the Watchdog timer on Rx path.*/ 252 253 FunctionalState Jabber; /*!< Enables or disables Jabber timer on Tx path.*/ 254 255 FunctionalState JumboPacket; /*!< Enables or disables receiving Jumbo Packet 256 When enabled, the MAC allows jumbo packets of 9,018 bytes 257 without reporting a giant packet error */ 258 259 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. 260 This parameter can be a value of @ref ETH_Speed */ 261 262 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode 263 This parameter can be a value of @ref ETH_Duplex_Mode */ 264 265 FunctionalState LoopbackMode; /*!< Enables or disables the loopback mode */ 266 267 FunctionalState 268 CarrierSenseBeforeTransmit; /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */ 269 270 FunctionalState ReceiveOwn; /*!< Enables or disables the Receive Own in Half Duplex mode. */ 271 272 FunctionalState 273 CarrierSenseDuringTransmit; /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */ 274 275 FunctionalState 276 RetryTransmission; /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/ 277 278 uint32_t BackOffLimit; /*!< Selects the BackOff limit value. 279 This parameter can be a value of @ref ETH_Back_Off_Limit */ 280 281 FunctionalState 282 DeferralCheck; /*!< Enables or disables the deferral check function in Half Duplex mode. */ 283 284 uint32_t 285 PreambleLength; /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode). 286 This parameter can be a value of @ref ETH_Preamble_Length */ 287 288 FunctionalState 289 UnicastSlowProtocolPacketDetect; /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */ 290 291 FunctionalState SlowProtocolDetect; /*!< Enable or disables the Slow Protocol Detection. */ 292 293 FunctionalState CRCCheckingRxPackets; /*!< Enable or disables the CRC Checking for Received Packets. */ 294 295 uint32_t 296 GiantPacketSizeLimit; /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is 297 greater than the value programmed in this field in units of bytes 298 This parameter must be a number between 299 Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte). */ 300 301 FunctionalState ExtendedInterPacketGap; /*!< Enable or disables the extended inter packet gap. */ 302 303 uint32_t ExtendedInterPacketGapVal; /*!< Sets the Extended IPG between Packet during transmission. 304 This parameter can be a value from 0x0 to 0xFF */ 305 306 FunctionalState ProgrammableWatchdog; /*!< Enable or disables the Programmable Watchdog.*/ 307 308 uint32_t WatchdogTimeout; /*!< This field is used as watchdog timeout for a received packet 309 This parameter can be a value of @ref ETH_Watchdog_Timeout */ 310 311 uint32_t 312 PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control packet. 313 This parameter must be a number between 314 Min_Data = 0x0 and Max_Data = 0xFFFF.*/ 315 316 FunctionalState 317 ZeroQuantaPause; /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/ 318 319 uint32_t 320 PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet. 321 This parameter can be a value of @ref ETH_Pause_Low_Threshold */ 322 323 FunctionalState 324 TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode 325 or the MAC back pressure operation in Half Duplex mode */ 326 327 FunctionalState 328 UnicastPausePacketDetect; /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */ 329 330 FunctionalState ReceiveFlowControl; /*!< Enables or disables the MAC to decodes the received Pause packet 331 and disables its transmitter for a specified (Pause) time */ 332 333 uint32_t TransmitQueueMode; /*!< Specifies the Transmit Queue operating mode. 334 This parameter can be a value of @ref ETH_Transmit_Mode */ 335 336 uint32_t ReceiveQueueMode; /*!< Specifies the Receive Queue operating mode. 337 This parameter can be a value of @ref ETH_Receive_Mode */ 338 339 FunctionalState DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets. */ 340 341 FunctionalState ForwardRxErrorPacket; /*!< Enables or disables forwarding Error Packets. */ 342 343 FunctionalState ForwardRxUndersizedGoodPacket; /*!< Enables or disables forwarding Undersized Good Packets.*/ 344 } ETH_MACConfigTypeDef; 345 /** 346 * 347 */ 348 349 /** 350 * @brief ETH DMA Configuration Structure definition 351 */ 352 typedef struct 353 { 354 uint32_t DMAArbitration; /*!< Sets the arbitration scheme between DMA Tx and Rx 355 This parameter can be a value of @ref ETH_DMA_Arbitration */ 356 357 FunctionalState AddressAlignedBeats; /*!< Enables or disables the AHB Master interface address aligned 358 burst transfers on Read and Write channels */ 359 360 uint32_t BurstMode; /*!< Sets the AHB Master interface burst transfers. 361 This parameter can be a value of @ref ETH_Burst_Mode */ 362 363 FunctionalState RebuildINCRxBurst; /*!< Enables or disables the AHB Master to rebuild the pending beats 364 of any initiated burst transfer with INCRx and SINGLE transfers. */ 365 366 FunctionalState PBLx8Mode; /*!< Enables or disables the PBL multiplication by eight. */ 367 368 uint32_t 369 TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. 370 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ 371 372 FunctionalState 373 SecondPacketOperate; /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second 374 Packet of Transmit data even before 375 obtaining the status for the first one. */ 376 377 uint32_t 378 RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. 379 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 380 381 FunctionalState FlushRxPacket; /*!< Enables or disables the Rx Packet Flush */ 382 383 FunctionalState TCPSegmentation; /*!< Enables or disables the TCP Segmentation */ 384 385 uint32_t 386 MaximumSegmentSize; /*!< Sets the maximum segment size that should be used while segmenting the packet 387 This parameter can be a value from 0x40 to 0x3FFF */ 388 } ETH_DMAConfigTypeDef; 389 /** 390 * 391 */ 392 393 /** 394 * @brief HAL ETH Media Interfaces enum definition 395 */ 396 typedef enum 397 { 398 HAL_ETH_MII_MODE = 0x00U, /*!< Media Independent Interface */ 399 HAL_ETH_RMII_MODE = 0x01U /*!< Reduced Media Independent Interface */ 400 } ETH_MediaInterfaceTypeDef; 401 /** 402 * 403 */ 404 405 #ifdef HAL_ETH_USE_PTP 406 /** 407 * @brief HAL ETH PTP Update type enum definition 408 */ 409 typedef enum 410 { 411 HAL_ETH_PTP_POSITIVE_UPDATE = 0x00000000U, /*!< PTP positive time update */ 412 HAL_ETH_PTP_NEGATIVE_UPDATE = 0x00000001U /*!< PTP negative time update */ 413 } ETH_PtpUpdateTypeDef; 414 /** 415 * 416 */ 417 #endif /* HAL_ETH_USE_PTP */ 418 419 /** 420 * @brief ETH Init Structure definition 421 */ 422 typedef struct 423 { 424 425 uint8_t 426 *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ 427 428 ETH_MediaInterfaceTypeDef MediaInterface; /*!< Selects the MII interface or the RMII interface. */ 429 430 ETH_DMADescTypeDef 431 *TxDesc; /*!< Provides the address of the first DMA Tx descriptor in the list */ 432 433 ETH_DMADescTypeDef 434 *RxDesc; /*!< Provides the address of the first DMA Rx descriptor in the list */ 435 436 uint32_t RxBuffLen; /*!< Provides the length of Rx buffers size */ 437 438 } ETH_InitTypeDef; 439 /** 440 * 441 */ 442 443 #ifdef HAL_ETH_USE_PTP 444 /** 445 * @brief ETH PTP Init Structure definition 446 */ 447 typedef struct 448 { 449 uint32_t Timestamp; /*!< Enable Timestamp */ 450 uint32_t TimestampUpdateMode; /*!< Fine or Coarse Timestamp Update */ 451 uint32_t TimestampInitialize; /*!< Initialize Timestamp */ 452 uint32_t TimestampUpdate; /*!< Timestamp Update */ 453 uint32_t TimestampAddendUpdate; /*!< Timestamp Addend Update */ 454 uint32_t TimestampAll; /*!< Enable Timestamp for All Packets */ 455 uint32_t TimestampRolloverMode; /*!< Timestamp Digital or Binary Rollover Control */ 456 uint32_t TimestampV2; /*!< Enable PTP Packet Processing for Version 2 Format */ 457 uint32_t TimestampEthernet; /*!< Enable Processing of PTP over Ethernet Packets */ 458 uint32_t TimestampIPv6; /*!< Enable Processing of PTP Packets Sent over IPv6-UDP */ 459 uint32_t TimestampIPv4; /*!< Enable Processing of PTP Packets Sent over IPv4-UDP */ 460 uint32_t TimestampEvent; /*!< Enable Timestamp Snapshot for Event Messages */ 461 uint32_t TimestampMaster; /*!< Enable Timestamp Snapshot for Event Messages */ 462 uint32_t TimestampSnapshots; /*!< Select PTP packets for Taking Snapshots */ 463 uint32_t TimestampFilter; /*!< Enable MAC Address for PTP Packet Filtering */ 464 uint32_t 465 TimestampChecksumCorrection; /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ 466 uint32_t TimestampStatusMode; /*!< Transmit Timestamp Status Mode */ 467 uint32_t TimestampAddend; /*!< Timestamp addend value */ 468 uint32_t TimestampSubsecondInc; /*!< Subsecond Increment */ 469 470 } ETH_PTP_ConfigTypeDef; 471 /** 472 * 473 */ 474 #endif /* HAL_ETH_USE_PTP */ 475 476 /** 477 * @brief HAL State structures definition 478 */ 479 typedef uint32_t HAL_ETH_StateTypeDef; 480 /** 481 * 482 */ 483 484 /** 485 * @brief HAL ETH Rx Get Buffer Function definition 486 */ 487 typedef void (*pETH_rxAllocateCallbackTypeDef)(uint8_t **buffer); /*!< pointer to an ETH Rx Get Buffer Function */ 488 /** 489 * 490 */ 491 492 /** 493 * @brief HAL ETH Rx Set App Data Function definition 494 */ 495 typedef void (*pETH_rxLinkCallbackTypeDef)(void **pStart, void **pEnd, uint8_t *buff, 496 uint16_t Length); /*!< pointer to an ETH Rx Set App Data Function */ 497 /** 498 * 499 */ 500 501 /** 502 * @brief HAL ETH Tx Free Function definition 503 */ 504 typedef void (*pETH_txFreeCallbackTypeDef)(uint32_t *buffer); /*!< pointer to an ETH Tx Free function */ 505 /** 506 * 507 */ 508 509 /** 510 * @brief HAL ETH Tx Free Function definition 511 */ 512 typedef void (*pETH_txPtpCallbackTypeDef)(uint32_t *buffer, 513 ETH_TimeStampTypeDef *timestamp); /*!< pointer to an ETH Tx Free function */ 514 /** 515 * 516 */ 517 518 /** 519 * @brief ETH Handle Structure definition 520 */ 521 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 522 typedef struct __ETH_HandleTypeDef 523 #else 524 typedef struct 525 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 526 { 527 ETH_TypeDef *Instance; /*!< Register base address */ 528 529 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ 530 531 ETH_TxDescListTypeDef TxDescList; /*!< Tx descriptor wrapper: holds all Tx descriptors list 532 addresses and current descriptor index */ 533 534 ETH_RxDescListTypeDef RxDescList; /*!< Rx descriptor wrapper: holds all Rx descriptors list 535 addresses and current descriptor index */ 536 537 #ifdef HAL_ETH_USE_PTP 538 ETH_TimeStampTypeDef TxTimestamp; /*!< Tx Timestamp */ 539 #endif /* HAL_ETH_USE_PTP */ 540 541 __IO HAL_ETH_StateTypeDef gState; /*!< ETH state information related to global Handle management 542 and also related to Tx operations. This parameter can 543 be a value of @ref HAL_ETH_StateTypeDef */ 544 545 __IO uint32_t ErrorCode; /*!< Holds the global Error code of the ETH HAL status machine 546 This parameter can be a value of @ref ETH_Error_Code.*/ 547 548 __IO uint32_t 549 DMAErrorCode; /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs 550 This parameter can be a combination of 551 @ref ETH_DMA_Status_Flags */ 552 553 __IO uint32_t 554 MACErrorCode; /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs 555 This parameter can be a combination of 556 @ref ETH_MAC_Rx_Tx_Status */ 557 558 __IO uint32_t MACWakeUpEvent; /*!< Holds the Wake Up event when the MAC exit the power down mode 559 This parameter can be a value of 560 @ref ETH_MAC_Wake_Up_Event */ 561 562 __IO uint32_t MACLPIEvent; /*!< Holds the LPI event when the an LPI status interrupt occurs. 563 This parameter can be a value of @ref ETHEx_LPI_Event */ 564 565 __IO uint32_t IsPtpConfigured; /*!< Holds the PTP configuration status. 566 This parameter can be a value of 567 @ref ETH_PTP_Config_Status */ 568 569 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 570 571 void (* TxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Tx Complete Callback */ 572 void (* RxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Rx Complete Callback */ 573 void (* ErrorCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Error Callback */ 574 void (* PMTCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Power Management Callback */ 575 void (* EEECallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH EEE Callback */ 576 void (* WakeUpCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Wake UP Callback */ 577 578 void (* MspInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp Init callback */ 579 void (* MspDeInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp DeInit callback */ 580 581 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 582 583 pETH_rxAllocateCallbackTypeDef rxAllocateCallback; /*!< ETH Rx Get Buffer Function */ 584 pETH_rxLinkCallbackTypeDef rxLinkCallback; /*!< ETH Rx Set App Data Function */ 585 pETH_txFreeCallbackTypeDef txFreeCallback; /*!< ETH Tx Free Function */ 586 pETH_txPtpCallbackTypeDef txPtpCallback; /*!< ETH Tx Handle Ptp Function */ 587 588 } ETH_HandleTypeDef; 589 /** 590 * 591 */ 592 593 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 594 /** 595 * @brief HAL ETH Callback ID enumeration definition 596 */ 597 typedef enum 598 { 599 HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */ 600 HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */ 601 602 HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */ 603 HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */ 604 HAL_ETH_ERROR_CB_ID = 0x04U, /*!< ETH Error Callback ID */ 605 HAL_ETH_PMT_CB_ID = 0x06U, /*!< ETH Power Management Callback ID */ 606 HAL_ETH_EEE_CB_ID = 0x07U, /*!< ETH EEE Callback ID */ 607 HAL_ETH_WAKEUP_CB_ID = 0x08U /*!< ETH Wake UP Callback ID */ 608 609 610 } HAL_ETH_CallbackIDTypeDef; 611 612 /** 613 * @brief HAL ETH Callback pointer definition 614 */ 615 typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef *heth); /*!< pointer to an ETH callback function */ 616 617 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 618 619 /** 620 * @brief ETH MAC filter structure definition 621 */ 622 typedef struct 623 { 624 FunctionalState PromiscuousMode; /*!< Enable or Disable Promiscuous Mode */ 625 626 FunctionalState ReceiveAllMode; /*!< Enable or Disable Receive All Mode */ 627 628 FunctionalState HachOrPerfectFilter; /*!< Enable or Disable Perfect filtering in addition to Hash filtering */ 629 630 FunctionalState HashUnicast; /*!< Enable or Disable Hash filtering on unicast packets */ 631 632 FunctionalState HashMulticast; /*!< Enable or Disable Hash filtering on multicast packets */ 633 634 FunctionalState PassAllMulticast; /*!< Enable or Disable passing all multicast packets */ 635 636 FunctionalState SrcAddrFiltering; /*!< Enable or Disable source address filtering module */ 637 638 FunctionalState SrcAddrInverseFiltering; /*!< Enable or Disable source address inverse filtering */ 639 640 FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */ 641 642 FunctionalState BroadcastFilter; /*!< Enable or Disable broadcast filter */ 643 644 uint32_t ControlPacketsFilter; /*!< Set the control packets filter 645 This parameter can be a value of @ref ETH_Control_Packets_Filter */ 646 } ETH_MACFilterConfigTypeDef; 647 /** 648 * 649 */ 650 651 /** 652 * @brief ETH Power Down structure definition 653 */ 654 typedef struct 655 { 656 FunctionalState WakeUpPacket; /*!< Enable or Disable Wake up packet detection in power down mode */ 657 658 FunctionalState MagicPacket; /*!< Enable or Disable Magic packet detection in power down mode */ 659 660 FunctionalState GlobalUnicast; /*!< Enable or Disable Global unicast packet detection in power down mode */ 661 662 FunctionalState WakeUpForward; /*!< Enable or Disable Forwarding Wake up packets */ 663 664 } ETH_PowerDownConfigTypeDef; 665 /** 666 * 667 */ 668 669 /** 670 * @} 671 */ 672 673 /* Exported constants --------------------------------------------------------*/ 674 /** @defgroup ETH_Exported_Constants ETH Exported Constants 675 * @{ 676 */ 677 678 /** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition 679 * @{ 680 */ 681 682 /* 683 DMA Tx Normal Descriptor Read Format 684 ----------------------------------------------------------------------------------------------- 685 TDES0 | Buffer1 or Header Address [31:0] | 686 ----------------------------------------------------------------------------------------------- 687 TDES1 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 688 ----------------------------------------------------------------------------------------------- 689 TDES2 | IOC(31) | TTSE(30) | Buff2 Length[29:16] | VTIR[15:14] | Header or Buff1 Length[13:0] | 690 ----------------------------------------------------------------------------------------------- 691 TDES3 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | 692 ----------------------------------------------------------------------------------------------- 693 */ 694 695 /** 696 * @brief Bit definition of TDES0 RF register 697 */ 698 #define ETH_DMATXNDESCRF_B1AP 0xFFFFFFFFU /*!< Transmit Packet Timestamp Low */ 699 700 /** 701 * @brief Bit definition of TDES1 RF register 702 */ 703 #define ETH_DMATXNDESCRF_B2AP 0xFFFFFFFFU /*!< Transmit Packet Timestamp High */ 704 705 /** 706 * @brief Bit definition of TDES2 RF register 707 */ 708 #define ETH_DMATXNDESCRF_IOC 0x80000000U /*!< Interrupt on Completion */ 709 #define ETH_DMATXNDESCRF_TTSE 0x40000000U /*!< Transmit Timestamp Enable */ 710 #define ETH_DMATXNDESCRF_B2L 0x3FFF0000U /*!< Buffer 2 Length */ 711 #define ETH_DMATXNDESCRF_VTIR 0x0000C000U /*!< VLAN Tag Insertion or Replacement mask */ 712 #define ETH_DMATXNDESCRF_VTIR_DISABLE 0x00000000U /*!< Do not add a VLAN tag. */ 713 #define ETH_DMATXNDESCRF_VTIR_REMOVE 0x00004000U /*!< Remove the VLAN tag from the packets before transmission. */ 714 #define ETH_DMATXNDESCRF_VTIR_INSERT 0x00008000U /*!< Insert a VLAN tag. */ 715 #define ETH_DMATXNDESCRF_VTIR_REPLACE 0x0000C000U /*!< Replace the VLAN tag. */ 716 #define ETH_DMATXNDESCRF_B1L 0x00003FFFU /*!< Buffer 1 Length */ 717 #define ETH_DMATXNDESCRF_HL 0x000003FFU /*!< Header Length */ 718 719 /** 720 * @brief Bit definition of TDES3 RF register 721 */ 722 #define ETH_DMATXNDESCRF_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ 723 #define ETH_DMATXNDESCRF_CTXT 0x40000000U /*!< Context Type */ 724 #define ETH_DMATXNDESCRF_FD 0x20000000U /*!< First Descriptor */ 725 #define ETH_DMATXNDESCRF_LD 0x10000000U /*!< Last Descriptor */ 726 #define ETH_DMATXNDESCRF_CPC 0x0C000000U /*!< CRC Pad Control mask */ 727 #define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT 0x00000000U /*!< CRC Pad Control: CRC and Pad Insertion */ 728 #define ETH_DMATXNDESCRF_CPC_CRC_INSERT 0x04000000U /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */ 729 #define ETH_DMATXNDESCRF_CPC_DISABLE 0x08000000U /*!< CRC Pad Control: Disable CRC Insertion */ 730 #define ETH_DMATXNDESCRF_CPC_CRC_REPLACE 0x0C000000U /*!< CRC Pad Control: CRC Replacement */ 731 #define ETH_DMATXNDESCRF_SAIC 0x03800000U /*!< SA Insertion Control mask*/ 732 #define ETH_DMATXNDESCRF_SAIC_DISABLE 0x00000000U /*!< SA Insertion Control: Do not include the source address */ 733 #define ETH_DMATXNDESCRF_SAIC_INSERT 0x00800000U /*!< SA Insertion Control: Include or insert the source address */ 734 #define ETH_DMATXNDESCRF_SAIC_REPLACE 0x01000000U /*!< SA Insertion Control: Replace the source address */ 735 #define ETH_DMATXNDESCRF_THL 0x00780000U /*!< TCP Header Length */ 736 #define ETH_DMATXNDESCRF_TSE 0x00040000U /*!< TCP segmentation enable */ 737 #define ETH_DMATXNDESCRF_CIC 0x00030000U /*!< Checksum Insertion Control: 4 cases */ 738 #define ETH_DMATXNDESCRF_CIC_DISABLE 0x00000000U /*!< Do Nothing: Checksum Engine is disabled */ 739 #define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT 0x00010000U /*!< Only IP header checksum calculation and insertion are enabled. */ 740 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT 0x00020000U /*!< IP header checksum and payload checksum calculation and insertion are 741 enabled, but pseudo header 742 checksum is not 743 calculated in hardware */ 744 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC 0x00030000U /*!< IP Header checksum and payload checksum calculation and insertion are 745 enabled, and pseudo header 746 checksum is 747 calculated in hardware. */ 748 #define ETH_DMATXNDESCRF_TPL 0x0003FFFFU /*!< TCP Payload Length */ 749 #define ETH_DMATXNDESCRF_FL 0x00007FFFU /*!< Transmit End of Ring */ 750 751 /* 752 DMA Tx Normal Descriptor Write Back Format 753 ----------------------------------------------------------------------------------------------- 754 TDES0 | Timestamp Low | 755 ----------------------------------------------------------------------------------------------- 756 TDES1 | Timestamp High | 757 ----------------------------------------------------------------------------------------------- 758 TDES2 | Reserved[31:0] | 759 ----------------------------------------------------------------------------------------------- 760 TDES3 | OWN(31) | Status[30:0] | 761 ----------------------------------------------------------------------------------------------- 762 */ 763 764 /** 765 * @brief Bit definition of TDES0 WBF register 766 */ 767 #define ETH_DMATXNDESCWBF_TTSL 0xFFFFFFFFU /*!< Buffer1 Address Pointer or TSO Header Address Pointer */ 768 769 /** 770 * @brief Bit definition of TDES1 WBF register 771 */ 772 #define ETH_DMATXNDESCWBF_TTSH 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ 773 774 /** 775 * @brief Bit definition of TDES3 WBF register 776 */ 777 #define ETH_DMATXNDESCWBF_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ 778 #define ETH_DMATXNDESCWBF_CTXT 0x40000000U /*!< Context Type */ 779 #define ETH_DMATXNDESCWBF_FD 0x20000000U /*!< First Descriptor */ 780 #define ETH_DMATXNDESCWBF_LD 0x10000000U /*!< Last Descriptor */ 781 #define ETH_DMATXNDESCWBF_TTSS 0x00020000U /*!< Tx Timestamp Status */ 782 #define ETH_DMATXNDESCWBF_DP 0x04000000U /*!< Disable Padding */ 783 #define ETH_DMATXNDESCWBF_TTSE 0x02000000U /*!< Transmit Timestamp Enable */ 784 #define ETH_DMATXNDESCWBF_ES 0x00008000U /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */ 785 #define ETH_DMATXNDESCWBF_JT 0x00004000U /*!< Jabber Timeout */ 786 #define ETH_DMATXNDESCWBF_FF 0x00002000U /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */ 787 #define ETH_DMATXNDESCWBF_PCE 0x00001000U /*!< Payload Checksum Error */ 788 #define ETH_DMATXNDESCWBF_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */ 789 #define ETH_DMATXNDESCWBF_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */ 790 #define ETH_DMATXNDESCWBF_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */ 791 #define ETH_DMATXNDESCWBF_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */ 792 #define ETH_DMATXNDESCWBF_CC 0x000000F0U /*!< Collision Count */ 793 #define ETH_DMATXNDESCWBF_ED 0x00000008U /*!< Excessive Deferral */ 794 #define ETH_DMATXNDESCWBF_UF 0x00000004U /*!< Underflow Error: late data arrival from the memory */ 795 #define ETH_DMATXNDESCWBF_DB 0x00000002U /*!< Deferred Bit */ 796 #define ETH_DMATXNDESCWBF_IHE 0x00000004U /*!< IP Header Error */ 797 798 799 /* 800 DMA Tx Context Descriptor 801 ----------------------------------------------------------------------------------------------- 802 TDES0 | Timestamp Low | 803 ----------------------------------------------------------------------------------------------- 804 TDES1 | Timestamp High | 805 ----------------------------------------------------------------------------------------------- 806 TDES2 | Inner VLAN Tag[31:16] | Reserved(15) | Maximum Segment Size [14:0] | 807 ----------------------------------------------------------------------------------------------- 808 TDES3 | OWN(31) | Status[30:0] | 809 ----------------------------------------------------------------------------------------------- 810 */ 811 812 /** 813 * @brief Bit definition of Tx context descriptor register 0 814 */ 815 #define ETH_DMATXCDESC_TTSL 0xFFFFFFFFU /*!< Transmit Packet Timestamp Low */ 816 817 /** 818 * @brief Bit definition of Tx context descriptor register 1 819 */ 820 #define ETH_DMATXCDESC_TTSH 0xFFFFFFFFU /*!< Transmit Packet Timestamp High */ 821 822 /** 823 * @brief Bit definition of Tx context descriptor register 2 824 */ 825 #define ETH_DMATXCDESC_IVT 0xFFFF0000U /*!< Inner VLAN Tag */ 826 #define ETH_DMATXCDESC_MSS 0x00003FFFU /*!< Maximum Segment Size */ 827 828 /** 829 * @brief Bit definition of Tx context descriptor register 3 830 */ 831 #define ETH_DMATXCDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ 832 #define ETH_DMATXCDESC_CTXT 0x40000000U /*!< Context Type */ 833 #define ETH_DMATXCDESC_OSTC 0x08000000U /*!< One-Step Timestamp Correction Enable */ 834 #define ETH_DMATXCDESC_TCMSSV 0x04000000U /*!< One-Step Timestamp Correction Input or MSS Valid */ 835 #define ETH_DMATXCDESC_CDE 0x00800000U /*!< Context Descriptor Error */ 836 #define ETH_DMATXCDESC_IVTIR 0x000C0000U /*!< Inner VLAN Tag Insert or Replace Mask */ 837 #define ETH_DMATXCDESC_IVTIR_DISABLE 0x00000000U /*!< Do not add the inner VLAN tag. */ 838 #define ETH_DMATXCDESC_IVTIR_REMOVE 0x00040000U /*!< Remove the inner VLAN tag from the packets before transmission. */ 839 #define ETH_DMATXCDESC_IVTIR_INSERT 0x00080000U /*!< Insert the inner VLAN tag. */ 840 #define ETH_DMATXCDESC_IVTIR_REPLACE 0x000C0000U /*!< Replace the inner VLAN tag. */ 841 #define ETH_DMATXCDESC_IVLTV 0x00020000U /*!< Inner VLAN Tag Valid */ 842 #define ETH_DMATXCDESC_VLTV 0x00010000U /*!< VLAN Tag Valid */ 843 #define ETH_DMATXCDESC_VT 0x0000FFFFU /*!< VLAN Tag */ 844 845 /** 846 * @} 847 */ 848 849 850 /** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition 851 * @{ 852 */ 853 854 /* 855 DMA Rx Normal Descriptor read format 856 ----------------------------------------------------------------------------------------------------------- 857 RDES0 | Buffer1 or Header Address [31:0] | 858 ----------------------------------------------------------------------------------------------------------- 859 RDES1 | Reserved | 860 ----------------------------------------------------------------------------------------------------------- 861 RDES2 | Payload or Buffer2 Address[31:0] | 862 ----------------------------------------------------------------------------------------------------------- 863 RDES3 | OWN(31) | IOC(30) | Reserved [29:26] | BUF2V(25) | BUF1V(24) | Reserved [23:0] | 864 ----------------------------------------------------------------------------------------------------------- 865 */ 866 867 /** 868 * @brief Bit definition of Rx normal descriptor register 0 read format 869 */ 870 #define ETH_DMARXNDESCRF_BUF1AP 0xFFFFFFFFU /*!< Header or Buffer 1 Address Pointer */ 871 872 /** 873 * @brief Bit definition of Rx normal descriptor register 2 read format 874 */ 875 #define ETH_DMARXNDESCRF_BUF2AP 0xFFFFFFFFU /*!< Buffer 2 Address Pointer */ 876 877 /** 878 * @brief Bit definition of Rx normal descriptor register 3 read format 879 */ 880 #define ETH_DMARXNDESCRF_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ 881 #define ETH_DMARXNDESCRF_IOC 0x40000000U /*!< Interrupt Enabled on Completion */ 882 #define ETH_DMARXNDESCRF_BUF2V 0x02000000U /*!< Buffer 2 Address Valid */ 883 #define ETH_DMARXNDESCRF_BUF1V 0x01000000U /*!< Buffer 1 Address Valid */ 884 885 /* 886 DMA Rx Normal Descriptor write back format 887 --------------------------------------------------------------------------------------------------------------------- 888 RDES0 | Inner VLAN Tag[31:16] | Outer VLAN Tag[15:0] | 889 --------------------------------------------------------------------------------------------------------------------- 890 RDES1 | OAM code, or MAC Control Opcode [31:16] | Extended Status | 891 --------------------------------------------------------------------------------------------------------------------- 892 RDES2 | MAC Filter Status[31:16] | VF(15) | Reserved [14:12] | ARP Status [11:10] | Header Length [9:0] | 893 --------------------------------------------------------------------------------------------------------------------- 894 RDES3 | OWN(31) | CTXT(30) | FD(29) | LD(28) | Status[27:16] | ES(15) | Packet Length[14:0] | 895 --------------------------------------------------------------------------------------------------------------------- 896 */ 897 898 /** 899 * @brief Bit definition of Rx normal descriptor register 0 write back format 900 */ 901 #define ETH_DMARXNDESCWBF_IVT 0xFFFF0000U /*!< Inner VLAN Tag */ 902 #define ETH_DMARXNDESCWBF_OVT 0x0000FFFFU /*!< Outer VLAN Tag */ 903 904 /** 905 * @brief Bit definition of Rx normal descriptor register 1 write back format 906 */ 907 #define ETH_DMARXNDESCWBF_OPC 0xFFFF0000U /*!< OAM Sub-Type Code, or MAC Control Packet opcode */ 908 #define ETH_DMARXNDESCWBF_TD 0x00008000U /*!< Timestamp Dropped */ 909 #define ETH_DMARXNDESCWBF_TSA 0x00004000U /*!< Timestamp Available */ 910 #define ETH_DMARXNDESCWBF_PV 0x00002000U /*!< PTP Version */ 911 #define ETH_DMARXNDESCWBF_PFT 0x00001000U /*!< PTP Packet Type */ 912 #define ETH_DMARXNDESCWBF_PMT_NO 0x00000000U /*!< PTP Message Type: No PTP message received */ 913 #define ETH_DMARXNDESCWBF_PMT_SYNC 0x00000100U /*!< PTP Message Type: SYNC (all clock types) */ 914 #define ETH_DMARXNDESCWBF_PMT_FUP 0x00000200U /*!< PTP Message Type: Follow_Up (all clock types) */ 915 #define ETH_DMARXNDESCWBF_PMT_DREQ 0x00000300U /*!< PTP Message Type: Delay_Req (all clock types) */ 916 #define ETH_DMARXNDESCWBF_PMT_DRESP 0x00000400U /*!< PTP Message Type: Delay_Resp (all clock types) */ 917 #define ETH_DMARXNDESCWBF_PMT_PDREQ 0x00000500U /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock) */ 918 #define ETH_DMARXNDESCWBF_PMT_PDRESP 0x00000600U /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock) */ 919 #define ETH_DMARXNDESCWBF_PMT_PDRESPFUP 0x00000700U /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock) */ 920 #define ETH_DMARXNDESCWBF_PMT_ANNOUNCE 0x00000800U /*!< PTP Message Type: Announce */ 921 #define ETH_DMARXNDESCWBF_PMT_MANAG 0x00000900U /*!< PTP Message Type: Management */ 922 #define ETH_DMARXNDESCWBF_PMT_SIGN 0x00000A00U /*!< PTP Message Type: Signaling */ 923 #define ETH_DMARXNDESCWBF_PMT_RESERVED 0x00000F00U /*!< PTP Message Type: PTP packet with Reserved message type */ 924 #define ETH_DMARXNDESCWBF_IPCE 0x00000080U /*!< IP Payload Error */ 925 #define ETH_DMARXNDESCWBF_IPCB 0x00000040U /*!< IP Checksum Bypassed */ 926 #define ETH_DMARXNDESCWBF_IPV6 0x00000020U /*!< IPv6 header Present */ 927 #define ETH_DMARXNDESCWBF_IPV4 0x00000010U /*!< IPv4 header Present */ 928 #define ETH_DMARXNDESCWBF_IPHE 0x00000008U /*!< IP Header Error */ 929 #define ETH_DMARXNDESCWBF_PT 0x00000003U /*!< Payload Type mask */ 930 #define ETH_DMARXNDESCWBF_PT_UNKNOWN 0x00000000U /*!< Payload Type: Unknown type or IP/AV payload not processed */ 931 #define ETH_DMARXNDESCWBF_PT_UDP 0x00000001U /*!< Payload Type: UDP */ 932 #define ETH_DMARXNDESCWBF_PT_TCP 0x00000002U /*!< Payload Type: TCP */ 933 #define ETH_DMARXNDESCWBF_PT_ICMP 0x00000003U /*!< Payload Type: ICMP */ 934 935 /** 936 * @brief Bit definition of Rx normal descriptor register 2 write back format 937 */ 938 #define ETH_DMARXNDESCWBF_L3L4FM 0x20000000U /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */ 939 #define ETH_DMARXNDESCWBF_L4FM 0x10000000U /*!< Layer 4 Filter Match */ 940 #define ETH_DMARXNDESCWBF_L3FM 0x08000000U /*!< Layer 3 Filter Match */ 941 #define ETH_DMARXNDESCWBF_MADRM 0x07F80000U /*!< MAC Address Match or Hash Value */ 942 #define ETH_DMARXNDESCWBF_HF 0x00040000U /*!< Hash Filter Status */ 943 #define ETH_DMARXNDESCWBF_DAF 0x00020000U /*!< Destination Address Filter Fail */ 944 #define ETH_DMARXNDESCWBF_SAF 0x00010000U /*!< SA Address Filter Fail */ 945 #define ETH_DMARXNDESCWBF_VF 0x00008000U /*!< VLAN Filter Status */ 946 #define ETH_DMARXNDESCWBF_ARPNR 0x00000400U /*!< ARP Reply Not Generated */ 947 948 949 /** 950 * @brief Bit definition of Rx normal descriptor register 3 write back format 951 */ 952 #define ETH_DMARXNDESCWBF_OWN 0x80000000U /*!< Own Bit */ 953 #define ETH_DMARXNDESCWBF_CTXT 0x40000000U /*!< Receive Context Descriptor */ 954 #define ETH_DMARXNDESCWBF_FD 0x20000000U /*!< First Descriptor */ 955 #define ETH_DMARXNDESCWBF_LD 0x10000000U /*!< Last Descriptor */ 956 #define ETH_DMARXNDESCWBF_RS2V 0x08000000U /*!< Receive Status RDES2 Valid */ 957 #define ETH_DMARXNDESCWBF_RS1V 0x04000000U /*!< Receive Status RDES1 Valid */ 958 #define ETH_DMARXNDESCWBF_RS0V 0x02000000U /*!< Receive Status RDES0 Valid */ 959 #define ETH_DMARXNDESCWBF_CE 0x01000000U /*!< CRC Error */ 960 #define ETH_DMARXNDESCWBF_GP 0x00800000U /*!< Giant Packet */ 961 #define ETH_DMARXNDESCWBF_RWT 0x00400000U /*!< Receive Watchdog Timeout */ 962 #define ETH_DMARXNDESCWBF_OE 0x00200000U /*!< Overflow Error */ 963 #define ETH_DMARXNDESCWBF_RE 0x00100000U /*!< Receive Error */ 964 #define ETH_DMARXNDESCWBF_DE 0x00080000U /*!< Dribble Bit Error */ 965 #define ETH_DMARXNDESCWBF_LT 0x00070000U /*!< Length/Type Field */ 966 #define ETH_DMARXNDESCWBF_LT_LP 0x00000000U /*!< The packet is a length packet */ 967 #define ETH_DMARXNDESCWBF_LT_TP 0x00010000U /*!< The packet is a type packet */ 968 #define ETH_DMARXNDESCWBF_LT_ARP 0x00030000U /*!< The packet is a ARP Request packet type */ 969 #define ETH_DMARXNDESCWBF_LT_VLAN 0x00040000U /*!< The packet is a type packet with VLAN Tag */ 970 #define ETH_DMARXNDESCWBF_LT_DVLAN 0x00050000U /*!< The packet is a type packet with Double VLAN Tag */ 971 #define ETH_DMARXNDESCWBF_LT_MAC 0x00060000U /*!< The packet is a MAC Control packet type */ 972 #define ETH_DMARXNDESCWBF_LT_OAM 0x00070000U /*!< The packet is a OAM packet type */ 973 #define ETH_DMARXNDESCWBF_ES 0x00008000U /*!< Error Summary */ 974 #define ETH_DMARXNDESCWBF_PL 0x00007FFFU /*!< Packet Length */ 975 976 /* 977 DMA Rx context Descriptor 978 --------------------------------------------------------------------------------------------------------------------- 979 RDES0 | Timestamp Low[31:0] | 980 --------------------------------------------------------------------------------------------------------------------- 981 RDES1 | Timestamp High[31:0] | 982 --------------------------------------------------------------------------------------------------------------------- 983 RDES2 | Reserved | 984 --------------------------------------------------------------------------------------------------------------------- 985 RDES3 | OWN(31) | CTXT(30) | Reserved[29:0] | 986 --------------------------------------------------------------------------------------------------------------------- 987 */ 988 989 /** 990 * @brief Bit definition of Rx context descriptor register 0 991 */ 992 #define ETH_DMARXCDESC_RTSL 0xFFFFFFFFU /*!< Receive Packet Timestamp Low */ 993 994 /** 995 * @brief Bit definition of Rx context descriptor register 1 996 */ 997 #define ETH_DMARXCDESC_RTSH 0xFFFFFFFFU /*!< Receive Packet Timestamp High */ 998 999 /** 1000 * @brief Bit definition of Rx context descriptor register 3 1001 */ 1002 #define ETH_DMARXCDESC_OWN 0x80000000U /*!< Own Bit */ 1003 #define ETH_DMARXCDESC_CTXT 0x40000000U /*!< Receive Context Descriptor */ 1004 1005 /** 1006 * @} 1007 */ 1008 1009 /** @defgroup ETH_Frame_settings ETH frame settings 1010 * @{ 1011 */ 1012 #define ETH_MAX_PACKET_SIZE 1528U /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */ 1013 #define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ 1014 #define ETH_CRC 4U /*!< Ethernet CRC */ 1015 #define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ 1016 #define ETH_MIN_PAYLOAD 46U /*!< Minimum Ethernet payload size */ 1017 #define ETH_MAX_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ 1018 #define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ 1019 /** 1020 * @} 1021 */ 1022 1023 /** @defgroup ETH_Error_Code ETH Error Code 1024 * @{ 1025 */ 1026 #define HAL_ETH_ERROR_NONE 0x00000000U /*!< No error */ 1027 #define HAL_ETH_ERROR_PARAM 0x00000001U /*!< Busy error */ 1028 #define HAL_ETH_ERROR_BUSY 0x00000002U /*!< Parameter error */ 1029 #define HAL_ETH_ERROR_TIMEOUT 0x00000004U /*!< Timeout error */ 1030 #define HAL_ETH_ERROR_DMA 0x00000008U /*!< DMA transfer error */ 1031 #define HAL_ETH_ERROR_MAC 0x00000010U /*!< MAC transfer error */ 1032 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 1033 #define HAL_ETH_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */ 1034 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 1035 /** 1036 * @} 1037 */ 1038 1039 /** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes 1040 * @{ 1041 */ 1042 #define ETH_TX_PACKETS_FEATURES_CSUM 0x00000001U 1043 #define ETH_TX_PACKETS_FEATURES_SAIC 0x00000002U 1044 #define ETH_TX_PACKETS_FEATURES_VLANTAG 0x00000004U 1045 #define ETH_TX_PACKETS_FEATURES_INNERVLANTAG 0x00000008U 1046 #define ETH_TX_PACKETS_FEATURES_TSO 0x00000010U 1047 #define ETH_TX_PACKETS_FEATURES_CRCPAD 0x00000020U 1048 /** 1049 * @} 1050 */ 1051 1052 /** @defgroup ETH_Tx_Packet_Source_Addr_Control ETH Tx Packet Source Addr Control 1053 * @{ 1054 */ 1055 #define ETH_SRC_ADDR_CONTROL_DISABLE ETH_DMATXNDESCRF_SAIC_DISABLE 1056 #define ETH_SRC_ADDR_INSERT ETH_DMATXNDESCRF_SAIC_INSERT 1057 #define ETH_SRC_ADDR_REPLACE ETH_DMATXNDESCRF_SAIC_REPLACE 1058 /** 1059 * @} 1060 */ 1061 1062 /** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control 1063 * @{ 1064 */ 1065 #define ETH_CRC_PAD_DISABLE ETH_DMATXNDESCRF_CPC_DISABLE 1066 #define ETH_CRC_PAD_INSERT ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT 1067 #define ETH_CRC_INSERT ETH_DMATXNDESCRF_CPC_CRC_INSERT 1068 #define ETH_CRC_REPLACE ETH_DMATXNDESCRF_CPC_CRC_REPLACE 1069 /** 1070 * @} 1071 */ 1072 1073 /** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control 1074 * @{ 1075 */ 1076 #define ETH_CHECKSUM_DISABLE ETH_DMATXNDESCRF_CIC_DISABLE 1077 #define ETH_CHECKSUM_IPHDR_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_INSERT 1078 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT 1079 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC 1080 /** 1081 * @} 1082 */ 1083 1084 /** @defgroup ETH_Tx_Packet_VLAN_Control ETH Tx Packet VLAN Control 1085 * @{ 1086 */ 1087 #define ETH_VLAN_DISABLE ETH_DMATXNDESCRF_VTIR_DISABLE 1088 #define ETH_VLAN_REMOVE ETH_DMATXNDESCRF_VTIR_REMOVE 1089 #define ETH_VLAN_INSERT ETH_DMATXNDESCRF_VTIR_INSERT 1090 #define ETH_VLAN_REPLACE ETH_DMATXNDESCRF_VTIR_REPLACE 1091 /** 1092 * @} 1093 */ 1094 1095 /** @defgroup ETH_Tx_Packet_Inner_VLAN_Control ETH Tx Packet Inner VLAN Control 1096 * @{ 1097 */ 1098 #define ETH_INNER_VLAN_DISABLE ETH_DMATXCDESC_IVTIR_DISABLE 1099 #define ETH_INNER_VLAN_REMOVE ETH_DMATXCDESC_IVTIR_REMOVE 1100 #define ETH_INNER_VLAN_INSERT ETH_DMATXCDESC_IVTIR_INSERT 1101 #define ETH_INNER_VLAN_REPLACE ETH_DMATXCDESC_IVTIR_REPLACE 1102 /** 1103 * @} 1104 */ 1105 1106 /** @defgroup ETH_Rx_Checksum_Status ETH Rx Checksum Status 1107 * @{ 1108 */ 1109 #define ETH_CHECKSUM_BYPASSED ETH_DMARXNDESCWBF_IPCB 1110 #define ETH_CHECKSUM_IP_HEADER_ERROR ETH_DMARXNDESCWBF_IPHE 1111 #define ETH_CHECKSUM_IP_PAYLOAD_ERROR ETH_DMARXNDESCWBF_IPCE 1112 /** 1113 * @} 1114 */ 1115 1116 /** @defgroup ETH_Rx_IP_Header_Type ETH Rx IP Header Type 1117 * @{ 1118 */ 1119 #define ETH_IP_HEADER_IPV4 ETH_DMARXNDESCWBF_IPV4 1120 #define ETH_IP_HEADER_IPV6 ETH_DMARXNDESCWBF_IPV6 1121 /** 1122 * @} 1123 */ 1124 1125 /** @defgroup ETH_Rx_Payload_Type ETH Rx Payload Type 1126 * @{ 1127 */ 1128 #define ETH_IP_PAYLOAD_UNKNOWN ETH_DMARXNDESCWBF_PT_UNKNOWN 1129 #define ETH_IP_PAYLOAD_UDP ETH_DMARXNDESCWBF_PT_UDP 1130 #define ETH_IP_PAYLOAD_TCP ETH_DMARXNDESCWBF_PT_TCP 1131 #define ETH_IP_PAYLOAD_ICMPN ETH_DMARXNDESCWBF_PT_ICMP 1132 /** 1133 * @} 1134 */ 1135 1136 /** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status 1137 * @{ 1138 */ 1139 #define ETH_HASH_FILTER_PASS ETH_DMARXNDESCWBF_HF 1140 #define ETH_VLAN_FILTER_PASS ETH_DMARXNDESCWBF_VF 1141 #define ETH_DEST_ADDRESS_FAIL ETH_DMARXNDESCWBF_DAF 1142 #define ETH_SOURCE_ADDRESS_FAIL ETH_DMARXNDESCWBF_SAF 1143 /** 1144 * @} 1145 */ 1146 /** @defgroup ETH_Rx_L3_Filter_Status ETH Rx L3 Filter Status 1147 * @{ 1148 */ 1149 #define ETH_L3_FILTER0_MATCH ETH_DMARXNDESCWBF_L3FM 1150 #define ETH_L3_FILTER1_MATCH (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM) 1151 /** 1152 * @} 1153 */ 1154 1155 /** @defgroup ETH_Rx_L4_Filter_Status ETH Rx L4 Filter Status 1156 * @{ 1157 */ 1158 #define ETH_L4_FILTER0_MATCH ETH_DMARXNDESCWBF_L4FM 1159 #define ETH_L4_FILTER1_MATCH (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM) 1160 /** 1161 * @} 1162 */ 1163 1164 /** @defgroup ETH_Rx_Error_Code ETH Rx Error Code 1165 * @{ 1166 */ 1167 #define ETH_DRIBBLE_BIT_ERROR ETH_DMARXNDESCWBF_DE 1168 #define ETH_RECEIVE_ERROR ETH_DMARXNDESCWBF_RE 1169 #define ETH_RECEIVE_OVERFLOW ETH_DMARXNDESCWBF_OE 1170 #define ETH_WATCHDOG_TIMEOUT ETH_DMARXNDESCWBF_RWT 1171 #define ETH_GIANT_PACKET ETH_DMARXNDESCWBF_GP 1172 #define ETH_CRC_ERROR ETH_DMARXNDESCWBF_CE 1173 /** 1174 * @} 1175 */ 1176 1177 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration 1178 * @{ 1179 */ 1180 #define ETH_DMAARBITRATION_RX ETH_DMAMR_DA 1181 #define ETH_DMAARBITRATION_RX1_TX1 0x00000000U 1182 #define ETH_DMAARBITRATION_RX2_TX1 ETH_DMAMR_PR_2_1 1183 #define ETH_DMAARBITRATION_RX3_TX1 ETH_DMAMR_PR_3_1 1184 #define ETH_DMAARBITRATION_RX4_TX1 ETH_DMAMR_PR_4_1 1185 #define ETH_DMAARBITRATION_RX5_TX1 ETH_DMAMR_PR_5_1 1186 #define ETH_DMAARBITRATION_RX6_TX1 ETH_DMAMR_PR_6_1 1187 #define ETH_DMAARBITRATION_RX7_TX1 ETH_DMAMR_PR_7_1 1188 #define ETH_DMAARBITRATION_RX8_TX1 ETH_DMAMR_PR_8_1 1189 #define ETH_DMAARBITRATION_TX (ETH_DMAMR_TXPR | ETH_DMAMR_DA) 1190 #define ETH_DMAARBITRATION_TX1_RX1 0x00000000U 1191 #define ETH_DMAARBITRATION_TX2_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1) 1192 #define ETH_DMAARBITRATION_TX3_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1) 1193 #define ETH_DMAARBITRATION_TX4_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1) 1194 #define ETH_DMAARBITRATION_TX5_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1) 1195 #define ETH_DMAARBITRATION_TX6_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1) 1196 #define ETH_DMAARBITRATION_TX7_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1) 1197 #define ETH_DMAARBITRATION_TX8_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1) 1198 /** 1199 * @} 1200 */ 1201 1202 /** @defgroup ETH_Burst_Mode ETH Burst Mode 1203 * @{ 1204 */ 1205 #define ETH_BURSTLENGTH_FIXED ETH_DMASBMR_FB 1206 #define ETH_BURSTLENGTH_MIXED ETH_DMASBMR_MB 1207 #define ETH_BURSTLENGTH_UNSPECIFIED 0x00000000U 1208 /** 1209 * @} 1210 */ 1211 1212 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length 1213 * @{ 1214 */ 1215 #define ETH_TXDMABURSTLENGTH_1BEAT ETH_DMACTCR_TPBL_1PBL 1216 #define ETH_TXDMABURSTLENGTH_2BEAT ETH_DMACTCR_TPBL_2PBL 1217 #define ETH_TXDMABURSTLENGTH_4BEAT ETH_DMACTCR_TPBL_4PBL 1218 #define ETH_TXDMABURSTLENGTH_8BEAT ETH_DMACTCR_TPBL_8PBL 1219 #define ETH_TXDMABURSTLENGTH_16BEAT ETH_DMACTCR_TPBL_16PBL 1220 #define ETH_TXDMABURSTLENGTH_32BEAT ETH_DMACTCR_TPBL_32PBL 1221 /** 1222 * @} 1223 */ 1224 1225 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length 1226 * @{ 1227 */ 1228 #define ETH_RXDMABURSTLENGTH_1BEAT ETH_DMACRCR_RPBL_1PBL 1229 #define ETH_RXDMABURSTLENGTH_2BEAT ETH_DMACRCR_RPBL_2PBL 1230 #define ETH_RXDMABURSTLENGTH_4BEAT ETH_DMACRCR_RPBL_4PBL 1231 #define ETH_RXDMABURSTLENGTH_8BEAT ETH_DMACRCR_RPBL_8PBL 1232 #define ETH_RXDMABURSTLENGTH_16BEAT ETH_DMACRCR_RPBL_16PBL 1233 #define ETH_RXDMABURSTLENGTH_32BEAT ETH_DMACRCR_RPBL_32PBL 1234 /** 1235 * @} 1236 */ 1237 1238 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts 1239 * @{ 1240 */ 1241 #define ETH_DMA_NORMAL_IT ETH_DMACIER_NIE 1242 #define ETH_DMA_ABNORMAL_IT ETH_DMACIER_AIE 1243 #define ETH_DMA_CONTEXT_DESC_ERROR_IT ETH_DMACIER_CDEE 1244 #define ETH_DMA_FATAL_BUS_ERROR_IT ETH_DMACIER_FBEE 1245 #define ETH_DMA_EARLY_RX_IT ETH_DMACIER_ERIE 1246 #define ETH_DMA_EARLY_TX_IT ETH_DMACIER_ETIE 1247 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT ETH_DMACIER_RWTE 1248 #define ETH_DMA_RX_PROCESS_STOPPED_IT ETH_DMACIER_RSE 1249 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_RBUE 1250 #define ETH_DMA_RX_IT ETH_DMACIER_RIE 1251 #define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_TBUE 1252 #define ETH_DMA_TX_PROCESS_STOPPED_IT ETH_DMACIER_TXSE 1253 #define ETH_DMA_TX_IT ETH_DMACIER_TIE 1254 /** 1255 * @} 1256 */ 1257 1258 /** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags 1259 * @{ 1260 */ 1261 #define ETH_DMA_RX_NO_ERROR_FLAG 0x00000000U 1262 #define ETH_DMA_RX_DESC_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0) 1263 #define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1) 1264 #define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0) 1265 #define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_REB_BIT_2 1266 #define ETH_DMA_TX_NO_ERROR_FLAG 0x00000000U 1267 #define ETH_DMA_TX_DESC_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0) 1268 #define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1) 1269 #define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0) 1270 #define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_TEB_BIT_2 1271 #define ETH_DMA_CONTEXT_DESC_ERROR_FLAG ETH_DMACSR_CDE 1272 #define ETH_DMA_FATAL_BUS_ERROR_FLAG ETH_DMACSR_FBE 1273 #define ETH_DMA_EARLY_TX_IT_FLAG ETH_DMACSR_ERI 1274 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG ETH_DMACSR_RWT 1275 #define ETH_DMA_RX_PROCESS_STOPPED_FLAG ETH_DMACSR_RPS 1276 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG ETH_DMACSR_RBU 1277 #define ETH_DMA_TX_PROCESS_STOPPED_FLAG ETH_DMACSR_TPS 1278 /** 1279 * @} 1280 */ 1281 1282 /** @defgroup ETH_Transmit_Mode ETH Transmit Mode 1283 * @{ 1284 */ 1285 #define ETH_TRANSMITSTOREFORWARD ETH_MTLTQOMR_TSF 1286 #define ETH_TRANSMITTHRESHOLD_32 ETH_MTLTQOMR_TTC_32BITS 1287 #define ETH_TRANSMITTHRESHOLD_64 ETH_MTLTQOMR_TTC_64BITS 1288 #define ETH_TRANSMITTHRESHOLD_96 ETH_MTLTQOMR_TTC_96BITS 1289 #define ETH_TRANSMITTHRESHOLD_128 ETH_MTLTQOMR_TTC_128BITS 1290 #define ETH_TRANSMITTHRESHOLD_192 ETH_MTLTQOMR_TTC_192BITS 1291 #define ETH_TRANSMITTHRESHOLD_256 ETH_MTLTQOMR_TTC_256BITS 1292 #define ETH_TRANSMITTHRESHOLD_384 ETH_MTLTQOMR_TTC_384BITS 1293 #define ETH_TRANSMITTHRESHOLD_512 ETH_MTLTQOMR_TTC_512BITS 1294 /** 1295 * @} 1296 */ 1297 1298 /** @defgroup ETH_Receive_Mode ETH Receive Mode 1299 * @{ 1300 */ 1301 #define ETH_RECEIVESTOREFORWARD ETH_MTLRQOMR_RSF 1302 #define ETH_RECEIVETHRESHOLD8_64 ETH_MTLRQOMR_RTC_64BITS 1303 #define ETH_RECEIVETHRESHOLD8_32 ETH_MTLRQOMR_RTC_32BITS 1304 #define ETH_RECEIVETHRESHOLD8_96 ETH_MTLRQOMR_RTC_96BITS 1305 #define ETH_RECEIVETHRESHOLD8_128 ETH_MTLRQOMR_RTC_128BITS 1306 /** 1307 * @} 1308 */ 1309 1310 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold 1311 * @{ 1312 */ 1313 #define ETH_PAUSELOWTHRESHOLD_MINUS_4 ETH_MACTFCR_PLT_MINUS4 1314 #define ETH_PAUSELOWTHRESHOLD_MINUS_28 ETH_MACTFCR_PLT_MINUS28 1315 #define ETH_PAUSELOWTHRESHOLD_MINUS_36 ETH_MACTFCR_PLT_MINUS36 1316 #define ETH_PAUSELOWTHRESHOLD_MINUS_144 ETH_MACTFCR_PLT_MINUS144 1317 #define ETH_PAUSELOWTHRESHOLD_MINUS_256 ETH_MACTFCR_PLT_MINUS256 1318 #define ETH_PAUSELOWTHRESHOLD_MINUS_512 ETH_MACTFCR_PLT_MINUS512 1319 /** 1320 * @} 1321 */ 1322 1323 /** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout 1324 * @{ 1325 */ 1326 #define ETH_WATCHDOGTIMEOUT_2KB ETH_MACWTR_WTO_2KB 1327 #define ETH_WATCHDOGTIMEOUT_3KB ETH_MACWTR_WTO_3KB 1328 #define ETH_WATCHDOGTIMEOUT_4KB ETH_MACWTR_WTO_4KB 1329 #define ETH_WATCHDOGTIMEOUT_5KB ETH_MACWTR_WTO_5KB 1330 #define ETH_WATCHDOGTIMEOUT_6KB ETH_MACWTR_WTO_6KB 1331 #define ETH_WATCHDOGTIMEOUT_7KB ETH_MACWTR_WTO_7KB 1332 #define ETH_WATCHDOGTIMEOUT_8KB ETH_MACWTR_WTO_8KB 1333 #define ETH_WATCHDOGTIMEOUT_9KB ETH_MACWTR_WTO_9KB 1334 #define ETH_WATCHDOGTIMEOUT_10KB ETH_MACWTR_WTO_10KB 1335 #define ETH_WATCHDOGTIMEOUT_11KB ETH_MACWTR_WTO_12KB 1336 #define ETH_WATCHDOGTIMEOUT_12KB ETH_MACWTR_WTO_12KB 1337 #define ETH_WATCHDOGTIMEOUT_13KB ETH_MACWTR_WTO_13KB 1338 #define ETH_WATCHDOGTIMEOUT_14KB ETH_MACWTR_WTO_14KB 1339 #define ETH_WATCHDOGTIMEOUT_15KB ETH_MACWTR_WTO_15KB 1340 #define ETH_WATCHDOGTIMEOUT_16KB ETH_MACWTR_WTO_16KB 1341 /** 1342 * @} 1343 */ 1344 1345 /** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap 1346 * @{ 1347 */ 1348 #define ETH_INTERPACKETGAP_96BIT ETH_MACCR_IPG_96BIT 1349 #define ETH_INTERPACKETGAP_88BIT ETH_MACCR_IPG_88BIT 1350 #define ETH_INTERPACKETGAP_80BIT ETH_MACCR_IPG_80BIT 1351 #define ETH_INTERPACKETGAP_72BIT ETH_MACCR_IPG_72BIT 1352 #define ETH_INTERPACKETGAP_64BIT ETH_MACCR_IPG_64BIT 1353 #define ETH_INTERPACKETGAP_56BIT ETH_MACCR_IPG_56BIT 1354 #define ETH_INTERPACKETGAP_48BIT ETH_MACCR_IPG_48BIT 1355 #define ETH_INTERPACKETGAP_40BIT ETH_MACCR_IPG_40BIT 1356 /** 1357 * @} 1358 */ 1359 1360 /** @defgroup ETH_Speed ETH Speed 1361 * @{ 1362 */ 1363 #define ETH_SPEED_10M 0x00000000U 1364 #define ETH_SPEED_100M ETH_MACCR_FES 1365 /** 1366 * @} 1367 */ 1368 1369 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode 1370 * @{ 1371 */ 1372 #define ETH_FULLDUPLEX_MODE ETH_MACCR_DM 1373 #define ETH_HALFDUPLEX_MODE 0x00000000U 1374 /** 1375 * @} 1376 */ 1377 1378 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit 1379 * @{ 1380 */ 1381 #define ETH_BACKOFFLIMIT_10 ETH_MACCR_BL_10 1382 #define ETH_BACKOFFLIMIT_8 ETH_MACCR_BL_8 1383 #define ETH_BACKOFFLIMIT_4 ETH_MACCR_BL_4 1384 #define ETH_BACKOFFLIMIT_1 ETH_MACCR_BL_1 1385 /** 1386 * @} 1387 */ 1388 1389 /** @defgroup ETH_Preamble_Length ETH Preamble Length 1390 * @{ 1391 */ 1392 #define ETH_PREAMBLELENGTH_7 ETH_MACCR_PRELEN_7 1393 #define ETH_PREAMBLELENGTH_5 ETH_MACCR_PRELEN_5 1394 #define ETH_PREAMBLELENGTH_3 ETH_MACCR_PRELEN_3 1395 /** 1396 * @} 1397 */ 1398 1399 /** @defgroup ETH_Source_Addr_Control ETH Source Addr Control 1400 * @{ 1401 */ 1402 #define ETH_SOURCEADDRESS_DISABLE 0x00000000U 1403 #define ETH_SOURCEADDRESS_INSERT_ADDR0 ETH_MACCR_SARC_INSADDR0 1404 #define ETH_SOURCEADDRESS_INSERT_ADDR1 ETH_MACCR_SARC_INSADDR1 1405 #define ETH_SOURCEADDRESS_REPLACE_ADDR0 ETH_MACCR_SARC_REPADDR0 1406 #define ETH_SOURCEADDRESS_REPLACE_ADDR1 ETH_MACCR_SARC_REPADDR1 1407 /** 1408 * @} 1409 */ 1410 1411 /** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter 1412 * @{ 1413 */ 1414 #define ETH_CTRLPACKETS_BLOCK_ALL ETH_MACPFR_PCF_BLOCKALL 1415 #define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA 1416 #define ETH_CTRLPACKETS_FORWARD_ALL ETH_MACPFR_PCF_FORWARDALL 1417 #define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER 1418 /** 1419 * @} 1420 */ 1421 1422 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison 1423 * @{ 1424 */ 1425 #define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U 1426 #define ETH_VLANTAGCOMPARISON_12BIT ETH_MACVTR_ETV 1427 /** 1428 * @} 1429 */ 1430 1431 /** @defgroup ETH_MAC_addresses ETH MAC addresses 1432 * @{ 1433 */ 1434 #define ETH_MAC_ADDRESS0 0x00000000U 1435 #define ETH_MAC_ADDRESS1 0x00000008U 1436 #define ETH_MAC_ADDRESS2 0x00000010U 1437 #define ETH_MAC_ADDRESS3 0x00000018U 1438 /** 1439 * @} 1440 */ 1441 1442 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts 1443 * @{ 1444 */ 1445 #define ETH_MAC_RX_STATUS_IT ETH_MACIER_RXSTSIE 1446 #define ETH_MAC_TX_STATUS_IT ETH_MACIER_TXSTSIE 1447 #define ETH_MAC_TIMESTAMP_IT ETH_MACIER_TSIE 1448 #define ETH_MAC_LPI_IT ETH_MACIER_LPIIE 1449 #define ETH_MAC_PMT_IT ETH_MACIER_PMTIE 1450 #define ETH_MAC_PHY_IT ETH_MACIER_PHYIE 1451 /** 1452 * @} 1453 */ 1454 1455 /** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event 1456 * @{ 1457 */ 1458 #define ETH_WAKEUP_PACKET_RECIEVED ETH_MACPCSR_RWKPRCVD 1459 #define ETH_MAGIC_PACKET_RECIEVED ETH_MACPCSR_MGKPRCVD 1460 /** 1461 * @} 1462 */ 1463 1464 /** @defgroup ETH_MAC_Rx_Tx_Status ETH MAC Rx Tx Status 1465 * @{ 1466 */ 1467 #define ETH_RECEIVE_WATCHDOG_TIMEOUT ETH_MACRXTXSR_RWT 1468 #define ETH_EXECESSIVE_COLLISIONS ETH_MACRXTXSR_EXCOL 1469 #define ETH_LATE_COLLISIONS ETH_MACRXTXSR_LCOL 1470 #define ETH_EXECESSIVE_DEFERRAL ETH_MACRXTXSR_EXDEF 1471 #define ETH_LOSS_OF_CARRIER ETH_MACRXTXSR_LCARR 1472 #define ETH_NO_CARRIER ETH_MACRXTXSR_NCARR 1473 #define ETH_TRANSMIT_JABBR_TIMEOUT ETH_MACRXTXSR_TJT 1474 /** 1475 * @} 1476 */ 1477 1478 /** @defgroup HAL_ETH_StateTypeDef ETH States 1479 * @{ 1480 */ 1481 #define HAL_ETH_STATE_RESET 0x00000000U /*!< Peripheral not yet Initialized or disabled */ 1482 #define HAL_ETH_STATE_READY 0x00000010U /*!< Peripheral Communication started */ 1483 #define HAL_ETH_STATE_BUSY 0x00000023U /*!< an internal process is ongoing */ 1484 #define HAL_ETH_STATE_STARTED 0x00000023U /*!< an internal process is started */ 1485 #define HAL_ETH_STATE_ERROR 0x000000E0U /*!< Error State */ 1486 /** 1487 * @} 1488 */ 1489 1490 /** @defgroup ETH_PTP_Config_Status ETH PTP Config Status 1491 * @{ 1492 */ 1493 #define HAL_ETH_PTP_NOT_CONFIGURATED 0x00000000U /*!< ETH PTP Configuration not done */ 1494 #define HAL_ETH_PTP_CONFIGURATED 0x00000001U /*!< ETH PTP Configuration done */ 1495 /** 1496 * @} 1497 */ 1498 /** 1499 * @} 1500 */ 1501 1502 /* Exported macro ------------------------------------------------------------*/ 1503 /** @defgroup ETH_Exported_Macros ETH Exported Macros 1504 * @{ 1505 */ 1506 1507 /** @brief Reset ETH handle state 1508 * @param __HANDLE__: specifies the ETH handle. 1509 * @retval None 1510 */ 1511 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 1512 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ 1513 (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ 1514 (__HANDLE__)->MspInitCallback = NULL; \ 1515 (__HANDLE__)->MspDeInitCallback = NULL; \ 1516 } while(0) 1517 #else 1518 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ 1519 (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ 1520 } while(0) 1521 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ 1522 1523 /** 1524 * @brief Enables the specified ETHERNET DMA interrupts. 1525 * @param __HANDLE__ : ETH Handle 1526 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be 1527 * enabled @ref ETH_DMA_Interrupts 1528 * @retval None 1529 */ 1530 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__)) 1531 1532 /** 1533 * @brief Disables the specified ETHERNET DMA interrupts. 1534 * @param __HANDLE__ : ETH Handle 1535 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be 1536 * disabled. @ref ETH_DMA_Interrupts 1537 * @retval None 1538 */ 1539 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__)) 1540 1541 /** 1542 * @brief Gets the ETHERNET DMA IT source enabled or disabled. 1543 * @param __HANDLE__ : ETH Handle 1544 * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts 1545 * @retval The ETH DMA IT Source enabled or disabled 1546 */ 1547 #define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 1548 (((__HANDLE__)->Instance->DMACIER & (__INTERRUPT__)) == (__INTERRUPT__)) 1549 1550 /** 1551 * @brief Gets the ETHERNET DMA IT pending bit. 1552 * @param __HANDLE__ : ETH Handle 1553 * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts 1554 * @retval The state of ETH DMA IT (SET or RESET) 1555 */ 1556 #define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) \ 1557 (((__HANDLE__)->Instance->DMACSR & (__INTERRUPT__)) == (__INTERRUPT__)) 1558 1559 /** 1560 * @brief Clears the ETHERNET DMA IT pending bit. 1561 * @param __HANDLE__ : ETH Handle 1562 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts 1563 * @retval None 1564 */ 1565 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__)) 1566 1567 /** 1568 * @brief Checks whether the specified ETHERNET DMA flag is set or not. 1569 * @param __HANDLE__: ETH Handle 1570 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags 1571 * @retval The state of ETH DMA FLAG (SET or RESET). 1572 */ 1573 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__)) 1574 1575 /** 1576 * @brief Clears the specified ETHERNET DMA flag. 1577 * @param __HANDLE__: ETH Handle 1578 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags 1579 * @retval The state of ETH DMA FLAG (SET or RESET). 1580 */ 1581 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__)) 1582 1583 /** 1584 * @brief Enables the specified ETHERNET MAC interrupts. 1585 * @param __HANDLE__ : ETH Handle 1586 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be 1587 * enabled @ref ETH_MAC_Interrupts 1588 * @retval None 1589 */ 1590 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__)) 1591 1592 /** 1593 * @brief Disables the specified ETHERNET MAC interrupts. 1594 * @param __HANDLE__ : ETH Handle 1595 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be 1596 * enabled @ref ETH_MAC_Interrupts 1597 * @retval None 1598 */ 1599 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__)) 1600 1601 /** 1602 * @brief Checks whether the specified ETHERNET MAC flag is set or not. 1603 * @param __HANDLE__: ETH Handle 1604 * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts 1605 * @retval The state of ETH MAC IT (SET or RESET). 1606 */ 1607 #define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) \ 1608 (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__)) 1609 1610 /*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */ 1611 #define ETH_WAKEUP_EXTI_LINE 0x00400000U /* !< 86 - 64 = 22 */ 1612 1613 /** 1614 * @brief Enable the ETH WAKEUP Exti Line. 1615 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. 1616 * @arg ETH_WAKEUP_EXTI_LINE 1617 * @retval None. 1618 */ 1619 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI_D1->IMR3 |= (__EXTI_LINE__)) 1620 1621 /** 1622 * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. 1623 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. 1624 * @arg ETH_WAKEUP_EXTI_LINE 1625 * @retval EXTI ETH WAKEUP Line Status. 1626 */ 1627 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 & (__EXTI_LINE__)) 1628 1629 /** 1630 * @brief Clear the ETH WAKEUP Exti flag. 1631 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. 1632 * @arg ETH_WAKEUP_EXTI_LINE 1633 * @retval None. 1634 */ 1635 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__)) 1636 1637 #if defined(DUAL_CORE) 1638 /** 1639 * @brief Enable the ETH WAKEUP Exti Line by Core2. 1640 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. 1641 * @arg ETH_WAKEUP_EXTI_LINE 1642 * @retval None. 1643 */ 1644 #define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__) (EXTI_D2->IMR3 |= (__EXTI_LINE__)) 1645 1646 /** 1647 * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. 1648 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. 1649 * @arg ETH_WAKEUP_EXTI_LINE 1650 * @retval EXTI ETH WAKEUP Line Status. 1651 */ 1652 #define __HAL_ETH_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 & (__EXTI_LINE__)) 1653 1654 /** 1655 * @brief Clear the ETH WAKEUP Exti flag. 1656 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. 1657 * @arg ETH_WAKEUP_EXTI_LINE 1658 * @retval None. 1659 */ 1660 #define __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 = (__EXTI_LINE__)) 1661 #endif /* DUAL_CORE */ 1662 1663 /** 1664 * @brief enable rising edge interrupt on selected EXTI line. 1665 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 1666 * @arg ETH_WAKEUP_EXTI_LINE 1667 * @retval None 1668 */ 1669 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \ 1670 (EXTI->RTSR3 |= (__EXTI_LINE__)) 1671 1672 /** 1673 * @brief enable falling edge interrupt on selected EXTI line. 1674 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 1675 * @arg ETH_WAKEUP_EXTI_LINE 1676 * @retval None 1677 */ 1678 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\ 1679 (EXTI->FTSR3 |= (__EXTI_LINE__)) 1680 1681 /** 1682 * @brief enable falling edge interrupt on selected EXTI line. 1683 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 1684 * @arg ETH_WAKEUP_EXTI_LINE 1685 * @retval None 1686 */ 1687 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\ 1688 (EXTI->FTSR3 |= (__EXTI_LINE__)) 1689 1690 /** 1691 * @brief Generates a Software interrupt on selected EXTI line. 1692 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 1693 * @arg ETH_WAKEUP_EXTI_LINE 1694 * @retval None 1695 */ 1696 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__)) 1697 1698 #define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->MACTSCR) & \ 1699 (__FLAG__)) == (__FLAG__)) ? SET : RESET) 1700 1701 #define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->MACTSCR |= (__FLAG__)) 1702 /** 1703 * @} 1704 */ 1705 1706 /* Include ETH HAL Extension module */ 1707 #include "stm32h7xx_hal_eth_ex.h" 1708 1709 /* Exported functions --------------------------------------------------------*/ 1710 1711 /** @addtogroup ETH_Exported_Functions 1712 * @{ 1713 */ 1714 1715 /** @addtogroup ETH_Exported_Functions_Group1 1716 * @{ 1717 */ 1718 /* Initialization and de initialization functions **********************************/ 1719 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); 1720 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); 1721 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); 1722 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); 1723 1724 /* Callbacks Register/UnRegister functions ***********************************/ 1725 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 1726 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, 1727 pETH_CallbackTypeDef pCallback); 1728 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); 1729 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 1730 1731 /** 1732 * @} 1733 */ 1734 1735 /** @addtogroup ETH_Exported_Functions_Group2 1736 * @{ 1737 */ 1738 /* IO operation functions *******************************************************/ 1739 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); 1740 HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth); 1741 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); 1742 HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth); 1743 1744 HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff); 1745 HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth, 1746 pETH_rxAllocateCallbackTypeDef rxAllocateCallback); 1747 HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth); 1748 HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback); 1749 HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth); 1750 HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode); 1751 HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback); 1752 HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth); 1753 HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth); 1754 1755 #ifdef HAL_ETH_USE_PTP 1756 HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig); 1757 HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig); 1758 HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time); 1759 HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time); 1760 HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype, 1761 ETH_TimeTypeDef *timeoffset); 1762 HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth); 1763 HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp); 1764 HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp); 1765 HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback); 1766 HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth); 1767 #endif /* HAL_ETH_USE_PTP */ 1768 1769 HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout); 1770 HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig); 1771 1772 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, 1773 uint32_t RegValue); 1774 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, 1775 uint32_t *pRegValue); 1776 1777 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); 1778 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); 1779 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); 1780 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); 1781 void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth); 1782 void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth); 1783 void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth); 1784 void HAL_ETH_RxAllocateCallback(uint8_t **buff); 1785 void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length); 1786 void HAL_ETH_TxFreeCallback(uint32_t *buff); 1787 void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp); 1788 /** 1789 * @} 1790 */ 1791 1792 /** @addtogroup ETH_Exported_Functions_Group3 1793 * @{ 1794 */ 1795 /* Peripheral Control functions **********************************************/ 1796 /* MAC & DMA Configuration APIs **********************************************/ 1797 HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); 1798 HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); 1799 HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); 1800 HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); 1801 void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth); 1802 1803 /* MAC VLAN Processing APIs ************************************************/ 1804 void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, 1805 uint32_t VLANIdentifier); 1806 1807 /* MAC L2 Packet Filtering APIs **********************************************/ 1808 HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); 1809 HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); 1810 HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable); 1811 HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr); 1812 1813 /* MAC Power Down APIs *****************************************************/ 1814 void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig); 1815 void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth); 1816 HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count); 1817 1818 /** 1819 * @} 1820 */ 1821 1822 /** @addtogroup ETH_Exported_Functions_Group4 1823 * @{ 1824 */ 1825 /* Peripheral State functions **************************************************/ 1826 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); 1827 uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth); 1828 uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth); 1829 uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth); 1830 uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth); 1831 /** 1832 * @} 1833 */ 1834 1835 /** 1836 * @} 1837 */ 1838 1839 /** 1840 * @} 1841 */ 1842 1843 /** 1844 * @} 1845 */ 1846 1847 #endif /* ETH */ 1848 1849 #ifdef __cplusplus 1850 } 1851 #endif 1852 1853 #endif /* STM32H7xx_HAL_ETH_H */ 1854 1855 1856
