1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_adc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H7xx_HAL_ADC_EX_H 21 #define STM32H7xx_HAL_ADC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h7xx_hal_def.h" 29 30 /** @addtogroup STM32H7xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup ADCEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief ADC Injected Conversion Oversampling structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Ratio; /*!< Configures the oversampling ratio. */ 49 #if defined(ADC_VER_V5_V90) 50 /* On devices STM32H72xx and STM32H73xx this parameter can be a value from 1 to 1023 for ADC1/2 and value of @ref ADC_HAL_EC_OVS_RATIO for ADC3*/ 51 #else 52 /* This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 53 #endif 54 55 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 56 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 57 } ADC_InjOversamplingTypeDef; 58 59 /** 60 * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected 61 * @note Parameters of this structure are shared within 2 scopes: 62 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset 63 * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, 64 * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling. 65 * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 66 * ADC state can be either: 67 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') 68 * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group. 69 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. 70 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going 71 * on ADC groups regular and injected. 72 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 73 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 74 */ 75 typedef struct 76 { 77 uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. 78 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 79 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 80 81 uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. 82 This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. 83 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 84 the new channel setting (or parameter number of conversions adjusted) */ 85 86 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 87 Unit: ADC clock cycles. 88 Conversion time is the addition of sampling time and processing time 89 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 90 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. 91 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 92 It overwrites the last setting. 93 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 94 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 95 Refer to device datasheet for timings values. */ 96 97 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. 98 In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 99 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 100 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. 101 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 102 It overwrites the last setting. 103 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 104 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 105 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 106 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 107 of another parameter update on the fly) */ 108 109 uint32_t InjectedOffsetNumber; /*!< Selects the offset number. 110 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. 111 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 112 113 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. 114 Offset value must be a positive number. 115 Maximum value depends on ADC resolution and oversampling ratio (in case of oversampling used). 116 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFFC00 (corresponding to resolution 16 bit and oversampling ratio 1024). 117 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 118 without continuous mode or external trigger that could launch a conversion). */ 119 120 uint32_t InjectedOffsetRightShift; /*!< Specifies whether the 1 bit Right-shift feature is used or not. 121 This parameter is applied only for 16-bit or 8-bit resolution. 122 This parameter can be set to ENABLE or DISABLE. */ 123 #if defined(ADC_VER_V5_V90) 124 uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. 125 This parameter can be a value of @ref ADCEx_OffsetSign. 126 Note: 127 - This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). 128 - On devices STM32H72xx and STM32H73xx, this parameter is specific to ADC3 only. */ 129 FunctionalState InjectedOffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. 130 This parameter value can be ENABLE or DISABLE. 131 Note: 132 - This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). 133 - On devices STM32H72xx and STM32H73xx, this parameter is specific to ADC3 only. */ 134 135 #endif 136 137 FunctionalState InjectedOffsetSignedSaturation; /*!< Specifies whether the Signed saturation feature is used or not. 138 This parameter is applied only for 16-bit or 8-bit resolution. 139 This parameter can be set to ENABLE or DISABLE. */ 140 141 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer. 142 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 143 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 144 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 145 configure a channel on injected group can impact the configuration of other channels previously set. */ 146 147 FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence 148 (main sequence subdivided in successive parts). 149 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 150 Discontinuous mode can be enabled only if continuous mode is disabled. 151 This parameter can be set to ENABLE or DISABLE. 152 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 153 Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). 154 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 155 configure a channel on injected group can impact the configuration of other channels previously set. */ 156 157 FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one 158 This parameter can be set to ENABLE or DISABLE. 159 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) 160 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) 161 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. 162 To maintain JAUTO always enabled, DMA must be configured in circular mode. 163 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 164 configure a channel on injected group can impact the configuration of other channels previously set. */ 165 166 FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. 167 This parameter can be set to ENABLE or DISABLE. 168 If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a 169 new injected context is set when queue is full, error is triggered by interruption and through function 170 'HAL_ADCEx_InjectedQueueOverflowCallback'. 171 Caution: This feature request that the sequence is fully configured before injected conversion start. 172 Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. 173 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 174 configure a channel on injected group can impact the configuration of other channels previously set. 175 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ 176 177 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. 178 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 179 This parameter can be a value of @ref ADC_injected_external_trigger_source. 180 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 181 configure a channel on injected group can impact the configuration of other channels previously set. */ 182 183 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 184 This parameter can be a value of @ref ADC_injected_external_trigger_edge. 185 If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. 186 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 187 configure a channel on injected group can impact the configuration of other channels previously set. */ 188 189 FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. 190 This parameter can be set to ENABLE or DISABLE. 191 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 192 193 ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. 194 Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. 195 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 196 } ADC_InjectionConfTypeDef; 197 198 /** 199 * @brief Structure definition of ADC multimode 200 * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). 201 * Both Master and Slave ADCs must be disabled. 202 */ 203 typedef struct 204 { 205 uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. 206 This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ 207 208 uint32_t DualModeData; /*!< Configures the Dual ADC Mode Data Format: 209 This parameter can be a value of @ref ADCEx_Dual_Mode_Data_Format */ 210 211 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. 212 This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. 213 Delay range depends on selected resolution: 214 from 1 to 9 clock cycles for 16 bits, 215 from 1 to 9 clock cycles for 14 bits 216 from 1 to 8 clock cycles for 12 bits 217 from 1 to 6 clock cycles for 10 bits 218 from 1 to 6 clock cycles for 8 bits */ 219 } ADC_MultiModeTypeDef; 220 221 /** 222 * @} 223 */ 224 225 /* Exported constants --------------------------------------------------------*/ 226 227 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants 228 * @{ 229 */ 230 231 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source 232 * @{ 233 */ 234 /* ADC group regular trigger sources for all ADC instances */ 235 #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */ 236 #define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */ 237 #define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 238 #define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */ 239 #define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 240 #define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 241 #define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */ 242 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */ 243 #define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 244 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */ 245 #define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */ 246 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */ 247 #define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 248 #define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */ 249 #define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 250 #define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */ 251 #define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */ 252 #if defined(HRTIM1) 253 #define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */ 254 #define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */ 255 #endif /* HRTIM1 */ 256 #define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */ 257 #define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */ 258 #define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. Trigger edge set to rising edge (default setting). */ 259 /** 260 * @} 261 */ 262 263 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) 264 * @{ 265 */ 266 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ 267 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ 268 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ 269 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ 270 /** 271 * @} 272 */ 273 274 /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending 275 * @{ 276 */ 277 #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ 278 #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ 279 /** 280 * @} 281 */ 282 283 /** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number 284 * @{ 285 */ 286 #define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */ 287 #define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 288 #define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 289 #define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 290 #define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 291 /** 292 * @} 293 */ 294 295 #if defined(ADC_VER_V5_V90) 296 /** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign 297 * @{ 298 */ 299 #define ADC3_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is subtracted */ 300 #define ADC3_OFFSET_SIGN_POSITIVE (ADC3_OFR1_OFFSETPOS) /*!< Offset sign positive, offset is added */ 301 /** 302 * @} 303 */ 304 #endif 305 306 /** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 307 * @{ 308 */ 309 #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ 310 #define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ 311 #define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ 312 #define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ 313 /** 314 * @} 315 */ 316 317 /** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode 318 * @{ 319 */ 320 #define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */ 321 #define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */ 322 #define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */ 323 #define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */ 324 #define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 325 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ 326 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 327 #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ 328 329 /** @defgroup ADCEx_Dual_Mode_Data_Format ADC Extended Dual Mode Data Formatting 330 * @{ 331 */ 332 #define ADC_DUALMODEDATAFORMAT_DISABLED (0x00000000UL) /*!< Dual ADC mode without data packing: ADCx_CDR and ADCx_CDR2 registers not used */ 333 #define ADC_DUALMODEDATAFORMAT_32_10_BITS (ADC_CCR_DAMDF_1) /*!< Data formatting mode for 32 down to 10-bit resolution */ 334 #define ADC_DUALMODEDATAFORMAT_8_BITS ((ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1)) /*!< Data formatting mode for 8-bit resolution */ 335 /** 336 * @} 337 */ 338 339 /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases 340 * @{ 341 */ 342 #define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ 343 #define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ 344 #define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ 345 #define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ 346 #define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ 347 #define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ 348 #define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ 349 #define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ 350 #define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ 351 /** 352 * @} 353 */ 354 355 /** 356 * @} 357 */ 358 359 /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups 360 * @{ 361 */ 362 #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ 363 #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/ 364 #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ 365 /** 366 * @} 367 */ 368 369 /** @defgroup ADC_CFGR_fields ADCx CFGR fields 370 * @{ 371 */ 372 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 373 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 374 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 375 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 376 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ 377 ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ) 378 /** 379 * @} 380 */ 381 382 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields 383 * @{ 384 */ 385 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 386 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 387 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 388 ADC_SMPR1_SMP0) 389 /** 390 * @} 391 */ 392 393 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields 394 * @{ 395 */ 396 /* ADC_CFGR fields of parameters that can be updated when no conversion 397 (neither regular nor injected) is on-going */ 398 #define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY)) 399 /** 400 * @} 401 */ 402 #if defined(ADC_VER_V5_V90) 403 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields 404 * @{ 405 */ 406 /* ADC_CFGR fields of parameters that can be updated when no conversion 407 (neither regular nor injected) is on-going */ 408 #define ADC3_CFGR_FIELDS_2 ((ADC3_CFGR_DMACFG | ADC_CFGR_AUTDLY)) 409 /** 410 * @} 411 */ 412 #endif 413 414 #if defined(DFSDM1_Channel0) 415 /** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data 416 * @{ 417 */ 418 #define ADC_DFSDM_MODE_DISABLE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */ 419 #define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transferred to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */ 420 /** 421 * @} 422 */ 423 #endif 424 425 /** 426 * @} 427 */ 428 429 /* Exported macros -----------------------------------------------------------*/ 430 431 /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros 432 * @{ 433 */ 434 435 /** @brief Force ADC instance in multimode mode independent (multimode disable). 436 * @note This macro must be used only in case of transition from multimode 437 * to mode independent and in case of unknown previous state, 438 * to ensure ADC configuration is in mode independent. 439 * @note Standard way of multimode configuration change is done from 440 * HAL ADC handle of ADC master using function 441 * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". 442 * Usage of this macro is not the Standard way of multimode 443 * configuration and can lead to have HAL ADC handles status 444 * misaligned. Usage of this macro must be limited to cases 445 * mentioned above. 446 * @param __HANDLE__ ADC handle. 447 * @retval None 448 */ 449 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ 450 LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) 451 452 /** 453 * @} 454 */ 455 456 /* Private macros ------------------------------------------------------------*/ 457 458 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros 459 * @{ 460 */ 461 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 462 /* code of final user. */ 463 464 /** 465 * @brief Test if conversion trigger of injected group is software start 466 * or external trigger. 467 * @param __HANDLE__ ADC handle. 468 * @retval SET (software start) or RESET (external trigger). 469 */ 470 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 471 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) 472 473 /** 474 * @brief Check if conversion is on going on regular or injected groups. 475 * @param __HANDLE__ ADC handle. 476 * @retval SET (conversion is on going) or RESET (no conversion is on going). 477 */ 478 #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \ 479 (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \ 480 ) ? RESET : SET) 481 482 /** 483 * @brief Check if conversion is on going on injected group. 484 * @param __HANDLE__ ADC handle. 485 * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) 486 */ 487 #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \ 488 (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance)) 489 490 491 #if defined (ADC3) 492 /** 493 * @brief Check whether or not ADC is independent. 494 * @param __HANDLE__ ADC handle. 495 * @note When multimode feature is not available, the macro always returns SET. 496 * @retval SET (ADC is independent) or RESET (ADC is not). 497 */ 498 499 #define ADC_IS_INDEPENDENT(__HANDLE__) \ 500 ( ( ( ((__HANDLE__)->Instance) == ADC3) \ 501 )? \ 502 SET \ 503 : \ 504 RESET \ 505 ) 506 #endif 507 508 /** 509 * @brief Set the selected injected Channel rank. 510 * @param __CHANNELNB__ Channel number. 511 * @param __RANKNB__ Rank number. 512 * @retval None 513 */ 514 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) 515 516 /** 517 * @brief Configure ADC injected context queue 518 * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. 519 * @retval None 520 */ 521 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) 522 523 /** 524 * @brief Configure ADC discontinuous conversion mode for injected group 525 * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. 526 * @retval None 527 */ 528 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) 529 530 /** 531 * @brief Configure ADC discontinuous conversion mode for regular group 532 * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. 533 * @retval None 534 */ 535 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) 536 537 /** 538 * @brief Configure the number of discontinuous conversions for regular group. 539 * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. 540 * @retval None 541 */ 542 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) 543 544 /** 545 * @brief Configure the ADC auto delay mode. 546 * @param __AUTOWAIT__ Auto delay bit enable or disable. 547 * @retval None 548 */ 549 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos) 550 551 /** 552 * @brief Configure ADC continuous conversion mode. 553 * @param __CONTINUOUS_MODE__ Continuous mode. 554 * @retval None 555 */ 556 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) 557 558 /** 559 * @brief Enable the ADC DMA continuous request. 560 * @param __DMACONTREQ_MODE__: DMA continuous request mode. 561 * @retval None 562 */ 563 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__)) 564 565 #if defined(ADC_VER_V5_V90) 566 /** 567 * @brief Configure the ADC DMA continuous request. 568 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 569 * @retval None 570 */ 571 #define ADC3_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC3_CFGR_DMACFG_Pos) 572 #endif 573 /** 574 * @brief Configure the channel number into offset OFRx register. 575 * @param __CHANNEL__ ADC Channel. 576 * @retval None 577 */ 578 #define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos) 579 580 /** 581 * @brief Configure the channel number into differential mode selection register. 582 * @param __CHANNEL__ ADC Channel. 583 * @retval None 584 */ 585 #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__)) 586 587 /** 588 * @brief Configure calibration factor in differential mode to be set into calibration register. 589 * @param __CALIBRATION_FACTOR__ Calibration factor value. 590 * @retval None 591 */ 592 #define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos) 593 594 /** 595 * @brief Calibration factor in differential mode to be retrieved from calibration register. 596 * @param __CALIBRATION_FACTOR__ Calibration factor value. 597 * @retval None 598 */ 599 #define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos) 600 601 /** 602 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. 603 * @param __THRESHOLD__ Threshold value. 604 * @retval None 605 */ 606 #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL) 607 608 /** 609 * @brief Configure the ADC DMA continuous request for ADC multimode. 610 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 611 * @retval None 612 */ 613 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) 614 615 /** 616 * @brief Shift the offset in function of the selected ADC resolution. 617 * @note Offset has to be left-aligned on bit 15, the LSB (right bits) are set to 0 618 * If resolution 16 bits, no shift. 619 * If resolution 14 bits, shift of 2 ranks on the left. 620 * If resolution 12 bits, shift of 4 ranks on the left. 621 * If resolution 10 bits, shift of 6 ranks on the left. 622 * If resolution 8 bits, shift of 8 ranks on the left. 623 * therefore, shift = (16 - resolution) = 16 - (16 - (((RES[2:0]) >> 2)*2)) 624 * @param __HANDLE__: ADC handle 625 * @param __OFFSET__: Value to be shifted 626 * @retval None 627 */ 628 #if defined(ADC_VER_V5_3) 629 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 630 ( \ 631 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 632 ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 633 : \ 634 ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 635 ) 636 #else 637 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 638 (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \ 639 ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 640 : \ 641 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 642 ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 643 : \ 644 ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 645 ) 646 #endif /* ADC_VER_V5_3 */ 647 648 #if defined(ADC_VER_V5_V90) 649 #define ADC3_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 650 ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC3_CFGR_RES) >> 3UL) * 2UL)) 651 652 #endif /* ADC_VER_V5_V90 */ 653 654 /** 655 * @brief Shift the AWD1 threshold in function of the selected ADC resolution. 656 * @note Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0. 657 * If resolution 16 bits, no shift. 658 * If resolution 14 bits, shift of 2 ranks on the left. 659 * If resolution 12 bits, shift of 4 ranks on the left. 660 * If resolution 10 bits, shift of 6 ranks on the left. 661 * If resolution 8 bits, shift of 8 ranks on the left. 662 * therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2)) 663 * @param __HANDLE__: ADC handle 664 * @param __THRESHOLD__: Value to be shifted 665 * @retval None 666 */ 667 #if defined(ADC_VER_V5_3) 668 #if defined(ADC_VER_V5_V90) 669 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 670 ( ((__HANDLE__)->Instance == ADC3) \ 671 ?((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC3_CFGR_RES)>> 3UL)*2UL)) \ 672 : \ 673 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 674 ?((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 675 : \ 676 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 677 ) 678 #else 679 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 680 ( \ 681 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 682 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 683 : \ 684 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 685 ) 686 #endif 687 688 #else 689 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 690 (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \ 691 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 692 : \ 693 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 694 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 695 : \ 696 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 697 ) 698 #endif /* ADC_VER_V5_3 */ 699 700 /** 701 * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution. 702 * @note Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0. 703 * If resolution 16 bits, no shift. 704 * If resolution 14 bits, shift of 2 ranks on the left. 705 * If resolution 12 bits, shift of 4 ranks on the left. 706 * If resolution 10 bits, shift of 6 ranks on the left. 707 * If resolution 8 bits, shift of 8 ranks on the left. 708 * therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2)) 709 * @param __HANDLE__: ADC handle 710 * @param __THRESHOLD__: Value to be shifted 711 * @retval None 712 */ 713 #if defined(ADC_VER_V5_3) || defined(ADC_VER_V5_V90) 714 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 715 ( \ 716 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 717 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 718 : \ 719 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 720 ) 721 #else 722 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 723 (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \ 724 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 725 : \ 726 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 727 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 728 : \ 729 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 730 ) 731 #endif /* ADC_VER_V5_3 */ 732 /** 733 * @brief Clear Common Control Register. 734 * @param __HANDLE__ ADC handle. 735 * @retval None 736 */ 737 /** 738 * @brief Report common register to ADC1 and ADC2 739 * @param __HANDLE__: ADC handle 740 * @retval Common control register 741 */ 742 #define ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON) 743 #if defined (ADC3) 744 /** 745 * @brief Report common register to ADC3 746 * @param __HANDLE__: ADC handle 747 * @retval Common control register 748 */ 749 #define ADC3_COMMON_REGISTER(__HANDLE__) (ADC3_COMMON) 750 #endif 751 /** 752 * @brief Report Master Instance 753 * @param __HANDLE__: ADC handle 754 * @note return same instance if ADC of input handle is independent ADC 755 * @retval Master Instance 756 */ 757 #if defined (ADC3) 758 #define ADC_MASTER_REGISTER(__HANDLE__) \ 759 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \ 760 )? \ 761 ((__HANDLE__)->Instance) \ 762 : \ 763 (ADC1) \ 764 ) 765 #else 766 #define ADC_MASTER_REGISTER(__HANDLE__) ( (ADC1)) 767 #endif 768 769 /** 770 * @brief Check whether or not dual regular conversions are enabled 771 * @param __HANDLE__: ADC handle 772 * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled) 773 */ 774 #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \ 775 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ 776 )? \ 777 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \ 778 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \ 779 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \ 780 : \ 781 RESET \ 782 ) 783 784 /** 785 * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master 786 * @param __HANDLE__: ADC handle 787 * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode) 788 */ 789 #define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ 790 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2) \ 791 )? \ 792 SET \ 793 : \ 794 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET) \ 795 ) 796 #if defined (ADC3) 797 /** 798 * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master 799 * @param __HANDLE__: ADC handle 800 * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode) 801 */ 802 #define ADC3_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ 803 ( ( ((__HANDLE__)->Instance == ADC3) \ 804 )? \ 805 SET \ 806 : \ 807 ((ADC3_COMMON->CCR & ADC_CCR_DUAL) == RESET) \ 808 ) 809 #endif 810 /** 811 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled 812 * @param __HANDLE__: ADC handle 813 * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled) 814 */ 815 #if defined (ADC3) 816 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \ 817 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ 818 )? \ 819 SET \ 820 : \ 821 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 822 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \ 823 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) )) 824 #else 825 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \ 826 ( ( ((__HANDLE__)->Instance == ADC1) \ 827 )? \ 828 SET \ 829 : \ 830 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 831 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \ 832 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) )) 833 #endif 834 835 /** 836 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled 837 * @param __HANDLE__: ADC handle 838 * @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled) 839 */ 840 #if defined (ADC3) 841 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \ 842 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ 843 )? \ 844 SET \ 845 : \ 846 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 847 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \ 848 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) )) 849 #else 850 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \ 851 ( ( ((__HANDLE__)->Instance == ADC1) \ 852 )? \ 853 SET \ 854 : \ 855 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 856 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \ 857 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) )) 858 #endif 859 860 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \ 861 ADC_CCR_PRESC | \ 862 ADC_CCR_VBATEN | \ 863 ADC_CCR_TSEN | \ 864 ADC_CCR_VREFEN | \ 865 ADC_CCR_DAMDF | \ 866 ADC_CCR_DELAY | \ 867 ADC_CCR_DUAL ) 868 869 /** 870 * @brief Set handle instance of the ADC slave associated to the ADC master. 871 * @param __HANDLE_MASTER__ ADC master handle. 872 * @param __HANDLE_SLAVE__ ADC slave handle. 873 * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. 874 * @retval None 875 */ 876 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ 877 ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) ) 878 879 880 /** 881 * @brief Verify the ADC instance connected to the temperature sensor. 882 * @param __HANDLE__ ADC handle. 883 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 884 */ 885 #if defined(ADC3) 886 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC3) 887 #else 888 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2) 889 #endif 890 891 /** 892 * @brief Verify the ADC instance connected to the battery voltage VBAT. 893 * @param __HANDLE__ ADC handle. 894 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 895 */ 896 #if defined(ADC3) 897 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC3) 898 #else 899 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2) 900 #endif 901 902 /** 903 * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. 904 * @param __HANDLE__ ADC handle. 905 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 906 */ 907 #if defined(ADC3) 908 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC3) 909 #else 910 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2) 911 #endif 912 913 /** 914 * @brief Verify the length of scheduled injected conversions group. 915 * @param __LENGTH__ number of programmed conversions. 916 * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) 917 */ 918 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) 919 920 /** 921 * @brief Calibration factor size verification (7 bits maximum). 922 * @param __CALIBRATION_FACTOR__ Calibration factor value. 923 * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) 924 */ 925 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) 926 927 928 /** 929 * @brief Verify the ADC channel setting. 930 * @param __CHANNEL__ programmed ADC channel. 931 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 932 */ 933 #define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \ 934 ((__CHANNEL__) == ADC_CHANNEL_1) || \ 935 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 936 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 937 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 938 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 939 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 940 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 941 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 942 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 943 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 944 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 945 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 946 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 947 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 948 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 949 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 950 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 951 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 952 ((__CHANNEL__) == ADC_CHANNEL_19) || \ 953 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 954 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 955 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2)|| \ 956 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2)|| \ 957 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) ) 958 959 /** 960 * @brief Verify the ADC channel setting in differential mode for ADC1. 961 * @param __CHANNEL__: programmed ADC channel. 962 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 963 */ 964 #define IS_ADC1_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 965 ((__CHANNEL__) == ADC_CHANNEL_2) ||\ 966 ((__CHANNEL__) == ADC_CHANNEL_3) ||\ 967 ((__CHANNEL__) == ADC_CHANNEL_4) ||\ 968 ((__CHANNEL__) == ADC_CHANNEL_5) ||\ 969 ((__CHANNEL__) == ADC_CHANNEL_10) ||\ 970 ((__CHANNEL__) == ADC_CHANNEL_11) ||\ 971 ((__CHANNEL__) == ADC_CHANNEL_12) ||\ 972 ((__CHANNEL__) == ADC_CHANNEL_16) ||\ 973 ((__CHANNEL__) == ADC_CHANNEL_18) ) 974 975 /** 976 * @brief Verify the ADC channel setting in differential mode for ADC2. 977 * @param __CHANNEL__: programmed ADC channel. 978 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 979 */ 980 #define IS_ADC2_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 981 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 982 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 983 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 984 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 985 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 986 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 987 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 988 ((__CHANNEL__) == ADC_CHANNEL_18) ) 989 990 /** 991 * @brief Verify the ADC channel setting in differential mode for ADC3. 992 * @param __CHANNEL__: programmed ADC channel. 993 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 994 */ 995 #define IS_ADC3_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 996 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 997 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 998 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 999 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 1000 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 1001 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 1002 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 1003 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 1004 ((__CHANNEL__) == ADC_CHANNEL_15) ) 1005 1006 /** 1007 * @brief Verify the ADC single-ended input or differential mode setting. 1008 * @param __SING_DIFF__ programmed channel setting. 1009 * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) 1010 */ 1011 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ 1012 ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) 1013 1014 /** 1015 * @brief Verify the ADC offset management setting. 1016 * @param __OFFSET_NUMBER__ ADC offset management. 1017 * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) 1018 */ 1019 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ 1020 ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ 1021 ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ 1022 ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ 1023 ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) 1024 #if defined(ADC_VER_V5_V90) 1025 /** 1026 * @brief Verify the ADC offset sign setting. 1027 * @param __OFFSET_SIGN__ ADC offset sign. 1028 * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid) 1029 */ 1030 #define IS_ADC3_OFFSET_SIGN(__OFFSET_SIGN__) (((__OFFSET_SIGN__) == ADC3_OFFSET_SIGN_NEGATIVE) || \ 1031 ((__OFFSET_SIGN__) == ADC3_OFFSET_SIGN_POSITIVE) ) 1032 #endif /* ADC_VER_V5_V90 */ 1033 /** 1034 * @brief Verify the ADC injected channel setting. 1035 * @param __CHANNEL__ programmed ADC injected channel. 1036 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 1037 */ 1038 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ 1039 ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ 1040 ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ 1041 ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) 1042 1043 /** 1044 * @brief Verify the ADC injected conversions external trigger. 1045 * @param __INJTRIG__ programmed ADC injected conversions external trigger. 1046 * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) 1047 */ 1048 #if defined (HRTIM1) 1049 #define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 1050 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 1051 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 1052 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 1053 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 1054 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 1055 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ 1056 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 1057 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 1058 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 1059 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 1060 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 1061 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 1062 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 1063 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 1064 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 1065 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2) || \ 1066 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4) || \ 1067 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_OUT) || \ 1068 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_OUT) || \ 1069 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_OUT) || \ 1070 \ 1071 ((__INJTRIG__) == ADC_SOFTWARE_START) ) 1072 #else 1073 #define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 1074 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 1075 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 1076 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 1077 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 1078 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 1079 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ 1080 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 1081 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 1082 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 1083 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 1084 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 1085 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 1086 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 1087 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 1088 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 1089 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_OUT) || \ 1090 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_OUT) || \ 1091 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_OUT) || \ 1092 \ 1093 ((__INJTRIG__) == ADC_SOFTWARE_START) ) 1094 #endif /* HRTIM */ 1095 /** 1096 * @brief Verify the ADC edge trigger setting for injected group. 1097 * @param __EDGE__ programmed ADC edge trigger setting. 1098 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 1099 */ 1100 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 1101 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 1102 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 1103 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 1104 1105 /** 1106 * @brief Verify the ADC multimode setting. 1107 * @param __MODE__ programmed ADC multimode setting. 1108 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1109 */ 1110 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ 1111 ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ 1112 ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ 1113 ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ 1114 ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ 1115 ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ 1116 ((__MODE__) == ADC_DUALMODE_INTERL) || \ 1117 ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) 1118 1119 /** 1120 * @brief Verify the ADC dual data mode setting. 1121 * @param MODE: programmed ADC dual mode setting. 1122 * @retval SET (MODE is valid) or RESET (MODE is invalid) 1123 */ 1124 #define IS_ADC_DUAL_DATA_MODE(MODE) (((MODE) == ADC_DUALMODEDATAFORMAT_DISABLED) || \ 1125 ((MODE) == ADC_DUALMODEDATAFORMAT_32_10_BITS) || \ 1126 ((MODE) == ADC_DUALMODEDATAFORMAT_8_BITS) ) 1127 1128 /** 1129 * @brief Verify the ADC multimode delay setting. 1130 * @param __DELAY__ programmed ADC multimode delay setting. 1131 * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) 1132 */ 1133 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ 1134 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ 1135 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ 1136 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ 1137 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 1138 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 1139 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 1140 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ 1141 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) ) 1142 1143 /** 1144 * @brief Verify the ADC analog watchdog setting. 1145 * @param __WATCHDOG__ programmed ADC analog watchdog setting. 1146 * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) 1147 */ 1148 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ 1149 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ 1150 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) 1151 1152 /** 1153 * @brief Verify the ADC analog watchdog mode setting. 1154 * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. 1155 * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) 1156 */ 1157 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ 1158 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 1159 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 1160 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 1161 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 1162 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 1163 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 1164 1165 #if defined(ADC_VER_V5_V90) 1166 /** 1167 * @brief Verify the ADC analog watchdog filtering setting. 1168 * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting. 1169 * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid) 1170 */ 1171 #define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE_ADC3(__FILTERING_MODE__) (((__FILTERING_MODE__) == ADC3_AWD_FILTERING_NONE) || \ 1172 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_2SAMPLES) || \ 1173 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_3SAMPLES) || \ 1174 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_4SAMPLES) || \ 1175 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_5SAMPLES) || \ 1176 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_6SAMPLES) || \ 1177 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_7SAMPLES) || \ 1178 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_8SAMPLES) ) 1179 1180 #endif /* ADC_VER_V5_V90 */ 1181 1182 /** 1183 * @brief Verify the ADC conversion (regular or injected or both). 1184 * @param __CONVERSION__ ADC conversion group. 1185 * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) 1186 */ 1187 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ 1188 ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ 1189 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) 1190 1191 /** 1192 * @brief Verify the ADC event type. 1193 * @param __EVENT__ ADC event. 1194 * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) 1195 */ 1196 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ 1197 ((__EVENT__) == ADC_AWD_EVENT) || \ 1198 ((__EVENT__) == ADC_AWD2_EVENT) || \ 1199 ((__EVENT__) == ADC_AWD3_EVENT) || \ 1200 ((__EVENT__) == ADC_OVR_EVENT) || \ 1201 ((__EVENT__) == ADC_JQOVF_EVENT) ) 1202 1203 /** 1204 * @brief Verify the ADC oversampling ratio. 1205 * @param RATIO: programmed ADC oversampling ratio. 1206 * @retval SET (RATIO is a valid value) or RESET (RATIO is invalid) 1207 */ 1208 #define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) >= 1UL) && ((RATIO) <= 1024UL)) 1209 1210 #if defined(ADC_VER_V5_V90) 1211 /** 1212 * @brief Verify the ADC3 oversampling ratio. 1213 * @param __RATIO__ programmed ADC oversampling ratio. 1214 * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) 1215 */ 1216 #define IS_ADC_OVERSAMPLING_RATIO_ADC3(__RATIO__) (((__RATIO__) == ADC3_OVERSAMPLING_RATIO_2 ) || \ 1217 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_4 ) || \ 1218 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_8 ) || \ 1219 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_16 ) || \ 1220 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_32 ) || \ 1221 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_64 ) || \ 1222 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_128 ) || \ 1223 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_256 )) 1224 #endif /* ADC_VER_V5_V90 */ 1225 1226 /** 1227 * @brief Verify the ADC oversampling shift. 1228 * @param __SHIFT__ programmed ADC oversampling shift. 1229 * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) 1230 */ 1231 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ 1232 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ 1233 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ 1234 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ 1235 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ 1236 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ 1237 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ 1238 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ 1239 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ) || \ 1240 ((__SHIFT__) == ADC_RIGHTBITSHIFT_9 ) || \ 1241 ((__SHIFT__) == ADC_RIGHTBITSHIFT_10 ) || \ 1242 ((__SHIFT__) == ADC_RIGHTBITSHIFT_11 )) 1243 1244 /** 1245 * @brief Verify the ADC oversampling triggered mode. 1246 * @param __MODE__ programmed ADC oversampling triggered mode. 1247 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1248 */ 1249 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ 1250 ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 1251 1252 /** 1253 * @brief Verify the ADC oversampling regular conversion resumed or continued mode. 1254 * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. 1255 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1256 */ 1257 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ 1258 ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) 1259 1260 /** 1261 * @brief Verify the DFSDM mode configuration. 1262 * @param __HANDLE__ ADC handle. 1263 * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For 1264 * this reason, the input parameter is the ADC handle and not the configuration parameter 1265 * directly. 1266 * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) 1267 */ 1268 #if defined(DFSDM1_Channel0) 1269 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \ 1270 ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) ) 1271 #else 1272 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) 1273 #endif 1274 1275 /** 1276 * @brief Return the DFSDM configuration mode. 1277 * @param __HANDLE__ ADC handle. 1278 * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). 1279 * For this reason, the input parameter is the ADC handle and not the configuration parameter 1280 * directly. 1281 * @retval DFSDM configuration mode 1282 */ 1283 #if defined(DFSDM1_Channel0) 1284 #define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig) 1285 #else 1286 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) 1287 #endif 1288 1289 /** 1290 * @} 1291 */ 1292 1293 1294 /* Exported functions --------------------------------------------------------*/ 1295 /** @addtogroup ADCEx_Exported_Functions 1296 * @{ 1297 */ 1298 1299 /** @addtogroup ADCEx_Exported_Functions_Group1 1300 * @{ 1301 */ 1302 /* IO operation functions *****************************************************/ 1303 1304 /* ADC calibration */ 1305 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff); 1306 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 1307 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer); 1308 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); 1309 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer); 1310 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_FactorLoad(ADC_HandleTypeDef *hadc); 1311 1312 1313 /* Blocking mode: Polling */ 1314 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); 1315 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); 1316 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1317 1318 /* Non-blocking mode: Interruption */ 1319 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); 1320 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); 1321 1322 /* ADC multimode */ 1323 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1324 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1325 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); 1326 1327 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1328 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); 1329 1330 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 1331 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); 1332 void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); 1333 void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); 1334 void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); 1335 void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); 1336 1337 /* ADC group regular conversions stop */ 1338 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); 1339 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); 1340 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); 1341 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1342 1343 /** 1344 * @} 1345 */ 1346 1347 /** @addtogroup ADCEx_Exported_Functions_Group2 1348 * @{ 1349 */ 1350 /* Peripheral Control functions ***********************************************/ 1351 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected); 1352 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); 1353 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); 1354 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); 1355 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); 1356 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); 1357 1358 /** 1359 * @} 1360 */ 1361 1362 /** 1363 * @} 1364 */ 1365 1366 /** 1367 * @} 1368 */ 1369 1370 /** 1371 * @} 1372 */ 1373 1374 #ifdef __cplusplus 1375 } 1376 #endif 1377 1378 #endif /* STM32H7xx_HAL_ADC_EX_H */ 1379 1380 1381
